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foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-008 / e12729d2aad359696c6761c37969f5fab028a916
commite12729d2aad359696c6761c37969f5fab028a916[log] [tgz]
authorStaf Verhaegen <staf@fibraservi.eu>Wed Mar 23 14:54:08 2022 +0100
committerStaf Verhaegen <staf@fibraservi.eu>Wed Mar 23 14:54:08 2022 +0100
tree14771accc43f4247f8ed3073b2d8c856862cea5c
parentc0e0fff60ebe846eba4ec5c096f3714600ef4c5f [diff]
Fix short.
1 file changed
tree: 14771accc43f4247f8ed3073b2d8c856862cea5c
  1. .github/
  2. docs/
  3. doitcode/
  4. gds/
  5. netgen/
  6. verilog/
  7. xschem/
  8. caravel
  9. .gitignore
  10. dodo.py
  11. LICENSE
  12. Makefile
  13. README.md
  14. user_analog_project_wrapper.png
README.md

PDKMaster based memory compiler test chip

TBD

Source

The top level is fully generated from python code in the doitcode subdirectory. pydoit is used to generate the desig with the provided dodo.py file in the top directory. The code depends on some external modules that are assumed to be installed:

  • PDKMaster: python framework (under heavy development) to ease generation of circuits and corresponding DRC compliant layout. This based on a description of a technology with python souce code to allow easy porting to different technologies.
  • c4m-flexcell: a (currently minimal) standard cell library based on PDKMaster
  • c4m-flexmem: the source for the memory compiler
  • c4m-pdk-sky130: the source for the PDKMaster based PDK for the Sky130 technology.

License

The resulting GDS files is released under the LGPL 2.1 or later license. Some of the source code to generate the GDS is under the GPL 2.0 or later license.