commit	ca4be4847098fe3c2d336259873e01aa1e364b6c	[log] [tgz]
author	Staf Verhaegen <staf@fibraservi.eu>	Sun Mar 20 16:50:53 2022 +0100
committer	Staf Verhaegen <staf@fibraservi.eu>	Sun Mar 20 19:38:08 2022 +0100
tree	d7d7cce850fa8973473a8f1dfcd68b3e02305a82
parent	45e94fd0a9a8533fa8afd2f2c7c441b0453f37bd [diff]

Empty top cell template

This was based on code from mpw4 io test at state of tape-out with
update fram pin locations.

.gitignore[diff]
LICENSE[diff]
dodo.py[Added - diff]
doitcode/__init__.py[Added - diff]
doitcode/frame.py[Added - diff]
doitcode/generate.py[Added - diff]
gds/user_analog_project_wrapper.gds[Deleted - diff]
gds/user_analog_project_wrapper.gds.gz[Added - diff]
gds/user_analog_project_wrapper_empty.gds[Added - diff]
mag/example_por.mag[Deleted - diff]
mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag[Deleted - diff]
mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag[Deleted - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag[Deleted - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag[Deleted - diff]
mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag[Deleted - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag[Deleted - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag[Deleted - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag[Deleted - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag[Deleted - diff]
mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag[Deleted - diff]
mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag[Deleted - diff]
mag/user_analog_proj_example.mag[Deleted - diff]
mag/user_analog_project_wrapper.mag[Deleted - diff]
mag/user_analog_project_wrapper_empty.mag[Deleted - diff]
netgen/comp.out[Deleted - diff]
netgen/example_por.spice[Deleted - diff]
netgen/run_lvs_por.sh[Deleted - diff]
netgen/run_lvs_wrapper_verilog.sh[Deleted - diff]
netgen/run_lvs_wrapper_xschem.sh[Deleted - diff]
netgen/user_analog_project_wrapper.spice[diff]
openlane/.gitignore[Deleted - diff]
openlane/Makefile[Deleted - diff]
user_analog_project_wrapper.png[Added - diff]
verilog/rtl/blocks.v[Added - diff]
verilog/rtl/example_por.v[Deleted - diff]
verilog/rtl/uprj_analog_netlists.v[diff]
verilog/rtl/user_analog_proj_example.v[Deleted - diff]
verilog/rtl/user_analog_project_wrapper.v[diff]

38 files changed

tree: d7d7cce850fa8973473a8f1dfcd68b3e02305a82

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.