commit | bf4f70434396d7290cc6b1f9e3a94ad1e4aba33f | [log] [tgz] |
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author | Jeff DiCorpo <jeffdi@efabless.com> | Mon Mar 27 18:14:21 2023 -0700 |
committer | Jeff DiCorpo <jeffdi@efabless.com> | Mon Mar 27 18:14:21 2023 -0700 |
tree | 5906bbf5f45ca7e7ad10d6a87636dfc168049bd9 | |
parent | a2580c026200b4c87b7913a96a1a267f5a511cd0 [diff] |
update repo
:exclamation: Important Note |
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Ahem! Testing? Testing? Everything seems to be in order...
Todo:
Cell A: TW Amplifier + SET + Integrated Amplifier
Cell B: TW Amplifier + SET
[x] Configuration Register
[ ] Digital lines wiring
[ ] TWG top wiring
[x] cell A top wiring
[ ] cell B
[ ] Opamp (400µA) DUTs
[ ] Opamp (200µA, Gain Boosted) DUTs
[ ] High Isolation 2-1 MUX DUTs
[ ] Standalone SET DUTs
[ ]