first version riscduino dual core
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index c8c838c..2aab7ff 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -30,7 +30,7 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 48e54f0..126b3c1 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -178,7 +178,7 @@
// Remove All Reset
- reg_mprj_wbhost_reg0 = 0x1F;
+ reg_mprj_globl_reg2 = 0x21F;
// Enable UART Multi Functional Ports
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 0461ba3..2c853fa 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -4,6 +4,7 @@
SIM ?= RTL
DUMP ?= OFF
+RISC_CORE ?=0
# PARAMETERS
@@ -47,7 +48,7 @@
VECT_IRQ ?= 0
IPIC ?= 0
TCM ?= 0
- SIM_CFG_DEF = YCR1_CFG_$(CFG)
+ SIM_CFG_DEF = YCR_CFG_$(CFG)
endif
endif
endif
@@ -136,7 +137,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = $(root_dir)/../model
UPRJ_BEHAVIOURAL_AGENTS = $(root_dir)/../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -283,6 +284,7 @@
printf "" > $(test_results); \
iverilog-vpi ../../../vpi/system/system.c; \
vvp -M. -msystem $(top_module).vvp \
+ +risc_core_id=$(RISC_CORE) \
+test_info=$(test_info) \
+test_results=$(test_results) \
| tee $(sim_results) ;\
@@ -303,6 +305,7 @@
printf "" > $(test_results); \
iverilog-vpi ../../../vpi/system/system.c; \
vvp -M. -msystem $(top_module).vvp \
+ +risc_core_id=$(RISC_CORE) \
+test_info=$(test_info) \
+test_results=$(test_results) \
| tee $(sim_results) ;\
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv
index 25c14a5..9a798ff 100644
--- a/verilog/dv/riscv_regress/riscv_runtests.sv
+++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -34,7 +34,7 @@
logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o_r; // DMEM address
logic core2dmem_cmd_o_r;
- `define RISC_CORE i_top.i_core_top
+ `define RISC_CORE i_top.i_core_top_0
always@(posedge `RISC_CORE.clk) begin
if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
@@ -55,7 +55,7 @@
**/
/***
logic [31:0] test_count;
- `define RISC_CORE u_top.u_riscv_top.i_core_top
+ `define RISC_CORE u_top.u_riscv_top.i_core_top_0
`define RISC_EXU u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu
initial begin
@@ -71,6 +71,10 @@
end
***/
+wire [31:0] pc_curr_ff = (d_risc_id == 0) ? u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_exu.pc_curr_ff : u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_pipe_exu.pc_curr_ff;
+wire [31:0] exu2pipe_pc_curr_o = (d_risc_id == 0) ? u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o : u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o;
+wire [31:0] mprf_int_10 = (d_risc_id == 0) ? u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_mprf.mprf_int[10] : u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_pipe_mprf.mprf_int[10];
+
always @(posedge clk) begin
bit test_pass;
int unsigned f_test;
@@ -78,11 +82,11 @@
if (test_running) begin
test_pass = 1;
rst_init <= 1'b0;
- if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.pc_curr_ff === 32'hxxxx_xxxx) begin
+ if(pc_curr_ff === 32'hxxxx_xxxx) begin
$display("ERROR: CURRENT PC Counter State is Known");
$finish;
end
- if ((u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o == YCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
+ if ((exu2pipe_pc_curr_o == YCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
`ifdef VERILATOR
logic [255:0] full_filename;
@@ -103,9 +107,9 @@
// Flush the content of dcache for signature validation at app
// memory
- force u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush = 1'b1;
- wait(u_top.u_riscv_top.u_intf.u_dcache.force_flush_done == 1'b1);
- release u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush;
+ force u_top.u_riscv_top.u_mintf.u_intf.u_dcache.cfg_force_flush = 1'b1;
+ wait(u_top.u_riscv_top.u_mintf.u_intf.u_dcache.force_flush_done == 1'b1);
+ release u_top.u_riscv_top.u_mintf.u_intf.u_dcache.cfg_force_flush;
repeat (2000) @(posedge clock); // wait data to flush in pipe
$display("STATUS: Checking Complaince Test Status .... ");
test_running <= 1'b0;
@@ -203,10 +207,10 @@
`endif // SIGNATURE_OUT
end else begin // Non compliance mode
test_running <= 1'b0;
- if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] != 0)
- $display("ERROR: mprf_int[10]: %x not zero",u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10]);
+ if(mprf_int_10 != 0)
+ $display("ERROR: mprf_int[10]: %x not zero",mprf_int_10);
- test_pass = (u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] == 0);
+ test_pass = (mprf_int_10 == 0);
tests_total += 1;
tests_passed += test_pass;
`ifndef SIGNATURE_OUT
@@ -236,7 +240,10 @@
if (f_test != 0) begin
// Launch new test
`ifdef YCR1_TRACE_LOG_EN
- u_top.u_riscv_top.i_core_top.i_pipe_top.i_tracelog.test_name = test_file;
+ if(d_risc_id == 0)
+ u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_tracelog.test_name = test_file;
+ else
+ u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_tracelog.test_name = test_file;
`endif // SCR1_TRACE_LOG_EN
//i_memory_tb.test_file = test_file;
//i_memory_tb.test_file_init = 1'b1;
diff --git a/verilog/dv/riscv_regress/run_iverilog b/verilog/dv/riscv_regress/run_iverilog
index fbd8e05..6245dbc 100755
--- a/verilog/dv/riscv_regress/run_iverilog
+++ b/verilog/dv/riscv_regress/run_iverilog
@@ -18,7 +18,7 @@
-I ../../../../../verilog/rtl \
-I ../../../../../verilog \
-I ../../../agents \
--I ../../../../../verilog/rtl/yifive/ycr1c/src/includes \
+-I ../../../../../verilog/rtl/yifive/ycr2c/src/includes \
-I ../../../../../verilog/rtl/sdram_ctrl/src/defs \
-I ../../../../../verilog/rtl/i2cm/src/includes \
-I ../../../../../verilog/rtl/usb1_host/src/includes \
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
index d7b3d63..19f8703 100644
--- a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
+++ b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
@@ -11,9 +11,9 @@
#define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER)
// IPIC
-#define IRQ_LINES_ADDR 0x10020018 // simulation
-#define TRIG_EXT_IRQ_ADDR 0x10020018 // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
-#define TRIG_SW_IRQ_ADDR 0x10020018 // software irq is triggered when tb memory is set to non-zero // Bit [16]
+#define IRQ_LINES_ADDR 0x10020020 // simulation
+#define TRIG_EXT_IRQ_ADDR 0x10020020 // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
+#define TRIG_SW_IRQ_ADDR 0x10020020 // software irq is triggered when tb memory is set to non-zero // Bit [16]
#define IPIC_EOI 0xBF4 // end of interrupt
#define IPIC_SOI 0xBF5 // start of interrupt
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 2bc1cfb..c23fe35 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -78,6 +78,9 @@
`include "mt48lc8m8a2.v"
`include "is62wvs1288.v"
+
+`define ADDR_SPACE_PINMUX 32'h3002_0000
+
localparam [31:0] YCR1_SIM_EXIT_ADDR = 32'h0000_00F8;
localparam [31:0] YCR1_SIM_PRINT_ADDR = 32'hF000_0000;
localparam [31:0] YCR1_SIM_EXT_IRQ_ADDR = 32'hF000_0100;
@@ -157,6 +160,7 @@
logic [7:0] tem_mem[0:4095];
logic [31:0] mem_data;
+ integer d_risc_id;
parameter P_FSM_C = 4'b0000; // Command Phase Only
@@ -220,6 +224,8 @@
wbd_ext_we_i ='h0; // write
wbd_ext_dat_i ='h0; // data output
wbd_ext_sel_i ='h0; // byte enable
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
end
`ifdef WFDUMP
@@ -230,7 +236,6 @@
$dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top);
$dumpvars(0, user_risc_regress_tb.u_top.u_qspi_master);
$dumpvars(0, user_risc_regress_tb.u_top.u_intercon);
- $dumpvars(0, user_risc_regress_tb.u_top.u_mbist);
end
`endif
@@ -289,7 +294,13 @@
repeat (2) @(posedge clock);
#1;
// Remove WB and SPI Reset, Keep SDARM and CORE under Reset
- wb_user_core_write('h3080_0000,'h5);
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+ end else begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+ end
// CS#2 Switch to QSPI Mode
wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile
index ec6f963..9be6ff7 100644
--- a/verilog/dv/uart_master/Makefile
+++ b/verilog/dv/uart_master/Makefile
@@ -31,7 +31,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index e9e1108..e534f3b 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 5788ed8..6f0b848 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 826774d..b56a263 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -127,7 +127,7 @@
`ifdef WFDUMP
initial begin
- $dumpfile("tb_top.vcd");
+ $dumpfile("simx.vcd");
$dumpvars(0, tb_top);
end
`endif
@@ -151,11 +151,14 @@
repeat (10) @(posedge clock);
#1;
// Enable I2M Block & WB Reset and Enable I2CM Mux Select
- wb_user_core_write('h3080_0000,'hA1);
+ wb_user_core_write('h3080_0000,'h01);
// Enable I2C Multi Functional Ports
wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h200);
+ // Remove i2m reset
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h010);
+
repeat (100) @(posedge clock);
@(posedge clock);
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 1057c10..46c4437 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -47,6 +47,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
DUMP?=OFF
+RISC_CORE?=0
.SUFFIXES:
@@ -92,7 +93,7 @@
endif
%.vcd: %.vvp
- vvp $<
+ vvp $< +risc_core_id=$(RISC_CORE)
%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index fff2408..11360d2 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -78,6 +78,7 @@
`include "uprj_netlists.v"
`include "mt48lc8m8a2.v"
+`define ADDR_SPACE_PINMUX 32'h3002_0000
module user_risc_boot_tb;
reg clock;
reg wb_rst_i;
@@ -105,6 +106,7 @@
wire [7:0] mprj_io_0;
reg test_fail;
reg [31:0] read_data;
+ integer d_risc_id;
@@ -133,6 +135,8 @@
initial begin
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
@@ -143,7 +147,13 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- wb_user_core_write('h3080_0000,'hF);
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+ end else begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+ end
// Repeat cycles of 1000 clock edges as needed to complete testbench
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index e0934e1..bedef96 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index cb37454..97b7c9f 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -101,6 +101,8 @@
`define QSPIM_IMEM_RDATA 32'h1000002C
`define QSPIM_SPI_STATUS 32'h10000030
+ `define ADDR_SPACE_PINMUX 32'h3002_0000
+
module user_spi_tb;
reg clock;
reg wb_rst_i;
@@ -221,8 +223,8 @@
repeat (2) @(posedge clock);
#1;
- // Remove WB and SPI Reset, Keep SDARM and CORE under Reset
- wb_user_core_write('h3080_0000,'h5);
+ // Remove only WB and SPI Reset
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h2);
wb_user_core_write('h3080_0004,'h0); // Change the Bank Sel 0
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 387f35d..320f113 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -47,6 +47,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
DUMP?=OFF
+RISC_CORE?=0
.SUFFIXES:
@@ -92,7 +93,7 @@
endif
%.vcd: %.vvp
- vvp $<
+ vvp $< +risc_core_id=$(RISC_CORE)
%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index dba2b77..9e150f4 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -129,6 +129,8 @@
reg [7:0] uart_write_data [0:39];
reg uart_fifo_enable ; // fifo mode disable
+ integer d_risc_id;
+
integer i,j;
// External clock is used by default. Make this artificially fast for the
@@ -171,6 +173,8 @@
uart_timeout = 500;// wait time limit
uart_fifo_enable = 0; // fifo mode disable
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Uart Test Started");
@@ -184,7 +188,13 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- wb_user_core_write('h3080_0000,'h1F);
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+ end else begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+ end
repeat (100) @(posedge clock); // wait for Processor Get Ready
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index b52caef..4e61e77 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index a19be6a..8844da3 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -30,7 +30,7 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
