gatesim setup cleanup
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index 37feef0..e8d50fd 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -42,7 +42,6 @@ all: ${PATTERN:=.vcd} -hex: ${PATTERN:=.hex} vvp: ${PATTERN:=.vvp} @@ -58,9 +57,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 94209cd..fb09225 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -416,6 +416,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -445,6 +446,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -466,29 +468,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile index e7d9b13..a801f55 100644 --- a/verilog/dv/user_i2cm/Makefile +++ b/verilog/dv/user_i2cm/Makefile
@@ -26,9 +26,6 @@ DESIGNS?=../../.. export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -45,7 +42,6 @@ all: ${PATTERN:=.vcd} -hex: ${PATTERN:=.hex} vvp: ${PATTERN:=.vvp} @@ -61,9 +57,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp @@ -73,6 +75,6 @@ # ---- Clean ---- clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.fst .PHONY: clean hex all
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index aedd191..0607308 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -405,6 +405,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -433,6 +434,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1;
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index cbe03cb..43ba01f 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -360,6 +360,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -389,6 +390,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1;
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile index 1932afc..90648dd 100644 --- a/verilog/dv/user_qspi/Makefile +++ b/verilog/dv/user_qspi/Makefile
@@ -26,9 +26,6 @@ DESIGNS?=../../.. export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -61,9 +58,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v index fdac089..4fd07e5 100644 --- a/verilog/dv/user_qspi/user_qspi_tb.v +++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -1297,6 +1297,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -1326,6 +1327,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -1348,29 +1350,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile index 4a0c488..85751d6 100644 --- a/verilog/dv/user_risc_boot/Makefile +++ b/verilog/dv/user_risc_boot/Makefile
@@ -46,7 +46,6 @@ all: ${PATTERN:=.vcd} -hex: ${PATTERN:=.hex} vvp: ${PATTERN:=.vvp} @@ -68,9 +67,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index 2bb2a1b..b6df7c1 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -335,6 +335,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -364,6 +365,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -385,29 +387,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile index 9d8bd45..8a734e8 100644 --- a/verilog/dv/user_sspi/Makefile +++ b/verilog/dv/user_sspi/Makefile
@@ -26,9 +26,6 @@ DESIGNS?=../../.. export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -61,9 +58,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp @@ -73,6 +76,6 @@ # ---- Clean ---- clean: - rm -f *.vvp *.vcd *.log *.fst + rm -f *.elf *.bin *.vvp *.vcd *.log *.dump *.fst .PHONY: clean hex all
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v index e3cd34e..1e81542 100644 --- a/verilog/dv/user_sspi/user_sspi_tb.v +++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -567,6 +567,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -596,6 +597,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -618,29 +620,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v index d7ef5e6..8fced3c 100644 --- a/verilog/dv/user_timer/user_timer_tb.v +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -394,6 +394,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -423,6 +424,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1;
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile index 97726ee..a97fa0f 100644 --- a/verilog/dv/user_uart/Makefile +++ b/verilog/dv/user_uart/Makefile
@@ -67,9 +67,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp @@ -81,4 +87,4 @@ clean: rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump -.PHONY: clean hex all +.PHONY: clean all
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 6f4e2ef..30fd1b8 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -215,14 +215,14 @@ for (i=0; i<40; i=i+1) begin $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]); - user_uart_tb.tb_uart.write_char (uart_write_data[i]); + tb_uart.write_char (uart_write_data[i]); end end begin for (j=0; j<40; j=j+1) begin - user_uart_tb.tb_uart.read_char_chk(uart_write_data[j]); + tb_uart.read_char_chk(uart_write_data[j]); end end join @@ -403,6 +403,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -419,29 +420,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile index 046c8df..04737d0 100644 --- a/verilog/dv/user_uart1/Makefile +++ b/verilog/dv/user_uart1/Makefile
@@ -67,9 +67,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v index 4946c9f..44587e4 100644 --- a/verilog/dv/user_uart1/user_uart1_tb.v +++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -403,6 +403,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -419,29 +420,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile index 7f9bc7b..5eccb5b 100644 --- a/verilog/dv/user_uart_master/Makefile +++ b/verilog/dv/user_uart_master/Makefile
@@ -60,9 +60,15 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp @@ -73,6 +79,6 @@ # ---- Clean ---- clean: - rm -f *.vvp *.vcd *.log + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump .PHONY: clean all
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile index a25bc69..1684a0d 100644 --- a/verilog/dv/user_usb/Makefile +++ b/verilog/dv/user_usb/Makefile
@@ -61,18 +61,24 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $< -o $@ + endif endif %.vcd: %.vvp - vvp $< + vvp $< +risc_core_id=$(RISC_CORE) # ---- Clean ---- clean: - rm -f *.vvp *.vcd *.log *.fst + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump .PHONY: clean hex all
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index d2e37b4..6d9f043 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -270,7 +270,7 @@ // Full Speed Device Indication pullup(usbd_txdp); -//pulldown(usbd_txdn); +pulldown(usbd_txdn); usb1d_top u_usb_top( @@ -452,6 +452,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1; @@ -503,29 +504,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 633a369..b7dd1b4 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -152,11 +152,11 @@ ## RTL ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif @@ -165,11 +165,11 @@ ## GL ifeq ($(SIM),GL) ifeq ($(CONFIG),caravel_user_project) - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< endif
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project new file mode 100644 index 0000000..1096f6c --- /dev/null +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -0,0 +1,29 @@ +# Caravel user project includes ++define+UNIT_DELAY=#0.1 ++incdir+$(USER_PROJECT_VERILOG)/rtl/ ++incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes ++incdir+$(USER_PROJECT_VERILOG)/dv/bfm ++incdir+$(USER_PROJECT_VERILOG)/dv/model ++incdir+$(USER_PROJECT_VERILOG)/dv/agents +$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v +$(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v +$(USER_PROJECT_VERILOG)/gl/ycr_intf.v +$(USER_PROJECT_VERILOG)/gl/qspim_top.v +$(USER_PROJECT_VERILOG)/gl/wb_host.v +$(USER_PROJECT_VERILOG)/gl/ycr4_iconnect.v +$(USER_PROJECT_VERILOG)/gl/ycr_core_top.v +$(USER_PROJECT_VERILOG)/gl/pinmux.v +$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v +$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v +########################################################### +# STD CELLS - they need to be below the defines.v files +########################################################### +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v +