digital pll integration
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index 46dd963..ae96bb8 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -93,6 +93,7 @@ pinmux_debug\[29\] pinmux_debug\[30\] pinmux_debug\[31\] +dbg_clk_mon #W
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc index 69c2345..4a33fc5 100644 --- a/openlane/uart_i2cm_usb_spi_top/base.sdc +++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -7,8 +7,8 @@ # Timing Constraints ############################################################################### create_clock -name app_clk -period 10.0000 [get_ports {app_clk}] -create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.u_mux/X}] -create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.u_mux/X}] +create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}] +create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}] create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}] set_clock_transition 0.1500 [all_clocks]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 9b0cbc5..a97080d 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -27,7 +27,7 @@ # Timing configuration set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "app_clk usb_clk u_uart_core.u_lineclk_buf.u_mux/X" +set ::env(CLOCK_PORT) "app_clk usb_clk u_uart0_core.u_lineclk_buf.genblk1.u_mux/X u_uart1_core.u_lineclk_buf.genblk1.u_mux/X" set ::env(SYNTH_MAX_FANOUT) 4
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 641005b..65abbfa 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -76,6 +76,7 @@ $proj_dir/../../verilog/gl/ycr_intf.v \ $proj_dir/../../verilog/gl/ycr_core_top.v \ $proj_dir/../../verilog/gl/ycr4_iconnect.v \ + $proj_dir/../../verilog/gl/digital_pll.v \ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ " @@ -88,6 +89,7 @@ $lef_root/ycr_intf.lef \ $lef_root/ycr_core_top.lef \ $lef_root/ycr4_iconnect.lef \ + $lef_root/digital_pll.lef \ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ " @@ -100,6 +102,7 @@ $gds_root/ycr_intf.gds \ $gds_root/ycr_core_top.gds \ $gds_root/ycr4_iconnect.gds \ + $gds_root/digital_pll.gds \ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ "
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 602ee8d..a96d256 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -15,3 +15,4 @@ u_intercon 1850 650 N u_wb_host 1750 100 N +u_pll 2200 100 N
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc index 9d9cc79..a5b2325 100644 --- a/openlane/wb_host/base.sdc +++ b/openlane/wb_host/base.sdc
@@ -8,7 +8,12 @@ ############################################################################### create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}] create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}] -create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.u_mux/X}] +create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}] + +create_clock -name int_pll_clock -period 10.0000 [get_pins {u_clkbuf_pll.u_buf/X}] +create_clock -name wbs_ref_clk -period 10.0000 [get_pins {u_wbs_ref_clkbuf.u_buf/X}] +create_clock -name cpu_ref_clk -period 10.0000 [get_pins {u_cpu_ref_clkbuf.u_buf/X}] +create_clock -name usb_ref_clk -period 10.0000 [get_pins {u_usb_ref_clkbuf.u_buf/X}] set_clock_transition 0.1500 [all_clocks] set_clock_uncertainty -setup 0.2500 [all_clocks] @@ -20,9 +25,14 @@ set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {uart_clk}] \ - -group [get_clocks {wbs_clk_i}] \ - -group [get_clocks {wbm_clk_i}] -comment {Async Clock group} + -group [get_clocks {uart_clk}] \ + -group [get_clocks {wbs_clk_i}] \ + -group [get_clocks {wbm_clk_i}] \ + -group [get_clocks {int_pll_clock}] \ + -group [get_clocks {wbs_ref_clk}] \ + -group [get_clocks {cpu_ref_clk}] \ + -group [get_clocks {usb_ref_clk}] \ + -comment {Async Clock group} ### ClkSkew Adjust set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index 4ebb2bb..0d8ff81 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -26,7 +26,7 @@ # Timing configuration set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.u_mux/X" +set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X" set ::env(SYNTH_MAX_FANOUT) 4 @@ -85,7 +85,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.38" +set ::env(PL_TARGET_DENSITY) "0.40"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg index 3448c6c..17b3e01 100644 --- a/openlane/wb_host/pin_order.cfg +++ b/openlane/wb_host/pin_order.cfg
@@ -5,22 +5,6 @@ #W usb_clk 0000 0 4 -cfg_clk_ctrl1\[31\] -cfg_clk_ctrl1\[30\] -cfg_clk_ctrl1\[29\] -cfg_clk_ctrl1\[28\] -cfg_clk_ctrl2\[27\] -cfg_clk_ctrl2\[26\] -cfg_clk_ctrl2\[25\] -cfg_clk_ctrl2\[24\] -cfg_clk_ctrl2\[23\] -cfg_clk_ctrl2\[22\] -cfg_clk_ctrl2\[21\] -cfg_clk_ctrl2\[20\] -cfg_clk_ctrl2\[19\] -cfg_clk_ctrl2\[18\] -cfg_clk_ctrl2\[17\] -cfg_clk_ctrl2\[16\] cpu_clk 0100 0 2 rtc_clk @@ -159,33 +143,61 @@ la_data_in\[17\] #E +cfg_dc_trim\[7\] 000 0 2 +cfg_dc_trim\[8\] +cfg_dc_trim\[9\] +cfg_dc_trim\[10\] +cfg_dc_trim\[11\] +cfg_dc_trim\[12\] +cfg_dc_trim\[13\] +cfg_dc_trim\[14\] +cfg_dc_trim\[15\] +cfg_dc_trim\[16\] +cfg_dc_trim\[17\] +cfg_dc_trim\[18\] +cfg_dc_trim\[19\] -uartm_rxd 100 0 2 +cfg_dc_trim\[25\] +cfg_dc_trim\[24\] +cfg_dc_trim\[23\] +cfg_dc_trim\[22\] +cfg_dc_trim\[21\] +cfg_dc_trim\[20\] + +pll_clk_out\[0\] +pll_clk_out\[1\] +cfg_pll_fed_div\[0\] +cfg_pll_fed_div\[1\] +cfg_pll_fed_div\[2\] +cfg_pll_fed_div\[3\] +cfg_pll_fed_div\[4\] +cfg_pll_enb +cfg_dco_mode +cfg_dc_trim\[0\] +cfg_dc_trim\[1\] +cfg_dc_trim\[2\] +cfg_dc_trim\[3\] +cfg_dc_trim\[4\] +cfg_dc_trim\[5\] +cfg_dc_trim\[6\] + +wbd_pll_rst_n +pll_ref_clk + + + +uartm_rxd 300 0 2 uartm_txd +dbg_clk_mon + #N wbd_int_rst_n 0100 0 2 -cfg_clk_ctrl2\[31\] -cfg_clk_ctrl2\[30\] -cfg_clk_ctrl2\[29\] -cfg_clk_ctrl2\[28\] -cfg_clk_ctrl2\[15\] -cfg_clk_ctrl2\[14\] -cfg_clk_ctrl2\[13\] -cfg_clk_ctrl2\[12\] -cfg_clk_ctrl2\[11\] -cfg_clk_ctrl2\[10\] -cfg_clk_ctrl2\[9\] -cfg_clk_ctrl2\[8\] -cfg_clk_ctrl2\[7\] -cfg_clk_ctrl2\[6\] -cfg_clk_ctrl2\[5\] -cfg_clk_ctrl2\[4\] -cfg_clk_ctrl2\[3\] -cfg_clk_ctrl2\[2\] -cfg_clk_ctrl2\[1\] -cfg_clk_ctrl2\[0\] +cfg_clk_ctrl1\[31\] +cfg_clk_ctrl1\[30\] +cfg_clk_ctrl1\[29\] +cfg_clk_ctrl1\[28\] cfg_clk_ctrl1\[27\] cfg_clk_ctrl1\[26\] cfg_clk_ctrl1\[25\]
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index d1d8819..e80b873 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -157,6 +157,7 @@ read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef + read_spef -path mprj/u_pll $::env(USER_ROOT)/spef/digital_pll.spef read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index c9efeb9..02e4326 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -14,14 +14,24 @@ #create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25 create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i] +create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_wb_host/u_clkbuf_pll.u_buf/X}] + +create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_wbs_ref_clkbuf.u_buf/X}] create_clock -name wbs_clk_i -period 10.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}] -create_clock -name cpu_ref_clk -period 10.0000 [get_pins {mprj/u_wb_host/u_cpu_ref_sel.u_mux/X}] + +create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_cpu_ref_clkbuf.u_buf/X}] create_clock -name cpu_clk -period 10.0000 [get_pins {mprj/u_wb_host/cpu_clk}] + create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}] + +create_clock -name pll_ref_clk -period 20.0000 [get_pins {mprj/u_wb_host/pll_ref_clk}] +create_clock -name pll_clk_0 -period 5.0000 [get_pins {mprj/u_pll/ringosc.ibufp01/Y}] + +create_clock -name usb_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_usb_ref_clkbuf.u_buf/X}] create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}] -create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}] -create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.u_mux/X}] -create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}] +create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}] +create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}] +create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}] ## Case analysis @@ -70,17 +80,22 @@ set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}] #disable clock gating check at static clock select pins -set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.u_mux/S] +set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.genblk1.u_mux/S] set_propagated_clock [all_clocks] set_clock_groups -name async_clock -asynchronous \ -group [get_clocks {clock wb_clk }]\ -group [get_clocks {user_clk2}]\ + -group [get_clocks {int_pll_clock}]\ -group [get_clocks {wbs_clk_i}]\ + -group [get_clocks {wbs_ref_clk}]\ -group [get_clocks {cpu_clk}]\ -group [get_clocks {cpu_ref_clk}]\ -group [get_clocks {rtc_clk}]\ + -group [get_clocks {usb_ref_clk}]\ + -group [get_clocks {pll_ref_clk}]\ + -group [get_clocks {pll_clk_0}]\ -group [get_clocks {usb_clk}]\ -group [get_clocks {uarts0_clk}]\ -group [get_clocks {uarts1_clk}]\ @@ -149,8 +164,6 @@ set_false_path -from [get_ports mprj_io[*]] set_false_path -from [get_ports gpio] -## User Project static signals -set_false_path -through [get_pins mprj/u_pinmux/bist_en] # TODO set this as parameter set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index 4422d7d..8d46511 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile @@ -139,7 +140,7 @@ %.lst: %.elf ${GCC_PREFIX}-objdump -d -S $< > $@ -%.hex: %.elf +%.hex: %.elf %.lst ${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -ie 's/@10/@00/g' $@ @@ -163,26 +164,26 @@ ## RTL ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif -endif +endif -## GL +##GL ifeq ($(SIM),GL) - ifeq ($(CONFIG),caravel_user_project) - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + ifeq ($(DUMP),OFF) + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ - -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ - -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + iverilog -g2005-sv -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< endif endif
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index 7de5444..00d308d 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -141,7 +141,7 @@ reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; @@ -150,6 +150,7 @@ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); + reg_la0_data = 0x001; // Remove Soft Reset reg_la0_data = 0x000; reg_la0_data = 0x001; // Remove Soft Reset
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v index e879f99..e9865d9 100644 --- a/verilog/dv/risc_boot/risc_boot_tb.v +++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -121,6 +121,9 @@ clock = 0; end +pullup(mprj_io[3]); + + `ifdef WFDUMP initial begin @@ -130,7 +133,6 @@ //$dumpvars(2,risc_boot_tb.uut); $dumpvars(1,risc_boot_tb.uut.mprj); $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host); - $dumpvars(1,risc_boot_tb.uut.mprj.u_riscv_top); //$dumpvars(0,risc_boot_tb.tb_uart); //$dumpvars(0,risc_boot_tb.u_user_spiflash); $display("Waveform Dump started");
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index f2e318f..15194cc 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -200,7 +200,7 @@ # Targets -.PHONY: tests run_iverilog run_iverilog_wf run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf +.PHONY: tests run_iverilog run_modelsim run_modelsim_wlf run_vcs run_ncsim run_verilator run_verilator_wf default: clean_test_list run_iverilog @@ -272,10 +272,67 @@ printf "$$(cat $(test_results)) \n" run_iverilog: $(test_info) +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) cd $(bld_dir); \ iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -I $(UPRJ_TESTS_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $(sv_list) \ + -o $(top_module).vvp; \ + printf "" > $(test_results); \ + iverilog-vpi ../../../vpi/system/system.c; \ + vvp -M. -msystem $(top_module).vvp \ + +risc_core_id=$(RISC_CORE) \ + +test_info=$(test_info) \ + +test_results=$(test_results) \ + | tee $(sim_results) ;\ + printf "Simulation performed on $$(vvp -V) \n" ;\ + printf " Test | build | simulation \n" ; \ + printf "$$(cat $(test_results)) \n" + else + cd $(bld_dir); \ + iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $(sv_list) \ + -o $(top_module).vvp; \ + printf "" > $(test_results); \ + iverilog-vpi ../../../vpi/system/system.c; \ + vvp -M. -msystem $(top_module).vvp \ + +risc_core_id=$(RISC_CORE) \ + +test_info=$(test_info) \ + +test_results=$(test_results) \ + | tee $(sim_results) ;\ + printf "Simulation performed on $$(vvp -V) \n" ;\ + printf " Test | build | simulation \n" ; \ + printf "$$(cat $(test_results)) \n" + endif +else + ifeq ($(DUMP),OFF) + cd $(bld_dir); \ + iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + $(sv_list) \ + -o $(top_module).vvp; \ + printf "" > $(test_results); \ + iverilog-vpi ../../../vpi/system/system.c; \ + vvp -M. -msystem $(top_module).vvp \ + +risc_core_id=$(RISC_CORE) \ + +test_info=$(test_info) \ + +test_results=$(test_results) \ + | tee $(sim_results) ;\ + printf "Simulation performed on $$(vvp -V) \n" ;\ + printf " Test | build | simulation \n" ; \ + printf "$$(cat $(test_results)) \n" + else + cd $(bld_dir); \ + iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(UPRJ_TESTS_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ $(sv_list) \ -o $(top_module).vvp; \ printf "" > $(test_results); \ @@ -289,23 +346,8 @@ printf " Test | build | simulation \n" ; \ printf "$$(cat $(test_results)) \n" -run_iverilog_wf: $(test_info) - cd $(bld_dir); \ - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(UPRJ_TESTS_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ - $(sv_list) \ - -o $(top_module).vvp; \ - printf "" > $(test_results); \ - iverilog-vpi ../../../vpi/system/system.c; \ - vvp -M. -msystem $(top_module).vvp \ - +risc_core_id=$(RISC_CORE) \ - +test_info=$(test_info) \ - +test_results=$(test_results) \ - | tee $(sim_results) ;\ - printf "Simulation performed on $$(vvp -V) \n" ;\ - printf " Test | build | simulation \n" ; \ - printf "$$(cat $(test_results)) \n" + endif +endif run_modelsim_wlf: $(test_info) $(MAKE) -C $(root_dir)/sim build_modelsim_wlf SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS); \
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 2fc3ce8..8d892af 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -480,6 +480,7 @@ wbd_ext_cyc_i ='h1; // strobe/request wbd_ext_stb_i ='h1; // strobe/request wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); data = wbd_ext_dat_o; repeat (1) @(posedge clock); #1;
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile index 0746413..3a63981 100644 --- a/verilog/dv/uart_master/Makefile +++ b/verilog/dv/uart_master/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index e8d50fd..c1ad8ae 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -50,20 +50,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index e3e17d9..69ee65d 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -20,7 +20,6 @@ //// //// //// This file is part of the YIFive cores project //// //// https://github.com/dineshannayya/yifive_r0.git //// -//// http://www.opencores.org/cores/yifive/ //// //// //// //// Description //// //// This is a standalone test bench to validate the //// @@ -152,6 +151,12 @@ initial begin $dumpfile("simx.vcd"); $dumpvars(0, user_basic_tb); + //$dumpvars(1, user_basic_tb.u_top); + //$dumpvars(0, user_basic_tb.u_top.u_pll); + //$dumpvars(1, user_basic_tb.u_top.u_wb_host); + //$dumpvars(1, user_basic_tb.u_top.u_intercon); + //$dumpvars(1, user_basic_tb.u_top.u_intercon); + //$dumpvars(1, user_basic_tb.u_top.u_pinmux); end `endif @@ -160,6 +165,8 @@ #100; wb_rst_i <= 1'b0; // Release reset end + + initial begin @@ -173,80 +180,111 @@ fork begin // Default Value Check - // cfg_glb_ctrl = reg_0[6:0]; - // uart_i2c_usb_sel = reg_0[8:7]; - // cfg_wb_clk_ctrl = reg_0[11:9]; - // cfg_rtc_clk_ctrl = reg_0[19:12]; - // cfg_cpu_clk_ctrl = reg_0[23:20]; - // cfg_usb_clk_ctrl = reg_0[31:24]; - $display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1"); + // cfg_wb_clk_ctrl = cfg_clk_ctrl2[7:0]; + // cfg_rtc_clk_ctrl = cfg_clk_ctrl2[15:8]; + // cfg_cpu_clk_ctrl = cfg_clk_ctrl2[23:16]; + // cfg_usb_clk_ctrl = cfg_clk_ctrl2[31:24]; + + + $display("Step-1, CPU: CLOCK1, USB: CLOCK2,RTC: CLOCK2 *2, WBS:CLOCK1"); test_step = 1; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h0,4'h0,8'h0,4'h0,8'h00}); - clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h0,8'h0,8'h0}); + clock_monitor(CLK1_PERIOD,CLK1_PERIOD,CLK2_PERIOD*2,CLK1_PERIOD); - $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK2"); + $display("Step-2, CPU: CLOCK2, USB: CLOCK2/2, RTC: CLOCK2/(2+1), WBS:CLOCK2"); test_step = 2; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h80,4'h8,8'h1,4'h8,8'h00}); - clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,CLK2_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h40,8'h60,8'h1,8'h40}); + clock_monitor(CLK2_PERIOD,2*CLK2_PERIOD,(3)*CLK2_PERIOD,CLK2_PERIOD); - $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/2"); + $display("Step-3, CPU: CLOCK1/2,USB: CLOCK2/(2+1), RTC: CLOCK2/(2+2), WBS:CLOCK1/2"); test_step = 3; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h81,4'h4,8'h2,4'h4,8'h00}); - clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,2*CLK1_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h20,8'h61,8'h2,8'h20}); + clock_monitor(2*CLK1_PERIOD,(3)*CLK2_PERIOD,4*CLK2_PERIOD,2*CLK1_PERIOD); - $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/3"); + $display("Step-4, CPU: CLOCK1/3, USB: CLOCK2/(2+2), RTC: CLOCK2/(2+3), WBS:CLOCK1/3"); test_step = 4; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h5,8'h3,4'h5,8'h00}); - clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,3*CLK1_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h21,8'h62,8'h3,8'h21}); + clock_monitor(3*CLK1_PERIOD,4*CLK2_PERIOD,5*CLK2_PERIOD,3*CLK1_PERIOD); - $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/4"); + $display("Step-5, CPU: CLOCK1/4, USB: CLOCK2/(2+3), RTC: CLOCK2/(2+4), WBS:CLOCK1/4"); test_step = 5; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h83,4'h6,8'h4,4'h6,8'h00}); - clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,4*CLK1_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h22,8'h63,8'h4,8'h22}); + clock_monitor(4*CLK1_PERIOD,5*CLK2_PERIOD,6*CLK2_PERIOD,4*CLK1_PERIOD); - $display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)"); + $display("Step-6, CPU: CLOCK1/(2+3),USB: CLOCK2/(2+4), RTC: CLOCK2/(2+5), WBS:CLOCK1/(2+3)"); test_step = 6; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h84,4'h7,8'h5,4'h7,8'h00}); - clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h23,8'h64,8'h5,8'h23}); + clock_monitor(5*CLK1_PERIOD,6*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD); - $display("Step-7, CPU: CLOCK2/(2), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK2/(2)"); + $display("Step-7, CPU: CLOCK2/(2), USB: CLOCK2/(2+5), RTC: CLOCK2/(2+6), WBS:CLOCK2/(2)"); test_step = 7; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h85,4'hC,8'h6,4'hC,8'h00}); - clock_monitor(2*CLK2_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,2*CLK2_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h60,8'h65,8'h6,8'h60}); + clock_monitor(2*CLK2_PERIOD,7*CLK2_PERIOD,8*CLK2_PERIOD,2*CLK2_PERIOD); - $display("Step-8, CPU: CLOCK2/3, RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK2/3"); + $display("Step-8, CPU: CLOCK2/3, USB: CLOCK2/(2+6), RTC: CLOCK2/(2+7), WBS:CLOCK2/3"); test_step = 8; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h86,4'hD,8'h7,4'hD,8'h00}); - clock_monitor(3*CLK2_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,3*CLK2_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h61,8'h66,8'h7,8'h61}); + clock_monitor(3*CLK2_PERIOD,8*CLK2_PERIOD,9*CLK2_PERIOD,3*CLK2_PERIOD); - $display("Step-9, CPU: CLOCK2/4, RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK2/4"); + $display("Step-9, CPU: CLOCK2/4,USB: CLOCK2/(2+7), RTC: CLOCK2/(2+8), WBS:CLOCK2/4"); test_step = 9; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h87,4'hE,8'h8,4'hE,8'h00}); - clock_monitor(4*CLK2_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,4*CLK2_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h62,8'h67,8'h8,8'h62}); + clock_monitor(4*CLK2_PERIOD,9*CLK2_PERIOD,10*CLK2_PERIOD,4*CLK2_PERIOD); - $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+8), WBS:CLOCK1/(2+3)"); + $display("Step-10, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+8), RTC: CLOCK2/(2+128), WBS:CLOCK1/(2+3)"); test_step = 10; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h88,4'hF,8'h80,4'hF,8'h00}); - clock_monitor(5*CLK2_PERIOD,130*CLK2_PERIOD,10*CLK2_PERIOD,5*CLK2_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h68,8'h80,8'h63}); + clock_monitor(5*CLK2_PERIOD,10*CLK2_PERIOD,130*CLK2_PERIOD,5*CLK2_PERIOD); - $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+9), WBS:CLOCK2/(2+3)"); + $display("Step-11, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)"); test_step = 10; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h89,4'hF,8'hFF,4'hF,8'h00}); - clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,11*CLK2_PERIOD,5*CLK2_PERIOD); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); + clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD); + + $display("###################################################"); + $display("Monitor: Checking the PLL:"); + $display("###################################################"); + test_step = 11; + // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000}); + repeat (100) @(posedge clock); + pll_clock_monitor(5); + + test_step = 12; + // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); + repeat (100) @(posedge clock); + pll_clock_monitor(4); $display("###################################################"); + $display("Monitor: Monitor Clock output:"); + $display("###################################################"); + $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)"); + test_step = 13; + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); + + // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); + dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD); + + $display("###################################################"); $display("Monitor: Checking the chip signature :"); + $display("###################################################"); + test_step = 14; // Remove Wb/PinMux Reset wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2405_2022); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_3000); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2905_2022); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_4000); end begin - repeat (20000) @(posedge clock); + repeat (30000) @(posedge clock); // $display("+1000 cycles"); test_fail = 1; end @@ -324,28 +362,71 @@ task clock_monitor; input [15:0] exp_cpu_period; -input [15:0] exp_rtc_period; input [15:0] exp_usb_period; +input [15:0] exp_rtc_period; input [15:0] exp_wbs_period; begin force clock_mon = u_top.u_wb_host.cpu_clk; check_clock_period("CPU CLock",exp_cpu_period); release clock_mon; - force clock_mon = u_top.u_wb_host.rtc_clk; - check_clock_period("RTC Clock",exp_rtc_period); - release clock_mon; - force clock_mon = u_top.u_wb_host.usb_clk; check_clock_period("USB Clock",exp_usb_period); release clock_mon; + force clock_mon = u_top.u_wb_host.rtc_clk; + check_clock_period("RTC Clock",exp_rtc_period); + release clock_mon; + force clock_mon = u_top.u_wb_host.wbs_clk_out; check_clock_period("WBS Clock",exp_wbs_period); release clock_mon; end endtask +task pll_clock_monitor; +input [15:0] exp_period; +begin + force clock_mon = u_top.u_wb_host.pll_clk_out[0]; + check_clock_period("PLL CLock",exp_period); + release clock_mon; +end +endtask + + +wire dbg_clk_mon = io_out[33]; + +task dbg_clk_monitor; +input [15:0] exp_pll_div16_period; +input [15:0] exp_pll_ref_period; +input [15:0] exp_cpu_period; +input [15:0] exp_usb_period; +input [15:0] exp_rtc_period; +input [15:0] exp_wbs_period; +begin + force clock_mon = dbg_clk_mon; + + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2}); + check_clock_period("PLL CLock",exp_pll_div16_period); + + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0001,8'h2}); + check_clock_period("PLL REF Clock",exp_pll_ref_period); + + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0010,8'h2}); + check_clock_period("WBS Clock",exp_wbs_period); + + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0011,8'h2}); + check_clock_period("CPU CLock",exp_cpu_period); + + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0100,8'h2}); + check_clock_period("RTC Clock",exp_rtc_period); + + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0101,8'h2}); + check_clock_period("USB Clock",exp_usb_period); + release clock_mon; +end +endtask + //---------------------------------- // Check the clock period //----------------------------------
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile index a801f55..f01c09d 100644 --- a/verilog/dv/user_i2cm/Makefile +++ b/verilog/dv/user_i2cm/Makefile
@@ -24,8 +24,12 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -50,20 +54,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index 0607308..e0f8219 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -444,13 +444,11 @@ wbd_ext_we_i ='h0; // write wbd_ext_dat_i ='h0; // data output wbd_ext_sel_i ='h0; // byte enable - if(data === cmp_data) begin - $display("STATUS: DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; end else begin - $display("ERROR: DEBUG WB USER ACCESS READ Address : %x, Exp Data : %x Rxd Data: ",address,cmp_data,data); - test_fail= 1; - #100 - $finish; + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); end repeat (2) @(posedge clock); end @@ -458,29 +456,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c.u_uart_core.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c.u_uart_core.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c.u_uart_core.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c.u_uart_core.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c.u_uart_core.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c.u_uart_core.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c.u_uart_core.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_mcore/Makefile b/verilog/dv/user_mcore/Makefile index a7d9f3f..a0795af 100644 --- a/verilog/dv/user_mcore/Makefile +++ b/verilog/dv/user_mcore/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -61,20 +62,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile index 96815e2..c521c74 100644 --- a/verilog/dv/user_pwm/Makefile +++ b/verilog/dv/user_pwm/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -54,16 +55,26 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif endif %.vcd: %.vvp
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index 43ba01f..e5222cc 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -20,7 +20,6 @@ //// //// //// This file is part of the YIFive cores project //// //// https://github.com/dineshannayya/yifive_r0.git //// -//// http://www.opencores.org/cores/yifive/ //// //// //// //// Description //// //// This is a standalone test bench to validate the //// @@ -413,21 +412,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile index 90648dd..6b87fce 100644 --- a/verilog/dv/user_qspi/Makefile +++ b/verilog/dv/user_qspi/Makefile
@@ -24,8 +24,12 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -51,20 +55,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile index 85751d6..da70cab 100644 --- a/verilog/dv/user_risc_boot/Makefile +++ b/verilog/dv/user_risc_boot/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -60,20 +61,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_sram_exec/Makefile b/verilog/dv/user_sram_exec/Makefile index b0f31fc..44f56ab 100644 --- a/verilog/dv/user_sram_exec/Makefile +++ b/verilog/dv/user_sram_exec/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -60,20 +61,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile index 8a734e8..f16f2a7 100644 --- a/verilog/dv/user_sspi/Makefile +++ b/verilog/dv/user_sspi/Makefile
@@ -24,8 +24,12 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -51,20 +55,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile index 6520c31..077652a 100644 --- a/verilog/dv/user_timer/Makefile +++ b/verilog/dv/user_timer/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -54,16 +55,26 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif endif %.vcd: %.vvp
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v index 8fced3c..b27d655 100644 --- a/verilog/dv/user_timer/user_timer_tb.v +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -447,21 +447,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile index a97fa0f..0c74848 100644 --- a/verilog/dv/user_uart/Makefile +++ b/verilog/dv/user_uart/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -60,20 +61,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 30fd1b8..e0656e9 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -191,7 +191,7 @@ $display("STATUS: Working with Risc core 2"); wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); end else if(d_risc_id == 3) begin - $display("STATUS: Working with Risc core 2"); + $display("STATUS: Working with Risc core 3"); wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); end
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile index 04737d0..7f299a1 100644 --- a/verilog/dv/user_uart1/Makefile +++ b/verilog/dv/user_uart1/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -60,20 +61,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile index 5eccb5b..800f73a 100644 --- a/verilog/dv/user_uart_master/Makefile +++ b/verilog/dv/user_uart_master/Makefile
@@ -53,20 +53,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile index 1684a0d..d8eee80 100644 --- a/verilog/dv/user_usb/Makefile +++ b/verilog/dv/user_usb/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -54,20 +55,24 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ $< -o $@ endif else ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else - iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index 6d9f043..5974990 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -53,7 +53,7 @@ module user_usb_tb; parameter USB_HPER = 10.4167; // 48Mhz Half cycle -parameter USER2_HPER = 2.6042; // 192Mhz Half cycle +parameter USER2_HPER = 2.7777; // 180Mhz Half cycle reg clock; reg user_clock2; @@ -135,7 +135,12 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(5, user_usb_tb); + $dumpvars(0, user_usb_tb); + //$dumpvars(1, user_usb_tb.u_top); + //$dumpvars(1, user_usb_tb.u_top.u_uart_i2c_usb_spi); + //$dumpvars(0, user_usb_tb.u_top.u_uart_i2c_usb_spi.u_usb_host); + //$dumpvars(0, user_usb_tb.u_top.u_intercon); + //$dumpvars(0, user_usb_tb.u_top.u_wb_host); end `endif @@ -166,8 +171,9 @@ repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); - // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); + + // Remove Wb/PinMux Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable SPI Multi Functional Ports wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400); @@ -175,8 +181,10 @@ repeat (2) @(posedge clock); #1; - // Set USB clock : 192/4 = 48Mhz - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h0,8'h0,4'h0,8'h01}); + // Remove Wb/PinMux Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + // Set USB clock : 180/3 = 60Mhz + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h61,8'h0,8'h0}); // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index b7dd1b4..0a94555 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile @@ -50,7 +51,8 @@ ## Compiler Information ####################################################################### -export GCC_PATH?= $(TOOLS)/bin +export TOOLS ?= /opt/riscv64i +export GCC_PATH ?= $(TOOLS)/bin export GCC_PREFIX?= riscv64-unknown-linux-gnu @@ -160,18 +162,18 @@ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif -endif +endif -## GL +##GL ifeq ($(SIM),GL) - ifeq ($(CONFIG),caravel_user_project) - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + ifeq ($(DUMP),OFF) + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ - -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ - -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< endif endif
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index d3d63fe..03a5799 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -57,7 +57,7 @@ /* Set up the housekeeping SPI to be connected internally so */ /* that external pin changes don't affect it. */ - reg_spi_enable = 1; + reg_spi_enable = 0; reg_wb_enable = 1; // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, // connect to housekeeping SPI
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index f2c62cb..ba2cae8 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -24,7 +24,7 @@ reg power1, power2; reg power3, power4; - wire gpio; + tri gpio; wire [37:0] mprj_io; wire [7:0] mprj_io_0; wire [15:0] checkbits; @@ -43,13 +43,18 @@ clock = 0; end +pullup(mprj_io[3]); + `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); $dumpvars(1, wb_port_tb); $dumpvars(1, wb_port_tb.uut); $dumpvars(1, wb_port_tb.uut.mgmt_buffers); + $dumpvars(1, wb_port_tb.uut.housekeeping); + $dumpvars(1, wb_port_tb.uut.pll); $dumpvars(1, wb_port_tb.uut.soc); + $dumpvars(1, wb_port_tb.uut.soc.core); $dumpvars(1, wb_port_tb.uut.mprj); $dumpvars(1, wb_port_tb.uut.mprj.u_wb_host); //$dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index 1096f6c..37573f0 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -17,13 +17,5 @@ $(USER_PROJECT_VERILOG)/gl/pinmux.v $(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v $(USER_PROJECT_VERILOG)/gl/wb_interconnect.v -########################################################### -# STD CELLS - they need to be below the defines.v files -########################################################### --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v +
diff --git a/verilog/includes/includes.gl.lib b/verilog/includes/includes.gl.lib new file mode 100644 index 0000000..d82a5c2 --- /dev/null +++ b/verilog/includes/includes.gl.lib
@@ -0,0 +1,11 @@ +########################################################### +# STD CELLS - they need to be below the defines.v files +########################################################### +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v +-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v + +$(USER_PROJECT_VERILOG)/gl/digital_pll.v
diff --git a/verilog/includes/includes.rtl.lib b/verilog/includes/includes.rtl.lib new file mode 100644 index 0000000..5045805 --- /dev/null +++ b/verilog/includes/includes.rtl.lib
@@ -0,0 +1,3 @@ +-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v +-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v +-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/digital_pll/src/digital_pll.v new file mode 100644 index 0000000..f5400d8 --- /dev/null +++ b/verilog/rtl/digital_pll/src/digital_pll.v
@@ -0,0 +1,68 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +// Digital PLL (ring oscillator + controller) +// Technically this is a frequency locked loop, not a phase locked loop. + +module digital_pll( +`ifdef USE_POWER_PINS + VPWR, + VGND, +`endif + resetb, enable, osc, clockp, div, dco, ext_trim); + +`ifdef USE_POWER_PINS + input VPWR; + input VGND; +`endif + + input resetb; // Sense negative reset + input enable; // Enable PLL + input osc; // Input oscillator to match + input [4:0] div; // PLL feedback division ratio + input dco; // Run in DCO mode + input [25:0] ext_trim; // External trim for DCO mode + + output [1:0] clockp; // Two 90 degree clock phases + + wire [25:0] itrim; // Internally generated trim bits + wire [25:0] otrim; // Trim bits applied to the ring oscillator + wire creset; // Controller reset + wire ireset; // Internal reset (external reset OR disable) + + assign ireset = ~resetb | ~enable; + + // In DCO mode: Hold controller in reset and apply external trim value + + assign itrim = (dco == 1'b0) ? otrim : ext_trim; + assign creset = (dco == 1'b0) ? ireset : 1'b1; + + ring_osc2x13 ringosc ( + .reset(ireset), + .trim(itrim), + .clockp(clockp) + ); + + digital_pll_controller pll_control ( + .reset(creset), + .clock(clockp[0]), + .osc(osc), + .div(div), + .trim(otrim) + ); + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/digital_pll/src/digital_pll_controller.v b/verilog/rtl/digital_pll/src/digital_pll_controller.v new file mode 100644 index 0000000..ae13d9d --- /dev/null +++ b/verilog/rtl/digital_pll/src/digital_pll_controller.v
@@ -0,0 +1,136 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +// (True) digital PLL +// +// Output goes to a trimmable ring oscillator (see documentation). +// Ring oscillator should be trimmable to above and below maximum +// ranges of the input. +// +// Input "osc" comes from a fixed clock source (e.g., crystal oscillator +// output). +// +// Input "div" is the target number of clock cycles per oscillator cycle. +// e.g., if div == 8 then this is an 8X PLL. +// +// Clock "clock" is the PLL output being trimmed. +// (NOTE: To be done: Pass-through enable) +// +// Algorithm: +// +// 1) Trim is done by thermometer code. Reset to the highest value +// in case the fastest rate clock is too fast for the logic. +// +// 2) Count the number of contiguous 1s and 0s in "osc" +// periods of the master clock. If the count maxes out, it does +// not roll over. +// +// 3) Add the two counts together. +// +// 4) If the sum is less than div, then the clock is too slow, so +// decrease the trim code. If the sum is greater than div, the +// clock is too fast, so increase the trim code. If the sum +// is equal to div, the the trim code does not change. +// + +module digital_pll_controller(reset, clock, osc, div, trim); + input reset; + input clock; + input osc; + input [4:0] div; + output [25:0] trim; // Use ring_osc2x13, with 26 trim bits + + wire [25:0] trim; + reg [2:0] oscbuf; + reg [2:0] prep; + + reg [4:0] count0; + reg [4:0] count1; + reg [6:0] tval; // Includes 2 bits fractional + wire [4:0] tint; // Integer part of the above + + wire [5:0] sum; + + assign sum = count0 + count1; + + // Integer to thermometer code (maybe there's an algorithmic way?) + assign tint = tval[6:2]; + // |<--second-->|<-- first-->| + assign trim = (tint == 5'd0) ? 26'b0000000000000_0000000000000 : + (tint == 5'd1) ? 26'b0000000000000_0000000000001 : + (tint == 5'd2) ? 26'b0000000000000_0000001000001 : + (tint == 5'd3) ? 26'b0000000000000_0010001000001 : + (tint == 5'd4) ? 26'b0000000000000_0010001001001 : + (tint == 5'd5) ? 26'b0000000000000_0010101001001 : + (tint == 5'd6) ? 26'b0000000000000_1010101001001 : + (tint == 5'd7) ? 26'b0000000000000_1010101101001 : + (tint == 5'd8) ? 26'b0000000000000_1010101101101 : + (tint == 5'd9) ? 26'b0000000000000_1011101101101 : + (tint == 5'd10) ? 26'b0000000000000_1011101111101 : + (tint == 5'd11) ? 26'b0000000000000_1111101111101 : + (tint == 5'd12) ? 26'b0000000000000_1111101111111 : + (tint == 5'd13) ? 26'b0000000000000_1111111111111 : + (tint == 5'd14) ? 26'b0000000000001_1111111111111 : + (tint == 5'd15) ? 26'b0000001000001_1111111111111 : + (tint == 5'd16) ? 26'b0010001000001_1111111111111 : + (tint == 5'd17) ? 26'b0010001001001_1111111111111 : + (tint == 5'd18) ? 26'b0010101001001_1111111111111 : + (tint == 5'd19) ? 26'b1010101001001_1111111111111 : + (tint == 5'd20) ? 26'b1010101101001_1111111111111 : + (tint == 5'd21) ? 26'b1010101101101_1111111111111 : + (tint == 5'd22) ? 26'b1011101101101_1111111111111 : + (tint == 5'd23) ? 26'b1011101111101_1111111111111 : + (tint == 5'd24) ? 26'b1111101111101_1111111111111 : + (tint == 5'd25) ? 26'b1111101111111_1111111111111 : + 26'b1111111111111_1111111111111; + + always @(posedge clock or posedge reset) begin + if (reset == 1'b1) begin + tval <= 7'd0; // Note: trim[0] must be zero for startup to work. + oscbuf <= 3'd0; + prep <= 3'd0; + count0 <= 5'd0; + count1 <= 5'd0; + + end else begin + oscbuf <= {oscbuf[1:0], osc}; + + if (oscbuf[2] != oscbuf[1]) begin + count1 <= count0; + count0 <= 5'b00001; + prep <= {prep[1:0], 1'b1}; + + if (prep == 3'b111) begin + if (sum > div) begin + if (tval < 127) begin + tval <= tval + 1; + end + end else if (sum < div) begin + if (tval > 0) begin + tval <= tval - 1; + end + end + end + end else begin + if (count0 != 5'b11111) begin + count0 <= count0 + 1; + end + end + end + end + +endmodule // digital_pll_controller +`default_nettype wire
diff --git a/verilog/rtl/digital_pll/src/ring_osc2x13.v b/verilog/rtl/digital_pll/src/ring_osc2x13.v new file mode 100644 index 0000000..f20110e --- /dev/null +++ b/verilog/rtl/digital_pll/src/ring_osc2x13.v
@@ -0,0 +1,250 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +// Tunable ring oscillator---synthesizable (physical) version. +// +// NOTE: This netlist cannot be simulated correctly due to lack +// of accurate timing in the digital cell verilog models. + +module delay_stage(in, trim, out); + input in; + input [1:0] trim; + output out; + + wire d0, d1, d2, ts; + + sky130_fd_sc_hd__clkbuf_2 delaybuf0 ( + .A(in), + .X(ts) + ); + + sky130_fd_sc_hd__clkbuf_1 delaybuf1 ( + .A(ts), + .X(d0) + ); + + sky130_fd_sc_hd__einvp_2 delayen1 ( + .A(d0), + .TE(trim[1]), + .Z(d1) + ); + + sky130_fd_sc_hd__einvn_4 delayenb1 ( + .A(ts), + .TE_B(trim[1]), + .Z(d1) + ); + + sky130_fd_sc_hd__clkinv_1 delayint0 ( + .A(d1), + .Y(d2) + ); + + sky130_fd_sc_hd__einvp_2 delayen0 ( + .A(d2), + .TE(trim[0]), + .Z(out) + ); + + sky130_fd_sc_hd__einvn_8 delayenb0 ( + .A(ts), + .TE_B(trim[0]), + .Z(out) + ); + +endmodule + +module start_stage(in, trim, reset, out); + input in; + input [1:0] trim; + input reset; + output out; + + wire d0, d1, d2, ctrl0, one; + + sky130_fd_sc_hd__clkbuf_1 delaybuf0 ( + .A(in), + .X(d0) + ); + + sky130_fd_sc_hd__einvp_2 delayen1 ( + .A(d0), + .TE(trim[1]), + .Z(d1) + ); + + sky130_fd_sc_hd__einvn_4 delayenb1 ( + .A(in), + .TE_B(trim[1]), + .Z(d1) + ); + + sky130_fd_sc_hd__clkinv_1 delayint0 ( + .A(d1), + .Y(d2) + ); + + sky130_fd_sc_hd__einvp_2 delayen0 ( + .A(d2), + .TE(trim[0]), + .Z(out) + ); + + sky130_fd_sc_hd__einvn_8 delayenb0 ( + .A(in), + .TE_B(ctrl0), + .Z(out) + ); + + sky130_fd_sc_hd__einvp_1 reseten0 ( + .A(one), + .TE(reset), + .Z(out) + ); + + sky130_fd_sc_hd__or2_2 ctrlen0 ( + .A(reset), + .B(trim[0]), + .X(ctrl0) + ); + + sky130_fd_sc_hd__conb_1 const1 ( + .HI(one), + .LO() + ); + +endmodule + +// Ring oscillator with 13 stages, each with two trim bits delay +// (see above). Trim is not binary: For trim[1:0], lower bit +// trim[0] is primary trim and must be applied first; upper +// bit trim[1] is secondary trim and should only be applied +// after the primary trim is applied, or it has no effect. +// +// Total effective number of inverter stages in this oscillator +// ranges from 13 at trim 0 to 65 at trim 24. The intention is +// to cover a range greater than 2x so that the midrange can be +// reached over all PVT conditions. +// +// Frequency of this ring oscillator under SPICE simulations at +// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24). + +module ring_osc2x13(reset, trim, clockp); + input reset; + input [25:0] trim; + output[1:0] clockp; + +`ifdef FUNCTIONAL // i.e., behavioral model below + + reg [1:0] clockp; + reg hiclock; + integer i; + real delay; + wire [5:0] bcount; + + assign bcount = trim[0] + trim[1] + trim[2] + + trim[3] + trim[4] + trim[5] + trim[6] + trim[7] + + trim[8] + trim[9] + trim[10] + trim[11] + trim[12] + + trim[13] + trim[14] + trim[15] + trim[16] + trim[17] + + trim[18] + trim[19] + trim[20] + trim[21] + trim[22] + + trim[23] + trim[24] + trim[25]; + + initial begin + hiclock <= 1'b0; + delay = 3.0; + end + + // Fastest operation is 214 MHz = 4.67ns + // Delay per trim is 0.02385 + // Run "hiclock" at 2x this rate, then use positive and negative + // edges to derive the 0 and 90 degree phase clocks. + + always #delay begin + hiclock <= (hiclock === 1'b0); + end + + always @(trim) begin + // Implement trim as a variable delay, one delay per trim bit + delay = 1.168 + 0.012 * $itor(bcount); + end + + always @(posedge hiclock or posedge reset) begin + if (reset == 1'b1) begin + clockp[0] <= 1'b0; + end else begin + clockp[0] <= (clockp[0] === 1'b0); + end + end + + always @(negedge hiclock or posedge reset) begin + if (reset == 1'b1) begin + clockp[1] <= 1'b0; + end else begin + clockp[1] <= (clockp[1] === 1'b0); + end + end + +`else // !FUNCTIONAL; i.e., gate level netlist below + + wire [1:0] clockp; + wire [12:0] d; + wire [1:0] c; + + // Main oscillator loop stages + + genvar i; + generate + for (i = 0; i < 12; i = i + 1) begin : dstage + delay_stage id ( + .in(d[i]), + .trim({trim[i+13], trim[i]}), + .out(d[i+1]) + ); + end + endgenerate + + // Reset/startup stage + + start_stage iss ( + .in(d[12]), + .trim({trim[25], trim[12]}), + .reset(reset), + .out(d[0]) + ); + + // Buffered outputs a 0 and 90 degrees phase (approximately) + + sky130_fd_sc_hd__clkinv_2 ibufp00 ( + .A(d[0]), + .Y(c[0]) + ); + sky130_fd_sc_hd__clkinv_8 ibufp01 ( + .A(c[0]), + .Y(clockp[0]) + ); + sky130_fd_sc_hd__clkinv_2 ibufp10 ( + .A(d[6]), + .Y(c[1]) + ); + sky130_fd_sc_hd__clkinv_8 ibufp11 ( + .A(c[1]), + .Y(clockp[1]) + ); + +`endif // !FUNCTIONAL + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv index ebbd617..bd34f11 100644 --- a/verilog/rtl/lib/ctech_cells.sv +++ b/verilog/rtl/lib/ctech_cells.sv
@@ -15,7 +15,7 @@ for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_ sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S (S), .X (X[tcnt])); end - end else begin : bit_ + end else begin sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X)); end endgenerate @@ -39,7 +39,7 @@ for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_ sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S (S), .X (X[tcnt])); end - end else begin : bit_ + end else begin sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X)); end endgenerate @@ -63,7 +63,7 @@ for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_ sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S (S), .X (X[tcnt])); end - end else begin : bit_ + end else begin sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S (S), .X (X)); end endgenerate
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index c43864f..f00d432 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -131,7 +131,9 @@ input logic uartm_txd , output logic pulse1m_mclk, - output logic [31:0] pinmux_debug + output logic [31:0] pinmux_debug, + + input logic dbg_clk_mon ); @@ -503,10 +505,10 @@ * Pin-6 PD4/TXD[1] digital_io[5] * Pin-7 VCC - * Pin-8 GND - -* Pin-9 PB6/XTAL1/TOSC1 digital_io[6] +* Pin-9 PB6/XTAL1/TOSC1 digital_io[6] * Pin-10 PB7/XTAL2/TOSC2 digital_io[7] * Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] -* Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] +* Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2] * Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] * Pin-14 PB0/CLKO/ICP1 digital_io[11] * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[12] @@ -515,7 +517,7 @@ * Pin-18 PB4/MISO digital_io[15] * Pin-19 PB5/SCK digital_io[16] * Pin-20 AVCC - -* Pin-21 AREF analog_io[10] +* Pin-21 AREF analog_io[10] * Pin-22 GND - * Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] * Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] @@ -534,7 +536,7 @@ * sflash_io1 digital_io[30] * sflash_io2 digital_io[31] * sflash_io3 digital_io[32] -* reserved digital_io[33] +* dbg_clk_mon digital_io[33] * uartm_rxd digital_io[34] * uartm_txd digital_io[35] * usb_dp digital_io[36] @@ -758,8 +760,8 @@ digital_io_out[31] = sflash_do[2] ; digital_io_out[32] = sflash_do[3] ; - // Reserved - digital_io_out[33] = 1'b0; + // dbg_clk_mon - Pll clock output monitor + digital_io_out[33] = dbg_clk_mon; // UART MASTER I/f digital_io_out[34] = 1'b0 ; // RXD @@ -874,7 +876,7 @@ digital_io_oen[31] = sflash_oen[2]; digital_io_oen[32] = sflash_oen[3]; - // Reserved + // dbg_clk_mon digital_io_oen[33] = 1'b0 ; // UART MASTER digital_io_oen[34] = 1'b1; // RXD
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index 4f21946..e02f2cd 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -718,7 +718,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h2405_2022) u_reg_23 ( +gen_32b_reg #(32'h2905_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -731,9 +731,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 4.3 = 0004300 +// Software Reg-3: Poject Revison 4.4 = 0004400 // ---------------------------------------- -gen_32b_reg #(32'h0004_3000) u_reg_24 ( +gen_32b_reg #(32'h0004_4000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv index d94013b..42a8cec 100644 --- a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv +++ b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
@@ -287,7 +287,7 @@ //--------------------------------- .reg_cs (reg_spim_cs ), .reg_wr (reg_wr ), - .reg_addr (reg_addr ), + .reg_addr ({2'b0,reg_addr[5:0]} ), .reg_wdata (reg_wdata ), .reg_be (reg_be ),
diff --git a/verilog/rtl/usb1_host/src/core/usbh_core.sv b/verilog/rtl/usb1_host/src/core/usbh_core.sv index adffecb..91073cc 100644 --- a/verilog/rtl/usb1_host/src/core/usbh_core.sv +++ b/verilog/rtl/usb1_host/src/core/usbh_core.sv
@@ -59,7 +59,7 @@ // Params //----------------------------------------------------------------- #( - parameter USB_CLK_FREQ = 48000000 + parameter USB_CLK_FREQ = 60000000 ) //----------------------------------------------------------------- // Ports
diff --git a/verilog/rtl/usb1_host/src/core/usbh_sie.sv b/verilog/rtl/usb1_host/src/core/usbh_sie.sv index 0d046c0..39d10f9 100644 --- a/verilog/rtl/usb1_host/src/core/usbh_sie.sv +++ b/verilog/rtl/usb1_host/src/core/usbh_sie.sv
@@ -54,7 +54,7 @@ // Params //----------------------------------------------------------------- #( - parameter USB_CLK_FREQ = 48000000 + parameter USB_CLK_FREQ = 60000000 ) //----------------------------------------------------------------- // Ports
diff --git a/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v b/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v index c7ac174..f83656d 100644 --- a/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v +++ b/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v
@@ -54,6 +54,13 @@ //----------------------------------------------------------------- module usb_fs_phy +//----------------------------------------------------------------- +// Params +//----------------------------------------------------------------- +#( + parameter USB_CLK_FREQ = 60000000 +) + ( // Inputs input clk_i @@ -87,6 +94,12 @@ +//------------------------------------------------------------------------- +// For 60Mhz usb clock, data need to sample at once in 4 cycle (60/4 = 12Mhz) +// For 48Mhz usb clock, data need to sample at once in 3 cycle (48/3 = 12Mhz) +// ------------------------------------------------------------------------ +localparam SAMPLE_RATE = (USB_CLK_FREQ == 60000000) ? 3'd4 : 3'd3; + //----------------------------------------------------------------- // Wires / Registers //----------------------------------------------------------------- @@ -454,31 +467,36 @@ //----------------------------------------------------------------- // Sample Timer //----------------------------------------------------------------- -reg [1:0] sample_cnt_q; +reg [2:0] sample_cnt_q; reg adjust_delayed_q; always @ (posedge clk_i or negedge rstn_i) -if (!rstn_i) -begin - sample_cnt_q <= 2'd0; +if (!rstn_i) begin + sample_cnt_q <= 3'd0; adjust_delayed_q <= 1'b0; +end else begin + // Delayed adjustment + if (adjust_delayed_q) + adjust_delayed_q <= 1'b0; + else if (bit_edge_w && (sample_cnt_q != 3'd0) && (state_q < STATE_TX_SYNC)) + sample_cnt_q <= 3'd0; + // Can't adjust sampling point now? + else if (bit_edge_w && (sample_cnt_q == 3'd0) && (state_q < STATE_TX_SYNC)) begin + // Want to reset sampling point but need to delay adjustment by 1 cycle! + adjust_delayed_q <= 1'b1; + if(sample_cnt_q == SAMPLE_RATE) + sample_cnt_q <= 'b0; + else + sample_cnt_q <= sample_cnt_q + 'd1; + end else begin + if(sample_cnt_q == SAMPLE_RATE) + sample_cnt_q <= 'b0; + else + sample_cnt_q <= sample_cnt_q + 'd1; + end end -// Delayed adjustment -else if (adjust_delayed_q) - adjust_delayed_q <= 1'b0; -else if (bit_edge_w && (sample_cnt_q != 2'd0) && (state_q < STATE_TX_SYNC)) - sample_cnt_q <= 2'd0; -// Can't adjust sampling point now? -else if (bit_edge_w && (sample_cnt_q == 2'd0) && (state_q < STATE_TX_SYNC)) -begin - // Want to reset sampling point but need to delay adjustment by 1 cycle! - adjust_delayed_q <= 1'b1; - sample_cnt_q <= sample_cnt_q + 2'd1; -end -else - sample_cnt_q <= sample_cnt_q + 2'd1; -assign sample_w = (sample_cnt_q == 2'd0); +assign sample_w = (sample_cnt_q == 'd0); //----------------------------------------------------------------- // NRZI Receiver
diff --git a/verilog/rtl/usb1_host/src/top/usb1_host.sv b/verilog/rtl/usb1_host/src/top/usb1_host.sv index 6ee0ff5..3d8f8dd 100644 --- a/verilog/rtl/usb1_host/src/top/usb1_host.sv +++ b/verilog/rtl/usb1_host/src/top/usb1_host.sv
@@ -37,7 +37,7 @@ //// 2. usb1_core: usb1 core //// //// 3. usb1_host : usb phy //// //// //// -//// Assumptiom: usb_clk is 48Mhz //// +//// Assumptiom: usb_clk is 60Mhz //// //// //// //// To Do: //// //// nothing //// @@ -49,7 +49,15 @@ //// //// ////////////////////////////////////////////////////////////////////// -module usb1_host ( +module usb1_host +//----------------------------------------------------------------- +// Params +//----------------------------------------------------------------- +#( + parameter USB_CLK_FREQ = 60000000 +) + +( input logic usb_clk_i , input logic usb_rstn_i , @@ -112,13 +120,35 @@ logic [31:0] reg_rdata; logic reg_ack; + logic wbm_rst_ssn; + logic usb_rst_ssn; +//################################### +// Wishbone Reset Synchronization +//################################### +reset_sync u_wb_rst ( + .scan_mode (1'b0 ), + .dclk (wbm_clk_i ), // Destination clock domain + .arst_n (wbm_rst_n ), // active low async reset + .srst_n (wbm_rst_ssn ) + ); + +//################################### +// USB Reset Synchronization +//################################### +reset_sync u_usb_rst ( + .scan_mode (1'b0 ), + .dclk (usb_clk_i ), // Destination clock domain + .arst_n (usb_rstn_i ), // active low async reset + .srst_n (usb_rst_ssn ) + ); + async_wb #(.AW (6)) u_async_wb( // Master Port - .wbm_rst_n (wbm_rst_n ), // Regular Reset signal + .wbm_rst_n (wbm_rst_ssn ), // Regular Reset signal .wbm_clk_i (wbm_clk_i ), // System clock .wbm_cyc_i (wbm_stb_i ), // strobe/request .wbm_stb_i (wbm_stb_i ), // strobe/request @@ -131,7 +161,7 @@ .wbm_err_o (wbm_err_o ), // error // Slave Port - .wbs_rst_n (usb_rstn_i ), // Regular Reset signal + .wbs_rst_n (usb_rst_ssn ), // Regular Reset signal .wbs_clk_i (usb_clk_i ), // System clock .wbs_cyc_o ( ), // strobe/request .wbs_stb_o (reg_cs ), // strobe/request @@ -145,10 +175,10 @@ ); -usbh_core u_core ( +usbh_core #(.USB_CLK_FREQ(USB_CLK_FREQ)) u_core ( // Inputs .clk_i (usb_clk_i ), - .rstn_i (usb_rstn_i ), + .rstn_i (usb_rst_ssn ), .reg_cs (reg_cs ), .reg_wr (reg_wr ), @@ -182,10 +212,10 @@ -usb_fs_phy u_phy( +usb_fs_phy #(.USB_CLK_FREQ(USB_CLK_FREQ)) u_phy( // Inputs .clk_i (usb_clk_i ), - .rstn_i (usb_rstn_i ), + .rstn_i (usb_rst_ssn ), .utmi_data_out_i (utmi_data_out_o ), .utmi_txvalid_i (utmi_txvalid_o ), .utmi_op_mode_i (utmi_op_mode_o ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 93cab85..6a9eaf3 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -206,6 +206,9 @@ //// 4.3 May 24 2022, Dinesh A //// //// Re targetted the design to mpw-6 tools set and risc //// //// core logic are timing optimized to 100mhz //// +//// 4.4 May 29 2022, Dinesh A //// +//// 1. Digital PLL integrated and clock debug signal add //// +//// @digitial io [33] port ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -448,6 +451,7 @@ wire wbd_clk_spi ; wire wbd_clk_pinmux ; wire wbd_int_rst_n ; +wire wbd_pll_rst_n ; wire [15:0] irq_lines ; wire soft_irq ; @@ -455,7 +459,6 @@ wire [7:0] cfg_glb_ctrl ; wire [31:0] cfg_clk_ctrl1 ; -wire [31:0] cfg_clk_ctrl2 ; wire [3:0] cfg_cska_wi ; // clock skew adjust for wishbone interconnect wire [3:0] cfg_cska_wh ; // clock skew adjust for web host @@ -493,6 +496,7 @@ wire [31:0] spi_debug ; wire [31:0] pinmux_debug ; +wire dbg_clk_mon ; // clock monitoring port wire [63:0] riscv_debug ; // SFLASH I/F @@ -588,7 +592,15 @@ wire uartm_rxd ; wire uartm_txd ; - +//---------------------------------------------------------------- +// Digital PLL I/F +// ------------------------------------------------------------- +wire cfg_pll_enb ; // Enable PLL +wire [4:0] cfg_pll_fed_div ; // PLL feedback division ratio +wire cfg_dco_mode ; // Run PLL in DCO mode +wire [25:0] cfg_dc_trim ; // External trim for DCO mode +wire pll_ref_clk ; // Input oscillator to match +wire [1:0] pll_clk_out ; // Two 90 degree clock phases wire [3:0] spi_csn ; @@ -629,6 +641,7 @@ .usb_clk (usb_clk ), .wbd_int_rst_n (wbd_int_rst_n ), + .wbd_pll_rst_n (wbd_pll_rst_n ), // Master Port .wbm_rst_i (wb_rst_i ), @@ -662,17 +675,40 @@ .wbs_err_i (wbd_int_err_o ), .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), - .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), + + .cfg_pll_enb (cfg_pll_enb ), + .cfg_pll_fed_div (cfg_pll_fed_div ), + .cfg_dco_mode (cfg_dco_mode ), + .cfg_dc_trim (cfg_dc_trim ), + .pll_ref_clk (pll_ref_clk ), + .pll_clk_out (pll_clk_out ), .la_data_in (la_data_in[17:0] ), .uartm_rxd (uartm_rxd ), - .uartm_txd (uartm_txd ) + .uartm_txd (uartm_txd ), + + .dbg_clk_mon (dbg_clk_mon ) ); +// This rtl/gds picked from efabless caravel project +digital_pll u_pll( +`ifdef USE_POWER_PINS + .VPWR (vccd1 ), + .VGND (vssd1 ), +`endif + .resetb (wbd_pll_rst_n ), + .enable (cfg_pll_enb ), + .div (cfg_pll_fed_div ), + .dco (cfg_dco_mode ), + .ext_trim (cfg_dc_trim ), + .osc (pll_ref_clk ), + .clockp (pll_clk_out ) + ); + //------------------------------------------------------------------------------ @@ -1236,7 +1272,9 @@ .pulse1m_mclk (pulse1m_mclk ), - .pinmux_debug (pinmux_debug ) + .pinmux_debug (pinmux_debug ), + + .dbg_clk_mon (dbg_clk_mon )
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v index dfe3a99..22a25c0 100644 --- a/verilog/rtl/user_reg_map.v +++ b/verilog/rtl/user_reg_map.v
@@ -18,6 +18,7 @@ `define WBHOST_BANK_SEL 8'h04 // reg_1 - Bank Select `define WBHOST_CLK_CTRL1 8'h08 // reg_2 - Clock Control-1 `define WBHOST_CLK_CTRL2 8'h0C // reg_3 - Clock Control-2 +`define WBHOST_PLL_CTRL 8'h10 // reg_4 - PLL Control //-------------------------------------------------- // Pinmux Register
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index a5738c8..8256742 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -92,6 +92,7 @@ output logic usb_clk , // Global Reset control output logic wbd_int_rst_n , + output logic wbd_pll_rst_n , // Master Port input logic wbm_rst_i , // Regular Reset signal @@ -125,12 +126,20 @@ input logic wbs_err_i , // error output logic [31:0] cfg_clk_ctrl1 , - output logic [31:0] cfg_clk_ctrl2 , + // Digital PLL I/F + output logic cfg_pll_enb , // Enable PLL + output logic[4:0] cfg_pll_fed_div , // PLL feedback division ratio + output logic cfg_dco_mode , // Run PLL in DCO mode + output logic[25:0] cfg_dc_trim , // External trim for DCO mode + output logic pll_ref_clk , // Input oscillator to match + input logic [1:0] pll_clk_out , // Two 90 degree clock phases input logic [17:0] la_data_in , input logic uartm_rxd , - output logic uartm_txd + output logic uartm_txd , + + output logic dbg_clk_mon ); @@ -143,7 +152,7 @@ logic wbs_rst_n; logic reg_sel ; -logic [1:0] sw_addr ; +logic [2:0] sw_addr ; logic sw_rd_en ; logic sw_wr_en ; logic [31:0] reg_rdata ; @@ -158,12 +167,15 @@ logic sw_wr_en_3; logic [15:0] cfg_bank_sel; logic [31:0] reg_0; // Software_Reg_0 +logic [31:0] cfg_clk_ctrl2; -logic [3:0] cfg_wb_clk_ctrl; -logic [3:0] cfg_cpu_clk_ctrl; +logic [31:0] cfg_pll_ctrl; +logic [7:0] cfg_wb_clk_ctrl; +logic [7:0] cfg_cpu_clk_ctrl; logic [7:0] cfg_rtc_clk_ctrl; logic [7:0] cfg_usb_clk_ctrl; -logic [7:0] cfg_glb_ctrl; +logic [31:0] cfg_glb_ctrl; + // uart Master Port logic wbm_uart_cyc_i ; // strobe/request @@ -192,8 +204,39 @@ logic wb_ack_int ; // acknowlegement logic wb_err_int ; // error +logic [3:0] cfg_mon_sel ; +logic int_pll_clock ; +logic pll_clk_div16 ; +logic pll_clk_div16_buf ; +logic [2:0] cfg_ref_pll_div ; + +assign cfg_pll_enb = cfg_glb_ctrl[15]; +assign cfg_ref_pll_div = cfg_glb_ctrl[14:12]; +assign cfg_mon_sel = cfg_glb_ctrl[11:8]; + +assign cfg_dco_mode = cfg_pll_ctrl[31]; +assign cfg_pll_fed_div = cfg_pll_ctrl[30:26]; +assign cfg_dc_trim = cfg_pll_ctrl[25:0]; + +//assign int_pll_clock = pll_clk_out[0]; +ctech_clk_buf u_clkbuf_pll (.A (pll_clk_out[0]), . X(int_pll_clock)); +ctech_clk_buf u_clkbuf_pll_div (.A (pll_clk_div16), . X(pll_clk_div16_buf)); + + +// Debug clock monitor optin +assign dbg_clk_mon = (cfg_mon_sel == 4'b000) ? pll_clk_div16_buf: + (cfg_mon_sel == 4'b001) ? pll_ref_clk : + (cfg_mon_sel == 4'b010) ? wbs_clk_out : + (cfg_mon_sel == 4'b011) ? cpu_clk_int : + (cfg_mon_sel == 4'b100) ? rtc_clk_div : + (cfg_mon_sel == 4'b101) ? usb_clk_int : 1'b0; + + + +// Reset control ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n)); +ctech_buf u_buf_pll_rst (.A(cfg_glb_ctrl[1]),.X(wbd_pll_rst_n)); //-------------------------------------------------------------------------------- // Look like wishbone reset removed early than user Power up sequence @@ -336,7 +379,7 @@ // --------------------------------------------------------------------- assign reg_sel = wb_req & (wb_adr_i[19] == 1'b1); -assign sw_addr = wb_adr_i [3:2]; +assign sw_addr = wb_adr_i [4:2]; assign sw_rd_en = reg_sel & !wb_we_i; assign sw_wr_en = reg_sel & wb_we_i; @@ -344,6 +387,8 @@ assign sw_wr_en_1 = sw_wr_en && (sw_addr==1); assign sw_wr_en_2 = sw_wr_en && (sw_addr==2); assign sw_wr_en_3 = sw_wr_en && (sw_addr==3); +assign sw_wr_en_4 = sw_wr_en && (sw_addr==4); +assign sw_wr_en_5 = sw_wr_en && (sw_addr==5); always @ (posedge wbm_clk_i or negedge wbm_rst_n) begin : preg_out_Seq @@ -369,11 +414,11 @@ //------------------------------------- // Global + Clock Control // ------------------------------------- -assign cfg_glb_ctrl = reg_0[7:0]; -assign cfg_wb_clk_ctrl = reg_0[11:8]; -assign cfg_rtc_clk_ctrl = reg_0[19:12]; -assign cfg_cpu_clk_ctrl = reg_0[23:20]; -assign cfg_usb_clk_ctrl = reg_0[31:24]; +assign cfg_glb_ctrl = reg_0[31:0]; +assign cfg_wb_clk_ctrl = cfg_clk_ctrl2[7:0]; +assign cfg_rtc_clk_ctrl = cfg_clk_ctrl2[15:8]; +assign cfg_usb_clk_ctrl = cfg_clk_ctrl2[23:16]; +assign cfg_cpu_clk_ctrl = cfg_clk_ctrl2[31:24]; always @( *) @@ -381,10 +426,11 @@ reg_out [31:0] = 8'd0; case (sw_addr [1:0]) - 2'b00 : reg_out [31:0] = reg_0; - 2'b01 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]}; - 2'b10 : reg_out [31:0] = cfg_clk_ctrl1 [31:0]; - 2'b11 : reg_out [31:0] = cfg_clk_ctrl2 [31:0]; + 3'b000 : reg_out [31:0] = reg_0; + 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]}; + 3'b010 : reg_out [31:0] = cfg_clk_ctrl1 [31:0]; + 3'b011 : reg_out [31:0] = cfg_clk_ctrl2 [31:0]; + 3'b100 : reg_out [31:0] = cfg_pll_ctrl [31:0]; default : reg_out [31:0] = 'h0; endcase end @@ -431,6 +477,15 @@ //List of Outs .data_out (cfg_clk_ctrl2[31:0]) ); +generic_register #(32,0 ) u_pll_ctrl ( + .we ({32{sw_wr_en_4}} ), + .data_in (wb_dat_i[31:0] ), + .reset_n (wbm_rst_n ), + .clk (wbm_clk_i ), + + //List of Outs + .data_out (cfg_pll_ctrl[31:0]) + ); assign wb_stb_int = wb_req & !reg_sel; @@ -468,29 +523,51 @@ ); +// PLL Ref CLock + +clk_ctl #(2) u_pll_ref_clk ( + // Outputs + .clk_o (pll_ref_clk ), + // Inputs + .mclk (user_clock1 ), + .reset_n (wbm_rst_n ), + .clk_div_ratio (cfg_ref_pll_div ) + ); + +// PLL DIv16 to debug monitor purpose + +clk_ctl #(3) u_pllclk ( + // Outputs + .clk_o (pll_clk_div16 ), + // Inputs + .mclk (int_pll_clock ), + .reset_n (wbm_rst_n ), + .clk_div_ratio (4'hF ) + ); //---------------------------------- // Generate Internal WishBone Clock //---------------------------------- logic wb_clk_div; +logic wbs_ref_clk_int; logic wbs_ref_clk; -logic cfg_wb_clk_src_sel; -logic cfg_wb_clk_div; -logic [1:0] cfg_wb_clk_ratio; -assign cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[3]; -assign cfg_wb_clk_div = cfg_wb_clk_ctrl[2]; -assign cfg_wb_clk_ratio = cfg_wb_clk_ctrl[1:0]; +wire [1:0] cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[7:6]; +wire cfg_wb_clk_div = cfg_wb_clk_ctrl[5]; +wire [4:0] cfg_wb_clk_ratio = cfg_wb_clk_ctrl[4:0]; -//assign wbs_ref_clk = (cfg_wb_clk_src_sel) ? user_clock2 : user_clock1; -ctech_mux2x1 u_wbs_ref_sel (.A0 (user_clock1), .A1 (user_clock2), .S (cfg_wb_clk_src_sel), .X (wbs_ref_clk)); +assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 : + (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 : + int_pll_clock; + +ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk)); //assign wbs_clk_out = (cfg_wb_clk_div) ? wb_clk_div : wbm_clk_i; ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S (cfg_wb_clk_div), .X (wbs_clk_out)); -clk_ctl #(1) u_wbclk ( +clk_ctl #(4) u_wbclk ( // Outputs .clk_o (wb_clk_div ), // Inputs @@ -504,22 +581,26 @@ // Generate CORE Clock Generation //---------------------------------- wire cpu_clk_div; +wire cpu_ref_clk_int; wire cpu_ref_clk; wire cpu_clk_int; -wire cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[3]; -wire cfg_cpu_clk_div = cfg_cpu_clk_ctrl[2]; -wire [1:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[1:0]; +wire [1:0] cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[7:6]; +wire cfg_cpu_clk_div = cfg_cpu_clk_ctrl[5]; +wire [4:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[4:0]; -//assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : user_clock1; +assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 : + (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 : + int_pll_clock; + +ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk)); + //assign cpu_clk_int = (cfg_cpu_clk_div) ? cpu_clk_div : cpu_ref_clk; - -ctech_mux2x1 u_cpu_ref_sel (.A0 (user_clock1), .A1 (user_clock2), .S (cfg_cpu_clk_src_sel), .X (cpu_ref_clk)); ctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S (cfg_cpu_clk_div), .X (cpu_clk_int)); ctech_clk_buf u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk)); -clk_ctl #(1) u_cpuclk ( +clk_ctl #(4) u_cpuclk ( // Outputs .clk_o (cpu_clk_div ), // Inputs @@ -551,20 +632,25 @@ // Generate USB Clock Generation //---------------------------------- wire usb_clk_div; +wire usb_ref_clk_int; wire usb_ref_clk; wire usb_clk_int; -wire cfg_usb_clk_div = cfg_usb_clk_ctrl[7]; -wire [6:0] cfg_usb_clk_ratio = cfg_usb_clk_ctrl[6:0]; +wire [1:0] cfg_usb_clk_sel_sel = cfg_usb_clk_ctrl[7:6]; +wire cfg_usb_clk_div = cfg_usb_clk_ctrl[5]; +wire [4:0] cfg_usb_clk_ratio = cfg_usb_clk_ctrl[4:0]; -assign usb_ref_clk = user_clock2 ; +assign usb_ref_clk_int = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 : + (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 : + int_pll_clock; +ctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk)); //assign usb_clk_int = (cfg_usb_clk_div) ? usb_clk_div : usb_ref_clk; ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S (cfg_usb_clk_div), .X (usb_clk_int)); ctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk)); -clk_ctl #(6) u_usbclk ( +clk_ctl #(4) u_usbclk ( // Outputs .clk_o (usb_clk_div ), // Inputs