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+# Timing scripts
+
+A set of scripts for rcx and sta for caravel top level
+
+## Dependencies
+- Docker
+
+## Prerequisites
+
+A set of exports are needed:
+```bash
+export CARAVEL_ROOT=${HOME}/caravel/
+export MCW_ROOT=${HOME}/caravel_mgmt_soc_litex/
+export CUP_ROOT=${HOME}/caravel_user_project/
+export TIMING_ROOT=${HOME}/timing-scripts/
+export PDK_ROOT=${HOME}/pdk/
+export PDK=sky130A
+export OPENLANE_IMAGE_NAME=efabless/openlane:4476a58407d670d251aa0be6a55e5391bb181c4e-amd64
+```
+
+python modules:
+- `pyverilog`
+- `click`
+
+## Usage
+
+### caravel_user_project
+
+1. After exporting the prerequisites, run:
+
+ ```
+ make -f timing.mk list-rcx
+ ```
+ You should get `rcx-user_project_wrapper` amongst others such as:
+
+ ```
+ rcx-buff_flash_clkrst
+ rcx-caravel
+ rcx-caravel_clocking
+ rcx-constant_block
+ rcx-digital_pll
+ rcx-gpio_control_block
+ rcx-gpio_defaults_block
+ rcx-gpio_logic_high
+ rcx-gpio_signal_buffering
+ rcx-gpio_signal_buffering_alt
+ rcx-housekeeping
+ rcx-mgmt_protect
+ rcx-mprj2_logic_high
+ rcx-mprj_logic_high
+ rcx-spare_logic_block
+ rcx-RAM256
+ rcx-mgmt_core_wrapper
+ rcx-user_proj_example
+ rcx-user_project_wrapper
+ ```
+
+2. extract multicorner spefs for `user_project_wrapper` and any other blocks inside:
+
+ ```
+ make -f timing.mk rcx-user_project_wrapper
+ make -f timing.mk rcx-user_proj_example
+ ```
+3. generate spef mapping file for caravel_user_project:
+
+ ```
+ python3 ./scripts/generate_spef_mapping -i ${CUP_ROOT}/verilog/gl/user_project_wrapper.v -o ${CUP_ROOT}/env/spef-mapping.tcl --project-root '$::env(CUP_ROOT)' --pdk-root ${PDK_ROOT} --pdk ${PDK}
+ ```
+
+4. run sta:
+
+ ```
+ make -f timing.mk caravel-timing-typ
+ make -f timing.mk caravel-timing-slow
+ make -f timing.mk caravel-timing-fast
+ ```
+
+## Limitations
+
+- Makefile
+- Makefile
+- Assumes a fixed folder structure for the exported directories
+- Probably a lot of corner cases that weren't considered
