ycr_intf power strip width correction
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 6e20ebb..0bbe026 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -2,17 +2,17 @@ u_uart_i2c_usb_spi 2250 1350 N u_pinmux 2250 2250 N -u_riscv_top.i_core_top_0 75 1400 N -u_riscv_top.i_core_top_1 1200 1400 FN -u_riscv_top.i_core_top_2 75 2475 N -u_riscv_top.i_core_top_3 1200 2475 FN -u_riscv_top.u_connect 735 1400 N -u_riscv_top.u_intf 950 650 N -u_dcache_2kb 150 130 N -u_icache_2kb 950 130 N -u_tsram0_2kb 150 750 N +u_riscv_top.i_core_top_0 75 1400 N +u_riscv_top.i_core_top_1 1200 1400 FN +u_riscv_top.i_core_top_2 75 2475 N +u_riscv_top.i_core_top_3 1200 2475 FN +u_riscv_top.u_connect 735 1400 N +u_riscv_top.u_intf 950 650 N +u_dcache_2kb 150 130 N +u_icache_2kb 950 130 N +u_tsram0_2kb 150 750 N -u_intercon 1850 650 N -u_wb_host 1750 100 N -u_pll 2300 68 N +u_intercon 1850 650 N +u_wb_host 1750 100 N +u_pll 2300 68 N
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index 1092a50..4e0c943 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -89,3 +89,8 @@ #Need to cross-check why global timing opimization creating setup vio with hugh hold fix set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" +#PDN +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 4a47892..f1f0d68 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema arduino_timer_intr user_mcore_test1 user_mcore_test2 +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema arduino_timer_intr user_mcore_test1 user_mcore_test2 arduino_gpio_intr arduino_i2c_scaner all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/user_risc_boot/user_uart.c b/verilog/dv/user_risc_boot/user_uart.c deleted file mode 100644 index 04512bc..0000000 --- a/verilog/dv/user_risc_boot/user_uart.c +++ /dev/null
@@ -1,60 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021, Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -// ////////////////////////////////////////////////////////////////////////// - -#define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long - -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C) - -#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000) -#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004) -#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008) -#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C) -#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010) -#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014) -#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018) -#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C) -#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020) - -int main() -{ - - while(1) { - // Check UART RX fifo has data, if available loop back the data - if(reg_mprj_uart_reg8 != 0) { - reg_mprj_uart_reg5 = reg_mprj_uart_reg6; - } - } - - return 0; -}
diff --git a/verilog/dv/user_uart1/user_uart.c b/verilog/dv/user_uart1/user_uart.c deleted file mode 100644 index ac8c50f..0000000 --- a/verilog/dv/user_uart1/user_uart.c +++ /dev/null
@@ -1,43 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021, Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -// ////////////////////////////////////////////////////////////////////////// -#define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long - - -#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010100) -#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010104) -#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010108) -#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001010C) -#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010110) -#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010114) -#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010118) -#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001011C) -#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010120) - -int main() -{ - - while(1) { - // Check UART RX fifo has data, if available loop back the data - if(reg_mprj_uart_reg8 != 0) { - reg_mprj_uart_reg5 = reg_mprj_uart_reg6; - } - } - - return 0; -}
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh index 3436cae..7664338 100644 --- a/verilog/rtl/user_params.svh +++ b/verilog/rtl/user_params.svh
@@ -8,7 +8,7 @@ // Software Reg-2: Poject Revison 5.1 = 0005200 parameter CHIP_REVISION = 32'h0005_3000; -parameter SKEW_RESET_VAL = 32'b0000_1000_1000_0111_1001_1000_1001_1000; +parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_1000; parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1011_0000;