xor clean up
diff --git a/Makefile b/Makefile
index ff9f8b3..53869ec 100644
--- a/Makefile
+++ b/Makefile
@@ -204,12 +204,14 @@
gzip -f gds/*
gzip -f spef/*
gzip -f spi/lvs/*
+ gzip -f verilog/gl/*
unzip:
gzip -d lef/*
gzip -d gds/*
gzip -d spef/*
gzip -d spi/lvs/*
+ gzip -d verilog/gl/*
.PHONY: help
help:
diff --git a/README.md b/README.md
index 72f385c..f08ff3f 100644
--- a/README.md
+++ b/README.md
@@ -194,7 +194,7 @@
<tr align="center"> <td> SFlash </td> <td> sflash_io1 </td> <td> </td> <td> digital_io[30] </td></tr>
<tr align="center"> <td> SFlash </td> <td> sflash_io2 </td> <td> </td> <td> digital_io[31] </td></tr>
<tr align="center"> <td> SFlash </td> <td> sflash_io3 </td> <td> </td> <td> digital_io[32] </td></tr>
- <tr align="center"> <td> SSRAM </td> <td> Reserved </td> <td> </td> <td> digital_io[33] </td></tr>
+ <tr align="center"> <td> SSRAM </td> <td> dbg_clk_mon </td> <td> </td> <td> digital_io[33] </td></tr>
<tr align="center"> <td> SSRAM </td> <td> uartm rxd </td> <td> </td> <td> digital_io[34] </td></tr>
<tr align="center"> <td> SSRAM </td> <td> uartm txd </td> <td> </td> <td> digital_io[35] </td></tr>
<tr align="center"> <td> usb1.1 </td> <td> usb_dp </td> <td> </td> <td> digital_io[36] </td></tr>
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 3cd9116..a75fa06 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/dinesha/workarea/opencore/git/riscduino_qcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,2h17m48s0ms,0h4m40s0ms,-2.0,-1,-1,-1,571.57,15,0,0,0,0,0,0,-1,0,0,-1,-1,1528755,14508,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.38,8.83,1.75,2.51,0.0,409,4330,409,4330,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/home/dinesha/workarea/opencore/git/riscduino_qcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h32m18s0ms,0h4m35s0ms,-2.0,-1,-1,-1,590.5,15,0,0,0,0,0,0,-1,0,0,-1,-1,1528755,14508,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.38,8.83,1.75,2.51,0.0,409,4330,409,4330,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
