2nd uart core and sspi cs# increase to 4
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index c26bbe4..c07e16e 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -34,6 +34,9 @@
//// Revision : ////
//// 0.1 - 16th Feb 2021, Dinesh A ////
//// initial version ////
+//// 0.2 - 6 April 2021, Dinesh A ////
+//// 1. SSPI CS# increased from 1 to 4 ////
+// 2. UART I/F increase from 1 to 2 ////
//////////////////////////////////////////////////////////////////////
module pinmux (
@@ -55,7 +58,7 @@
output logic cpu_intf_rst_n ,
output logic qspim_rst_n ,
output logic sspim_rst_n ,
- output logic uart_rst_n ,
+ output logic [1:0] uart_rst_n ,
output logic i2cm_rst_n ,
output logic usb_rst_n ,
@@ -106,8 +109,8 @@
output logic usb_dn_i,
// UART I/F
- input logic uart_txd,
- output logic uart_rxd,
+ input logic [1:0] uart_txd,
+ output logic [1:0] uart_rxd,
// I2CM I/F
input logic i2cm_clk_o,
@@ -119,7 +122,7 @@
// SPI MASTER
input logic spim_sck,
- input logic spim_ss,
+ input logic [3:0] spim_ssn,
input logic spim_miso,
output logic spim_mosi,
@@ -542,9 +545,9 @@
assign cfg_pwm_enb = cfg_multi_func_sel[5:0];
wire [1:0] cfg_int_enb = cfg_multi_func_sel[7:6];
-wire cfg_uart_enb = cfg_multi_func_sel[8];
-wire cfg_i2cm_enb = cfg_multi_func_sel[9];
-wire cfg_spim_enb = cfg_multi_func_sel[10];
+wire [1:0] cfg_uart_enb = cfg_multi_func_sel[9:8];
+wire [3:0] cfg_spim_enb = cfg_multi_func_sel[13:10];
+wire cfg_i2cm_enb = cfg_multi_func_sel[14];
wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0];
wire [7:0] cfg_port_b_dir_sel = cfg_gpio_dir_sel[15:8];
@@ -567,23 +570,24 @@
//Pin-1 PC6/RESET* digital_io[0]
port_c_in[6] = digital_io_in[0];
- //Pin-2 PD0/RXD digital_io[1]
+ //Pin-2 PD0/RXD[0] digital_io[1]
port_d_in[0] = digital_io_in[1];
- if(cfg_uart_enb) uart_rxd = digital_io_in[1];
+ if(cfg_uart_enb[0]) uart_rxd[0] = digital_io_in[1];
- //Pin-3 PD1/TXD digital_io[2]
+ //Pin-3 PD1/TXD[0] digital_io[2]
port_d_in[1] = digital_io_in[2];
- //Pin-4 PD2/INT0 digital_io[3]
+ //Pin-4 PD2/RXD[1]/INT0 digital_io[3]
port_d_in[2] = digital_io_in[3];
- if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3];
+ if(cfg_uart_enb[1]) uart_rxd[1] = digital_io_in[3];
+ else if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3];
//Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4]
port_d_in[3] = digital_io_in[4];
if(cfg_int_enb[1]) ext_intr_in[1] = digital_io_in[4];
- //Pin-6 PD4 digital_io[5]
+ //Pin-6 PD4/TXD[1] digital_io[5]
port_d_in[4] = digital_io_in[5];
//Pin-9 PB6/XTAL1/TOSC1 digital_io[6]
@@ -612,7 +616,7 @@
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
port_b_in[3] = digital_io_in[14];
- if(cfg_spim_enb) spim_mosi = digital_io_in[14];
+ if(cfg_spim_enb[0]) spim_mosi = digital_io_in[14];
//Pin-18 PB4/MISO digital_io[15]
port_b_in[4] = digital_io_in[15];
@@ -658,23 +662,24 @@
//Pin-1 PC6/RESET* digital_io[0]
if(cfg_port_c_dir_sel[6]) digital_io_out[0] = port_c_out[6];
- //Pin-2 PD0/RXD digital_io[1]
+ //Pin-2 PD0/RXD[0] digital_io[1]
if(cfg_port_d_dir_sel[0]) digital_io_out[1] = port_d_out[0];
- //Pin-3 PD1/TXD digital_io[2]
- if (cfg_uart_enb) digital_io_out[2] = uart_txd;
+ //Pin-3 PD1/TXD[0] digital_io[2]
+ if (cfg_uart_enb[0]) digital_io_out[2] = uart_txd[0];
else if(cfg_port_d_dir_sel[1]) digital_io_out[2] = port_d_out[1];
- //Pin-4 PD2/INT0 digital_io[3]
+ //Pin-4 PD2/RXD[1]/INT0 digital_io[3]
if(cfg_port_d_dir_sel[2]) digital_io_out[3] = port_d_out[2];
//Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4]
if(cfg_pwm_enb[0]) digital_io_out[4] = pwm_wfm[0];
else if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3];
- //Pin-6 PD4 digital_io[5]
- if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4];
+ //Pin-6 PD4/TXD[1] digital_io[5]
+ if (cfg_uart_enb[1]) digital_io_out[5] = uart_txd[1];
+ else if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4];
//Pin-9 PB6/XTAL1/TOSC1 digital_io[6]
if(cfg_port_b_dir_sel[6]) digital_io_out[6] = port_b_out[6];
@@ -683,12 +688,14 @@
// Pin-10 PB7/XTAL2/TOSC2 digital_io[7]
if(cfg_port_b_dir_sel[7]) digital_io_out[7] = port_b_out[7];
- //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8]
+ //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
if(cfg_pwm_enb[1]) digital_io_out[8] = pwm_wfm[1];
+ else if(cfg_spim_enb[3]) digital_io_out[8] = spim_ssn[3];
else if(cfg_port_d_dir_sel[5]) digital_io_out[8] = port_d_out[5];
- //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
+ //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
if(cfg_pwm_enb[2]) digital_io_out[9] = pwm_wfm[2];
+ else if(cfg_spim_enb[2]) digital_io_out[9] = spim_ssn[2];
else if(cfg_port_d_dir_sel[6]) digital_io_out[9] = port_d_out[6];
@@ -698,13 +705,14 @@
//Pin-14 PB0/CLKO/ICP1 digital_io[11]
if(cfg_port_b_dir_sel[0]) digital_io_out[11] = port_b_out[0];
- //Pin-15 PB1/OC1A(PWM3) digital_io[12]
+ //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12]
if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3];
+ else if(cfg_spim_enb[1]) digital_io_out[12] = spim_ssn[1];
else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1];
- //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13]
+ //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
if(cfg_pwm_enb[4]) digital_io_out[13] = pwm_wfm[4];
- else if(cfg_spim_enb) digital_io_out[13] = spim_ss;
+ else if(cfg_spim_enb[0]) digital_io_out[13] = spim_ssn[0];
else if(cfg_port_b_dir_sel[2]) digital_io_out[13] = port_b_out[2];
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
@@ -712,11 +720,11 @@
else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3];
//Pin-18 PB4/MISO digital_io[15]
- if(cfg_spim_enb) digital_io_out[15] = spim_miso;
+ if(cfg_spim_enb[0]) digital_io_out[15] = spim_miso;
else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4];
//Pin-19 PB5/SCK digital_io[16]
- if(cfg_spim_enb) digital_io_out[16] = spim_sck;
+ if(cfg_spim_enb[0]) digital_io_out[16] = spim_sck;
else if(cfg_port_b_dir_sel[5]) digital_io_out[16] = port_b_out[5];
//Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
@@ -768,16 +776,17 @@
//Pin-1 PC6/RESET* digital_io[0]
if(cfg_port_c_dir_sel[6]) digital_io_oen[0] = 1'b0;
- //Pin-2 PD0/RXD digital_io[1]
- if (cfg_uart_enb) digital_io_oen[1] = 1'b1;
+ //Pin-2 PD0/RXD[0] digital_io[1]
+ if (cfg_uart_enb[0]) digital_io_oen[1] = 1'b1;
else if(cfg_port_d_dir_sel[0]) digital_io_oen[1] = 1'b0;
- //Pin-3 PD1/TXD digital_io[2]
- if (cfg_uart_enb) digital_io_oen[2] = 1'b0;
+ //Pin-3 PD1/TXD[0] digital_io[2]
+ if (cfg_uart_enb[0]) digital_io_oen[2] = 1'b0;
else if(cfg_port_d_dir_sel[1]) digital_io_oen[2] = 1'b0;
- //Pin-4 PD2/INT0 digital_io[3]
- if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1;
+ //Pin-4 PD2/RXD[1]/INT0 digital_io[3]
+ if (cfg_uart_enb[1]) digital_io_oen[3] = 1'b1;
+ else if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1;
else if(cfg_port_d_dir_sel[2]) digital_io_oen[3] = 1'b0;
//Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4]
@@ -785,8 +794,9 @@
else if(cfg_int_enb[1]) digital_io_oen[4] = 1'b1;
else if(cfg_port_d_dir_sel[3]) digital_io_oen[4] = 1'b0;
- //Pin-6 PD4 digital_io[5]
- if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0;
+ //Pin-6 PD4/TXD[1] digital_io[5]
+ if (cfg_uart_enb[1]) digital_io_oen[5] = 1'b0;
+ else if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0;
//Pin-9 PB6/XTAL1/TOSC1 digital_io[6]
if(cfg_port_b_dir_sel[6]) digital_io_oen[6] = 1'b0;
@@ -794,12 +804,14 @@
// Pin-10 PB7/XTAL2/TOSC2 digital_io[7]
if(cfg_port_b_dir_sel[7]) digital_io_oen[7] = 1'b0;
- //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8]
+ //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
if(cfg_pwm_enb[1]) digital_io_oen[8] = 1'b0;
+ else if(cfg_spim_enb[3]) digital_io_oen[8] = 1'b0;
else if(cfg_port_d_dir_sel[5]) digital_io_oen[8] = 1'b0;
- //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
+ //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
if(cfg_pwm_enb[2]) digital_io_oen[9] = 1'b0;
+ else if(cfg_spim_enb[2]) digital_io_oen[9] = 1'b0;
else if(cfg_port_d_dir_sel[6]) digital_io_oen[9] = 1'b0;
//Pin-13 PD7/A1N1 digital_io[10]/analog_io[3]
@@ -808,26 +820,27 @@
//Pin-14 PB0/CLKO/ICP1 digital_io[11]
if(cfg_port_b_dir_sel[0]) digital_io_oen[11] = 1'b0;
- //Pin-15 PB1/OC1A(PWM3) digital_io[12]
+ //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12]
if(cfg_pwm_enb[3]) digital_io_oen[12] = 1'b0;
+ else if(cfg_spim_enb[1]) digital_io_oen[12] = 1'b0;
else if(cfg_port_b_dir_sel[1]) digital_io_oen[12] = 1'b0;
- //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13]
+ //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
if(cfg_pwm_enb[4]) digital_io_oen[13] = 1'b0;
- else if(cfg_spim_enb) digital_io_oen[13] = 1'b0;
+ else if(cfg_spim_enb[0]) digital_io_oen[13] = 1'b0;
else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0;
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
- if(cfg_spim_enb) digital_io_oen[14] = 1'b1;
+ if(cfg_spim_enb[0]) digital_io_oen[14] = 1'b1;
else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0;
else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0;
- //Pin-18 PB4/MISO digital_io[15]
- if(cfg_spim_enb) digital_io_oen[15] = 1'b0;
+ //Pin-18 PB4/MISO digital_io[15]
+ if(cfg_spim_enb[0]) digital_io_oen[15] = 1'b0;
else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0;
//Pin-19 PB5/SCK digital_io[16]
- if(cfg_spim_enb) digital_io_oen[16] = 1'b0;
+ if(cfg_spim_enb[0]) digital_io_oen[16] = 1'b0;
else if(cfg_port_b_dir_sel[5]) digital_io_oen[16] = 1'b0;
//Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 131207f..7966d8b 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -47,7 +47,7 @@
output logic cpu_intf_rst_n ,
output logic qspim_rst_n ,
output logic sspim_rst_n ,
- output logic uart_rst_n ,
+ output logic [1:0] uart_rst_n ,
output logic i2cm_rst_n ,
output logic usb_rst_n ,
@@ -281,9 +281,10 @@
ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
-ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n));
+ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0]));
ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
+ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1]));
ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
@@ -715,7 +716,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h0104_2022) u_reg_23 (
+gen_32b_reg #(32'h0604_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -728,9 +729,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 4.1 = 0004100
+// Software Reg-3: Poject Revison 4.1 = 0004200
// ----------------------------------------
-gen_32b_reg #(32'h0004_1000) u_reg_24 (
+gen_32b_reg #(32'h0004_2000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
index 8a632a0..2a28d2e 100755
--- a/verilog/rtl/sspim/src/sspim_top.sv
+++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -44,6 +44,8 @@
//// i.e byte transfer [7:0],[15:8] ...[31:24] ////
//// Note: As per SPI transfer still first bit sent ////
//// out is big endian, i.e bit[7],[6] ..[0] ////
+//// 0.3 - April 6, 2022, Dinesh A ////
+//// Four chip select are driven out ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -98,7 +100,7 @@
output logic sck , // clock out
output logic so , // serial data out
input logic si , // serial data in
- output logic ssn // cs_n
+ output logic [3:0] ssn // Chip Select
);
@@ -123,9 +125,7 @@
logic [31:0] cfg_datain ; // data for transfer
logic [31:0] cfg_dataout ; // data for received
logic hware_op_done ; // operation done
-logic [3:0] cs_n ; // cs_n
-assign ssn = cs_n[0]; // Only 1 chip select supported in riscdunio
sspim_if u_spi_if
(
@@ -147,7 +147,7 @@
. sck (sck ),
. so (so ),
. si (si ),
- . cs_n (cs_n )
+ . cs_n (ssn )
);
diff --git a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
index 028f1d7..d94013b 100644
--- a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+++ b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
@@ -35,7 +35,8 @@
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : ////
-//// ////
+//// 0.2 - 7 April 2022, Dinesh-A ////
+//// 2nd Uart Integrated ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -75,17 +76,17 @@
input logic wbd_clk_int,
output logic wbd_clk_uart,
- input logic uart_rstn , // async reset
- input logic i2c_rstn , // async reset
- input logic usb_rstn , // async reset
- input logic spi_rstn , // async reset
- input logic app_clk ,
- input logic usb_clk , // 48Mhz usb clock
+ input logic [1:0] uart_rstn , // async reset
+ input logic i2c_rstn , // async reset
+ input logic usb_rstn , // async reset
+ input logic spi_rstn , // async reset
+ input logic app_clk ,
+ input logic usb_clk , // 48Mhz usb clock
// Reg Bus Interface Signal
input logic reg_cs,
input logic reg_wr,
- input logic [7:0] reg_addr,
+ input logic [8:0] reg_addr,
input logic [31:0] reg_wdata,
input logic [3:0] reg_be,
@@ -106,8 +107,8 @@
output logic i2cm_intr_o ,
// UART I/F
- input logic uart_rxd ,
- output logic uart_txd ,
+ input logic [1:0] uart_rxd ,
+ output logic [1:0] uart_txd ,
// USB 1.1 HOST I/F
input logic usb_in_dp ,
@@ -123,7 +124,7 @@
output logic sspim_sck, // clock out
output logic sspim_so, // serial data out
input logic sspim_si, // serial data in
- output logic sspim_ssn // cs_n
+ output logic [3:0] sspim_ssn // cs_n
);
@@ -139,57 +140,84 @@
.clk_out (wbd_clk_uart )
);
-`define SEL_UART 2'b00
-`define SEL_I2C 2'b01
-`define SEL_USB 2'b10
-`define SEL_SPI 2'b11
+`define SEL_UART0 3'b000
+`define SEL_I2C 3'b001
+`define SEL_USB 3'b010
+`define SEL_SPI 3'b011
+`define SEL_UART1 3'b100
//----------------------------------------
// Register Response Path Mux
// --------------------------------------
-logic [7:0] reg_uart_rdata;
+logic [7:0] reg_uart0_rdata;
+logic [7:0] reg_uart1_rdata;
logic [7:0] reg_i2c_rdata;
logic [31:0] reg_usb_rdata;
logic [31:0] reg_spim_rdata;
-logic reg_uart_ack;
+logic reg_uart0_ack;
+logic reg_uart1_ack;
logic reg_i2c_ack;
logic reg_usb_ack;
logic reg_spim_ack;
-assign reg_rdata = (reg_addr[7:6] == `SEL_UART) ? {24'h0,reg_uart_rdata} :
- (reg_addr[7:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} :
- (reg_addr[7:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata;
-assign reg_ack = (reg_addr[7:6] == `SEL_UART) ? reg_uart_ack :
- (reg_addr[7:6] == `SEL_I2C) ? reg_i2c_ack :
- (reg_addr[7:6] == `SEL_USB) ? reg_usb_ack : reg_spim_ack;
+assign reg_rdata = (reg_addr[8:6] == `SEL_UART0) ? {24'h0,reg_uart0_rdata} :
+ (reg_addr[8:6] == `SEL_UART1) ? {24'h0,reg_uart1_rdata} :
+ (reg_addr[8:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} :
+ (reg_addr[8:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata;
+assign reg_ack = (reg_addr[8:6] == `SEL_UART0) ? reg_uart0_ack :
+ (reg_addr[8:6] == `SEL_UART1) ? reg_uart1_ack :
+ (reg_addr[8:6] == `SEL_I2C) ? reg_i2c_ack :
+ (reg_addr[8:6] == `SEL_USB) ? reg_usb_ack : reg_spim_ack;
-wire reg_uart_cs = (reg_addr[7:6] == `SEL_UART) ? reg_cs : 1'b0;
-wire reg_i2cm_cs = (reg_addr[7:6] == `SEL_I2C) ? reg_cs : 1'b0;
-wire reg_usb_cs = (reg_addr[7:6] == `SEL_USB) ? reg_cs : 1'b0;
-wire reg_spim_cs = (reg_addr[7:6] == `SEL_SPI) ? reg_cs : 1'b0;
+wire reg_uart0_cs = (reg_addr[8:6] == `SEL_UART0) ? reg_cs : 1'b0;
+wire reg_uart1_cs = (reg_addr[8:6] == `SEL_UART1) ? reg_cs : 1'b0;
+wire reg_i2cm_cs = (reg_addr[8:6] == `SEL_I2C) ? reg_cs : 1'b0;
+wire reg_usb_cs = (reg_addr[8:6] == `SEL_USB) ? reg_cs : 1'b0;
+wire reg_spim_cs = (reg_addr[8:6] == `SEL_SPI) ? reg_cs : 1'b0;
-uart_core u_uart_core (
+uart_core u_uart0_core (
- .arst_n (uart_rstn ), // async reset
+ .arst_n (uart_rstn[0] ), // async reset
.app_clk (app_clk ),
// Reg Bus Interface Signal
- .reg_cs (reg_uart_cs ),
+ .reg_cs (reg_uart0_cs ),
.reg_wr (reg_wr ),
.reg_addr (reg_addr[5:2] ),
.reg_wdata (reg_wdata[7:0] ),
.reg_be (reg_be[0] ),
// Outputs
- .reg_rdata (reg_uart_rdata[7:0]),
- .reg_ack (reg_uart_ack ),
+ .reg_rdata (reg_uart0_rdata[7:0]),
+ .reg_ack (reg_uart0_ack ),
// Pad Control
- .rxd (uart_rxd ),
- .txd (uart_txd )
+ .rxd (uart_rxd[0] ),
+ .txd (uart_txd[0] )
+ );
+
+uart_core u_uart1_core (
+
+ .arst_n (uart_rstn[1] ), // async reset
+ .app_clk (app_clk ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_uart1_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[5:2] ),
+ .reg_wdata (reg_wdata[7:0] ),
+ .reg_be (reg_be[0] ),
+
+ // Outputs
+ .reg_rdata (reg_uart1_rdata[7:0]),
+ .reg_ack (reg_uart1_ack ),
+
+ // Pad Control
+ .rxd (uart_rxd[1] ),
+ .txd (uart_txd[1] )
);
i2cm_top u_i2cm (
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0c341d6..6e42c0d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -198,6 +198,9 @@
//// 4. caravel wb addressing issue restrict to 0x300FFFFF////
//// 4.1 April 1 2022, Dinesh A ////
//// 1. sram lanuch phase control added inside risc core ////
+//// 4.2 April 6 2022, Dinesh A ////
+//// 1. SSPI CS# increased from 1 to 4 ////
+//// 2. uart port increase to two ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -410,7 +413,7 @@
// Global Register Wishbone Interface
//---------------------------------------------------------------------
wire wbd_uart_stb_o ; // strobe/request
-wire [7:0] wbd_uart_adr_o ; // address
+wire [8:0] wbd_uart_adr_o ; // address
wire wbd_uart_we_o ; // write
wire [31:0] wbd_uart_dat_o ; // data output
wire [3:0] wbd_uart_sel_o ; // byte enable
@@ -427,7 +430,7 @@
wire [1:0] cpu_core_rst_n ;
wire qspim_rst_n ;
wire sspim_rst_n ;
-wire uart_rst_n ; // uart reset
+wire [1:0] uart_rst_n ; // uart reset
wire i2c_rst_n ; // i2c reset
wire usb_rst_n ; // i2c reset
wire bist_rst_n ; // i2c reset
@@ -509,8 +512,8 @@
wire usb_dn_i ;
// UART I/F
-wire uart_txd ;
-wire uart_rxd ;
+wire [1:0] uart_txd ;
+wire [1:0] uart_rxd ;
// I2CM I/F
wire i2cm_clk_o ;
@@ -568,7 +571,7 @@
wire sspim_sck ; // clock out
wire sspim_so ; // serial data out
wire sspim_si ; // serial data in
-wire sspim_ssn ; // cs_n
+wire [3:0] sspim_ssn ; // cs_n
wire usb_intr_o ;
@@ -1099,7 +1102,7 @@
// Reg Bus Interface Signal
.reg_cs (wbd_uart_stb_o ),
.reg_wr (wbd_uart_we_o ),
- .reg_addr (wbd_uart_adr_o[7:0] ),
+ .reg_addr (wbd_uart_adr_o[8:0] ),
.reg_wdata (wbd_uart_dat_o ),
.reg_be (wbd_uart_sel_o ),
@@ -1217,7 +1220,7 @@
// SPI MASTER
.spim_sck (sspim_sck ),
- .spim_ss (sspim_ssn ),
+ .spim_ssn (sspim_ssn ),
.spim_miso (sspim_so ),
.spim_mosi (sspim_si ),
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 1926c76..dfe3a99 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -3,10 +3,11 @@
// So, using wb_host bank select we have changing MSB address [31:16] = 0x1000
//
`define ADDR_SPACE_QSPI 32'h3000_0000
-`define ADDR_SPACE_UART 32'h3001_0000
+`define ADDR_SPACE_UART0 32'h3001_0000
`define ADDR_SPACE_I2CM 32'h3001_0040
`define ADDR_SPACE_USB 32'h3001_0080
`define ADDR_SPACE_SSPI 32'h3001_00C0
+`define ADDR_SPACE_UART1 32'h3001_0100
`define ADDR_SPACE_PINMUX 32'h3002_0000
`define ADDR_SPACE_WBHOST 32'h3008_0000
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index fd68e08..8ab9487 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -190,7 +190,7 @@
input logic s1_wbd_ack_i,
// input logic s1_wbd_err_i, - unused
output logic [31:0] s1_wbd_dat_o,
- output logic [7:0] s1_wbd_adr_o,
+ output logic [8:0] s1_wbd_adr_o, // Uart
output logic [3:0] s1_wbd_sel_o,
output logic s1_wbd_we_o,
output logic s1_wbd_cyc_o,
@@ -299,6 +299,7 @@
// 0x1001_0080 to 0x1001_00BF - USB
// 0x1001_00C0 to 0x1001_00FF - SSPIM
// 0x1002_0000 to 0x1002_00FF - PINMUX
+// 0x1001_0100 to 0x1001_013F - UART1
// 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block)
// ---------------------------------------------------------------------------
//
@@ -312,10 +313,11 @@
// RISC Data Memory Map
// 0x0000_0000 to 0x0FFF_FFFF - QSPIM MEMORY
// 0x1000_0000 to 0x1000_00FF - QSPIM REG
-// 0x1001_0000 to 0x1001_003F - UART
+// 0x1001_0000 to 0x1001_003F - UART0
// 0x1001_0040 to 0x1001_007F - I2
// 0x1001_0080 to 0x1001_00BF - USB
// 0x1001_00C0 to 0x1001_00FF - SSPIM
+// 0x1001_0100 to 0x1001_013F - UART1
// 0x1002_0000 to 0x1002_00FF - PINMUX
//-----------------------------
//
@@ -660,7 +662,7 @@
assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ;
assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ;
- assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[7:0] ;
+ assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[8:0] ;
assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ;
assign s1_wbd_we_o = s1_wb_wr.wbd_we ;
assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;
