spi isp option added
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 2f1ba44..e36556c 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -42,6 +42,9 @@
//// GPIO, So we have moved the Auto generated SPI CS ////
//// different config bit. I2C config position moved from////
//// bit[14] to bit [15] ////
+//// 0.4 - 20 July 2022, Dinesh A ////
+//// On Power On, If RESET* = 0, then system will enter ////
+//// in to SPIS slave mode to support boot ////
//////////////////////////////////////////////////////////////////////
module pinmux (
@@ -130,6 +133,12 @@
input logic [3:0] spim_ssn,
input logic spim_miso,
output logic spim_mosi,
+
+ // SPI SLAVE
+ output logic spis_sck,
+ output logic spis_ssn,
+ input logic spis_miso,
+ output logic spis_mosi,
// UART MASTER I/F
output logic uartm_rxd ,
@@ -563,6 +572,14 @@
wire [7:0] cfg_port_d_dir_sel = cfg_gpio_dir_sel[31:24];
+// This logic to create spi slave interface
+logic pin_resetn,spis_boot;
+
+// On Reset internal SPI Master is disabled, If pin_reset = 0, then we are in
+// SPIS Boot Mode
+assign spis_boot = (cfg_spim_enb ) ? 1'b0: !pin_resetn;
+assign spis_ssn = (spis_boot ) ? pin_resetn : 1'b1;
+
// datain selection
always_comb begin
port_a_in = 'h0;
@@ -577,6 +594,7 @@
//Pin-1 PC6/RESET* digital_io[0]
port_c_in[6] = digital_io_in[0];
+ pin_resetn = digital_io_in[0];
//Pin-2 PD0/RXD[0] digital_io[1]
port_d_in[0] = digital_io_in[1];
@@ -624,13 +642,15 @@
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
port_b_in[3] = digital_io_in[14];
- if(cfg_spim_enb) spim_mosi = digital_io_in[14];
+ if(cfg_spim_enb) spim_mosi = digital_io_in[14]; // SPIM MOSI (Input) = SPIS MISO (Output)
//Pin-18 PB4/MISO digital_io[15]
port_b_in[4] = digital_io_in[15];
+ spis_mosi = (spis_boot) ? digital_io_in[15] : 1'b0; // SPIM MISO (Output) = SPIS MOSI (Input)
//Pin-19 PB5/SCK digital_io[16]
port_b_in[5]= digital_io_in[16];
+ spis_sck = (spis_boot) ? digital_io_in[16] : 1'b1; // SPIM SCK (Output) = SPIS SCK (Input)
//Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
port_c_in[0] = digital_io_in[18];
@@ -726,13 +746,14 @@
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
if(cfg_pwm_enb[5]) digital_io_out[14] = pwm_wfm[5];
else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3];
+ else if(spis_boot) digital_io_out[14] = spis_miso; // SPIM MOSI (Input) = SPIS MISO (Output)
//Pin-18 PB4/MISO digital_io[15]
- if(cfg_spim_enb) digital_io_out[15] = spim_miso;
+ if(cfg_spim_enb) digital_io_out[15] = spim_miso; // SPIM MISO (Output) = SPIS MOSI (Input)
else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4];
//Pin-19 PB5/SCK digital_io[16]
- if(cfg_spim_enb) digital_io_out[16] = spim_sck;
+ if(cfg_spim_enb) digital_io_out[16] = spim_sck; // SPIM SCK (Output) = SPIS SCK (Input)
else if(cfg_port_b_dir_sel[5]) digital_io_out[16] = port_b_out[5];
//Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
@@ -839,17 +860,20 @@
else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0;
//Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
- if(cfg_spim_enb) digital_io_oen[14] = 1'b1;
+ if(cfg_spim_enb) digital_io_oen[14] = 1'b1; // SPIM MOSI (Input)
else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0;
else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0;
+ else if(spis_boot) digital_io_oen[14] = 1'b0; // SPIS MISO (Output)
//Pin-18 PB4/MISO digital_io[15]
- if(cfg_spim_enb) digital_io_oen[15] = 1'b0;
+ if(cfg_spim_enb) digital_io_oen[15] = 1'b0; // SPIM MISO (Output)
else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0;
+ else if(spis_boot) digital_io_oen[15] = 1'b1; // SPIS MOSI (Input)
//Pin-19 PB5/SCK digital_io[16]
- if(cfg_spim_enb) digital_io_oen[16] = 1'b0;
+ if(cfg_spim_enb) digital_io_oen[16] = 1'b0; // SPIM SCK (Output)
else if(cfg_port_b_dir_sel[5]) digital_io_oen[16] = 1'b0;
+ else if(spis_boot) digital_io_oen[16] = 1'b1; // SPIS SCK (Input)
//Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
if(cfg_port_c_dir_sel[0]) digital_io_oen[18] = 1'b0;
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 8ad8bd2..744c07b 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -716,7 +716,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h0807_2022) u_reg_23 (
+gen_32b_reg #(32'h2007_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -729,9 +729,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 4.7 = 0004700
+// Software Reg-3: Poject Revison 4.7 = 0004800
// ----------------------------------------
-gen_32b_reg #(32'h0004_7000) u_reg_24 (
+gen_32b_reg #(32'h0004_8000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/sspis/src/spi2wb.sv b/verilog/rtl/sspis/src/spi2wb.sv
new file mode 100644
index 0000000..76f52d6
--- /dev/null
+++ b/verilog/rtl/sspis/src/spi2wb.sv
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Reg2WB Interface ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description : This module contains Register To Wishbone ////
+//// Translation ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 20th July 2022, Dinesh A ////
+//// Initial version ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module spi2wb(
+
+ //spis_if Interface
+ input logic reg_wr , // write request
+ input logic reg_rd , // read request
+ input logic [31:0] reg_addr , // address
+ input logic [3:0] reg_be , // Byte enable
+ input logic [31:0] reg_wdata , // write data
+ output logic [31:0] reg_rdata , // read data
+ output logic reg_ack , // read valid
+
+ // WB Master Port
+ output logic wbm_cyc_o , // strobe/request
+ output logic wbm_stb_o , // strobe/request
+ output logic [31:0] wbm_adr_o , // address
+ output logic wbm_we_o , // write
+ output logic [31:0] wbm_dat_o , // data output
+ output logic [3:0] wbm_sel_o , // byte enable
+ input logic [31:0] wbm_dat_i , // data input
+ input logic wbm_ack_i , // acknowlegement
+ input logic wbm_err_i // error
+
+);
+
+
+
+assign wbm_cyc_o = reg_wr | reg_rd;
+assign wbm_stb_o = reg_wr | reg_rd;
+assign wbm_adr_o = reg_addr;
+assign wbm_we_o = reg_wr;
+assign wbm_sel_o = reg_be;
+assign wbm_dat_o = reg_wdata;
+assign reg_rdata = wbm_dat_i;
+assign reg_ack = wbm_ack_i;
+
+
+endmodule
diff --git a/verilog/rtl/sspis/src/sspis_if.sv b/verilog/rtl/sspis/src/sspis_if.sv
new file mode 100644
index 0000000..10a5d1d
--- /dev/null
+++ b/verilog/rtl/sspis/src/sspis_if.sv
@@ -0,0 +1,310 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SPI Interface ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description : This module contains SPI interface ////
+//// state machine ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 20th July 2022, Dinesh A ////
+//// Initial version ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/*********************************************************************
+ CMD Decoding [7:0]
+ [7:4] = 4'b1 - READ REGISTER
+ = 4'b2 - WRITE REGISTER
+ [3:0] = Byte Enable valid only during Write Command
+*********************************************************************/
+
+module sspis_if (
+
+ input logic sys_clk ,
+ input logic rst_n ,
+
+ input logic sclk ,
+ input logic ssn ,
+ input logic sdin ,
+ output logic sdout ,
+ output logic sdout_oen ,
+
+ //spi_sm Interface
+ output logic reg_wr , // write request
+ output logic reg_rd , // read request
+ output logic [31:0] reg_addr , // address
+ output logic [3:0] reg_be , // Byte enable
+ output logic [31:0] reg_wdata , // write data
+ input logic [31:0] reg_rdata , // read data
+ input logic reg_ack // read valid
+ );
+
+
+//--------------------------------------------------------
+// Wire and reg definitions
+// -------------------------------------------------------
+
+reg [5:0] bitcnt ;
+reg [7:0] cmd_reg ;
+reg [31:0] RegSdOut ;
+reg [2:0] spi_if_st ;
+
+parameter idle_st = 3'b000,
+ cmd_st = 3'b001,
+ adr_st = 3'b010,
+ wr_st = 3'b011,
+ wwait_st = 3'b100,
+ rwait_st = 3'b101,
+ rd_st = 3'b110;
+
+parameter READ_CMD = 4'h1,
+ WRITE_CMD = 4'h2;
+
+
+wire adr_phase = (spi_if_st == adr_st);
+wire cmd_phase = (spi_if_st == cmd_st);
+wire wr_phase = (spi_if_st == wr_st);
+wire rd_phase = (spi_if_st == rd_st);
+wire cnt_phase = (spi_if_st != wwait_st) && (spi_if_st != rwait_st);
+wire wwait_phase = (spi_if_st == wwait_st);
+wire rwait_phase = (spi_if_st == rwait_st);
+
+
+
+
+// sclk pos and ned edge generation
+logic sck_l0,sck_l1,sck_l2;
+
+assign sck_pdetect = (!sck_l2 && sck_l1) ? 1'b1: 1'b0;
+assign sck_ndetect = (sck_l2 && !sck_l1) ? 1'b1: 1'b0;
+
+always @ (posedge sys_clk or negedge rst_n) begin
+if (!rst_n) begin
+ sck_l0 <= 1'b1;
+ sck_l1 <= 1'b1;
+ sck_l2 <= 1'b1;
+ end
+ else begin
+ sck_l0 <= sclk;
+ sck_l1 <= sck_l0; // double sync
+ sck_l2 <= sck_l1;
+ end
+end
+
+// SSN double sync
+logic ssn_l0,ssn_l1, ssn_ss;
+
+assign ssn_ss = ssn_l1;
+
+always @ (posedge sys_clk or negedge rst_n) begin
+if (!rst_n) begin
+ ssn_l0 <= 1'b1;
+ ssn_l1 <= 1'b1;
+ end
+ else begin
+ ssn_l0 <= ssn;
+ ssn_l1 <= ssn_l0; // double sync
+ end
+end
+
+
+//command register accumation
+assign reg_be = cmd_reg[3:0];
+
+always @(negedge rst_n or posedge sys_clk)
+begin
+ if (!rst_n)
+ cmd_reg[7:0] <= 8'b0;
+ else if (cmd_phase & (sck_pdetect))
+ cmd_reg[7:0] <= {cmd_reg[6:0], sdin};
+end
+
+
+// address accumation at posedge sclk
+always @(negedge rst_n or posedge sys_clk)
+begin
+ if (!rst_n)
+ reg_addr[31:0] <= 32'b0;
+ else if (adr_phase & (sck_pdetect))
+ reg_addr[31:0] <= {reg_addr[30:0], sdin};
+end
+
+// write data accumation at posedge sclk
+always @(negedge rst_n or posedge sys_clk)
+begin
+ if (!rst_n)
+ reg_wdata[31:0] <= 32'b0;
+ else if (wr_phase & (sck_pdetect))
+ reg_wdata[31:0] <= {reg_wdata[30:0], sdin};
+end
+
+
+
+// drive sdout at negedge sclk
+always @(negedge rst_n or posedge sys_clk)
+begin
+ if (!rst_n) begin
+ RegSdOut[31:0] <= 32'b0;
+ sdout <= 1'b0;
+ end else begin
+ if (reg_ack)
+ RegSdOut <= reg_rdata[31:0];
+ else if (rd_phase && sck_ndetect)
+ RegSdOut <= {RegSdOut[30:0], 1'b0};
+
+ sdout <= (rd_phase && sck_ndetect) ? RegSdOut[31] : sdout;
+ end
+end
+
+
+// SPI State Machine
+always @(negedge rst_n or posedge sys_clk)
+begin
+ if (!rst_n) begin
+ reg_wr <= 1'b0;
+ reg_rd <= 1'b0;
+ sdout_oen <= 1'b1;
+ bitcnt <= 6'b0;
+ spi_if_st <= idle_st;
+ end else if(ssn_ss) begin
+ reg_wr <= 1'b0;
+ reg_rd <= 1'b0;
+ sdout_oen <= 1'b1;
+ bitcnt <= 6'b0;
+ spi_if_st <= idle_st;
+ end else begin
+ case (spi_if_st)
+ idle_st : begin // Idle State
+ reg_wr <= 1'b0;
+ reg_rd <= 1'b0;
+ sdout_oen <= 1'b1;
+ bitcnt <= 6'b0;
+ if (ssn_ss == 1'b0) begin
+ spi_if_st <= cmd_st;
+ end
+ end
+
+ cmd_st : begin // Command State
+ if (ssn_ss == 1'b1) begin
+ spi_if_st <= idle_st;
+ end else if (sck_pdetect) begin
+ if(bitcnt == 6'b000111) begin
+ bitcnt <= 6'b0;
+ spi_if_st <= adr_st;
+ end else begin
+ bitcnt <= bitcnt +1;
+ end
+ end
+ end
+
+ adr_st : begin // Address Phase
+ reg_wr <= 1'b0;
+ reg_rd <= 1'b0;
+ sdout_oen <= 1'b1;
+ if (ssn_ss == 1'b1) begin
+ spi_if_st <= idle_st;
+ end else if (sck_pdetect) begin
+ if (bitcnt == 6'b011111) begin
+ bitcnt <= 6'b0;
+ if(cmd_reg[7:4] == READ_CMD) begin
+ spi_if_st <= rwait_st;
+ reg_rd <= 1'b1;
+ end else if(cmd_reg[7:4] == WRITE_CMD) begin
+ spi_if_st <= wr_st;
+ end else begin
+ spi_if_st <= cmd_st;
+ end
+ end else begin
+ bitcnt <= bitcnt +1;
+ end
+ end
+ end
+
+ wr_st : begin // Write State
+ if (ssn_ss == 1'b1) begin
+ spi_if_st <= idle_st;
+ end else if (sck_pdetect) begin
+ if (bitcnt == 6'b011111) begin
+ bitcnt <= 6'b0;
+ spi_if_st <= wwait_st;
+ reg_wr <= 1;
+ end else begin
+ bitcnt <= bitcnt +1;
+ end
+ end
+ end
+ wwait_st : begin // Register Bus Busy Check State
+ if(reg_ack) reg_wr <= 0;
+ if (ssn_ss == 1'b1) begin
+ spi_if_st <= idle_st;
+ end else if (sck_pdetect) begin
+ if (bitcnt == 6'b000111) begin
+ bitcnt <= 6'b0;
+ spi_if_st <= cmd_st;
+ end else begin
+ bitcnt <= bitcnt +1;
+ end
+ end
+ end
+
+ rwait_st : begin // Read Wait State
+ if(reg_ack) reg_rd <= 1'b0;
+ if (ssn_ss == 1'b1) begin
+ spi_if_st <= idle_st;
+ end else if (sck_pdetect) begin
+ if (bitcnt == 6'b000111) begin
+ reg_rd <= 1'b0;
+ bitcnt <= 6'b0;
+ sdout_oen <= 1'b0;
+ spi_if_st <= rd_st;
+ end else begin
+ bitcnt <= bitcnt +1;
+ end
+ end
+ end
+
+ rd_st : begin // Send Data to SPI
+ if (ssn_ss == 1'b1) begin
+ spi_if_st <= idle_st;
+ end else if (sck_pdetect) begin
+ if (bitcnt == 6'b011111) begin
+ bitcnt <= 6'b0;
+ sdout_oen <= 1'b1;
+ spi_if_st <= cmd_st;
+ end else begin
+ bitcnt <= bitcnt +1;
+ end
+ end
+ end
+
+ default : spi_if_st <= idle_st;
+ endcase
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/sspis/src/sspis_top.sv b/verilog/rtl/sspis/src/sspis_top.sv
new file mode 100644
index 0000000..e42d630
--- /dev/null
+++ b/verilog/rtl/sspis/src/sspis_top.sv
@@ -0,0 +1,119 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SPI With Wishbone ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description : This module contains SPI interface + WB Master////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 20th July 2022, Dinesh A ////
+//// Initial version ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+module sspis_top (
+
+ input logic sys_clk ,
+ input logic rst_n ,
+
+ input logic sclk ,
+ input logic ssn ,
+ input logic sdin ,
+ output logic sdout ,
+ output logic sdout_oen ,
+
+ // WB Master Port
+ output logic wbm_cyc_o , // strobe/request
+ output logic wbm_stb_o , // strobe/request
+ output logic [31:0] wbm_adr_o , // address
+ output logic wbm_we_o , // write
+ output logic [31:0] wbm_dat_o , // data output
+ output logic [3:0] wbm_sel_o , // byte enable
+ input logic [31:0] wbm_dat_i , // data input
+ input logic wbm_ack_i , // acknowlegement
+ input logic wbm_err_i // error
+ );
+
+//-----------------------------------
+// Register I/F
+//-----------------------------------
+
+logic reg_wr ; // write request
+logic reg_rd ; // read request
+logic [31:0] reg_addr ; // address
+logic [3:0] reg_be ; // Byte enable
+logic [31:0] reg_wdata ; // write data
+logic [31:0] reg_rdata ; // read data
+logic reg_ack ; // read valid
+
+sspis_if u_if (
+
+ .sys_clk (sys_clk ),
+ .rst_n (rst_n ),
+
+ .sclk (sclk ),
+ .ssn (ssn ),
+ .sdin (sdin ),
+ .sdout (sdout ),
+ .sdout_oen (sdout_oen ),
+
+ //spi_sm Interface
+ .reg_wr (reg_wr ), // write request
+ .reg_rd (reg_rd ), // read request
+ .reg_addr (reg_addr ), // address
+ .reg_be (reg_be ), // Byte enable
+ .reg_wdata (reg_wdata ), // write data
+ .reg_rdata (reg_rdata ), // read data
+ .reg_ack (reg_ack ) // read valid
+ );
+
+spi2wb u_spi2wb (
+
+ //spis_if Interface
+ .reg_wr (reg_wr ), // write request
+ .reg_rd (reg_rd ), // read request
+ .reg_addr (reg_addr ), // address
+ .reg_be (reg_be ), // Byte enable
+ .reg_wdata (reg_wdata ), // write data
+ .reg_rdata (reg_rdata ), // read data
+ .reg_ack (reg_ack ), // read valid
+
+ // WB Master Port
+ .wbm_cyc_o (wbm_cyc_o ), // strobe/request
+ .wbm_stb_o (wbm_stb_o ), // strobe/request
+ .wbm_adr_o (wbm_adr_o ), // address
+ .wbm_we_o (wbm_we_o ), // write
+ .wbm_dat_o (wbm_dat_o ), // data output
+ .wbm_sel_o (wbm_sel_o ), // byte enable
+ .wbm_dat_i (wbm_dat_i ), // data input
+ .wbm_ack_i (wbm_ack_i ), // acknowlegement
+ .wbm_err_i (wbm_err_i ) // error
+
+);
+
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 16297b2..34c8794 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -40,7 +40,7 @@
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
//// 0.1 - 16th Feb 2021, Dinesh A ////
@@ -212,6 +212,10 @@
//// 4.7 July 08 2022, Dinesh A ////
//// Pinmux changes to support SPI CS port matching to ////
//// arduino ////
+//// 4.8 July 20 2022, Dinesh A ////
+//// SPI ISP boot option added in wb_host, spi slave uses ////
+//// same spi master interface, but will be active only ////
+//// when internal SPI config disabled + RESET PIN = 0 ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -588,6 +592,12 @@
wire sspim_si ; // serial data in
wire [3:0] sspim_ssn ; // cs_n
+// SPIS I/F
+wire sspis_sck ; // clock out
+wire sspis_so ; // serial data out
+wire sspis_si ; // serial data in
+wire sspis_ssn ; // cs_n
+
wire usb_intr_o ;
wire i2cm_intr_o ;
@@ -696,6 +706,12 @@
.uartm_rxd (uartm_rxd ),
.uartm_txd (uartm_txd ),
+ .sclk (sspis_sck ),
+ .ssn (sspis_ssn ),
+ .sdin (sspis_si ),
+ .sdout (sspis_so ),
+ .sdout_oen ( ),
+
.dbg_clk_mon (dbg_clk_mon )
@@ -1280,6 +1296,12 @@
.spim_ssn (sspim_ssn ),
.spim_miso (sspim_so ),
.spim_mosi (sspim_si ),
+
+ // SPI SLAVE
+ .spis_sck (sspis_sck ),
+ .spis_ssn (sspis_ssn ),
+ .spis_miso (sspis_so ),
+ .spis_mosi (sspis_si ),
// UART MASTER I/F
.uartm_rxd (uartm_rxd ),
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 22a25c0..42f9e73 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -76,3 +76,15 @@
`define QSPIM_IMEM_RDATA 8'h2C
`define QSPIM_SPI_STATUS 8'h30
+//----------------------------------------------------------
+// UART Register Map
+//----------------------------------------------------------
+`define UART_CTRL 8'h00 // Reg-0
+`define UART_INTR_STAT 8'h04 // Reg-1
+`define UART_BAUD_CTRL1 8'h08 // Reg-2
+`define UART_BAUD_CTRL2 8'h0C // Reg-3
+`define UART_STATUS 8'h10 // Reg-4
+`define UART_TDATA 8'h14 // Reg-5
+`define UART_RDATA 8'h18 // Reg-6
+`define UART_TFIFO_STAT 8'h1C // Reg-7
+`define UART_RFIFO_STAT 8'h20 // Reg-8
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 8256742..26029c2 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -139,6 +139,12 @@
input logic uartm_rxd ,
output logic uartm_txd ,
+ input logic sclk ,
+ input logic ssn ,
+ input logic sdin ,
+ output logic sdout ,
+ output logic sdout_oen ,
+
output logic dbg_clk_mon
);
@@ -188,6 +194,17 @@
logic wbm_uart_ack_o ; // acknowlegement
logic wbm_uart_err_o ; // error
+// SPI SLAVE Port
+logic wbm_spi_cyc_i ; // strobe/request
+logic wbm_spi_stb_i ; // strobe/request
+logic [31:0] wbm_spi_adr_i ; // address
+logic wbm_spi_we_i ; // write
+logic [31:0] wbm_spi_dat_i ; // data output
+logic [3:0] wbm_spi_sel_i ; // byte enable
+logic [31:0] wbm_spi_dat_o ; // data input
+logic wbm_spi_ack_o ; // acknowlegement
+logic wbm_spi_err_o ; // error
+
// Selected Master Port
logic wb_cyc_i ; // strobe/request
logic wb_stb_i ; // strobe/request
@@ -292,33 +309,57 @@
);
+sspis_top u_spi2wb(
+
+ .sys_clk (wbm_clk_i ),
+ .rst_n (wbm_rst_n ),
+
+ .sclk (sclk ),
+ .ssn (ssn ),
+ .sdin (sdin ),
+ .sdout (sdout ),
+ .sdout_oen (sdout_oen ),
+
+ // WB Master Port
+ .wbm_cyc_o (wbm_spi_cyc_i ), // strobe/request
+ .wbm_stb_o (wbm_spi_stb_i ), // strobe/request
+ .wbm_adr_o (wbm_spi_adr_i ), // address
+ .wbm_we_o (wbm_spi_we_i ), // write
+ .wbm_dat_o (wbm_spi_dat_i ), // data output
+ .wbm_sel_o (wbm_spi_sel_i ), // byte enable
+ .wbm_dat_i (wbm_spi_dat_o ), // data input
+ .wbm_ack_i (wbm_spi_ack_o ), // acknowlegement
+ .wbm_err_i (wbm_spi_err_o ) // error
+ );
// Arbitor to select between external wb vs uart wb
wire [1:0] grnt;
wb_arb u_arb(
.clk (wbm_clk_i),
.rstn (wbm_rst_n),
- .req ({2'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}),
+ .req ({1'b0,wbm_spi_stb_i,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}),
.gnt (grnt)
);
// Select the master based on the grant
-assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i : wbm_uart_cyc_i;
-assign wb_stb_i = (grnt == 2'b00) ? (wbm_cyc_i & wbm_stb_i) : wbm_uart_stb_i;
-assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i : wbm_uart_adr_i;
-assign wb_we_i = (grnt == 2'b00) ? wbm_we_i : wbm_uart_we_i;
-assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i : wbm_uart_dat_i;
-assign wb_sel_i = (grnt == 2'b00) ? wbm_sel_i : wbm_uart_sel_i;
+assign wb_cyc_i = (grnt == 2'b00) ? wbm_cyc_i :(grnt == 2'b01) ? wbm_uart_cyc_i :wbm_spi_cyc_i;
+assign wb_stb_i = (grnt == 2'b00) ? (wbm_cyc_i & wbm_stb_i) :(grnt == 2'b01) ? wbm_uart_stb_i :wbm_spi_stb_i;
+assign wb_adr_i = (grnt == 2'b00) ? wbm_adr_i :(grnt == 2'b01) ? wbm_uart_adr_i :wbm_spi_adr_i;
+assign wb_we_i = (grnt == 2'b00) ? wbm_we_i :(grnt == 2'b01) ? wbm_uart_we_i :wbm_spi_we_i ;
+assign wb_dat_i = (grnt == 2'b00) ? wbm_dat_i :(grnt == 2'b01) ? wbm_uart_dat_i :wbm_spi_dat_i;
+assign wb_sel_i = (grnt == 2'b00) ? wbm_sel_i :(grnt == 2'b01) ? wbm_uart_sel_i :wbm_spi_sel_i;
assign wbm_dat_o = (grnt == 2'b00) ? wb_dat_o : 'h0;
assign wbm_ack_o = (grnt == 2'b00) ? wb_ack_o : 'h0;
assign wbm_err_o = (grnt == 2'b00) ? wb_err_o : 'h0;
-
assign wbm_uart_dat_o = (grnt == 2'b01) ? wb_dat_o : 'h0;
assign wbm_uart_ack_o = (grnt == 2'b01) ? wb_ack_o : 'h0;
assign wbm_uart_err_o = (grnt == 2'b01) ? wb_err_o : 'h0;
+assign wbm_spi_dat_o = (grnt == 2'b10) ? wb_dat_o : 'h0;
+assign wbm_spi_ack_o = (grnt == 2'b10) ? wb_ack_o : 'h0;
+assign wbm_spi_err_o = (grnt == 2'b10) ? wb_err_o : 'h0;
