Riscduino Dual Risc Core SOC Permission to use, copy, modify, and/or distribute this soc for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* Dual 32 Bit RISC-V core
* 2KB SRAM for instruction cache
* 2KB SRAM for data cache
* 2KB SRAM for Tightly coupled memory - For Data Memory
* Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
* 2 x UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
* UART Master
* Simple SPI Master with 4 Chip select
* 6 Channel ADC (in Progress)
* 6 x PWM
* 3 x Timer (16 Bit), 1us/1ms/1second resolution
* 2 x ws281x driver
* 16 Hardware Semaphore
* Pin Compatbible to arduino uno
* Wishbone compatible design
* Written in System Verilog
* Open-source tool set
* simulation - iverilog
* synthesis - yosys
* backend/sta - openlane tool set
* Verification suite provided.
Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino
Riscduino SOC Integrated Dual 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from Syntacore SCR1 (https://github.com/syntacore/scr1)
Following Design changes are done on the basic version of syntacore RISC core
* Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys * local Instruction Memory depth increased from 4 to 8 location * Instruction Mem Request are changed from Single word to 4 Word Burst * Multiplication and Divsion are changed to improve timing * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz * 2KB instruction cache * 2KB data cache * Additional router are added towards instruction cache * Additional router are added towards data cache * Dual core related changes * Modified AXI/AHB interface to wishbone interface for instruction and data memory interface
* RV32I or RV32E ISA base + optional RVM and RVC standard extensions * Machine privilege mode only * 2 to 5 stage pipeline * 2KB icache * 2KB dcache * Optional Integrated Programmable Interrupt Controller with 16 IRQ lines * Optional RISC-V Debug subsystem with JTAG interface * Optional on-chip Tightly-Coupled Memory
In Process - Looking for community help ...
| Block | Total Cell | Combo | Seq |
|---|---|---|---|
| RISC | 52527 | 46858 | 5669 |
| QSPI | 8654 | 7149 | 1505 |
| UART_I2C_USB_SPI | 15926 | 13061 | 2865 |
| WB_HOST | 5800 | 4701 | 1099 |
| WB_INTC | 11477 | 10081 | 1396 |
| PINMUX | 6746 | 5574 | 1172 |
| TOTAL | 120381 | 103826 | 16555 |
sudo apt update sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add - sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable" sudo apt update apt-cache policy docker-ce sudo apt install docker-ce #Add User Name to docker sudo usermod -aG docker <your user name> # Reboot the system to enable the docker setup
git clone https://github.com/dineshannayya/riscduino.git cd riscduino git submodule init git submodule update make unzip
- Required openlane and pdk are moved inside the riscduino docker to avoid the external dependency. - flow automatically pull the required docker based on MPW version. - RTL to gds docker is hardcoded inside File: openlane/Makefile
OPENLANE_TAG = mpw6 OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
- for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker - caravel, openlane and pdk envionment are automatically pointed to internal docker pointer - To view the docker contents
docker run -ti --rm riscduino/openlane:mpw6 bash cd /opt/pdk_mpw6 - pdk folder cd /opt/caravel - caravel folder cd /openlane - openlane folder env - Show the internally defined env's CARAVEL_ROOT=/opt/caravel PDK_ROOT=/opt/pdk_mpw6
- Required caravel and pdk are moved inside the riscduino docker to avoid the external dependency.
- flow automatically pull the required docker based on MPW version.
- To view the docker contents
- RTL simulation docker hardcoded inside File: Makefile
simenv:
docker pull riscduino/dv_setup:mpw6
- for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows - caravel and pdk envionment are automatically pointed to internal docker pointer - To view the docker contents
docker run -ti --rm riscduino/dv_setup:mpw6 bash cd /opt/pdk_mpw6 - pdk folder cd /opt/caravel - caravel folder env - Show the internally defined env's CARAVEL_ROOT=/opt/caravel PDK_ROOT=/opt/pdk_mpw6
The simulation package includes the following tests:
Examples:
make verify-wb_port - User Wishbone Test from caravel make verify-risc_boot - User Risc core test from caravel make verify-uart_master - User uart master test from caravel make verify-user_basic - Standalone Basic signal and clock divider test make verify-user_uart - Standalone user uart-0 test using user risc core make verify-user_uart1 - Standalone user uart-0 test using user risc core make verify-user_i2cm - Standalone user i2c test make verify-user_risc_boot - standalone user risc core-0 boot test make verify-user_pwm - standalone user pwm test make verify-user_timer - standalone user timer test make verify-user_sspi - standalone user spi test make verify-user_qspi - standalone user quad spi test make verify-user_usb - standalone user usb host test make verify-user_gpio - standalone user gpio test make verify-user_aes - standalone aes test with risc core-0 make verify-user_cache_bypass - standalone icache and dcache bypass test with risc core-0 make verify-user_uart_master - standalone user uart master test make verify-user_sram_exec - standalone riscv core-0 test with executing code from data memory make verify-riscv_regress - standalone riscv compliance test suite make verify-arduino_risc_boot - standalone riscv core-0 boot using arduino tool set make verify-arduino_hello_world - standalone riscv core-0 hello world test using arduino tool set make verify-arduino_digital_port_control - standalone riscv core-0 digital port control using arduino tool set make verify-arduino_ascii_table - standalone riscv core-0 ascii table using arduino tool set make verify-arduino_character_analysis - standalone riscv core-0 character analysis using arduino tool set make verify-arduino_multi_serial - standalone riscv core-0 multi uart test using arduino tool set make verify-arduino_switchCase2 - standalone riscv core-0 switch case using arduino tool set make verify-arduino_risc_boot - standalone riscv core-0 boot test using arduino tool set make verify-arduino_string - standalone riscv core-0 string usage test using arduino tool set make verify-user_mcore - standalone riscv multi-core test make verify-user_sram_exec RISC_CORE=1 - standalone riscv core-1 test with executing code from data memory make verify-user_risc_boot RISC_CORE=1 - standalone user risc core-1 boot test make verify-user_uart RISC_CORE=1 - Standalone user uart test using user risc core-1 make verify-user_uart1 RISC_CORE=1 - Standalone user uart test using user risc core-1 make verify-user_aes RISC_CORE=1 - standalone aes test with risc core-1 make verify-user_cache_bypass RISC_CORE=1 - standalone icache and dcache bypass test with risc core-1 make verify-arduino_risc_boot RISC_CORE=1 - standalone riscv core-1 boot using arduino tool set make verify-user_uart SIM=RTL DUMP=OFF - Standalone user uart-0 test using user risc core with waveform dump off make verify-user_uart SIM=RTL DUMP=ON - Standalone user uart-0 test using user risc core with waveform dump on make verify-user_uart SIM=GL DUMP=OFF - Standalone user uart-0 test using user risc core with gatelevel netlist make verify-user_uart SIM=GL DUMP=ON - Standalone user uart-0 test using user risc core with gatelevel netlist and waveform on
cd openlane
make pinmux
make qspim_top
make uart_i2cm_usb_spi_top
make wb_host
make wb_interconnect
make ycr_intf
make ycr_core_top
make ycr_iconnect
make user_project_wrapper
#Timing Analysis
make setup-timing-scripts make install make install_mcw
his will update Caravel design files and install the scripts for running timing.
make extract-parasitics make create-spef-mapping make caravel-sta
#Other Miscellaneous Targets The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane’s flow.
Run make help to display available targets.
Run lvs on the mag view,
make lvs-<macro_name>
Run lvs on the gds,
make lvs-gds-<macro_name>
Run lvs on the maglef,
make lvs-maglef-<macro_name>
Run drc using magic,
make drc-<macro_name>
Run antenna check using magic,
make antenna-<macro_name>
Run XOR check,
make xor-wrapper
Riscduino Soc flow uses Openlane tool sets.
yosys - Performs RTL synthesisabc - Performs technology mappingOpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reportsinit_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)ioplacer - Places the macro input and output portspdn - Generates the power distribution networktapcell - Inserts welltap and decap cells in the floorplanRePLace - Performs global placementResizer - Performs optional optimizations on the designOpenPhySyn - Performs timing optimizations on the designOpenDP - Perfroms detailed placement to legalize the globally placed componentsTritonCTS - Synthesizes the clock distribution network (the clock tree)FastRoute - Performs global routing to generate a guide file for the detailed routerCU-GR - Another option for performing global routing.TritonRoute - Performs detailed routingSPEF-Extractor - Performs SPEF extractionMagic - Streams out the final GDSII layout file from the routed defKlayout - Streams out the final GDSII layout file from the routed def as a back-upMagic - Performs DRC Checks & Antenna ChecksKlayout - Performs DRC ChecksNetgen - Performs LVS ChecksCVC - Performs Circuit Validity ChecksWe are looking for community help in following activity, interested user can ping me in efabless slack platform
Report an issue: https://github.com/dineshannayya/riscduino_dcore/issues