Riscduino Dual Risc Core SOC


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

Table of contents

• Overview
• Riscduino Block Diagram
• Key Feature
• Riscduino derivatives
• MPW Shuttle on Riscduino
• Sub IP Feature
• SOC Memory Map
• Pin Mapping
• Repository contents
• Prerequisites
• Tests preparation
  • Running Simuation
• Tool sets
• News
• Contacts
• How To Contribute
• Documentation

Overview

Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.

Riscduino Block Diagram

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * Dual 32 Bit RISC-V core
    * 2KB SRAM for instruction cache 
    * 2KB SRAM for data cache
    * 2KB SRAM for Tightly coupled memory - For Data Memory
    * Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
    * 2 x UART with 16Byte FIFO
    * USB 1.1 Host
    * I2C Master
    * UART Master
    * Simple SPI Master with 4 Chip select
    * 6 Channel ADC (in Progress)
    * 6 x PWM
    * 3 x Timer (16 Bit), 1us/1ms/1second resolution
    * Pin Compatbible to arduino uno
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Riscduino derivatives

MPW Shuttle on Riscduino

SOC Pin Mapping

Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino

Riscduino documentation

• Riscduino documentation available at : https://riscduino.readthedocs.io/en/latest/

Arduino ide integration

• We are in initial phase of Riscduino board integration into arduino and integration details are available at : https://github.com/dineshannayya/riscduino_board/

Sub IP features

RISC V Core

Riscduino SOC Integrated Dual 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from Syntacore SCR1 (https://github.com/syntacore/scr1)

RISC V core customization for Riscduino SOC

Following Design changes are done on the basic version of syntacore RISC core

   * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
   * local Instruction Memory depth increased from 4 to 8 location
   * Instruction Mem Request are changed from Single word to 4 Word Burst
   * Multiplication and Divsion are changed to improve timing
   * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
   * 2KB instruction cache 
   * 2KB data cache
   * Additional router are added towards instruction cache
   * Additional router are added towards data cache
   * Dual core related changes
   * Modified AXI/AHB interface to wishbone interface for instruction and data memory interface

Block Diagram

RISC V Core Key feature

   * RV32I or RV32E ISA base + optional RVM and RVC standard extensions
   * Machine privilege mode only
   * 2 to 5 stage pipeline
   * 2KB icache
   * 2KB dcache
   * Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
   * Optional RISC-V Debug subsystem with JTAG interface
   * Optional on-chip Tightly-Coupled Memory

6 Channel SAR ADC

In Process - Looking for community help ...

SOC Memory Map

SOC Size

SOC Register Map

Register Map: Wishbone HOST

Register: GLBL_CTRL

Register: BANK_CTRL

Register: CLK_SKEW_CTRL1

Register Map: SPI MASTER

Register: GLBL_CTRL

Register: DMEM_CTRL1

Register: DMEM_CTRL2

Register: IMEM_CTRL1

Register: IMEM_CTRL2

Register: IMEM_ADDR

Register: IMEM_WDATA

Register: IMEM_RDATA

Register: SPI_STATUS

Register Map: Global Register

Register: RISC_FUSE

Register: INTR_CTRL

Repository contents

|verilog
|   ├─  rtl
|   |     |-  syntacore
|   |     |     |─  scr1
|   |     |     |    ├─ **docs**                           | **SCR1 documentation**
|   |     |     |    |      ├─ scr1_eas.pdf                | SCR1 External Architecture Specification
|   |     |     |    |      └─ scr1_um.pdf                 | SCR1 User Manual
|   |     |     |    |─  **src**                           | **SCR1 RTL source and testbench files**
|   |     |     |    |   ├─ includes                       | Header files
|   |     |     |    |   ├─ core                           | Core top source files
|   |     |     |    |   ├─ top                            | Cluster source files
|   |     |     |    |─  **synth**                         | **SCR1 RTL Synthesis files **
|   |     |- Qspi_master
|   |     |     |- src                                     | Qard SPI Master Source files
|   |     |-wb_interconnect
|   |     |     |- src                                     | 3x4 Wishbone Interconnect
|   |     |- digital_core
|   |     |     |- src                                     | Digital core Source files
|   |     |- lib                                           | common library source files
|   |- dv
|   |   |- la_test1                                        | carevel LA test
|   |   |- risc_boot                                       | user core risc boot test
|   |   |- wb_port                                         | user wishbone test
|   |   |- user_risc_boot                                  | user standalone test without carevel soc
|   |- gl                                                  | ** GLS Source files **
|
|- openlane
    |- spi_master                                          | spi_master openlane scripts   
    |- syntacore                                           | Risc Core openlane scripts   
    |- user_project_wrapper                                | carvel user project wrapper 

Prerequisites

• Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.

Step-1: Docker in ubuntu 20.04 version

   sudo apt update
   sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
   curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
   sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
   sudo apt update
   apt-cache policy docker-ce
   sudo apt install docker-ce

   #Add User Name to docker
   sudo usermod -aG docker <your user name>
   # Reboot the system to enable the docker setup

Step-2: Clone , update the Submodule, unzip the content

   git clone https://github.com/dineshannayya/riscduino.git
   cd riscduino
   git submodule init
   git submodule update
   make unzip

Note-1: RTL to GDS Docker

- Required openlane and pdk are moved inside the riscduino docker to avoid the external dependency. 
- flow automatically pull the required docker based on MPW version.
- RTL to gds docker is hardcoded inside File: openlane/Makefile

     OPENLANE_TAG = mpw6
     OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)

Note-1.1: View the RTL to GDS Docker content

- for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker 
- caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents

    docker run -ti --rm riscduino/openlane:mpw6  bash
    cd /opt/pdk_mpw6     -  pdk folder
    cd /opt/caravel      -  caravel folder 
    cd /openlane         -  openlane folder
    env   - Show the internally defined env's
        CARAVEL_ROOT=/opt/caravel
        PDK_ROOT=/opt/pdk_mpw6

Note-2: RTL Simulation Docker

- Required caravel and pdk are moved inside the riscduino docker to avoid the external dependency. 
- flow automatically pull the required docker based on MPW version.
- To view the docker contents
- RTL simulation docker hardcoded inside File: Makefile
    simenv:
    docker pull riscduino/dv_setup:mpw6

Note-2.1: View the RTL Simulation Docker content

- for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows
- caravel and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents

    docker run -ti --rm riscduino/dv_setup:mpw6  bash
    cd /opt/pdk_mpw6     -  pdk folder
    cd /opt/caravel      -  caravel folder 
    env   - Show the internally defined env's
        CARAVEL_ROOT=/opt/caravel
        PDK_ROOT=/opt/pdk_mpw6

Tests preparation

The simulation package includes the following tests:

• risc_boot - Complete caravel User Risc core boot
• wb_port - Complete caravel User Wishbone validation
• uart_master - complete caravel user uart master test
• user_risc_boot - Standalone User Risc core boot
• user_sspi - Standalone SSPI test
• user_qspi - Standalone Quad SPI test
• user_spi - Standalone SPI test
• user_i2c - Standalone I2C test
• user_usb - Standalone USB Host test
• user_risc_boot - Standalone Risc Boot test
• user_uart - Standalone Risc with UART-0 Test
• user_uart1 - Standalone Risc with UART-1 Test
• user_gpio - Standalone GPIO Test
• user_pwm - Standalone pwm Test
• user_timer - Standalone timer Test
• user_uart_master - Standalone uart master test
• riscv_regress - Standalone riscv compliance and regression test suite

Running Simulation

Examples:

    make verify-wb_port                        - User Wishbone Test from caravel
    make verify-risc_boot                      - User Risc core test from caravel
    make verify-uart_master                    - User uart master test from caravel
    make verify-user_basic                     - Standalone Basic signal and clock divider test
    make verify-user_uart                      - Standalone user uart-0 test using user risc core
    make verify-user_uart1                     - Standalone user uart-0 test using user risc core
    make verify-user_i2cm                      - Standalone user i2c test
    make verify-user_risc_boot                 - standalone user risc core-0 boot test
    make verify-user_pwm                       - standalone user pwm test
    make verify-user_timer                     - standalone user timer test
    make verify-user_sspi                      - standalone user spi test
    make verify-user_qspi                      - standalone user quad spi test
    make verify-user_usb                       - standalone user usb host test
    make verify-user_gpio                      - standalone user gpio test
    make verify-user_aes                       - standalone aes test with risc core-0
    make verify-user_cache_bypass              - standalone icache and dcache bypass test with risc core-0
    make verify-user_uart_master               - standalone user uart master test
    make verify-user_sram_exec                 - standalone riscv core-0 test with executing code from data memory
    make verify-riscv_regress                  - standalone riscv compliance test suite
    make verify-arduino_risc_boot              - standalone riscv core-0 boot using arduino tool set
    make verify-arduino_hello_world            - standalone riscv core-0 hello world test using arduino tool set
    make verify-user_mcore                     - standalone riscv multi-core test
    make verify-user_sram_exec RISC_CORE=1     - standalone riscv core-1 test with executing code from data memory
    make verify-user_risc_boot RISC_CORE=1     - standalone user risc core-1 boot test
    make verify-user_uart RISC_CORE=1          - Standalone user uart test using user risc core-1
    make verify-user_uart1 RISC_CORE=1         - Standalone user uart test using user risc core-1
    make verify-user_aes  RISC_CORE=1          - standalone aes test with risc core-1
    make verify-user_cache_bypass RISC_CORE=1  - standalone icache and dcache bypass test with risc core-1
    make verify-arduino_risc_boot RISC_CORE=1  - standalone riscv core-1 boot using arduino tool set
    make verify-arduino_hello_world RISC_CORE=1 - standalone riscv core-1 hello world test using arduino tool set
    
    make verify-user_uart SIM=RTL DUMP=OFF     - Standalone user uart-0 test using user risc core with waveform dump off
    make verify-user_uart SIM=RTL DUMP=ON      - Standalone user uart-0 test using user risc core with waveform dump on
    make verify-user_uart SIM=GL DUMP=OFF      - Standalone user uart-0 test using user risc core with gatelevel netlist
    make verify-user_uart SIM=GL DUMP=ON       - Standalone user uart-0 test using user risc core with gatelevel netlist and waveform on

Running RTL to GDS flows

• First run the individual macro file
• Last run the user_project_wrapper

   cd openlane
   make pinmux
   make qspim_top
   make uart_i2cm_usb_spi_top
   make wb_host
   make wb_interconnect
   make ycr_intf
   make ycr_core_top
   make ycr_iconnect
   make user_project_wrapper

Tool Sets

Riscduino Soc flow uses Openlane tool sets.

1. Synthesis
   1. yosys - Performs RTL synthesis
   2. abc - Performs technology mapping
   3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
2. Floorplan and PDN
   1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
   2. ioplacer - Places the macro input and output ports
   3. pdn - Generates the power distribution network
   4. tapcell - Inserts welltap and decap cells in the floorplan
3. Placement
   1. RePLace - Performs global placement
   2. Resizer - Performs optional optimizations on the design
   3. OpenPhySyn - Performs timing optimizations on the design
   4. OpenDP - Perfroms detailed placement to legalize the globally placed components
4. CTS
   1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
5. Routing
   1. FastRoute - Performs global routing to generate a guide file for the detailed router
   2. CU-GR - Another option for performing global routing.
   3. TritonRoute - Performs detailed routing
   4. SPEF-Extractor - Performs SPEF extraction
6. GDSII Generation
   1. Magic - Streams out the final GDSII layout file from the routed def
   2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
7. Checks
   1. Magic - Performs DRC Checks & Antenna Checks
   2. Klayout - Performs DRC Checks
   3. Netgen - Performs LVS Checks
   4. CVC - Performs Circuit Validity Checks

News

• Riscduino Aim - https://www.youtube.com/watch?v=lFVnicPhTI0

How To Contribute

We are looking for community help in following activity, interested user can ping me in efabless slack platform

• Analog Design - ADC, DAC, PLL,
• Digital Design - New IP Integration, Encription,DSP, Floating point functions
• Verification - Improving the Verification flow
• Linux Porting - Build Root integration
• Arudino Software Update - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
• Riscv Simulator - integration to Riscduino
• Any other ideas

Contacts

Report an issue: https://github.com/dineshannayya/riscduino_dcore/issues

Documentation

• Syntacore Link - https://github.com/syntacore/scr1

News on Riscduino

• Riscduino Aim - https://www.youtube.com/watch?v=lFVnicPhTI0