gatesim setup cleanup
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 2627452..47fba8d 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -72,6 +72,7 @@
$script_dir/../../verilog/rtl/lib/ctech_cells.sv \
"
+set ::env(SYNTH_NO_FLAT) {1}
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 2fc3ce8..8d892af 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -480,6 +480,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index 37feef0..e8d50fd 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -42,7 +42,6 @@
all: ${PATTERN:=.vcd}
-hex: ${PATTERN:=.hex}
vvp: ${PATTERN:=.vvp}
@@ -58,9 +57,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 94209cd..5c9addd 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -151,7 +151,12 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(0, user_basic_tb);
+ $dumpvars(1, user_basic_tb);
+ $dumpvars(1, user_basic_tb.u_top);
+ $dumpvars(1, user_basic_tb.u_top.u_wb_host);
+ $dumpvars(1, user_basic_tb.u_top.u_intercon);
+ $dumpvars(1, user_basic_tb.u_top.u_intercon);
+ $dumpvars(1, user_basic_tb.u_top.u_pinmux);
end
`endif
@@ -179,6 +184,7 @@
// cfg_rtc_clk_ctrl = reg_0[19:12];
// cfg_cpu_clk_ctrl = reg_0[23:20];
// cfg_usb_clk_ctrl = reg_0[31:24];
+
$display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1");
test_step = 1;
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h0,4'h0,8'h0,4'h0,8'h00});
@@ -233,7 +239,7 @@
test_step = 10;
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h89,4'hF,8'hFF,4'hF,8'h00});
clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,11*CLK2_PERIOD,5*CLK2_PERIOD);
-
+
$display("###################################################");
$display("Monitor: Checking the chip signature :");
// Remove Wb/PinMux Reset
@@ -416,6 +422,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -445,6 +452,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -466,29 +474,21 @@
`ifdef GL
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
`endif
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index e7d9b13..a801f55 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -26,9 +26,6 @@
DESIGNS?=../../..
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
-## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-GCC64_PREFIX?=riscv64-unknown-elf
## Simulation mode: RTL/GL
@@ -45,7 +42,6 @@
all: ${PATTERN:=.vcd}
-hex: ${PATTERN:=.hex}
vvp: ${PATTERN:=.vvp}
@@ -61,9 +57,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
@@ -73,6 +75,6 @@
# ---- Clean ----
clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.fst
.PHONY: clean hex all
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index aedd191..0607308 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -405,6 +405,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -433,6 +434,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index cbe03cb..43ba01f 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -360,6 +360,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -389,6 +390,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile
index 1932afc..ca06f65 100644
--- a/verilog/dv/user_qspi/Makefile
+++ b/verilog/dv/user_qspi/Makefile
@@ -26,15 +26,11 @@
DESIGNS?=../../..
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
-## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-GCC64_PREFIX?=riscv64-unknown-elf
## Simulation mode: RTL/GL
SIM?=RTL
DUMP?=OFF
-RISC_CORE?=0
### To Enable IVERILOG FST DUMP
export IVERILOG_DUMPER = fst
@@ -61,9 +57,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index fdac089..4fd07e5 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -1297,6 +1297,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -1326,6 +1327,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -1348,29 +1350,21 @@
`ifdef GL
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
`endif
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 4a0c488..85751d6 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -46,7 +46,6 @@
all: ${PATTERN:=.vcd}
-hex: ${PATTERN:=.hex}
vvp: ${PATTERN:=.vvp}
@@ -68,9 +67,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 82bd34a..f8af2e8 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -329,6 +329,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -358,6 +359,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -379,29 +381,21 @@
`ifdef GL
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
`endif
diff --git a/verilog/dv/user_sspi/.user_sspi_tb.v.swp b/verilog/dv/user_sspi/.user_sspi_tb.v.swp
deleted file mode 100644
index 7af26eb..0000000
--- a/verilog/dv/user_sspi/.user_sspi_tb.v.swp
+++ /dev/null
Binary files differ
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile
index 9d8bd45..8968de7 100644
--- a/verilog/dv/user_sspi/Makefile
+++ b/verilog/dv/user_sspi/Makefile
@@ -26,15 +26,11 @@
DESIGNS?=../../..
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
-## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-GCC64_PREFIX?=riscv64-unknown-elf
## Simulation mode: RTL/GL
SIM?=RTL
DUMP?=OFF
-RISC_CORE?=0
### To Enable IVERILOG FST DUMP
export IVERILOG_DUMPER = fst
@@ -61,9 +57,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
@@ -73,6 +75,6 @@
# ---- Clean ----
clean:
- rm -f *.vvp *.vcd *.log *.fst
+ rm -f *.elf *.bin *.vvp *.vcd *.log *.dump *.fst
.PHONY: clean hex all
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index e3cd34e..1e81542 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -567,6 +567,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -596,6 +597,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -618,29 +620,21 @@
`ifdef GL
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
`endif
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v
index d7ef5e6..8fced3c 100644
--- a/verilog/dv/user_timer/user_timer_tb.v
+++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -394,6 +394,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -423,6 +424,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 97726ee..a97fa0f 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -67,9 +67,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
@@ -81,4 +87,4 @@
clean:
rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
-.PHONY: clean hex all
+.PHONY: clean all
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 41e89c2..ffb5584 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -186,7 +186,13 @@
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
end else begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
@@ -209,14 +215,14 @@
for (i=0; i<40; i=i+1)
begin
$display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
- user_uart_tb.tb_uart.write_char (uart_write_data[i]);
+ tb_uart.write_char (uart_write_data[i]);
end
end
begin
for (j=0; j<40; j=j+1)
begin
- user_uart_tb.tb_uart.read_char_chk(uart_write_data[j]);
+ tb_uart.read_char_chk(uart_write_data[j]);
end
end
join
@@ -397,6 +403,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -413,29 +420,21 @@
`ifdef GL
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
`endif
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile
index 046c8df..04737d0 100644
--- a/verilog/dv/user_uart1/Makefile
+++ b/verilog/dv/user_uart1/Makefile
@@ -67,9 +67,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v
index 4946c9f..44587e4 100644
--- a/verilog/dv/user_uart1/user_uart1_tb.v
+++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -403,6 +403,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -419,29 +420,21 @@
`ifdef GL
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
`endif
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index 7f9bc7b..5eccb5b 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile
@@ -60,9 +60,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
@@ -73,6 +79,6 @@
# ---- Clean ----
clean:
- rm -f *.vvp *.vcd *.log
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
.PHONY: clean all
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile
index a25bc69..1684a0d 100644
--- a/verilog/dv/user_usb/Makefile
+++ b/verilog/dv/user_usb/Makefile
@@ -61,18 +61,24 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
- vvp $<
+ vvp $< +risc_core_id=$(RISC_CORE)
# ---- Clean ----
clean:
- rm -f *.vvp *.vcd *.log *.fst
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
.PHONY: clean hex all
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index d2e37b4..b6b4892 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -135,7 +135,12 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(5, user_usb_tb);
+ $dumpvars(1, user_usb_tb);
+ $dumpvars(1, user_usb_tb.u_top);
+ $dumpvars(1, user_usb_tb.u_top.u_uart_i2c_usb_spi);
+ $dumpvars(0, user_usb_tb.u_top.u_uart_i2c_usb_spi.u_usb_host);
+ //$dumpvars(0, user_usb_tb.u_top.u_intercon);
+ //$dumpvars(0, user_usb_tb.u_top.u_wb_host);
end
`endif
@@ -270,7 +275,7 @@
// Full Speed Device Indication
pullup(usbd_txdp);
-//pulldown(usbd_txdn);
+pulldown(usbd_txdn);
usb1d_top u_usb_top(
@@ -452,6 +457,7 @@
wbd_ext_cyc_i ='h1; // strobe/request
wbd_ext_stb_i ='h1; // strobe/request
wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
data = wbd_ext_dat_o;
repeat (1) @(posedge clock);
#1;
@@ -503,29 +509,21 @@
`ifdef GL
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
`endif
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 633a369..b7dd1b4 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -152,11 +152,11 @@
## RTL
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+ iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
else
- iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+ iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
endif
@@ -165,11 +165,11 @@
## GL
ifeq ($(SIM),GL)
ifeq ($(CONFIG),caravel_user_project)
- iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+ iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.gl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
else
- iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+ iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
endif
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
new file mode 100644
index 0000000..fbeb490
--- /dev/null
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -0,0 +1,29 @@
+# Caravel user project includes
++define+UNIT_DELAY=#0.1
++incdir+$(USER_PROJECT_VERILOG)/rtl/
++incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes
++incdir+$(USER_PROJECT_VERILOG)/dv/bfm
++incdir+$(USER_PROJECT_VERILOG)/dv/model
++incdir+$(USER_PROJECT_VERILOG)/dv/agents
+$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
+$(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
+$(USER_PROJECT_VERILOG)/gl/ycr_intf.v
+$(USER_PROJECT_VERILOG)/gl/qspim_top.v
+$(USER_PROJECT_VERILOG)/gl/wb_host.v
+$(USER_PROJECT_VERILOG)/gl/ycr2_iconnect.v
+$(USER_PROJECT_VERILOG)/gl/ycr_core_top.v
+$(USER_PROJECT_VERILOG)/gl/pinmux.v
+$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v
+$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v
+###########################################################
+# STD CELLS - they need to be below the defines.v files
+###########################################################
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+
