rtl: user_project_wrapper: use wb_pio instead of example
Now that we have our own project, use our own topfile instead of the
example one.
Signed-off-by: Sean Cross <sean@xobs.io>
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..b350953 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,7 +82,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+wb_pio mprj (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
