verilog: fix includes for testing hardware
This is required in order to get test cases working.
Signed-off-by: Sean Cross <sean@xobs.io>
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
index 284a97c..b272314 100644
--- a/verilog/includes/includes.gl+sdf.caravel_user_project
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -1,3 +1,3 @@
// Caravel user project includes
-$USER_PROJECT_VERILOG/gl/user_project_wrapper.v
-$USER_PROJECT_VERILOG/gl/user_proj_example.v
+$USER_PROJECT_VERILOG/gl/user_project_wrapper.v
+$USER_PROJECT_VERILOG/gl/wb_pio.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index f5047d5..b30e4b6 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,3 +1,3 @@
# Caravel user project includes
--v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
--v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/gl/wb_pio.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..822adb4 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,14 @@
# Caravel user project includes
--v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-
-
\ No newline at end of file
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
++incdir+$(USER_PROJECT_VERILOG)/rtl
++incdir+$(USER_PROJECT_VERILOG)/rtl/fpga_pio/src
+-v $(USER_PROJECT_VERILOG)/rtl/wb_pio_top.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/decoder.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/divider.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/fifo.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/isr.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/machine.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/osr.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/pc.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/pio.v
+-v $(USER_PROJECT_VERILOG)/rtl/fpga_pio/src/scratch.v
