include
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..5ce77d2 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,5 @@
# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/aes128.v
-
\ No newline at end of file
+
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..ef6e317 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,40 +82,40 @@
/* User project is instantiated here */
/*--------------------------------------*/
-user_proj_example mprj (
+aes128 aes128 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
`endif
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
+ .clk(wb_clk_i),
+ //.wb_rst_i(wb_rst_i),
// MGMT SoC Wishbone Slave
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
+ // .wbs_cyc_i(wbs_cyc_i),
+ // .wbs_stb_i(wbs_stb_i),
+ // .wbs_we_i(wbs_we_i),
+ // .wbs_sel_i(wbs_sel_i),
+ // .wbs_adr_i(wbs_adr_i),
+ // .wbs_dat_i(wbs_dat_i),
+ // .wbs_ack_o(wbs_ack_o),
+ // .wbs_dat_o(wbs_dat_o),
// Logic Analyzer
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
+ .state(la_data_in),
+ .out(la_data_out),
+ .key (la_oenb),
// IO Pads
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
+ // .io_in (io_in),
+ // .io_out(io_out),
+ // .io_oeb(io_oeb),
// IRQ
- .irq(user_irq)
+ // .irq(user_irq)
);
endmodule // user_project_wrapper
