netlist
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..4d3c559 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -21,8 +21,8 @@
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.v"
+ `include "gl/aes128.v"
`else
`include "user_project_wrapper.v"
- `include "user_proj_example.v"
-`endif
\ No newline at end of file
+ `include "aes128.v"
+`endif
