commit 7d5d46aa8658b38ccf4624e76ff4761bcc4d32a8
author DaveX13342 <zeweix@andrew.cmu.edu> Sun Sep 11 19:17:47 2022 +0000
committer DaveX13342 <zeweix@andrew.cmu.edu> Sun Sep 11 19:17:47 2022 +0000
tree 722514cd66f69421e1338b9aec6f01fd6efe8be5
parent a3c83d92817789c7d22729f3fdedad64b1ed45c6

VCO and defult block in. compare out have issue on top level net nameing, @Zexi,please help that if you can

mag/VCO.ext

diff --git a/mag/VCO.ext b/mag/VCO.ext
new file mode 100644
index 0000000..03acee2
--- /dev/null
+++ b/mag/VCO.ext
@@ -0,0 +1,2965 @@
+timestamp 1662920576
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use bias_calc bias_calc_0 1 0 14295 0 1 25060
+use cap_bank X7 1 0 54405 0 1 22905
+use cap_bank X6 1 0 52305 0 1 22905
+use cap_bank X5 1 0 54405 0 -1 34725
+use cap_bank X4 1 0 52305 0 -1 34725
+use core_osc X1 1 0 46065 0 1 21045
+use cap_bank X11 1 0 58605 0 -1 34725
+use cap_bank X10 1 0 56505 0 -1 34725
+use cap_bank X9 1 0 58605 0 1 22905
+use cap_bank X8 1 0 56505 0 1 22905
+use output_buffer output_buffer_0 1 0 34825 0 1 39195
+use sky130_fd_pr__pfet_01v8_lvt_75KH85 sky130_fd_pr__pfet_01v8_lvt_75KH85_0 1 0 33689 0 1 32864
+use buffer_amp_vop X3 1 0 26070 0 1 10600
+port "GND" 1 60540 36070 61280 37200 m2
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+node "GND" 4 29987.5 60540 36070 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13480037 47480 7508910 34624 7803700 28640 11547800 35640 0 0
+node "GND" 2 16030 43710 37930 v2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 173400 1700 10093650 36390 2447400 8180 7072800 21980 0 0
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+node "m1_57370_23765#" 1 190.046 57370 23765 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22500 870 0 0 0 0 0 0 0 0 0 0
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+node "CTRL5" 22 4269.32 63585 23765 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 630300 21130 0 0 0 0 0 0 0 0 0 0
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+node "CTRL3" 30 2790.44 63645 22265 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 869100 29090 0 0 0 0 0 0 0 0 0 0
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+node "CTRL2" 33 2227.86 63690 35845 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 958800 32080 0 0 0 0 0 0 0 0 0 0
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+node "li_55184_29702#" 49 84.6545 55184 29702 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6160 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_36440_31120#" 60 753.835 36440 31120 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46000 1120 55200 1160 46000 1120 46000 1120 0 0 0 0 0 0
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+node "li_33260_31990#" 18 345.961 33260 31990 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19800 570 19800 570 19800 570 0 0 0 0 0 0 0 0
+node "li_55194_32310#" 49 84.6545 55194 32310 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6160 388 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 21 35447.7 33895 33070 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9350 390 31850 1490 14303260 52952 4159320 21826 3505996 15704 23675860 72316 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_46210_32690#" "m1_47700_36500#" 42.1899
+cap "m1_33455_32800#" "li_33260_31990#" 9.02308
+cap "m3_57735_29855#" "m3_55465_29875#" 34.7604
+cap "m1_61580_36205#" "m1_61570_34715#" 9.41853
+cap "m1_59460_33805#" "m1_59460_34715#" 16.2794
+cap "m1_57380_34715#" "m1_57365_35845#" 12.5874
+cap "CTRL3" "CTRL5" 858.938
+cap "m3_59620_27555#" "m3_61090_27360#" 12.7935
+cap "m1_59460_22855#" "m1_59475_21725#" 12.415
+cap "li_33670_25540#" "li_34160_25810#" 269.043
+cap "m1_61555_33805#" "m1_61595_35305#" 8.58437
+cap "CTRL1" "CTRL3" 1149.97
+cap "CTRL1" "CTRL5" 394.381
+cap "m1_61575_22855#" "m1_61565_21725#" 12.5874
+cap "m1_61585_35845#" "m1_61570_34715#" 12.415
+cap "m1_57355_35305#" "m1_57365_35845#" 28.0594
+cap "li_55174_27882#" "GND" 16.1747
+cap "m1_57380_34715#" "m1_57385_33805#" 16.0624
+cap "li_55178_25280#" "VDD" 47.9598
+cap "m1_59465_35305#" "m1_59490_35845#" 26.9062
+cap "li_34160_25810#" "m1_36045_25020#" 46.7746
+cap "m1_57355_35305#" "m1_57385_33805#" 8.84062
+cap "m1_61580_23765#" "m1_61575_22855#" 16.0624
+cap "GND" "li_34160_25810#" 11.9639
+cap "m3_59300_29490#" "m3_59620_27555#" 13.3787
+cap "m1_57370_21725#" "m1_57350_22855#" 12.2425
+cap "m3_59300_29490#" "m3_57735_29855#" 19.8573
+cap "m1_61580_36205#" "m1_61595_35305#" 15.8143
+cap "m1_50680_31080#" "VDD" 129.876
+cap "li_33670_25540#" "m1_35620_27495#" 19.55
+cap "m1_57370_23765#" "m1_57370_22265#" 9.60938
+cap "m1_57370_22265#" "m1_57350_22855#" 24.716
+cap "li_33670_25540#" "m1_36045_25020#" 61.3119
+cap "li_55194_32310#" "VDD" 47.9598
+cap "m1_61585_35845#" "m1_61595_35305#" 28.0594
+cap "li_33670_25540#" "GND" 380.58
+cap "m1_61575_22265#" "m1_61570_21365#" 16.2536
+cap "m1_36045_25020#" "m1_35620_27495#" 449.643
+cap "GND" "m1_35620_27495#" 389.655
+cap "GND" "VDD" 8298.74
+cap "m1_59465_35305#" "m1_59485_36205#" 15.5946
+cap "GND" "VDD" 2058.96
+cap "GND" "m1_36045_25020#" 269.735
+cap "m1_59465_35305#" "m1_59460_34715#" 25.7604
+cap "m1_59485_36205#" "m1_59490_35845#" 45.51
+cap "m1_59460_22265#" "m1_59480_21365#" 15.5946
+cap "m1_46210_32690#" "m1_48170_36500#" 11.6806
+cap "m1_57390_36205#" "m1_57380_34715#" 9.28951
+cap "m1_59460_34715#" "m1_59490_35845#" 11.8977
+cap "m1_57370_21725#" "m1_57360_21365#" 44.895
+cap "m1_47700_36500#" "m1_48170_36500#" 182.424
+cap "m1_57390_36205#" "m1_57355_35305#" 14.9357
+cap "m1_61570_21365#" "m1_61565_21725#" 45.51
+cap "m3_59620_27555#" "m3_57710_27380#" 20.8038
+cap "GND" "li_55184_29702#" 15.3304
+cap "m1_59480_21365#" "m1_59475_21725#" 45.51
+cap "m1_59460_22855#" "m1_59480_21365#" 9.16049
+cap "GND" "m3_56407_27820#" 0.53563
+cap "m3_55465_29875#" "m3_57480_29855#" 5.24051
+cap "m1_61570_34715#" "m1_61595_35305#" 24.3679
+cap "m3_57710_27380#" "m3_55465_27385#" 35.8937
+cap "m1_57370_22265#" "m1_57360_21365#" 16.0339
+cap "CTRL2" "CTRL4" 997.391
+cap "m1_59465_35305#" "m1_59460_33805#" 9.48125
+cap "m3_57735_29855#" "m3_57480_29855#" 740.74
+cap "m1_57370_23765#" "m1_57350_22855#" 15.4112
+cap "m3_59300_29490#" "m3_61085_29785#" 11.6324
+cap "m1_59445_23765#" "m1_59460_22265#" 9.225
+cap "m1_46210_32690#" "VDD" 142.401
+cap "m1_55108_31074#" "GND" 35.6506
+cap "GND" "m3_55465_29875#" 91.8352
+cap "m1_61575_22265#" "m1_61565_21725#" 28.0594
+cap "m1_33455_32800#" "VDD" 872.735
+cap "m1_57380_34715#" "m1_57355_35305#" 24.3679
+cap "m1_61585_35845#" "m1_61580_36205#" 45.51
+cap "GND" "m3_55465_27385#" 94.463
+cap "m1_61575_22855#" "m1_61570_21365#" 9.54755
+cap "li_52140_31175#" "m1_50680_31080#" 10.5989
+cap "CTRL3" "CTRL2" 2653.32
+cap "CTRL2" "CTRL5" 540.13
+cap "m1_55094_26496#" "GND" 37.5325
+cap "m1_35580_30580#" "m1_36045_25020#" 216.746
+cap "CTRL1" "CTRL2" 2919.45
+cap "m1_59460_34715#" "m1_59485_36205#" 9.03147
+cap "m1_59460_22855#" "m1_59445_23765#" 15.6282
+cap "m1_61580_23765#" "m1_61575_22265#" 9.48125
+cap "m1_61555_33805#" "m1_61570_34715#" 15.6282
+cap "m2_55046_36460#" "GND" 67.8519
+cap "m1_57390_36205#" "m1_57365_35845#" 43.665
+cap "m1_57370_21725#" "m1_57370_22265#" 28.8281
+cap "m1_36045_25020#" "li_36440_31120#" 15.8143
+cap "CTRL3" "CTRL4" 2213.48
+cap "GND" "li_36440_31120#" 517.125
+cap "m1_59460_22855#" "m1_59460_22265#" 26.1085
+cap "CTRL4" "CTRL5" 2150.28
+cap "m1_59460_22265#" "m1_59475_21725#" 27.675
+cap "m1_61575_22265#" "m1_61575_22855#" 26.1085
+cap "CTRL1" "CTRL4" 643.244
+cap "m1_57360_21365#" "m1_57350_22855#" 9.41853
+cap "X3/X2/VDD" "X3/X2/XR1/a_n703_n3602#" -3.3697
+cap "X3/X2/XR1/a_n703_n3602#" "X3/X2/VDD" -0.0337917
+cap "X6/ctrll1" "X3/X2/VDD" 0.912412
+cap "X6/XM1/a_n73_n100#" "X6/GND" 9.2468
+cap "X6/XM1/a_n73_n100#" "X3/X2/VDD" 20.018
+cap "X3/X2/VDD" "X6/GND" 44.0641
+cap "X3/X2/XR1/a_n703_n3602#" "X3/X2/VDD" 66.668
+cap "X3/X2/XR1/a_n703_n3602#" "X6/GND" 22.5779
+cap "X3/X2/VDD" "X7/ctrll1" 11.1345
+cap "X6/XM1/a_n73_n100#" "X6/GND" 45.5256
+cap "X7/ctrll2" "X6/XM1/a_n73_n100#" -3.89729
+cap "X7/ctrll2" "X6/GND" -1.23374
+cap "X3/X2/VDD" "X6/XM1/a_n73_n100#" 30.7291
+cap "X7/ctrll1" "X6/XM1/a_n73_n100#" -28.763
+cap "X3/X2/VDD" "X6/GND" 193.474
+cap "X7/ctrll1" "X6/GND" -237.707
+cap "X3/X2/VDD" "X7/GND" 12.7892
+cap "X6/XM2/a_15_n100#" "X7/GND" 102.77
+cap "X7/GND" "X6/XM1/a_n73_n100#" 13.1882
+cap "X7/ctrll1" "X7/ctrll2" -0.670369
+cap "X7/ctrll2" "X7/GND" 32.2056
+cap "X7/ctrll1" "X7/GND" -104.141
+cap "X7/XM1/a_n73_n100#" "X6/XM2/a_15_n100#" 37.032
+cap "X7/ctrll3" "X7/ctrll2" -3.11344
+cap "X7/ctrll1" "X7/ctrll3" -1.64732
+cap "X7/ctrll2" "X7/XM1/a_n73_n100#" 2.00386
+cap "X7/XM1/a_n73_n100#" "X7/GND" 9.67414
+cap "X6/XM4/a_111_n100#" "X7/GND" 4.32447
+cap "X6/XM3/a_n33_n100#" "X7/GND" 7.07782
+cap "X7/ctrll2" "X6/XM2/a_15_n100#" -6.11419
+cap "X7/ctrll2" "X7/ctrll4" -1.12079
+cap "X7/ctrll1" "X6/XM2/a_15_n100#" -30.8583
+cap "X7/ctrll1" "X3/X2/VDD" 3.96212
+cap "X7/ctrll2" "X6/XM1/a_n73_n100#" 0.0809304
+cap "X7/ctrll1" "X7/ctrll4" -0.967657
+cap "X7/ctrll1" "X6/XM1/a_n73_n100#" -7.98215
+cap "X6/XM2/a_15_n100#" "X7/ctrll1" 1.607
+cap "X7/GND" "X7/XM1/a_n73_n100#" 39.0406
+cap "X7/ctrll2" "X7/XM1/a_n73_n100#" -6.09474
+cap "X7/ctrll2" "X7/ctrll3" -0.15375
+cap "X7/XM1/a_n73_n100#" "X7/ctrll1" -79.5581
+cap "X6/XM2/a_15_n100#" "X7/XM1/a_n73_n100#" 37.032
+cap "X8/XM1/a_n73_n100#" "X7/GND" 6.40472
+cap "X8/XM1/a_n73_n100#" "X7/ctrll2" 0.47556
+cap "X7/GND" "X7/XM2/a_15_n100#" -106.527
+cap "X7/ctrll2" "X7/GND" -6.53394
+cap "X7/GND" "X7/ctrll1" -5.94544
+cap "X7/ctrll2" "X7/ctrll1" 12.1601
+cap "X7/GND" "X6/XM2/a_15_n100#" 9.43138
+cap "X8/XM1/a_n73_n100#" "X7/GND" 35.4381
+cap "X8/XM1/a_n73_n100#" "X7/ctrll2" -10.0239
+cap "X7/XM4/a_111_n100#" "X7/GND" 4.32447
+cap "X7/XM2/a_15_n100#" "X7/ctrll1" -64.9399
+cap "X7/ctrll4" "X7/ctrll2" -1.20701
+cap "X7/GND" "X7/XM3/a_n33_n100#" 7.07782
+cap "X7/XM2/a_15_n100#" "X7/GND" 111.69
+cap "X7/ctrll2" "X7/XM2/a_15_n100#" -5.06652
+cap "X7/GND" "X7/ctrll1" 943.034
+cap "X7/ctrll2" "X7/ctrll1" 0.0583849
+cap "X7/ctrll2" "X7/GND" 1755.6
+cap "X7/ctrll3" "X7/ctrll1" -1.42768
+cap "X8/XM1/a_n73_n100#" "X7/XM2/a_15_n100#" 74.064
+cap "X8/XM1/a_n73_n100#" "X7/ctrll1" -67.9943
+cap "X7/ctrll4" "X7/ctrll1" -0.838636
+cap "X7/ctrll3" "X7/GND" 1.77636e-15
+cap "X7/ctrll3" "X7/ctrll2" -2.69062
+cap "X7/ctrll3" "X7/ctrll2" -2.88281
+cap "X8/XM1/a_n73_n100#" "X7/ctrll2" 29.9205
+cap "X7/GND" "X8/XM1/a_n73_n100#" 62.8066
+cap "X7/ctrll1" "X8/XM2/a_15_n100#" -52.239
+cap "X7/GND" "X7/ctrll2" 823.017
+cap "X8/XM1/a_n73_n100#" "X7/XM2/a_15_n100#" 1.95549
+cap "X7/GND" "X7/XM2/a_15_n100#" 7.86268
+cap "X7/ctrll1" "X7/ctrll4" -0.980559
+cap "X9/XM1/a_n73_n100#" "X8/XM2/a_15_n100#" 37.032
+cap "X7/ctrll1" "X7/ctrll3" -1.66929
+cap "X8/XM2/a_15_n100#" "X7/ctrll2" -6.11419
+cap "X7/GND" "X8/XM2/a_15_n100#" 102.77
+cap "X7/GND" "X8/XM4/a_111_n100#" 4.32447
+cap "X7/ctrll4" "X7/ctrll2" -1.29322
+cap "X7/ctrll1" "X8/XM1/a_n73_n100#" 82.3941
+cap "X7/ctrll1" "X7/ctrll2" 2.32007
+cap "X7/GND" "X8/XM3/a_n33_n100#" 7.07782
+cap "X7/GND" "X7/ctrll1" 894.972
+cap "X7/ctrll1" "X7/XM2/a_15_n100#" 1.16399
+cap "X9/XM1/a_n73_n100#" "X7/ctrll2" 2.00386
+cap "X7/GND" "X9/XM1/a_n73_n100#" 9.67414
+cap "X8/XM2/a_15_n100#" "X9/GND" 9.43138
+cap "X9/ctrll2" "X9/GND" 7.08624
+cap "X9/XM2/a_15_n100#" "X9/GND" -9.85266
+cap "X9/ctrll3" "X9/ctrll1" -0.0878571
+cap "X9/XM1/a_n73_n100#" "X9/ctrll1" -64.5477
+cap "X9/XM1/a_n73_n100#" "X9/GND" 39.0406
+cap "X9/ctrll4" "X9/ctrll1" -0.0516084
+cap "X9/XM1/a_n73_n100#" "X8/XM2/a_15_n100#" 37.032
+cap "X9/ctrll2" "X9/XM1/a_n73_n100#" -6.09474
+cap "X9/ctrll1" "X9/GND" 3.65513
+cap "X9/ctrll2" "X9/ctrll1" 10.1082
+cap "X8/XM2/a_15_n100#" "X9/ctrll1" 1.607
+cap "X9/GND" "X9/XM2/a_15_n100#" 19.6351
+cap "X9/ctrll3" "X9/ctrll1" -0.549107
+cap "X9/GND" "X9/ctrll2" 2961.61
+cap "X9/ctrll1" "X9/XM2/a_15_n100#" -1.11624
+cap "X9/ctrll2" "X9/ctrll4" -0.258645
+cap "X9/ctrll1" "X9/ctrll2" 0.801215
+cap "X9/ctrll3" "X9/ctrll2" -0.576563
+cap "X9/ctrll2" "X9/XM2/a_15_n100#" -0.42963
+cap "X9/ctrll1" "X9/GND" 2458.23
+cap "X9/ctrll1" "X9/ctrll4" -0.322552
+cap "X9/GND" "X9/ctrll1" 1.05919
+cap "X9/ctrll2" "X9/ctrll1" 3.46622
+cap "X9/ctrll1" "X9/XM2/a_15_n100#" 1.0974
+cap "X6/XM1/a_n73_n100#" "X1/X2/VDD" 4.53846
+cap "X1/X2/VDD" "X3/X2/XR1/a_n703_n3602#" 157.84
+cap "X6/XM1/a_n73_n100#" "X6/GND" 4.60912
+cap "X6/GND" "X1/X2/VDD" -22.5265
+cap "X6/GND" "X6/XC6/c2_n451_n200#" 3.83468
+cap "X6/XM3/a_n33_n100#" "X6/GND" 13.2984
+cap "X6/GND" "X6/XM1/a_n73_n100#" 92.4588
+cap "X7/XC6/m4_n551_n300#" "X6/XM1/a_n73_n100#" 1.77346
+cap "X6/XC6/c2_n451_n200#" "X6/GND" 155.221
+cap "X6/XC6/c2_n451_n200#" "X6/XM1/a_n73_n100#" -107.779
+cap "X1/X2/VDD" "X6/XM1/a_n73_n100#" 4.53846
+cap "X6/XM1/a_n73_n100#" "X7/XC6/c2_n451_n200#" 22.154
+cap "X7/XM1/a_n73_n100#" "X6/XM4/a_111_n100#" 117.108
+cap "X7/XM1/a_n73_n100#" "X6/XM1/a_n73_n100#" 35.4709
+cap "X6/XM1/a_n73_n100#" "X7/ctrll4" 28.6575
+cap "X6/XM2/a_15_n100#" "X6/XM5/a_159_n100#" -5.77043
+cap "X7/ctrll4" "X6/XM4/a_111_n100#" 44.5165
+cap "X7/ctrll4" "X7/ctrll2" -1.12079
+cap "X1/X2/BIAS" "X6/XM4/a_111_n100#" 3.64598
+cap "X6/XM1/a_n73_n100#" "X7/ctrll3" 0.0851449
+cap "X7/ctrll1" "X7/ctrll4" -0.967657
+cap "X7/GND" "X6/XM1/a_n73_n100#" 30.9672
+cap "X7/GND" "X6/XM4/a_111_n100#" 13.0854
+cap "X7/ctrll2" "X7/ctrll3" -3.11344
+cap "X7/m1_4820_n890#" "X6/XM4/a_111_n100#" 11.0133
+cap "X7/XM1/a_n73_n100#" "X6/XM3/a_n33_n100#" 69.0731
+cap "X7/XM1/a_n73_n100#" "X7/ctrll4" 2.50565
+cap "X6/XM3/a_n33_n100#" "X7/ctrll4" 0.0163471
+cap "X7/ctrll1" "X7/ctrll3" -1.64732
+cap "X6/XM3/a_n33_n100#" "X7/ctrll3" 14.8925
+cap "X7/m1_4820_n890#" "X6/XM3/a_n33_n100#" 8.64948
+cap "X6/XM5/a_159_n100#" "X6/XM4/a_111_n100#" 0.810749
+cap "X7/GND" "X6/XM3/a_n33_n100#" 156.285
+cap "X7/ctrll4" "X7/ctrll3" -4.52547
+cap "X7/GND" "X7/ctrll4" 1.65029
+cap "X6/XM2/a_15_n100#" "X6/XM4/a_111_n100#" -9.33596
+cap "X7/GND" "X7/ctrll3" 1.59067
+cap "X7/XM1/a_n73_n100#" "X6/XM5/a_159_n100#" 2.23793
+cap "X7/XM1/a_n73_n100#" "X6/XM2/a_15_n100#" 25.4672
+cap "X6/XM2/a_15_n100#" "X7/XC6/c2_n451_n200#" 88.5619
+cap "X6/XM2/a_15_n100#" "X6/XM3/a_n33_n100#" 11.6679
+cap "X7/GND" "X6/XM5/a_159_n100#" 3.39879
+cap "X7/m1_4820_n890#" "X6/XM5/a_159_n100#" 5.21167
+cap "X6/XM2/a_15_n100#" "X7/ctrll4" 0.22744
+cap "X6/XM2/a_15_n100#" "X7/GND" -0.00342334
+cap "X6/XM2/a_15_n100#" "X7/ctrll3" 0.346272
+cap "X7/ctrll5" "X7/ctrll4" -1.41088
+cap "X7/ctrll5" "X7/ctrll3" -1.03781
+cap "X8/XM1/a_n73_n100#" "X7/XM3/a_n33_n100#" 28.433
+cap "X7/XM3/a_n33_n100#" "X7/ctrll3" -69.9727
+cap "X7/XM2/a_15_n100#" "X7/XM4/a_111_n100#" 4.95737
+cap "X7/GND" "X7/XM3/a_n33_n100#" 95.7345
+cap "X7/ctrll4" "X7/XM3/a_n33_n100#" 0.00167427
+cap "X6/XM4/a_111_n100#" "X7/XM3/a_n33_n100#" 11.0133
+cap "X7/ctrll5" "X7/ctrll3" -0.05125
+cap "X6/XM5/a_159_n100#" "X7/GND" 3.43096
+cap "X7/XM1/a_n73_n100#" "X7/XC6/c2_n451_n200#" -125.505
+cap "X6/XM3/a_n33_n100#" "X7/GND" 5.95311
+cap "X6/XM5/a_159_n100#" "X7/XM1/a_n73_n100#" 0.995399
+cap "X6/XM3/a_n33_n100#" "X7/XM1/a_n73_n100#" 43.687
+cap "X8/XM1/a_n73_n100#" "X7/XM1/a_n73_n100#" 17.7355
+cap "X7/GND" "X7/ctrll3" -0.0431854
+cap "X6/XM2/a_15_n100#" "X7/XC6/c2_n451_n200#" 88.5619
+cap "X6/XM1/a_n73_n100#" "X7/XC6/c2_n451_n200#" 22.154
+cap "X7/ctrll4" "X7/GND" -0.0749551
+cap "X7/XM1/a_n73_n100#" "X8/XC6/c2_n451_n200#" 22.154
+cap "X6/XM4/a_111_n100#" "X7/GND" 7.37728
+cap "X7/XM1/a_n73_n100#" "X7/ctrll3" -1.71482
+cap "X7/ctrll4" "X7/XM1/a_n73_n100#" 40.3122
+cap "X6/XM4/a_111_n100#" "X7/XM1/a_n73_n100#" 52.9759
+cap "X7/XM4/a_111_n100#" "X7/XM5/a_159_n100#" -4.4353
+cap "X7/ctrll2" "X7/ctrll3" -0.15375
+cap "X7/ctrll5" "X7/XM4/a_111_n100#" -0.36302
+cap "X6/XM2/a_15_n100#" "X7/XM1/a_n73_n100#" 25.4672
+cap "X6/XM1/a_n73_n100#" "X7/XM1/a_n73_n100#" 17.118
+cap "X8/XM1/a_n73_n100#" "X7/XM4/a_111_n100#" 5.29616
+cap "X6/XM5/a_159_n100#" "X7/XM3/a_n33_n100#" 5.21167
+cap "X6/XM3/a_n33_n100#" "X7/XM3/a_n33_n100#" 8.64948
+cap "X7/ctrll4" "X7/XM4/a_111_n100#" -74.3817
+cap "X7/XM4/a_111_n100#" "X7/GND" -3.40425
+cap "X7/XM4/a_111_n100#" "X7/ctrll4" 475.178
+cap "X7/XM5/a_159_n100#" "X8/XM3/a_n33_n100#" 5.21167
+cap "X7/XM2/a_15_n100#" "X7/XM3/a_n33_n100#" 6.43313
+cap "X7/GND" "X7/XM3/a_n33_n100#" 31.5896
+cap "X7/ctrll4" "X7/ctrll5" -1.51941
+cap "X8/XC6/c2_n451_n200#" "X7/XM1/a_n73_n100#" 22.154
+cap "X8/XM1/a_n73_n100#" "X7/XM4/a_111_n100#" 118.378
+cap "X7/GND" "X7/XM2/a_15_n100#" -0.00342334
+cap "X7/ctrll5" "X7/ctrll3" -0.896875
+cap "X8/XM1/a_n73_n100#" "X7/XM1/a_n73_n100#" 17.7355
+cap "X8/XM1/a_n73_n100#" "X7/XM5/a_159_n100#" 2.23793
+cap "X7/ctrll4" "X7/ctrll1" -0.838636
+cap "X7/ctrll1" "X7/ctrll3" -1.42768
+cap "X7/ctrll4" "X7/ctrll3" -5.91792
+cap "X7/XM4/a_111_n100#" "X7/GND" 13.0527
+cap "X8/XM1/a_n73_n100#" "X7/ctrll4" -25.6471
+cap "X7/XM4/a_111_n100#" "X7/XM2/a_15_n100#" -9.41817
+cap "X8/XM1/a_n73_n100#" "X9/XC6/m4_n551_n300#" 1.77346
+cap "X8/XC6/c2_n451_n200#" "X8/XM1/a_n73_n100#" -125.505
+cap "X8/XM1/a_n73_n100#" "X7/ctrll3" -8.52536
+cap "X7/GND" "X7/XM5/a_159_n100#" 3.39879
+cap "X7/XM2/a_15_n100#" "X7/XM5/a_159_n100#" -5.77043
+cap "X8/XM3/a_n33_n100#" "X7/XM3/a_n33_n100#" 8.64948
+cap "X7/XM4/a_111_n100#" "X1/X3/BIAS" 3.64598
+cap "X7/GND" "X7/ctrll4" 1318.29
+cap "X7/ctrll3" "X7/XM3/a_n33_n100#" 158.24
+cap "X7/XM2/a_15_n100#" "X7/ctrll4" 0.952151
+cap "X8/XM1/a_n73_n100#" "X7/XM3/a_n33_n100#" 62.8379
+cap "X7/GND" "X7/ctrll3" 1318.32
+cap "X7/XM2/a_15_n100#" "X7/ctrll3" 1.52955
+cap "X8/XC6/c2_n451_n200#" "X7/XM2/a_15_n100#" 177.124
+cap "X8/XM1/a_n73_n100#" "X7/XM2/a_15_n100#" 25.4672
+cap "X7/XM4/a_111_n100#" "X7/XM5/a_159_n100#" 0.810749
+cap "X7/ctrll4" "X7/ctrll2" -1.20701
+cap "X7/XM4/a_111_n100#" "X8/XM3/a_n33_n100#" 11.0133
+cap "X7/ctrll2" "X7/ctrll3" -2.69062
+cap "X9/XM1/a_n73_n100#" "X8/XM3/a_n33_n100#" 69.0731
+cap "X8/XM1/a_n73_n100#" "X9/XM1/a_n73_n100#" 35.4709
+cap "X8/XM1/a_n73_n100#" "X9/XC6/c2_n451_n200#" 22.154
+cap "X7/XM4/a_111_n100#" "X8/XM3/a_n33_n100#" 11.0133
+cap "X8/XM1/a_n73_n100#" "X7/XM4/a_111_n100#" 17.7823
+cap "X7/XM5/a_159_n100#" "X7/GND" 3.43096
+cap "X7/ctrll4" "X7/ctrll1" -0.980559
+cap "X8/XM2/a_15_n100#" "X7/ctrll3" 0.346272
+cap "X8/XM2/a_15_n100#" "X8/XM3/a_n33_n100#" 8.9139
+cap "X7/ctrll5" "X7/ctrll4" -1.54112
+cap "X8/XM1/a_n73_n100#" "X7/XM2/a_15_n100#" 25.4672
+cap "X8/XM4/a_111_n100#" "X7/ctrll4" 44.5165
+cap "X7/ctrll4" "X7/GND" 1.57534
+cap "X9/m1_4820_n890#" "X8/XM4/a_111_n100#" 11.0133
+cap "X8/XM5/a_159_n100#" "X9/m1_4820_n890#" 5.21167
+cap "X9/XM1/a_n73_n100#" "X7/ctrll4" 2.50565
+cap "X8/XM3/a_n33_n100#" "X7/XM3/a_n33_n100#" 8.64948
+cap "X8/XM1/a_n73_n100#" "X7/XM3/a_n33_n100#" 26.749
+cap "X8/XM4/a_111_n100#" "X7/GND" 13.3433
+cap "X8/XM1/a_n73_n100#" "X7/ctrll3" 31.3323
+cap "X8/XM5/a_159_n100#" "X8/XM4/a_111_n100#" 0.810749
+cap "X8/XM5/a_159_n100#" "X7/GND" 3.39879
+cap "X8/XM3/a_n33_n100#" "X7/ctrll3" 14.8925
+cap "X9/XM1/a_n73_n100#" "X8/XM4/a_111_n100#" 117.108
+cap "X8/XM2/a_15_n100#" "X7/ctrll4" 0.22744
+cap "X7/ctrll2" "X7/ctrll3" -2.88281
+cap "X9/XM1/a_n73_n100#" "X8/XM5/a_159_n100#" 2.23793
+cap "X7/XM4/a_111_n100#" "X7/GND" 7.37728
+cap "X8/XM2/a_15_n100#" "X7/GND" -0.00342334
+cap "X8/XM3/a_n33_n100#" "X7/XM5/a_159_n100#" 5.21167
+cap "X8/XM1/a_n73_n100#" "X7/XM5/a_159_n100#" 0.316277
+cap "X8/XM2/a_15_n100#" "X8/XM4/a_111_n100#" -8.6863
+cap "X1/X3/BIAS" "X8/XM4/a_111_n100#" 3.64598
+cap "X8/XM5/a_159_n100#" "X8/XM2/a_15_n100#" -5.77043
+cap "X9/XM1/a_n73_n100#" "X8/XM2/a_15_n100#" 25.4672
+cap "X8/XM2/a_15_n100#" "X9/XC6/c2_n451_n200#" 88.5619
+cap "X7/ctrll4" "X7/ctrll3" -5.29132
+cap "X7/ctrll1" "X7/ctrll3" -1.66929
+cap "X8/XM1/a_n73_n100#" "X7/ctrll4" -26.1513
+cap "X8/XM3/a_n33_n100#" "X7/ctrll4" 0.0180267
+cap "X9/m1_4820_n890#" "X8/XM3/a_n33_n100#" 8.64948
+cap "X7/GND" "X7/XM3/a_n33_n100#" 5.95311
+cap "X7/ctrll5" "X7/ctrll3" -0.909688
+cap "X7/ctrll3" "X7/GND" 1.54748
+cap "X7/ctrll2" "X7/ctrll4" -1.29322
+cap "X8/XM3/a_n33_n100#" "X7/GND" 134.501
+cap "X9/GND" "X9/ctrll2" 1.47129
+cap "X9/GND" "X9/ctrll5" 4.50083
+cap "X9/ctrll4" "X9/XM3/a_n33_n100#" 0.00167427
+cap "X8/XM3/a_n33_n100#" "X9/GND" 5.95311
+cap "X9/GND" "X8/XM5/a_159_n100#" 3.43096
+cap "X9/XM1/a_n73_n100#" "X9/ctrll4" 113.618
+cap "X9/GND" "X9/ctrll1" 1.22266
+cap "X9/XM1/a_n73_n100#" "X8/XM1/a_n73_n100#" 17.118
+cap "X9/ctrll3" "X9/XM3/a_n33_n100#" -78.6664
+cap "X9/ctrll4" "X9/ctrll3" 6.68346
+cap "X9/XM1/a_n73_n100#" "X9/ctrll3" -1.71482
+cap "X9/XM3/a_n33_n100#" "X8/XM4/a_111_n100#" 11.0133
+cap "X9/XM1/a_n73_n100#" "X8/XM4/a_111_n100#" 52.9759
+cap "X9/ctrll4" "X9/ctrll2" 5.91459
+cap "X9/GND" "X9/XM2/a_15_n100#" -14.4464
+cap "X9/ctrll3" "X9/ctrll2" 3.56053
+cap "X9/ctrll4" "X9/ctrll5" 0.377628
+cap "X9/XM1/a_n73_n100#" "X8/XM2/a_15_n100#" 25.4672
+cap "X9/XM4/a_111_n100#" "X9/GND" -11.1522
+cap "X8/XM5/a_159_n100#" "X9/XM3/a_n33_n100#" 5.21167
+cap "X9/ctrll4" "X9/ctrll1" 4.89913
+cap "X9/ctrll5" "X9/ctrll3" 0.315762
+cap "X8/XM1/a_n73_n100#" "X9/XC6/c2_n451_n200#" 22.154
+cap "X8/XM3/a_n33_n100#" "X9/XM3/a_n33_n100#" 8.64948
+cap "X9/XM1/a_n73_n100#" "X9/XC6/c2_n451_n200#" -125.505
+cap "X9/XM1/a_n73_n100#" "X8/XM5/a_159_n100#" 0.995399
+cap "X8/XM3/a_n33_n100#" "X9/XM1/a_n73_n100#" 43.687
+cap "X9/ctrll1" "X9/ctrll3" 2.88683
+cap "X9/ctrll5" "X9/ctrll2" 0.349432
+cap "X9/GND" "X9/XM3/a_n33_n100#" -9.10156
+cap "X9/ctrll4" "X9/GND" 49.81
+cap "X9/GND" "X9/ctrll3" 14.2135
+cap "X8/XM2/a_15_n100#" "X9/XC6/c2_n451_n200#" 88.5619
+cap "X9/ctrll1" "X9/ctrll5" 0.292857
+cap "X9/ctrll3" "X9/XM2/a_15_n100#" 0.0606183
+cap "X9/ctrll4" "X9/XM4/a_111_n100#" -79.5872
+cap "X9/GND" "X8/XM4/a_111_n100#" 7.37728
+cap "X9/XM4/a_111_n100#" "X9/ctrll1" 2.1948
+cap "X9/ctrll4" "X9/ctrll1" 3.49976
+cap "X9/ctrll2" "X9/XM5/a_159_n100#" 2.53899
+cap "X9/ctrll2" "X9/GND" 12.984
+cap "X9/ctrll3" "X9/ctrll1" 3.71424
+cap "X9/ctrll1" "X9/ctrll5" 1.69064
+cap "X9/ctrll3" "X9/XM3/a_n33_n100#" 245.5
+cap "X9/ctrll1" "X9/XM5/a_159_n100#" 1.02881
+cap "X9/ctrll1" "X9/GND" 5.30047
+cap "X9/ctrll4" "X9/XM2/a_15_n100#" 0.33612
+cap "X9/GND" "X9/XM3/a_n33_n100#" 16.033
+cap "X9/ctrll3" "X9/XM2/a_15_n100#" 0.978292
+cap "X9/XM4/a_111_n100#" "X9/ctrll4" 676.382
+cap "X9/ctrll3" "X9/XM4/a_111_n100#" 7.02857
+cap "X9/ctrll3" "X9/ctrll4" 14.1259
+cap "X9/ctrll4" "X9/ctrll5" 7.586
+cap "X9/ctrll2" "X9/XM3/a_n33_n100#" 2.70826
+cap "X9/ctrll3" "X9/ctrll5" 5.1922
+cap "X9/ctrll4" "X9/XM5/a_159_n100#" 4.81304
+cap "X9/ctrll4" "X9/GND" 1943.96
+cap "X9/XM4/a_111_n100#" "X9/GND" 15.3498
+cap "X9/ctrll3" "X9/XM5/a_159_n100#" 3.29464
+cap "X9/ctrll3" "X9/GND" 2140.5
+cap "X9/XM5/a_159_n100#" "X9/ctrll5" 0.525481
+cap "X9/ctrll1" "X9/XM3/a_n33_n100#" 1.0974
+cap "X9/ctrll2" "X9/XM4/a_111_n100#" 5.41651
+cap "X9/ctrll2" "X9/ctrll4" 14.3672
+cap "X9/GND" "X9/XM5/a_159_n100#" 1.96349
+cap "X9/ctrll2" "X9/ctrll3" 12.3608
+cap "X9/ctrll2" "X9/ctrll5" 4.59293
+cap "X9/ctrll1" "X9/XM5/a_159_n100#" 1.02881
+cap "X9/ctrll1" "X9/ctrll5" 1.98349
+cap "X9/ctrll1" "X9/ctrll4" 8.03945
+cap "X9/ctrll1" "X9/GND" 5.30047
+cap "X9/ctrll1" "X9/XM4/a_111_n100#" 2.1948
+cap "X9/ctrll1" "X9/ctrll3" 6.13763
+cap "X9/XM3/a_n33_n100#" "X9/ctrll1" 1.0974
+cap "bias_calc_0/XM39/a_n465_n188#" "bias_calc_0/GND" 9.66338e-13
+cap "bias_calc_0/BIASOUT" "bias_calc_0/GND" 1.77636e-15
+cap "bias_calc_0/GND" "bias_calc_0/BIASOUT" 37.8198
+cap "bias_calc_0/GND" "bias_calc_0/XM39/a_n465_n188#" 65.3014
+cap "bias_calc_0/GND" "bias_calc_0/XM38/a_1821_n197#" 5.23919
+cap "bias_calc_0/GND" "X3/X6/XC2/c1_n2050_n3000#" 22.2996
+cap "bias_calc_0/XR20/a_n415_n1702#" "X3/X6/XC2/c1_n2050_n3000#" 61.3158
+cap "bias_calc_0/BIASOUT" "bias_calc_0/XR20/a_n415_n1702#" 3.92069
+cap "X3/BIAS" "X3/X6/XC2/c1_n2050_n3000#" -17.241
+cap "X3/BIAS" "X3/X6/GND" -26.4563
+cap "X3/X6/XC2/c1_n2050_n3000#" "X3/X6/GND" 1152.61
+cap "X1/X2/XR17/a_n415_n1322#" "X6/XC1/m4_n551_n300#" 14.3496
+cap "X1/X2/VDD" "X6/XC2/m4_n651_n300#" -217.754
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/VDD" -211.95
+cap "X6/XC6/c2_n451_n200#" "X1/X2/XR17/a_n415_n1322#" 68.3851
+cap "X1/X2/VDD" "X1/X2/XM4/a_n945_n188#" 1.59755
+cap "X6/XC6/c2_n451_n200#" "X1/X2/VDD" -153.003
+cap "X7/XC1/m4_n551_n300#" "X6/m1_4820_n1420#" 1.77346
+cap "X6/m1_4820_n1420#" "X1/X2/GND" 77.0707
+cap "X1/X2/VDD" "X1/X2/XR17/a_n415_n1322#" 22.6129
+cap "X1/X2/BIAS" "X7/ctrll5" 0.568585
+cap "X1/X2/GND" "X6/XC6/c2_n451_n200#" 306.069
+cap "X1/X2/VDD" "X1/X2/GND" -953.372
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/GND" 222.432
+cap "X6/XM3/a_n33_n100#" "X6/XC6/c2_n451_n200#" -41.3419
+cap "X1/X2/VDD" "X1/X2/BIAS" 2.00797
+cap "X1/X2/VDD" "X6/XM3/a_n33_n100#" 308.106
+cap "X6/XM3/a_n33_n100#" "X7/XC2/m4_n651_n300#" 0.88673
+cap "X6/m1_4820_n1420#" "X7/ctrll5" -0.00593505
+cap "X6/XM3/a_n33_n100#" "X1/X2/GND" 21.3127
+cap "X1/X2/VDD" "X7/ctrll5" 4.63585
+cap "X6/XC6/c2_n451_n200#" "X7/XC6/c2_n451_n200#" 9.37149
+cap "X6/m1_4820_n1420#" "X6/XC6/c2_n451_n200#" -129.311
+cap "X6/XM3/a_n33_n100#" "X1/X2/BIAS" 16.7554
+cap "X6/m1_4820_n1420#" "X7/XC6/c2_n451_n200#" 80.3307
+cap "X1/X2/GND" "X1/X2/VDD" 0.519889
+cap "X7/ctrll5" "X6/XM4/a_111_n100#" 1.05837
+cap "X6/XM5/a_159_n100#" "X7/XC1/m4_n551_n300#" 122.069
+cap "X7/XC6/c2_n451_n200#" "X6/XM3/a_n33_n100#" 21.9419
+cap "X1/X2/VDD" "X6/XM4/a_111_n100#" 67.8618
+cap "X6/XM5/a_159_n100#" "X7/ctrll5" 31.7116
+cap "X1/X2/GND" "X6/XM5/a_159_n100#" 3.87586
+cap "X6/XM5/a_159_n100#" "X1/X2/VDD" 81.8543
+cap "X1/X2/VDD" "X7/m1_4820_n890#" -34.028
+cap "X6/XM5/a_159_n100#" "X6/XM4/a_111_n100#" 67.5753
+cap "X6/XM4/a_111_n100#" "X7/m1_4820_n890#" 45.5804
+cap "X1/X2/XM4/a_927_n100#" "X7/ctrll5" 4.76526
+cap "X6/XM2/a_n73_n100#" "X1/X2/XR17/a_n415_n1322#" 1.84187
+cap "X6/XM5/a_159_n100#" "X7/m1_4820_n890#" 99.9433
+cap "X7/XM2/a_n73_n100#" "X6/XM5/a_159_n100#" 7.70348
+cap "X1/X2/VDD" "X7/XC6/c2_n451_n200#" -35.8774
+cap "X1/X2/BIAS" "X6/XM2/a_n73_n100#" 18.1207
+cap "X6/m1_4820_n1420#" "X6/XM2/a_n73_n100#" -1.92132
+cap "X6/m1_4820_n1420#" "X6/XM3/a_n33_n100#" 58.9542
+cap "X1/X2/BIAS" "X6/XM3/a_n33_n100#" -191.219
+cap "X1/X2/XM4/a_927_n100#" "X6/XM5/a_159_n100#" 0.468188
+cap "X6/XM2/a_n73_n100#" "X6/XM3/a_n33_n100#" 50.8705
+cap "X6/m1_4820_n1420#" "X7/XC1/m4_n551_n300#" 60.8535
+cap "X7/ctrll5" "X7/ctrll4" -1.41088
+cap "X7/ctrll5" "X1/X2/XR17/a_n415_n1322#" -0.708321
+cap "X7/XC1/m4_n551_n300#" "X6/XM3/a_n33_n100#" 48.4932
+cap "X7/ctrll3" "X7/ctrll5" -1.03781
+cap "X1/X2/BIAS" "X7/ctrll5" 9.7185
+cap "X6/m1_4820_n1420#" "X7/ctrll5" 2.65225
+cap "X6/m1_4820_n1420#" "X1/X2/GND" 33.3793
+cap "X1/X2/BIAS" "X1/X2/VDD" 36.6028
+cap "X7/ctrll5" "X6/XM3/a_n33_n100#" -0.0497906
+cap "X1/X2/GND" "X6/XM3/a_n33_n100#" 21.3127
+cap "X6/m1_4820_n1420#" "X6/XM4/a_111_n100#" 82.6367
+cap "X1/X2/BIAS" "X6/XM4/a_111_n100#" 55.2357
+cap "X1/X2/VDD" "X6/XM3/a_n33_n100#" -473.543
+cap "X6/XM2/a_n73_n100#" "X6/XM4/a_111_n100#" -2.27869
+cap "X6/XM5/a_159_n100#" "X1/X2/XR17/a_n415_n1322#" -0.0640187
+cap "X7/XC1/m4_n551_n300#" "X7/ctrll5" 3.62156
+cap "X6/m1_4820_n1420#" "X6/XM5/a_159_n100#" -28.726
+cap "X1/X2/BIAS" "X6/XM5/a_159_n100#" 69.8449
+cap "X1/X2/BIAS" "X7/m1_4820_n890#" 12.4344
+cap "X1/X2/XM4/a_927_n100#" "X1/X2/XR17/a_n415_n1322#" 1.84187
+cap "X7/XC1/m4_n551_n300#" "X6/XM4/a_111_n100#" 69.4118
+cap "X6/XM3/a_n33_n100#" "X7/m1_4820_n890#" 31.8438
+cap "X6/XM2/a_n73_n100#" "X1/X2/XM4/a_927_n100#" 0.356612
+cap "X1/X2/VDD" "X7/ctrll5" 0.572184
+cap "X7/XM3/a_n33_n100#" "X7/m1_4820_n1420#" 58.9418
+cap "X6/XM5/a_159_n100#" "X7/m1_4820_n1420#" 54.2945
+cap "X7/XM2/a_n73_n100#" "X1/X2/VDD" 11.2608
+cap "X6/m1_4820_n1420#" "X7/XC6/c2_n451_n200#" 80.3307
+cap "X6/XM3/a_n33_n100#" "X7/XC6/c2_n451_n200#" 21.9419
+cap "X1/X2/VDD" "X7/XM4/a_111_n100#" -110.548
+cap "X7/XM4/a_111_n100#" "X8/XC2/m4_n651_n300#" 17.5045
+cap "X1/X2/BIAS" "X7/XM3/a_n33_n100#" 78.103
+cap "X7/XM2/a_n73_n100#" "X7/XM4/a_111_n100#" -202.903
+cap "X8/XC1/m4_n551_n300#" "X7/XM3/a_n33_n100#" 24.2466
+cap "X1/X2/VDD" "X7/ctrll5" 9.69209
+cap "X1/X2/VDD" "X6/XM1/a_n175_n274#" 1.84095
+cap "X7/XM5/a_159_n100#" "X7/m1_4820_n1420#" 6.2556
+cap "X7/XM2/a_n73_n100#" "X7/ctrll5" -0.0739475
+cap "X8/XC1/m4_n551_n300#" "X7/m1_4820_n1420#" 37.1701
+cap "X7/XM3/a_n33_n100#" "X6/XM3/a_n33_n100#" 15.1736
+cap "X7/XM2/a_n73_n100#" "X6/XM1/a_n175_n274#" 0.290188
+cap "X6/XC2/c2_n551_n200#" "X7/XC6/c2_n451_n200#" 9.37149
+cap "X1/X2/VDD" "X7/XM3/a_n33_n100#" 531.079
+cap "X7/m1_4820_n1420#" "X6/m1_4820_n1420#" 42.5006
+cap "X7/XM3/a_n33_n100#" "X8/XC2/m4_n651_n300#" 15.9219
+cap "X7/XM4/a_111_n100#" "X7/ctrll5" -56.2122
+cap "X7/XM4/a_111_n100#" "X6/XM1/a_n175_n274#" -18.6353
+cap "X6/XM3/a_n33_n100#" "X7/m1_4820_n1420#" 23.107
+cap "X7/XM2/a_n73_n100#" "X7/XM3/a_n33_n100#" 50.615
+cap "X6/XM4/a_111_n100#" "X7/XM3/a_n33_n100#" 21.2875
+cap "X7/XM2/a_n73_n100#" "X6/XM5/a_159_n100#" 7.70348
+cap "X8/XC6/c2_n451_n200#" "X7/XC6/c2_n451_n200#" 9.37149
+cap "X7/ctrll5" "X6/XM1/a_n175_n274#" -0.317671
+cap "X7/XM2/a_n73_n100#" "X7/m1_4820_n1420#" -1.92132
+cap "X6/XM4/a_111_n100#" "X7/m1_4820_n1420#" 32.4176
+cap "X7/XM3/a_n33_n100#" "X7/XC6/c2_n451_n200#" 13.5921
+cap "X7/ctrll3" "X7/ctrll5" -0.05125
+cap "X7/XM4/a_111_n100#" "X7/m1_4820_n1420#" -45.315
+cap "X1/X2/VDD" "X7/XM5/a_159_n100#" -29.138
+cap "X7/XM3/a_n33_n100#" "X7/ctrll5" -0.00123496
+cap "X7/XM3/a_n33_n100#" "X8/XC6/c2_n451_n200#" 21.9419
+cap "X7/m1_4820_n1420#" "X7/XC6/c2_n451_n200#" -136.945
+cap "X7/XM2/a_n73_n100#" "X1/X2/BIAS" 13.094
+cap "X7/ctrll5" "X7/m1_4820_n1420#" 36.7471
+cap "X8/XC6/c2_n451_n200#" "X7/m1_4820_n1420#" 38.4368
+cap "X7/XM3/a_n33_n100#" "X6/XM5/a_159_n100#" 55.438
+cap "X7/XM5/a_159_n100#" "X7/XM4/a_111_n100#" -210.329
+cap "X8/XC1/m4_n551_n300#" "X7/XM4/a_111_n100#" 26.6566
+cap "X1/X2/BIAS" "X7/XM4/a_111_n100#" -19.3316
+cap "X8/m1_4820_n1420#" "X7/XM4/a_111_n100#" 69.4118
+cap "X7/XM5/a_159_n100#" "X7/ctrll5" 31.7158
+cap "X8/m1_4820_n1420#" "X9/XC1/m4_n551_n300#" 1.77346
+cap "X8/m1_4820_n1420#" "X7/m1_4820_n1420#" 43.118
+cap "X8/XM3/a_n33_n100#" "X7/XM3/a_n33_n100#" 15.9219
+cap "X8/m1_4820_n1420#" "X7/XM5/a_159_n100#" 122.069
+cap "X8/XM2/a_n73_n100#" "X7/XM5/a_159_n100#" 7.70348
+cap "X1/X2/XR16/a_n415_n1322#" "X7/XM2/a_n73_n100#" 1.48767
+cap "X1/X3/VDD" "X7/ctrll5" 3.04775
+cap "X1/X3/BIAS" "X7/ctrll5" 6.90976
+cap "X1/X2/XR16/a_n415_n1322#" "X7/XM5/a_159_n100#" -0.0640187
+cap "X1/X3/XM4/a_927_n100#" "X7/ctrll5" 3.15188
+cap "X7/XM4/a_111_n100#" "X8/XM3/a_n33_n100#" 45.5804
+cap "X7/XM4/a_111_n100#" "X7/XM2/a_n73_n100#" -2.00525
+cap "X8/XM3/a_n33_n100#" "X7/XM5/a_159_n100#" 99.9433
+cap "X7/XM4/a_111_n100#" "X7/m1_4820_n1420#" 82.6367
+cap "X9/XC6/c2_n451_n200#" "X8/XC6/c2_n451_n200#" 9.37149
+cap "X7/XM4/a_111_n100#" "X7/XM5/a_159_n100#" 67.5753
+cap "X1/X2/XR16/a_n415_n1322#" "X1/X3/VDD" 2.27927
+cap "X7/m1_4820_n1420#" "X7/XM5/a_159_n100#" -28.726
+cap "X8/m1_4820_n1420#" "X8/XC6/c2_n451_n200#" -136.945
+cap "X8/m1_4820_n1420#" "X7/ctrll5" 3.41891
+cap "X7/XC6/c2_n451_n200#" "X8/XC6/c2_n451_n200#" 9.37149
+cap "X1/X3/VDD" "X8/XM3/a_n33_n100#" 239.875
+cap "X7/XM3/a_n33_n100#" "X8/XC6/c2_n451_n200#" 21.9419
+cap "X7/XM5/a_159_n100#" "X1/X3/GND" 7.34768
+cap "X1/X3/BIAS" "X7/XM2/a_n73_n100#" 2.66729
+cap "X8/XM3/a_n33_n100#" "X1/X3/BIAS" 174.624
+cap "X1/X3/VDD" "X7/XM4/a_111_n100#" 217.682
+cap "X1/X3/VDD" "X7/XM2/a_n73_n100#" 2.29387
+cap "X7/XM4/a_111_n100#" "X1/X3/BIAS" 75.4875
+cap "X1/X3/VDD" "X7/XM5/a_159_n100#" 96.2183
+cap "X8/m1_4820_n1420#" "X7/XM3/a_n33_n100#" 24.2466
+cap "X8/XM3/a_n33_n100#" "X9/XC2/m4_n651_n300#" 0.88673
+cap "X1/X3/BIAS" "X7/XM5/a_159_n100#" 60.3316
+cap "X1/X2/XR16/a_n415_n1322#" "X7/ctrll5" 895.328
+cap "X7/ctrll3" "X7/ctrll5" -0.896875
+cap "X8/XM3/a_n33_n100#" "X8/XC6/c2_n451_n200#" 13.5921
+cap "X7/ctrll4" "X7/ctrll5" -1.51941
+cap "X1/X3/VDD" "X1/X3/BIAS" -3.76928
+cap "X7/ctrll5" "X7/XM2/a_n73_n100#" 420.746
+cap "X7/m1_4820_n1420#" "X8/XC6/c2_n451_n200#" 160.571
+cap "X7/XM4/a_111_n100#" "X7/ctrll5" 144.427
+cap "X7/m1_4820_n1420#" "X7/ctrll5" 104.934
+cap "X8/m1_4820_n1420#" "X8/XM3/a_n33_n100#" 58.9418
+cap "X1/X3/BIAS" "X8/XM4/a_111_n100#" 44.2406
+cap "X8/XM5/a_159_n100#" "X7/ctrll5" 31.7382
+cap "X7/ctrll5" "X9/XC1/m4_n551_n300#" 3.62754
+cap "X7/XM3/a_n33_n100#" "X8/m1_4820_n1420#" 12.0737
+cap "X8/XM5/a_159_n100#" "X1/X3/GND" 3.97189
+cap "X1/X3/VDD" "X8/XM4/a_111_n100#" 85.4338
+cap "X9/m1_4820_n890#" "X8/XM4/a_111_n100#" 45.5804
+cap "X7/ctrll5" "X8/XM2/a_n73_n100#" -0.0739475
+cap "X8/XM5/a_159_n100#" "X9/XC1/m4_n551_n300#" 122.069
+cap "X8/m1_4820_n1420#" "X9/XC6/c2_n451_n200#" 80.3307
+cap "X1/X3/BIAS" "X8/XM3/a_n33_n100#" 164.308
+cap "X1/X3/BIAS" "X1/X3/VDD" -1.31275
+cap "X7/ctrll5" "X8/m1_4820_n1420#" 112.537
+cap "X7/XM5/a_159_n100#" "X8/XM2/a_n73_n100#" 7.70348
+cap "X1/X3/BIAS" "X9/m1_4820_n890#" -12.7255
+cap "X7/ctrll5" "X8/XM4/a_111_n100#" 1.08494
+cap "X1/X3/VDD" "X8/XM3/a_n33_n100#" 109.991
+cap "X7/XM2/a_n175_n274#" "X1/X3/VDD" 4.27802
+cap "X9/m1_4820_n890#" "X8/XM3/a_n33_n100#" 31.8438
+cap "X7/XM3/a_n33_n100#" "X8/XM3/a_n33_n100#" 7.92838
+cap "X7/m1_4820_n1420#" "X8/m1_4820_n1420#" 25.3826
+cap "X8/m1_4820_n1420#" "X7/XM4/a_111_n100#" 14.2055
+cap "X8/XM5/a_159_n100#" "X8/m1_4820_n1420#" -28.726
+cap "X7/XM5/a_159_n100#" "X8/m1_4820_n1420#" 17.2515
+cap "X1/X3/BIAS" "X9/XC6/c2_n451_n200#" -16.396
+cap "X8/m1_4820_n1420#" "X9/XC1/m4_n551_n300#" 60.8535
+cap "X1/X3/BIAS" "X7/ctrll5" 3.37732
+cap "X8/XM5/a_159_n100#" "X8/XM4/a_111_n100#" 67.5753
+cap "X9/XC6/c2_n451_n200#" "X8/XM3/a_n33_n100#" 21.9419
+cap "X8/XM4/a_111_n100#" "X9/XC1/m4_n551_n300#" 69.4118
+cap "X8/m1_4820_n1420#" "X8/XM2/a_n73_n100#" -1.92132
+cap "X7/XM2/a_n175_n274#" "X7/ctrll5" -0.795931
+cap "X7/ctrll5" "X7/ctrll4" -1.54112
+cap "X7/ctrll5" "X8/XM3/a_n33_n100#" -0.0242482
+cap "X7/ctrll5" "X1/X3/XM4/a_927_n100#" 1.61338
+cap "X8/XM4/a_111_n100#" "X8/XM2/a_n73_n100#" -2.27869
+cap "X1/X3/BIAS" "X8/XM5/a_159_n100#" 59.8507
+cap "X7/ctrll5" "X1/X3/VDD" 6.65601
+cap "X8/XM5/a_159_n100#" "X9/XM2/a_n73_n100#" 7.70348
+cap "X8/XM4/a_111_n100#" "X8/m1_4820_n1420#" 82.6367
+cap "X7/XM4/a_111_n100#" "X8/XM3/a_n33_n100#" 9.32825
+cap "X7/XM2/a_n175_n274#" "X8/XM5/a_159_n100#" -0.0640187
+cap "X7/XM5/a_159_n100#" "X8/XM3/a_n33_n100#" 31.1131
+cap "X1/X3/BIAS" "X8/XM2/a_n73_n100#" 15.7612
+cap "X8/XM5/a_159_n100#" "X1/X3/VDD" 114.456
+cap "X8/XM5/a_159_n100#" "X9/m1_4820_n890#" 99.9433
+cap "X9/XC1/m4_n551_n300#" "X8/XM3/a_n33_n100#" 48.4932
+cap "X8/XM2/a_n73_n100#" "X8/XM3/a_n33_n100#" 50.615
+cap "X7/XM2/a_n175_n274#" "X8/XM2/a_n73_n100#" 1.77785
+cap "X7/ctrll3" "X7/ctrll5" -0.909688
+cap "X1/X3/VDD" "X8/XM2/a_n73_n100#" 10.0617
+cap "X9/XC6/c2_n451_n200#" "X9/XM3/a_n33_n100#" -40.6347
+cap "X8/XM3/a_n33_n100#" "X9/XM3/a_n33_n100#" 15.1736
+cap "X9/ctrll5" "X9/XM3/a_n33_n100#" -0.000124048
+cap "X9/XM3/a_n33_n100#" "X9/XM2/a_n73_n100#" -0.255471
+cap "X9/m1_4820_n1420#" "X8/XM5/a_159_n100#" 54.2945
+cap "X8/XM4/a_111_n100#" "X9/XM3/a_n33_n100#" 21.2875
+cap "X9/ctrll5" "X9/ctrll2" 8.36062
+cap "X9/ctrll5" "X9/ctrll3" 10.2123
+cap "X9/ctrll5" "X9/ctrll4" 13.5644
+cap "CTRL1" "X9/ctrll5" 7.00074
+cap "X8/XM3/a_n33_n100#" "X9/m1_4820_n1420#" 23.107
+cap "X9/XC6/c2_n451_n200#" "X9/m1_4820_n1420#" -136.945
+cap "X9/ctrll5" "X9/m1_4820_n1420#" 131.305
+cap "X9/ctrll2" "X9/XM2/a_n73_n100#" 0.882775
+cap "X9/ctrll3" "X9/XM2/a_n73_n100#" 1.10259
+cap "X9/ctrll4" "X9/XM2/a_n73_n100#" 1.49797
+cap "X8/XM5/a_159_n100#" "X9/XM2/a_n73_n100#" 7.70348
+cap "CTRL1" "X9/XM2/a_n73_n100#" 0.733598
+cap "X9/m1_4820_n1420#" "X9/XM2/a_n73_n100#" -12.6082
+cap "X8/XM3/a_n33_n100#" "X9/XC6/c2_n451_n200#" 21.9419
+cap "X9/m1_4820_n1420#" "X8/XM4/a_111_n100#" 32.4176
+cap "X9/m1_4820_n1420#" "X8/m1_4820_n1420#" 42.5006
+cap "X9/XM4/a_111_n100#" "X9/XM2/a_n73_n100#" -17.2235
+cap "X9/XC6/c2_n451_n200#" "X8/XC2/c2_n551_n200#" 9.37149
+cap "X9/ctrll5" "X9/XM2/a_n73_n100#" 63.353
+cap "X9/ctrll5" "X8/XM1/a_n175_n274#" -0.0084038
+cap "X9/XC6/c2_n451_n200#" "X8/m1_4820_n1420#" 80.3307
+cap "X8/XM5/a_159_n100#" "X9/XM3/a_n33_n100#" 55.438
+cap "X9/m1_4820_n1420#" "X9/XM3/a_n33_n100#" -0.00249374
+cap "X1/X3/BIAS" "X9/XM3/a_n33_n100#" 95.0158
+cap "X8/XM1/a_n175_n274#" "X9/XM2/a_n73_n100#" -0.0640187
+cap "X9/ctrll2" "X9/ctrll5" 27.2193
+cap "X1/X3/XR16/a_n415_n1322#" "X9/ctrll5" 1168.6
+cap "CTRL1" "X9/XM5/a_159_n100#" 2.26338
+cap "CTRL1" "X9/ctrll5" 7.86514
+cap "X9/ctrll2" "X9/XM2/a_n73_n100#" 7.79575
+cap "X9/ctrll4" "X9/XM5/a_159_n100#" 10.5887
+cap "X9/ctrll3" "X9/XM5/a_159_n100#" 7.24821
+cap "X9/ctrll5" "X9/XM4/a_111_n100#" 187.022
+cap "X9/XM2/a_n73_n100#" "CTRL1" 3.18208
+cap "X9/ctrll5" "X9/ctrll4" 51.2295
+cap "X9/ctrll5" "X9/XM5/a_159_n100#" 48.8495
+cap "X9/ctrll3" "X9/ctrll5" 34.6501
+cap "X9/m1_4820_n1420#" "X9/ctrll5" 136.906
+cap "X9/XM2/a_n73_n100#" "X9/XM4/a_111_n100#" 6.73468
+cap "X9/XM2/a_n73_n100#" "X9/ctrll4" 14.3159
+cap "X9/XM2/a_n73_n100#" "X9/XM5/a_159_n100#" 32.1421
+cap "X9/ctrll2" "X9/XM5/a_159_n100#" 5.58578
+cap "X9/XM2/a_n73_n100#" "X9/ctrll3" 10.0047
+cap "X9/XM2/a_n73_n100#" "X9/ctrll5" 554.28
+cap "X9/XM2/a_n73_n100#" "CTRL1" 3.18208
+cap "X9/ctrll5" "CTRL1" 14.1323
+cap "X9/XM5/a_159_n100#" "CTRL1" 2.26338
+cap "bias_calc_0/GND" "bias_calc_0/XM37/a_1763_n100#" 1.06581e-14
+cap "bias_calc_0/GND" "bias_calc_0/BIASOUT" -2.27374e-13
+cap "bias_calc_0/XM37/a_1763_n100#" "bias_calc_0/w_17930_210#" -1.15513
+cap "bias_calc_0/GND" "bias_calc_0/XM39/a_n465_n188#" 2.72848e-12
+cap "bias_calc_0/GND" "bias_calc_0/XM37/a_1821_n197#" 3.55271e-15
+cap "bias_calc_0/GND" "bias_calc_0/w_17930_210#" 1.42109e-14
+cap "bias_calc_0/BIASOUT" "bias_calc_0/XM39/a_n465_n188#" 32.9948
+cap "bias_calc_0/BIASOUT" "bias_calc_0/w_17930_210#" -0.727687
+cap "bias_calc_0/GND" "bias_calc_0/XM39/a_n465_n188#" 19.6966
+cap "bias_calc_0/GND" "bias_calc_0/w_17930_210#" 0.000786164
+cap "bias_calc_0/GND" "bias_calc_0/BIASOUT" 36.5379
+cap "bias_calc_0/w_17930_210#" "bias_calc_0/XM38/a_1821_n197#" 2.59569
+cap "bias_calc_0/BIASOUT" "bias_calc_0/XM38/a_1821_n197#" 3.17977
+cap "bias_calc_0/XM37/a_1763_n100#" "bias_calc_0/w_17930_210#" -0.303195
+cap "bias_calc_0/GND" "bias_calc_0/XM38/a_1821_n197#" 25.6349
+cap "bias_calc_0/GND" "bias_calc_0/XM37/a_1763_n100#" 1.77636e-14
+cap "bias_calc_0/XM1/a_803_n100#" "bias_calc_0/GND" 6.23235
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/GND" 6.86534
+cap "bias_calc_0/XM1/a_803_n100#" "bias_calc_0/BIASOUT" 0.933917
+cap "bias_calc_0/XM38/a_1821_n197#" "bias_calc_0/GND" 15.7965
+cap "bias_calc_0/GND" "bias_calc_0/BIASOUT" -953.716
+cap "bias_calc_0/XM38/a_1763_n100#" "bias_calc_0/GND" 0.417521
+cap "bias_calc_0/XM38/a_1821_n197#" "bias_calc_0/BIASOUT" 34.8943
+cap "bias_calc_0/GND" "X3/X6/XC2/c1_n2050_n3000#" 1.88069
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/GND" 14.2149
+cap "bias_calc_0/XM1/a_861_n197#" "bias_calc_0/GND" 4.13758
+cap "bias_calc_0/GND" "bias_calc_0/w_17930_210#" 1.38259
+cap "bias_calc_0/BIASOUT" "bias_calc_0/XR20/a_n285_n1572#" 19.32
+cap "bias_calc_0/XR20/a_n415_n1702#" "bias_calc_0/BIASOUT" 56.7523
+cap "bias_calc_0/XR20/a_n415_n1702#" "X3/X6/XC2/c1_n2050_n3000#" 174.392
+cap "bias_calc_0/XR20/a_n415_n1702#" "bias_calc_0/XR20/a_n285_n1572#" 5.29173
+cap "X3/BIAS" "X3/X6/GND" 3.85582
+cap "X3/X6/GND" "X3/X6/XC2/c1_n2050_n3000#" 501.01
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/VDD" -795.911
+cap "X1/X2/VDD" "VDD" -4.82454
+cap "X1/X2/XR17/a_n415_n1322#" "X6/IN" 89.4758
+cap "X1/X2/VDD" "X1/X2/BIAS" 7.59715
+cap "X1/X2/XR17/a_n415_n1322#" "VDD" 115.736
+cap "X6/IN" "X1/X2/VDD" -242.575
+cap "X1/X2/VDD" "X6/XC3/m4_n651_n500#" -115.077
+cap "X1/X2/m1_3550_1144#" "X1/X2/VDD" 0.245757
+cap "X7/XC2/m4_n651_n300#" "X6/m1_4820_n890#" 0.88673
+cap "X6/m1_4820_n460#" "X1/X2/GND" 97.1722
+cap "X7/IN" "X6/IN" 44.333
+cap "X1/X2/GND" "X6/IN" 387.173
+cap "X1/X2/BIAS" "X7/ctrll5" 0.568585
+cap "X1/X2/GND" "X1/X2/BIAS" 0.96837
+cap "X1/X2/GND" "X6/m1_4820_n890#" 7.24272
+cap "X7/ctrll5" "X1/X2/VDD" 4.63585
+cap "X1/X2/GND" "X1/X2/VDD" -489.295
+cap "X6/m1_4820_n460#" "X6/IN" -45.4263
+cap "X6/m1_4820_n460#" "X1/X2/BIAS" -66.6641
+cap "X1/X2/GND" "X1/X2/XM4/a_927_n100#" 14.9561
+cap "X6/m1_4820_n460#" "X1/X2/VDD" 550.908
+cap "X6/m1_4820_n890#" "X6/IN" -9.9309
+cap "X6/m1_4820_n890#" "X1/X2/BIAS" -151.376
+cap "X1/X2/VDD" "X6/IN" 150.66
+cap "X1/X2/BIAS" "X1/X2/VDD" 16.3517
+cap "X6/m1_4820_n890#" "X1/X2/VDD" 61.9358
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/GND" 107.295
+cap "X6/m1_4820_n460#" "X1/X2/XR17/a_n415_n1322#" 73.0723
+cap "X1/X2/XR17/a_n415_n1322#" "X6/IN" 0.431632
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/BIAS" 4.84095
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/VDD" 283.647
+cap "X6/m1_4820_n460#" "X7/XC3/m4_n651_n500#" 0.88673
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/XM4/a_927_n100#" 1.58535
+cap "X1/X2/BIAS" "X6/XM5/a_159_n100#" 19.0421
+cap "X7/m1_4820_n460#" "X1/X2/GND" -507.327
+cap "X1/X2/BIAS" "X6/m1_4820_n890#" -519.814
+cap "X1/X2/XM4/a_927_n100#" "X7/ctrll5" 4.76526
+cap "X1/X2/XM4/a_927_n100#" "X6/XM5/a_159_n100#" 0.468188
+cap "X1/X2/SUB" "X1/X2/GND" 18.4409
+cap "X7/m1_4820_n890#" "X1/X2/VDD" -1448.76
+cap "X7/m1_4820_n460#" "X1/X2/VDD" -581.773
+cap "X6/XM5/a_159_n100#" "X1/X2/GND" 824.9
+cap "X6/m1_4820_n890#" "X7/IN" 11.4987
+cap "X6/m1_4820_n890#" "X1/X2/GND" 7.24272
+cap "X1/X2/BIAS" "X6/m1_4820_n460#" -5892.84
+cap "X6/XM5/a_159_n100#" "X1/X2/VDD" 186.464
+cap "X7/ctrll5" "X1/X2/VDD" 0.572184
+cap "X1/X2/XM4/a_927_n100#" "X6/m1_4820_n460#" 1106.1
+cap "X6/XM5/a_159_n100#" "X7/m1_4820_n890#" 41.9103
+cap "X7/m1_4820_n460#" "X6/XM5/a_159_n100#" 175.801
+cap "X7/m1_4820_n890#" "X6/m1_4820_n890#" 16.6424
+cap "X6/m1_4820_n890#" "X1/X2/VDD" -357.404
+cap "X6/m1_4820_n460#" "X7/IN" 48.0499
+cap "X6/XM5/a_255_n100#" "X1/X2/BIAS" 2.35943
+cap "X6/m1_4820_n460#" "X1/X2/GND" -1456.11
+cap "X1/X2/XM4/a_927_n100#" "X1/X2/BIAS" -0.162025
+cap "X6/XM5/a_255_n100#" "X1/X2/XM4/a_927_n100#" 0.356612
+cap "X6/m1_4820_n460#" "X1/X2/VDD" 145.374
+cap "X6/m1_4820_n460#" "X7/m1_4820_n890#" 23.8314
+cap "X7/m1_4820_n460#" "X6/m1_4820_n460#" 75.547
+cap "X6/m1_4820_n460#" "X1/X2/SUB" -267.288
+cap "X1/X2/BIAS" "X1/X2/GND" 299.653
+cap "X1/X2/XM4/a_927_n100#" "X1/X2/GND" 32.3282
+cap "X1/X2/BIAS" "X1/X2/VDD" 40.0021
+cap "X6/XM5/a_255_n100#" "X1/X2/SUB" 1.84187
+cap "X1/X2/BIAS" "X1/X2/SUB" 3.20159
+cap "X1/X2/XM4/a_927_n100#" "X1/X2/SUB" 3.42722
+cap "X1/X2/BIAS" "X7/ctrll5" 9.7185
+cap "X7/IN" "X1/X2/VDD" -233.472
+cap "X1/X2/GND" "X1/X2/VDD" 2.47085
+cap "X6/m1_4820_n890#" "X7/IN" 11.4987
+cap "X7/m1_4820_n460#" "X1/X2/GND" 435.01
+cap "X7/IN" "X8/IN" 44.333
+cap "X7/m1_4820_n460#" "X8/IN" 48.0499
+cap "X7/XM5/a_255_n100#" "X1/X2/SUB" 0.354206
+cap "X7/m1_4820_n890#" "X6/m1_4820_n890#" 7.93028
+cap "X7/m1_4820_n460#" "X6/XM5/a_159_n100#" 78.2057
+cap "X7/m1_4820_n890#" "X8/IN" 11.4987
+cap "X7/m1_4820_n460#" "X8/XC3/m4_n651_n500#" 34.0213
+cap "X7/m1_4820_n890#" "X6/XM5/a_159_n100#" 18.6411
+cap "X7/IN" "X1/X2/SUB" 3.02143
+cap "X7/m1_4820_n460#" "X1/X2/SUB" 95.2421
+cap "X6/IN" "X7/IN" 44.333
+cap "X7/m1_4820_n460#" "X8/XC2/m4_n651_n300#" 9.15211
+cap "X7/m1_4820_n460#" "X7/IN" 73.8347
+cap "X8/XC2/m4_n651_n300#" "X7/m1_4820_n890#" 8.32121
+cap "X1/X2/SUB" "X1/X2/VDD" 2.71891
+cap "X7/XM5/a_159_n100#" "X1/X2/VDD" -148.805
+cap "X7/IN" "X6/m1_4820_n460#" 48.0499
+cap "X7/m1_4820_n460#" "X6/m1_4820_n460#" 35.7853
+cap "X7/m1_4820_n890#" "X7/IN" 19.5399
+cap "X1/X2/SUB" "X1/X2/GND" -0.00953942
+cap "X7/IN" "X1/X2/VDD" 82.8404
+cap "X7/m1_4820_n890#" "X6/m1_4820_n460#" 11.13
+cap "X7/m1_4820_n460#" "X1/X2/VDD" 445.491
+cap "X7/IN" "X1/X2/GND" 205.605
+cap "X7/m1_4820_n890#" "X1/X2/VDD" 782.785
+cap "X7/ctrll5" "X1/X2/VDD" 9.69209
+cap "X7/ctrll5" "X1/X3/XM4/a_927_n100#" 3.15188
+cap "X1/X3/VDD" "X8/m1_4820_n460#" -192.759
+cap "X7/m1_4820_n460#" "X8/m1_4820_n460#" 53.9211
+cap "X7/XM5/a_159_n100#" "X1/X3/SUB" 160.724
+cap "X1/X3/GND" "X1/X3/XM4/a_927_n100#" 8.62519
+cap "X1/X3/BIAS" "X1/X3/SUB" -1.52905
+cap "X7/m1_4820_n890#" "X8/IN" 11.4987
+cap "X1/X3/BIAS" "X7/ctrll5" 6.90976
+cap "X1/X3/SUB" "X1/X3/GND" -0.0279368
+cap "X7/XM5/a_159_n100#" "X1/X3/GND" 257.792
+cap "X1/X3/VDD" "X1/X3/SUB" 4.30416
+cap "X8/m1_4820_n460#" "X8/IN" 73.8347
+cap "X1/X3/VDD" "X7/XM5/a_159_n100#" 371.863
+cap "X1/X3/BIAS" "X1/X3/GND" 9.57078
+cap "X9/XC3/m4_n651_n500#" "X8/m1_4820_n460#" 0.88673
+cap "X1/X3/VDD" "X7/ctrll5" 3.04775
+cap "X9/IN" "X8/IN" 44.333
+cap "X8/m1_4820_n890#" "X7/XM5/a_159_n100#" 41.9103
+cap "X1/X3/XM4/a_927_n100#" "X8/IN" 2.02814
+cap "X1/X3/VDD" "X1/X3/GND" 34.3937
+cap "X7/m1_4820_n460#" "X1/X3/GND" 890.502
+cap "X7/m1_4820_n460#" "X1/X3/VDD" -155.697
+cap "X1/X3/VDD" "X8/m1_4820_n890#" -261.151
+cap "X7/m1_4820_n460#" "X8/m1_4820_n890#" 23.8314
+cap "X8/m1_4820_n460#" "X1/X3/XM4/a_927_n100#" 961.021
+cap "X1/X3/BIAS" "X8/IN" 24.7325
+cap "X1/X3/SUB" "X8/m1_4820_n460#" 16.2274
+cap "X1/X3/GND" "X8/IN" 190.025
+cap "X7/XM5/a_159_n100#" "X8/m1_4820_n460#" 175.801
+cap "X7/XM5/a_255_n100#" "X1/X3/SUB" 1.48767
+cap "X1/X3/VDD" "X8/IN" 41.1208
+cap "X7/m1_4820_n460#" "X8/IN" 48.0499
+cap "X8/m1_4820_n890#" "X9/XC2/m4_n651_n300#" 0.88673
+cap "X9/XC3/m4_n651_n500#" "X1/X3/GND" -301.465
+cap "X7/IN" "X8/IN" 44.333
+cap "X8/m1_4820_n890#" "X8/IN" 19.5399
+cap "X1/X3/BIAS" "X8/m1_4820_n460#" 11.2149
+cap "X8/m1_4820_n890#" "X7/m1_4820_n890#" 8.32121
+cap "X1/X3/GND" "X8/m1_4820_n460#" 516.179
+cap "X7/m1_4820_n460#" "X8/m1_4820_n890#" 4.87721
+cap "X7/XM5/a_159_n100#" "X8/m1_4820_n460#" 24.8638
+cap "X8/XM5/a_159_n100#" "X9/m1_4820_n460#" 175.801
+cap "X8/m1_4820_n890#" "X7/XM5/a_159_n100#" 5.923
+cap "X7/ctrll5" "X1/X3/VDD" 6.65601
+cap "X7/ctrll5" "X1/X3/XM4/a_927_n100#" 1.61338
+cap "X1/X3/SUB" "X1/X3/BIAS" -0.659773
+cap "X1/X3/GND" "X1/X3/BIAS" 2.89305
+cap "X1/X3/BIAS" "X8/m1_4820_n460#" -963.845
+cap "X1/X3/SUB" "X8/XM5/a_255_n100#" 1.84187
+cap "X9/m1_4820_n890#" "X8/m1_4820_n460#" 23.8314
+cap "X1/X3/SUB" "X8/m1_4820_n460#" -196.645
+cap "X1/X3/GND" "X8/m1_4820_n460#" -674.724
+cap "X1/X3/GND" "X1/X3/SUB" -0.0356602
+cap "X9/m1_4820_n890#" "X8/m1_4820_n890#" 16.6424
+cap "X9/m1_4820_n890#" "X1/X3/VDD" -1.81623
+cap "X1/X3/GND" "X1/X3/XM4/a_927_n100#" 8.62519
+cap "X9/IN" "X8/m1_4820_n460#" 48.0499
+cap "X8/XM5/a_159_n100#" "X9/m1_4820_n890#" 41.9103
+cap "X1/X3/GND" "X8/XM5/a_159_n100#" 318.175
+cap "X1/X3/VDD" "X8/m1_4820_n460#" 505.339
+cap "X1/X3/XM4/a_927_n100#" "X8/m1_4820_n460#" -8559.25
+cap "X1/X3/GND" "X1/X3/VDD" 24.2646
+cap "X1/X3/SUB" "X1/X3/VDD" 7.17037
+cap "X1/X3/BIAS" "X7/ctrll5" 3.37732
+cap "X9/IN" "X8/m1_4820_n890#" 11.4987
+cap "X8/m1_4820_n890#" "X1/X3/VDD" -237.079
+cap "X7/m1_4820_n460#" "X8/m1_4820_n460#" 17.8742
+cap "X9/IN" "X1/X3/VDD" -15.8688
+cap "X8/XM5/a_159_n100#" "X1/X3/VDD" 447.612
+cap "X9/m1_4820_n460#" "X8/m1_4820_n460#" 75.547
+cap "X1/X3/GND" "X9/m1_4820_n460#" 94.0968
+cap "X7/m1_4820_n890#" "X8/m1_4820_n890#" 4.1444
+cap "X9/IN" "X9/m1_4820_n890#" -20.4966
+cap "X9/IN" "X1/X3/VDD" 16.787
+cap "X1/X3/VDD" "X9/m1_4820_n460#" 51.6105
+cap "X8/XM5/a_159_n100#" "X9/m1_4820_n890#" 18.6411
+cap "X9/IN" "X8/m1_4820_n460#" 48.0499
+cap "X8/m1_4820_n460#" "X9/m1_4820_n460#" 35.7853
+cap "X9/IN" "X8/m1_4820_n890#" 11.4987
+cap "X9/IN" "X1/X3/BIAS" 33.2341
+cap "X1/X3/BIAS" "X9/m1_4820_n460#" 144.118
+cap "X1/X3/GND" "X9/m1_4820_n460#" 14.7538
+cap "X9/IN" "X9/m1_4820_n460#" -90.311
+cap "X1/X3/VDD" "X9/m1_4820_n890#" 81.0038
+cap "X8/XM5/a_159_n100#" "X9/m1_4820_n460#" 78.2057
+cap "X9/IN" "X8/IN" 44.333
+cap "X9/m1_4820_n890#" "X8/m1_4820_n460#" 11.13
+cap "X9/m1_4820_n890#" "X8/m1_4820_n890#" 7.93028
+cap "X1/X3/BIAS" "X9/m1_4820_n890#" 39.685
+cap "bias_calc_0/SUB" "bias_calc_0/XM39/a_n465_n188#" 2.66454e-15
+cap "bias_calc_0/SUB" "bias_calc_0/XM37/a_1763_n100#" -3.55271e-15
+cap "bias_calc_0/XM1/a_861_n197#" "bias_calc_0/SUB" 1.77636e-15
+cap "bias_calc_0/SUB" "bias_calc_0/BIASOUT" -5.68434e-14
+cap "bias_calc_0/XM37/a_1763_n100#" "bias_calc_0/SUB" -3.19744e-14
+cap "bias_calc_0/SUB" "bias_calc_0/XM1/a_803_n100#" 4.44089e-16
+cap "bias_calc_0/XM38/a_1821_n197#" "bias_calc_0/SUB" -1.7053e-13
+cap "bias_calc_0/SUB" "bias_calc_0/XM39/a_n465_n188#" -8.88178e-16
+cap "bias_calc_0/w_17930_210#" "bias_calc_0/XM37/a_1763_n100#" 0.000289392
+cap "bias_calc_0/SUB" "bias_calc_0/XM37/a_1821_n197#" 1.06581e-14
+cap "bias_calc_0/SUB" "bias_calc_0/XM1/a_861_n197#" 4.13758
+cap "bias_calc_0/SUB" "bias_calc_0/XM38/a_1821_n197#" 7.72623
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/XM1/a_861_n197#" 73.4037
+cap "bias_calc_0/SUB" "bias_calc_0/XM1/w_n1127_n319#" 14.2149
+cap "bias_calc_0/BIASOUT" "bias_calc_0/XM1/a_803_n100#" 3.02014
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/BIASOUT" 2.0124
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/XM1/a_803_n100#" 22.776
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/VOP" 4.44639
+cap "bias_calc_0/VOP" "bias_calc_0/XM1/a_803_n100#" 5.28766
+cap "bias_calc_0/BIASOUT" "bias_calc_0/XM1/a_861_n197#" 7.31038
+cap "bias_calc_0/VOP" "bias_calc_0/XM38/a_1821_n197#" 20.0632
+cap "bias_calc_0/XM1/a_861_n197#" "bias_calc_0/XM1/a_803_n100#" 6.3242
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/XM1/a_861_n197#" 92.9809
+cap "bias_calc_0/VOP" "bias_calc_0/XM1/a_861_n197#" 16.9753
+cap "bias_calc_0/SUB" "bias_calc_0/XM1/a_803_n100#" 6.23235
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/XM1/w_n1127_n319#" 24.5323
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/XM1/a_803_n100#" 26.9696
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/SUB" 6.86534
+cap "bias_calc_0/VOP" "bias_calc_0/XR20/a_n285_n1572#" 134.504
+cap "X3/X5/XC1/c1_n2050_n3000#" "bias_calc_0/XR20/a_n415_n1702#" 33.4857
+cap "bias_calc_0/XM1/a_931_n100#" "bias_calc_0/BIASOUT" 2.0124
+cap "bias_calc_0/VOP" "bias_calc_0/XM1/a_803_n100#" 5.28766
+cap "bias_calc_0/VOP" "bias_calc_0/XM1/a_861_n197#" 16.9753
+cap "bias_calc_0/XM1/a_803_n100#" "bias_calc_0/BIASOUT" 2.08622
+cap "bias_calc_0/XM1/a_861_n197#" "bias_calc_0/BIASOUT" 7.31038
+cap "bias_calc_0/VOP" "bias_calc_0/BIASOUT" -0.235014
+cap "bias_calc_0/XR20/a_n285_n1572#" "bias_calc_0/XR20/a_n415_n1702#" 22.2841
+cap "bias_calc_0/VOP" "bias_calc_0/XR20/a_n415_n1702#" -132.93
+cap "bias_calc_0/BIASOUT" "bias_calc_0/XR20/a_n415_n1702#" 36.7581
+cap "bias_calc_0/VOP" "bias_calc_0/XM1/a_931_n100#" 4.44639
+cap "X3/X5/XC1/c1_n2050_n3000#" "X3/X6/GND" -75.0207
+cap "bias_calc_0/VOP" "X3/X6/GND" -213.218
+cap "m1_36045_25020#" "X3/X6/GND" 1.27022
+cap "bias_calc_0/VOP" "bias_calc_0/XM30/a_483_n100#" 0.459584
+cap "bias_calc_0/XM30/a_483_n100#" "X3/X6/GND" 2.82821
+cap "X3/X2/XR1/a_n703_n3602#" "X3/X3/BIAS" 0.0228776
+cap "X3/X2/BIAS" "X3/X2/GND" 4.79612
+cap "X3/X2/GND" "X3/X2/XM1/a_n417_n100#" 5.64186
+cap "X3/X2/BIAS" "X3/X2/GND" 40.4221
+cap "VDD" "X3/X2/GND" -167.883
+cap "X3/X2/GND" "X3/X2/OUTB" -8.88178e-16
+cap "X3/X2/GND" "X3/I2B" -7.77156e-16
+cap "X3/X2/BIAS" "X3/X2/XM1/a_n417_n100#" 65.194
+cap "X3/I2A" "X3/X2/GND" -1.77636e-15
+cap "X6/XC3/m4_n651_n500#" "X1/X2/XR17/a_n415_n1322#" 1.33283
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/BIAS" -2129.22
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/VDD" 27.3248
+cap "X1/X2/XR17/a_n415_n1322#" "X6/IN" 66.5453
+cap "X1/X2/XM4/a_n225_n100#" "X1/X2/BIAS" 0.435544
+cap "VDD" "X1/X2/BIAS" 50.1748
+cap "X1/X2/XR17/a_n415_n1322#" "X3/X2/XM1/a_n417_n100#" 2.13163e-14
+cap "X1/X2/XR17/a_n415_n1322#" "X3/X2/OUTA" 3.46093
+cap "X1/X2/XR17/a_n415_n1322#" "VDD" 646.598
+cap "X1/X2/BIAS" "X1/X2/VDD" 16.0312
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/GND" 216.72
+cap "X1/X2/XM4/a_927_n100#" "X6/m1_4820_n460#" -388.494
+cap "X1/X2/XM4/a_927_n100#" "X1/X2/BIAS" 11.0529
+cap "X1/X2/BIAS" "X6/m1_4820_n460#" -14.0198
+cap "X6/IN" "X1/X2/GND" -30.8381
+cap "X1/X2/XM4/a_927_n100#" "X1/X2/XR17/a_n415_n1322#" 2.77435
+cap "X6/m1_4700_270#" "X6/IN" 18.1405
+cap "X1/X2/XR17/a_n415_n1322#" "X6/m1_4820_n460#" -210.6
+cap "X1/X2/XR17/a_n415_n1322#" "X1/X2/BIAS" 112.832
+cap "X3/X2/OUTA" "X1/X2/GND" 3.18589
+cap "X6/m1_4700_270#" "X1/X2/GND" -118.142
+cap "X7/XC3/m4_n651_n500#" "X6/m1_4820_n460#" 0.88673
+cap "X1/X2/GND" "X1/X2/VDD" 19.5238
+cap "X6/m1_4820_n460#" "X6/IN" 15.0405
+cap "X1/X2/XM4/a_927_n100#" "X1/X2/GND" 3.20378
+cap "X1/X2/BIAS" "X6/IN" -700.087
+cap "X6/m1_4820_n460#" "X1/X2/GND" 516.323
+cap "X1/X2/BIAS" "X1/X2/GND" 16.0572
+cap "X7/IN" "X6/IN" 17.8813
+cap "X1/X2/XR17/a_n415_n1322#" "X6/IN" 96.3517
+cap "X6/m1_4820_n460#" "X1/X2/GND" -2314.12
+cap "X6/m1_4820_n460#" "X1/X2/BIAS" -1345.09
+cap "X1/X2/GND" "X1/X2/BIAS" -5864.48
+cap "X7/m1_4820_n460#" "X7/IN" 1.77889
+cap "X6/m1_4700_270#" "X7/IN" 14.8029
+cap "X6/m1_4700_270#" "X1/X2/XM4/a_927_n100#" 1588.96
+cap "X6/m1_4700_270#" "X1/X2/SUB" 28.1307
+cap "X6/m1_4820_n460#" "X7/m1_4820_n460#" 10.0551
+cap "X7/XC4/m4_n951_n500#" "X6/m1_4700_270#" 25.075
+cap "X6/m1_4700_270#" "X1/X2/BIAS" 14.0341
+cap "X6/m1_4700_270#" "X1/X2/GND" 1886.58
+cap "X7/IN" "X6/IN" 90.0233
+cap "X1/X2/SUB" "X6/IN" 7.1764
+cap "X6/m1_4700_270#" "X7/m1_4820_n460#" 27.669
+cap "X1/X2/BIAS" "X6/IN" -5334.45
+cap "X1/X2/GND" "X6/IN" -1875.38
+cap "X1/X2/SUB" "X1/X2/XM4/a_927_n100#" 2.77435
+cap "X6/m1_4820_n460#" "X7/IN" 7.61022
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+cap "X8/m1_4700_270#" "X1/S2A" 47.419
+cap "X8/m1_4700_270#" "X1/S3B" -9.18942
+cap "X8/m1_4700_270#" "X7/m1_4700_270#" 39.7911
+cap "X7/XC4/c2_n851_n400#" "X1/S3B" 4.27953
+cap "X1/X3/SUB" "X1/S3A" 50.5537
+cap "X1/X3/SUB" "X1/X3/XM4/a_351_n100#" 8.68398
+cap "X1/S3A" "X8/m1_4700_270#" 2.72308
+cap "X11/XC4/m4_n951_n500#" "X9/m1_4700_270#" 59.6381
+cap "X1/X3/XM1/a_351_n100#" "X1/S3A" 0.705524
+cap "X9/m1_4700_270#" "X8/m1_4700_270#" 39.7911
+cap "X1/VDD" "X1/S3A" 85.1661
+cap "X11/XC4/m4_n951_n500#" "X1/S3A" 20.6707
+cap "X1/S4A" "X9/m1_4700_270#" 20.6707
+cap "X9/m1_4700_270#" "X1/S3A" 180.721
+cap "X1/S3A" "X1/BIAS" 172.046
+cap "X1/GND" "X1/S3A" -475.717
+cap "X8/IN" "X1/S3A" 31.4733
+cap "X9/IN" "X11/XC4/m4_n951_n500#" 8.60017
+cap "X9/m1_4700_270#" "X11/XC4/m4_n951_n500#" 35.8069
+cap "X9/IN" "X9/m1_4700_270#" 117.895
+cap "X9/m1_4700_270#" "X11/IN" 8.60017
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/AMP" 44.5606
+cap "bias_calc_0/VOP" "bias_calc_0/XM1/a_547_n100#" 9.37317
+cap "bias_calc_0/XM1/a_547_n100#" "bias_calc_0/XM1/a_605_n197#" 99.0579
+cap "bias_calc_0/XM1/a_547_n100#" "bias_calc_0/XM1/a_675_n100#" 13.7072
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/XR19/a_n285_760#" -74.648
+cap "bias_calc_0/AMP" "m1_36045_25020#" 19.9623
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/XM1/a_547_n100#" -78.9044
+cap "bias_calc_0/XR19/a_n285_760#" "m1_36045_25020#" 1.97063
+cap "bias_calc_0/XM1/a_675_n100#" "bias_calc_0/XM1/a_605_n197#" 4.55874
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/AMP" -95.1177
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/VOP" 1.7617
+cap "m1_36045_25020#" "bias_calc_0/XM1/a_547_n100#" 11.3908
+cap "bias_calc_0/AMP" "bias_calc_0/XM1/a_547_n100#" 130.87
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/XM1/a_605_n197#" 77.127
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/XM1/a_675_n100#" 11.5398
+cap "bias_calc_0/VOP" "m1_36045_25020#" 1.31066
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/XM1/a_547_n100#" -97.4168
+cap "m1_36045_25020#" "bias_calc_0/XM1/a_605_n197#" 19.4943
+cap "m1_36045_25020#" "bias_calc_0/XM1/a_675_n100#" 4.03579
+cap "bias_calc_0/XM1/w_n1127_n319#" "bias_calc_0/AMP" -93.3701
+cap "X3/X5/XR18/a_n415_n4762#" "bias_calc_0/AMP" -1.86517e-14
+cap "bias_calc_0/VOP" "m1_36045_25020#" 5.48196
+cap "m1_36045_25020#" "bias_calc_0/XR19/a_n285_760#" 18.3113
+cap "bias_calc_0/XM1/a_675_n100#" "m1_36045_25020#" 4.03579
+cap "m1_36045_25020#" "bias_calc_0/AMP" 83.4945
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+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/AMP" -88.9474
+cap "bias_calc_0/XM1/a_547_n100#" "bias_calc_0/XM1/w_n1127_n319#" 13.4443
+cap "bias_calc_0/XM1/a_605_n197#" "m1_36045_25020#" 19.4943
+cap "bias_calc_0/XM1/a_547_n100#" "m1_36045_25020#" 23.2534
+cap "GND" "bias_calc_0/AMP" 907.518
+cap "bias_calc_0/XM1/a_547_n100#" "bias_calc_0/XR19/a_n285_760#" 20.6103
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/XM1/w_n1127_n319#" 27.205
+cap "bias_calc_0/VOP" "bias_calc_0/XM1/w_n1127_n319#" -6.13036
+cap "bias_calc_0/AMP" "GND" 1100.7
+cap "GND" "X3/X5/XR18/a_n415_n4762#" -171.273
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+cap "X3/X4/GND" "X3/I4B" -8.52651e-14
+cap "X3/X4/GND" "X3/I2A" -1.55431e-15
+cap "X3/X4/OUTB" "GND" -642.686
+cap "X3/X4/GND" "X3/I4A" 8.52651e-14
+cap "X3/X4/OUTB" "X3/X4/GND" -9.09495e-13
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+cap "X3/X4/XM2/a_n73_n100#" "X3/X4/GND" -3.63798e-12
+cap "VDD" "X3/X4/GND" -67.1532
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+cap "X4/IN" "GND" -156.334
+cap "X1/S4B" "GND" -291.913
+cap "X3/X4/OUTA" "X1/X1/XR17/a_n415_n1322#" 18.9093
+cap "X3/X4/OUTA" "X1/S1A" -284.709
+cap "X1/S1A" "GND" -19.7075
+cap "X3/I4A" "GND" -159.241
+cap "X1/X1/XR17/a_n415_n1322#" "GND" -127.153
+cap "X3/X4/OUTA" "VDD" 627.433
+cap "X3/X4/OUTA" "X1/X1/INB" 0.217061
+cap "X4/IN" "X1/X1/XR17/a_n415_n1322#" 3.4758
+cap "X4/IN" "VDD" 59.4121
+cap "X1/S4B" "VDD" 63.9759
+cap "X4/XC4/m4_n951_n500#" "GND" 10.3229
+cap "X1/S1A" "VDD" 23.919
+cap "X3/I4A" "VDD" 59.7473
+cap "X1/X1/XR17/a_n415_n1322#" "VDD" 168.078
+cap "X3/X4/OUTA" "GND" 172.872
+cap "X3/X4/OUTA" "X4/IN" 10.7073
+cap "X3/X4/OUTA" "X1/X1/GND" 3.17295
+cap "X3/X4/OUTA" "GND" -1334.63
+cap "X4/IN" "X3/X4/OUTA" 94.9554
+cap "X1/S4B" "X1/X1/XR17/a_n415_n1322#" -0.149228
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+cap "X3/X4/OUTA" "X1/X1/INB" 28.621
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+cap "GND" "X1/X1/XR17/a_n415_n1322#" -62.2101
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+cap "X3/X4/OUTA" "X1/X1/XM3/a_n129_n100#" 13.1534
+cap "X4/IN" "X1/X1/GND" -8.75603
+cap "X1/X1/XM3/a_n129_n100#" "X1/X1/XR17/a_n415_n1322#" 0.792673
+cap "X6/IN" "X5/IN" 7.10543e-15
+cap "X6/IN" "X1/S4B" 7.10543e-15
+cap "X5/IN" "GND" -6.90852
+cap "X6/IN" "X4/IN" -7.10543e-15
+cap "X4/IN" "X5/IN" -12.3211
+cap "X4/IN" "GND" 36.5187
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+cap "X4/IN" "X1/S4B" -0.182659
+cap "X3/X4/OUTA" "X1/X1/XR17/a_n415_n1322#" 57.8755
+cap "X1/X1/INB" "GND" -97.2517
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+cap "X1/S4B" "X1/S3B" 7.10543e-15
+cap "X4/IN" "X1/S3B" 2.84217e-14
+cap "X1/S4B" "X1/S2A" 3.55271e-15
+cap "X6/m1_4700_270#" "X4/IN" 29.2709
+cap "X3/X4/XR2/a_n573_n3472#" "X4/IN" 18.2618
+cap "X4/XC4/m4_n951_n500#" "X4/IN" 586.449
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+cap "X4/IN" "X1/S4A" -156.09
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+cap "X5/XC4/m4_n951_n500#" "X5/IN" 0.76129
+cap "X1/S4B" "X4/IN" 937.541
+cap "X6/IN" "X4/XC4/m4_n951_n500#" 29.2709
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+cap "X1/SUB" "X1/S4A" 2.83255
+cap "X4/XC4/m4_n951_n500#" "X1/S4A" 123.868
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+cap "X1/X1/XM3/a_n129_n100#" "X3/X4/XR2/a_n573_n3472#" 13.1534
+cap "X1/X1/XM3/a_n129_n100#" "X4/XC4/m4_n951_n500#" 1154.5
+cap "X1/SUB" "X1/X1/XM3/a_n129_n100#" 1.02436
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+cap "GND" "X4/XC4/m4_n951_n500#" 13.0609
+cap "X5/IN" "X4/IN" 1240.25
+cap "X1/S4B" "X4/XC4/m4_n951_n500#" 641.079
+cap "X5/IN" "X4/IN" 3.08024
+cap "X5/XC4/m4_n951_n500#" "X5/IN" 115.562
+cap "X1/S4B" "X1/SUB" -0.114332
+cap "X5/XC4/m4_n951_n500#" "X7/IN" 20.6707
+cap "X1/S4B" "X5/IN" -435.446
+cap "X7/m1_4700_270#" "X5/IN" 20.6707
+cap "X10/XC4/m4_n951_n500#" "X5/XC4/m4_n951_n500#" 17.9298
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+cap "X1/X4/XM2/a_n221_n100#" "X1/S4B" -1.34175
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+cap "X5/XC4/m4_n951_n500#" "X4/XC4/m4_n951_n500#" 40.5957
+cap "X1/SUB" "X5/IN" 21.4165
+cap "X5/XC4/m4_n951_n500#" "X1/SUB" -772.448
+cap "X5/XC4/m4_n951_n500#" "X7/m1_4700_270#" 35.8069
+cap "X10/XC4/m4_n951_n500#" "X1/S3A" -50.1111
+cap "X1/S4A" "X1/X4/XM3/a_n129_n100#" -0.699933
+cap "X5/XC4/m4_n951_n500#" "X10/XC4/m4_n951_n500#" 40.5957
+cap "X1/S4B" "X5/IN" -914.582
+cap "X1/S4B" "X1/S3B" -6.33382
+cap "X1/S4B" "X1/SUB" 57.1893
+cap "X7/IN" "X5/XC4/m4_n951_n500#" 8.60017
+cap "X1/S4B" "X1/X4/XM3/a_n129_n100#" 569.253
+cap "X5/IN" "X7/m1_4700_270#" 8.60017
+cap "X5/XC4/m4_n951_n500#" "X1/S4B" -457.173
+cap "X1/S4B" "X10/XC4/m4_n951_n500#" 27.7146
+cap "X1/S4A" "X1/S4B" -5.81622
+cap "X1/S3B" "X1/X4/XM3/a_n129_n100#" -1.07668
+cap "X10/XC3/m4_n651_n500#" "X1/S4B" 8.23954
+cap "X5/XC4/m4_n951_n500#" "X5/IN" 169.135
+cap "X1/SUB" "X1/X4/XM3/a_n129_n100#" -0.636993
+cap "X5/XC4/m4_n951_n500#" "X1/SUB" -203.744
+cap "X1/S3A" "X1/X4/XM3/a_n129_n100#" -0.201848
+cap "X1/X4/XM3/a_n129_n100#" "X1/S4A" 44.7253
+cap "X10/XC4/m4_n951_n500#" "X1/X4/SUB" 113.796
+cap "X1/X4/XM3/a_n129_n100#" "X1/X4/OUTB" -769.186
+cap "X1/X4/XM3/a_n129_n100#" "X1/X4/SUB" 7.22923
+cap "X8/m1_4700_270#" "X1/X4/OUTB" 29.2709
+cap "X11/XC4/m4_n951_n500#" "X10/XC4/m4_n951_n500#" 40.5957
+cap "X10/XC4/m4_n951_n500#" "X1/S3B" 29.2709
+cap "X1/S3A" "X1/S4A" 0.0190697
+cap "X1/S4A" "X1/GND" 106.723
+cap "X1/S4B" "X10/XC4/m4_n951_n500#" 359.955
+cap "X10/XC4/m4_n951_n500#" "X8/m1_4700_270#" 95.445
+cap "X1/S4A" "X1/X4/OUTB" -580.815
+cap "X1/X4/OUTB" "X5/XC4/c2_n851_n400#" 5.52975
+cap "X1/S3A" "X10/XC4/m4_n951_n500#" 191.175
+cap "X1/S4A" "X1/X4/SUB" 54.7641
+cap "X1/X4/OUTB" "X1/X4/SUB" -241.007
+cap "X1/S3A" "X1/X4/XM3/a_n129_n100#" 16.6162
+cap "X11/XC4/m4_n951_n500#" "X1/S4A" 1.14194
+cap "X1/S4A" "X10/XC4/m4_n951_n500#" 1964.45
+cap "X10/XC4/m4_n951_n500#" "X1/X4/OUTB" 138.592
+cap "X10/XC4/m4_n951_n500#" "X5/XC4/m4_n951_n500#" 40.5957
+cap "X1/S4A" "X1/GND" -483.94
+cap "X10/XC4/m4_n951_n500#" "X1/S4A" 5.9
+cap "X11/XC4/m4_n951_n500#" "X10/XC4/m4_n951_n500#" 40.5957
+cap "X1/X4/XM2/a_n129_n100#" "X1/S4A" 0.503945
+cap "X1/S4A" "X1/BIAS" 202.609
+cap "X10/IN" "X1/S4A" 34.4145
+cap "X11/XC4/m4_n951_n500#" "X1/S4A" 231.078
+cap "X9/m1_4700_270#" "X1/S4A" 20.6707
+cap "X11/XC4/m4_n951_n500#" "X9/m1_4700_270#" 59.6381
+cap "X11/XC4/m4_n951_n500#" "X1/S3A" 20.6707
+cap "X1/VDD" "X1/S4A" 106.61
+cap "X11/IN" "X11/XC4/m4_n951_n500#" 153.617
+cap "X9/IN" "X11/XC4/m4_n951_n500#" 8.60017
+cap "X9/m1_4700_270#" "X11/XC4/m4_n951_n500#" 35.8069
+cap "X9/m1_4700_270#" "X11/IN" 8.60017
+cap "bias_calc_0/VDD" "bias_calc_0/XM36/a_803_n100#" -1.81899e-12
+cap "bias_calc_0/VDD" "bias_calc_0/BIAS2V" -5.36602e-11
+cap "bias_calc_0/VDD" "bias_calc_0/XR20/a_n415_n1702#" -3.55271e-15
+cap "bias_calc_0/BIAS2V" "bias_calc_0/VDD" -3.63798e-12
+cap "bias_calc_0/XR20/a_n415_n1702#" "bias_calc_0/VDD" -3.41061e-13
+cap "bias_calc_0/VDD" "bias_calc_0/XM36/a_803_n100#" 7.95808e-13
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/VDD" 9.90493
+cap "bias_calc_0/VDD" "bias_calc_0/XM1/a_n733_n100#" 3.33067e-15
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/XM1/a_n733_n100#" -45.2725
+cap "bias_calc_0/BIAS2V" "bias_calc_0/XM1/a_n733_n100#" 43.6291
+cap "bias_calc_0/XM1/a_n733_n100#" "bias_calc_0/VDD" 41.877
+cap "X3/BIAS" "bias_calc_0/AMP" 8.28902
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/AMP" -208.856
+cap "bias_calc_0/BIAS2V" "bias_calc_0/AMP" 11.8633
+cap "bias_calc_0/VDD" "bias_calc_0/AMP" 30.9149
+cap "bias_calc_0/XR19/a_n285_760#" "X3/BIAS" 0.492657
+cap "bias_calc_0/BIAS2V" "X3/BIAS" 19.4943
+cap "X3/BIAS" "bias_calc_0/VDD" 4.02581
+cap "X3/X5/GND" "bias_calc_0/XR19/a_n285_760#" 9.26398
+cap "X3/X5/GND" "bias_calc_0/VDD" 1.56069
+cap "bias_calc_0/XM1/a_n733_n100#" "bias_calc_0/AMP" 51.6526
+cap "bias_calc_0/BIAS2V" "bias_calc_0/XR19/a_n285_760#" -2.35368
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/VDD" -19.0569
+cap "bias_calc_0/BIAS2V" "bias_calc_0/VDD" 133.856
+cap "bias_calc_0/XM1/a_n733_n100#" "X3/BIAS" 5.62821
+cap "X3/X5/GND" "bias_calc_0/XM1/a_n733_n100#" 1.25723
+cap "bias_calc_0/AMP" "bias_calc_0/XR19/a_n285_760#" 91.4526
+cap "bias_calc_0/VDD" "bias_calc_0/AMP" 9.17939
+cap "bias_calc_0/PSUB" "bias_calc_0/XR19/a_n285_760#" 6.80126
+cap "X3/BIAS" "bias_calc_0/BIAS2V" 19.4943
+cap "bias_calc_0/AMP" "X3/BIAS" 29.5433
+cap "bias_calc_0/AMP" "bias_calc_0/XM1/a_n733_n100#" 10.6499
+cap "bias_calc_0/XM1/a_n733_n100#" "bias_calc_0/PSUB" 11.7263
+cap "X3/X5/GND" "bias_calc_0/XR19/a_n285_760#" 26.3477
+cap "X3/BIAS" "X3/X5/GND" 58.5375
+cap "bias_calc_0/XM1/a_n733_n100#" "X3/X5/GND" 1.25723
+cap "bias_calc_0/VDD" "X3/BIAS" 4.02581
+cap "X3/BIAS" "bias_calc_0/XR19/a_n285_760#" 4.4391
+cap "bias_calc_0/AMP" "bias_calc_0/BIAS2V" 11.8633
+cap "bias_calc_0/AMP" "bias_calc_0/PSUB" -120.304
+cap "bias_calc_0/XM1/a_n733_n100#" "bias_calc_0/XR19/a_n285_760#" 13.9288
+cap "bias_calc_0/XM1/a_n733_n100#" "X3/BIAS" 10.3888
+cap "bias_calc_0/AMP" "X3/X5/GND" 565.876
+cap "X3/X5/GND" "bias_calc_0/PSUB" 1.56069
+cap "X3/X5/GND" "bias_calc_0/XM31/a_483_n100#" 1.4141
+cap "bias_calc_0/AMP" "X3/X5/GND" 411.917
+cap "X3/X5/GND" "X3/BIAS" 3.26584
+cap "GND" "X3/m2_20210_20620#" 53.0904
+cap "X3/m2_20210_20620#" "GND" 86.5931
+cap "X3/m2_20210_20620#" "GND" 131.133
+cap "X3/X5/VDD" "X3/X1/GND" -32.7116
+cap "GND" "X3/X1/GND" 49.5497
+cap "X3/X5/XR18/a_n285_4200#" "X3/X1/XM1/a_447_n100#" 3.40774
+cap "X3/OUT180" "m1_46335_31170#" 0.982992
+cap "X3/BIAS" "m1_46335_31170#" 385.773
+cap "X3/X1/XM1/a_447_n100#" "X3/BIAS" -91.8087
+cap "X3/X1/XM1/a_447_n100#" "m1_46335_31170#" 312.069
+cap "X3/X5/XR18/a_n285_4200#" "m1_46335_31170#" 17.7246
+cap "X3/X1/GND" "X3/X1/BIAS" 536.585
+cap "X3/X4/BIAS" "X3/X4/GND" 0.963127
+cap "X3/X4/BIAS" "X3/X4/GND" 38.5524
+cap "X3/I4B" "X3/X4/GND" 1.77636e-15
+cap "X3/X4/XM2/a_n73_n100#" "X3/X4/GND" -7.27596e-12
+cap "X3/X4/GND" "VDD" -167.883
+cap "X3/X4/GND" "X3/X4/OUTB" -1.42109e-14
+cap "X1/X1/XM4/a_n945_n188#" "VDD" 49.4107
+cap "X1/X1/XR17/a_n415_n1322#" "GND" -42.9347
+cap "X1/X1/XR17/a_n415_n1322#" "X1/X1/XR17/a_n285_n1192#" 32.2623
+cap "X1/X1/XR17/a_n415_n1322#" "X1/X1/XM4/a_n945_n188#" -2059.95
+cap "X1/X1/XM4/a_n945_n188#" "GND" 24.9756
+cap "X1/X1/XR17/a_n415_n1322#" "X3/X4/XM2/a_n73_n100#" 1.77636e-14
+cap "X1/X1/XR17/a_n415_n1322#" "X4/IN" 0.325581
+cap "X1/X1/XM4/a_n225_n100#" "X1/X1/XM4/a_n945_n188#" 0.360544
+cap "GND" "X4/IN" 89.4758
+cap "X1/X1/XR17/a_n415_n1322#" "X3/X4/OUTA" 3.62949
+cap "X1/X1/XR17/a_n415_n1322#" "VDD" 606.814
+cap "X4/XC3/m4_n651_n500#" "X1/X1/BIAS" -18.0203
+cap "X4/XC3/m4_n651_n500#" "X1/X1/XR17/a_n415_n1322#" -207.957
+cap "X4/XC3/m4_n651_n500#" "X1/X1/GND" 545.209
+cap "X1/X1/BIAS" "X1/X1/XR17/a_n285_n1192#" 16.1544
+cap "X3/X4/OUTA" "X1/X1/GND" 3.17295
+cap "X4/XC3/m4_n651_n500#" "GND" 5.84316
+cap "X4/XC4/m4_n951_n500#" "X1/X1/GND" -118.142
+cap "X1/X1/XR17/a_n285_n1192#" "X1/X1/GND" 20.679
+cap "X1/X1/BIAS" "X1/X1/XM3/a_n129_n100#" 11.0529
+cap "X4/IN" "X5/IN" 20.0541
+cap "X4/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 0.88673
+cap "X1/X1/XR17/a_n415_n1322#" "X1/X1/XM3/a_n129_n100#" 2.83264
+cap "X1/X1/XM3/a_n129_n100#" "X1/X1/GND" 3.71903
+cap "X4/IN" "X1/X1/BIAS" -709.158
+cap "X4/IN" "X1/X1/XR17/a_n415_n1322#" 77.0673
+cap "X4/IN" "X1/X1/GND" -291.045
+cap "X4/IN" "GND" 306.069
+cap "X4/XC3/m4_n651_n500#" "X1/X1/XM3/a_n129_n100#" -388.494
+cap "X4/IN" "X4/XC3/m4_n651_n500#" 25.3213
+cap "X4/IN" "X4/XC4/m4_n951_n500#" 12.5576
+cap "X1/X1/BIAS" "X1/X1/XR17/a_n415_n1322#" 107.976
+cap "X1/X1/BIAS" "X1/X1/GND" -41.2334
+cap "X1/X1/BIAS" "GND" 12.9593
+cap "X1/X1/XR17/a_n415_n1322#" "X1/X1/GND" 130.471
+cap "X1/X1/XR17/a_n415_n1322#" "GND" 72.413
+cap "X1/X1/GND" "GND" -147.126
+cap "GND" "X4/XC3/m4_n651_n500#" 5.84316
+cap "X4/XC4/m4_n951_n500#" "X5/XC3/m4_n651_n500#" 33.7724
+cap "X5/XC4/m4_n951_n500#" "X5/IN" 0.951613
+cap "X4/XC4/m4_n951_n500#" "X1/X1/GND" 1924.91
+cap "X4/IN" "GND" 34.6492
+cap "X4/XC4/m4_n951_n500#" "X4/IN" -63.9452
+cap "X1/X1/XM3/a_n129_n100#" "X4/XC3/m4_n651_n500#" 363.857
+cap "X4/XC4/m4_n951_n500#" "X5/IN" 8.45878
+cap "X1/X1/XM3/a_n129_n100#" "X1/X1/GND" 5.24646
+cap "X5/XC3/m4_n651_n500#" "X4/XC3/m4_n651_n500#" 12.2732
+cap "X1/X1/GND" "X4/XC3/m4_n651_n500#" -2424.84
+cap "X1/X1/BIAS" "X4/XC4/m4_n951_n500#" 19.9949
+cap "X5/IN" "X5/XC3/m4_n651_n500#" 1.77889
+cap "X4/IN" "X1/X1/GND" -1907
+cap "X1/X1/XM3/a_n129_n100#" "X1/SUB" 2.83264
+cap "X5/IN" "X4/XC3/m4_n651_n500#" 9.27669
+cap "X4/XC4/m4_n951_n500#" "X5/XC4/m4_n951_n500#" 24.2705
+cap "X1/X1/BIAS" "X1/X1/XM3/a_n129_n100#" 0.812963
+cap "X1/SUB" "X1/X1/GND" 2.77435
+cap "X4/IN" "X5/IN" 83.582
+cap "X1/X1/BIAS" "X4/XC3/m4_n651_n500#" -1909.97
+cap "X1/X1/BIAS" "X1/X1/GND" -7811.73
+cap "X1/X1/BIAS" "X4/IN" -5334.45
+cap "X4/XC4/m4_n951_n500#" "X1/X1/XM3/a_n129_n100#" 1425.53
+cap "X1/X1/BIAS" "X1/SUB" 10.1911
+cap "X5/XC4/m4_n951_n500#" "X10/XC4/m4_n951_n500#" 18.1
+cap "X4/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 5.8717
+cap "X1/SUB" "X5/XC3/m4_n651_n500#" 43.2899
+cap "X5/XC4/m4_n951_n500#" "X4/XC4/m4_n951_n500#" 24.2705
+cap "X5/IN" "X1/S4B" 6.11117
+cap "X5/XC4/m4_n951_n500#" "X1/S4B" -0.847283
+cap "X4/XC3/m4_n651_n500#" "X5/IN" 9.27669
+cap "X5/XC4/m4_n951_n500#" "X5/IN" 41.5446
+cap "X1/SUB" "X5/IN" 171.279
+cap "X5/XC4/m4_n951_n500#" "X1/SUB" -72.553
+cap "X5/XC3/m4_n651_n500#" "X4/XC4/m4_n951_n500#" 15.0215
+cap "X5/XC3/m4_n651_n500#" "X1/S4B" 9.27669
+cap "X4/IN" "X5/IN" 95.7134
+cap "X5/XC3/m4_n651_n500#" "X5/IN" 44.5556
+cap "X10/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 6.13659
+cap "X4/XC4/m4_n951_n500#" "X5/IN" 2.26923
+cap "X1/S4A" "X1/GND" 0.120004
+cap "X1/GND" "X1/S4B" 403.868
+cap "X1/S4B" "X10/XC3/m4_n651_n500#" 28.9926
+cap "X5/IN" "X1/S4B" 104.948
+cap "X1/S4A" "X1/S4B" 20.0541
+cap "X10/XC4/m4_n951_n500#" "X1/S4B" 8.96003
+cap "X1/SUB" "X5/XC4/m4_n951_n500#" 305.106
+cap "X1/BIAS" "X10/XC3/m4_n651_n500#" 0.769519
+cap "X1/BIAS" "X1/GND" 0.0932498
+cap "X10/XC3/m4_n651_n500#" "X5/XC4/m4_n951_n500#" 33.7724
+cap "X5/IN" "X5/XC4/m4_n951_n500#" -134.417
+cap "X10/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 6.13659
+cap "X10/XC3/m4_n651_n500#" "X1/X4/XM3/a_n129_n100#" 437.292
+cap "X1/GND" "X1/X4/XM3/a_n129_n100#" 0.183649
+cap "X1/SUB" "X1/GND" 0.00183671
+cap "X11/XC3/m4_n651_n500#" "X10/XC3/m4_n651_n500#" 0.88673
+cap "X1/BIAS" "X1/S4B" 12.2395
+cap "X10/XC4/m4_n951_n500#" "X5/XC4/m4_n951_n500#" 24.2705
+cap "X1/S4B" "X5/XC4/m4_n951_n500#" -1199.05
+cap "X1/S4A" "X1/X4/XM3/a_n129_n100#" 0.48561
+cap "X1/GND" "X10/XC3/m4_n651_n500#" 115.405
+cap "X1/S4B" "X5/XC3/m4_n651_n500#" 9.27669
+cap "X1/S4B" "X1/X4/XM3/a_n129_n100#" 543.043
+cap "X11/XC3/m4_n651_n500#" "X1/S4A" 2.14762
+cap "X1/S4A" "X10/XC4/m4_n951_n500#" 247.318
+cap "X1/S4A" "X1/X4/SUB" 12.3363
+cap "X11/XC4/m4_n951_n500#" "X10/XC4/m4_n951_n500#" 24.2705
+cap "X10/XC3/m4_n651_n500#" "X1/GND" -648.393
+cap "X1/BIAS" "X1/X4/OUTB" -1055.85
+cap "X10/XC4/m4_n951_n500#" "X1/X4/OUTB" -84.2197
+cap "X11/XC3/m4_n651_n500#" "X10/XC4/m4_n951_n500#" 33.7724
+cap "X10/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 3.19231
+cap "X1/X4/SUB" "X10/XC4/m4_n951_n500#" 50.0704
+cap "X1/X4/XM3/a_n129_n100#" "X1/S4A" 0.773635
+cap "X10/XC3/m4_n651_n500#" "X1/S4A" 9.27669
+cap "X1/X4/XM3/a_n129_n100#" "X1/X4/OUTB" -8212.28
+cap "X10/XC4/m4_n951_n500#" "X5/XC4/m4_n951_n500#" 24.2705
+cap "X11/XC3/m4_n651_n500#" "X10/XC3/m4_n651_n500#" 12.2732
+cap "X10/XC3/m4_n651_n500#" "X1/BIAS" -354.385
+cap "X10/XC3/m4_n651_n500#" "X1/X4/SUB" 18.1466
+cap "X5/XC4/c2_n851_n400#" "X1/X4/OUTB" 33.1173
+cap "X1/S4A" "X1/GND" 64.5464
+cap "X10/XC3/m4_n651_n500#" "X5/XC4/m4_n951_n500#" 4.7729
+cap "X1/GND" "X1/X4/OUTB" -3491.19
+cap "X10/XC3/m4_n651_n500#" "X1/X4/XM3/a_n129_n100#" -3099.54
+cap "X11/XC3/m4_n651_n500#" "X1/GND" 21.7415
+cap "X1/GND" "X10/XC4/m4_n951_n500#" 1108.04
+cap "X1/S4A" "X11/XC4/m4_n951_n500#" 1.52258
+cap "X1/S4A" "X1/X4/OUTB" 77.8733
+cap "X1/S4A" "X1/X4/XM2/a_n129_n100#" 0.946047
+cap "X1/S4A" "X1/BIAS" 178.326
+cap "X1/S4A" "X1/VDD" 72.7223
+cap "X10/XC3/m4_n651_n500#" "X11/XC3/m4_n651_n500#" 5.8717
+cap "X10/XC4/m4_n951_n500#" "X11/XC4/m4_n951_n500#" 24.2705
+cap "X11/XC3/m4_n651_n500#" "X1/GND" -10.2508
+cap "X1/S4A" "X10/XC4/m4_n951_n500#" 22.2385
+cap "X1/S4A" "X11/XC3/m4_n651_n500#" 21.745
+cap "X1/VDD" "X11/XC3/m4_n651_n500#" 17.5154
+cap "X11/XC3/m4_n651_n500#" "X1/BIAS" 35.4125
+cap "X1/S4A" "X10/IN" 96.9395
+cap "X10/XC4/m4_n951_n500#" "X11/XC3/m4_n651_n500#" 15.0215
+cap "X1/S4A" "X10/XC3/m4_n651_n500#" 9.27669
+cap "X1/S4A" "X11/XC4/m4_n951_n500#" -4.62719
+cap "X1/S4A" "X1/GND" -307.88
+cap "X11/IN" "X11/XC4/m4_n951_n500#" -91.2285
+cap "bias_calc_0/XR19/a_n415_n1322#" "bias_calc_0/VDD" 8.88178e-16
+cap "bias_calc_0/BIAS2V" "bias_calc_0/VDD" 10.9047
+cap "bias_calc_0/XM36/a_803_n100#" "bias_calc_0/VDD" 8.95845
+cap "bias_calc_0/XM36/a_803_n100#" "bias_calc_0/BIAS2V" 9.02079
+cap "bias_calc_0/VDD" "bias_calc_0/XR19/a_n285_760#" 1.33227e-15
+cap "bias_calc_0/XR19/a_n415_n1322#" "bias_calc_0/BIAS2V" 9.65109
+cap "bias_calc_0/XM36/a_803_n100#" "bias_calc_0/BIAS2V" 8.00768
+cap "bias_calc_0/BIAS2V" "bias_calc_0/XR19/a_n285_760#" 39.9277
+cap "bias_calc_0/XR19/a_n415_n1322#" "bias_calc_0/VDD" 33.8654
+cap "bias_calc_0/VDD" "bias_calc_0/XM36/a_803_n100#" 17.3242
+cap "bias_calc_0/VDD" "bias_calc_0/XR19/a_n285_760#" 54.6311
+cap "bias_calc_0/VDD" "bias_calc_0/BIAS2V" 365.831
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/VDD" 17.0303
+cap "X3/X5/GND" "bias_calc_0/VDD" 3.35235
+cap "bias_calc_0/BIAS2V" "bias_calc_0/VDD" -2.31716
+cap "bias_calc_0/BIAS2V" "bias_calc_0/XM3/a_803_n100#" -2.22045e-16
+cap "X3/X5/GND" "bias_calc_0/XR19/a_n285_760#" 2.79933
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/BIAS2V" -3.39719
+cap "bias_calc_0/BIAS2V" "X3/BIAS" 9.05094
+cap "X3/BIAS" "X3/X5/GND" 49.3863
+cap "bias_calc_0/AMP" "X3/X5/GND" 11.6228
+cap "bias_calc_0/BIAS2V" "X3/BIAS" 9.05094
+cap "bias_calc_0/XR19/a_n285_760#" "X3/X5/GND" 10.137
+cap "bias_calc_0/AMP" "X3/X5/GND" 6.98869
+cap "X3/BIAS" "X3/X5/GND" 3.26584
+cap "X3/X5/XR18/a_n415_n4762#" "GND" 363.479
+cap "X3/m2_20210_20620#" "GND" 53.0904
+cap "GND" "X3/X5/XR18/a_n415_n4762#" 363.479
+cap "X3/m2_20210_20620#" "GND" 86.5931
+cap "X3/BIAS" "GND" -102.555
+cap "X3/m2_20210_20620#" "GND" 131.133
+cap "X3/X5/XR18/a_n415_n4762#" "GND" 665.448
+cap "GND" "X3/SUB" 547.747
+cap "X3/BIAS" "GND" 301.854
+cap "GND" "X3/X1/GND" 49.5497
+cap "X3/BIAS" "X3/SUB" 62.9389
+cap "X3/X1/GND" "X3/X1/BIAS" 704.6
+cap "X1/X1/XR17/a_n415_n1322#" "GND" -97.8682
+cap "X1/X1/XR17/a_n285_n1192#" "X4/IN" -242.642
+cap "X1/X1/XR17/a_n285_n1192#" "X1/X1/m1_3550_1144#" 0.307197
+cap "X1/X1/XR17/a_n285_n1192#" "VDD" -2.44899
+cap "X1/X1/XR17/a_n285_n1192#" "X4/XC3/m4_n651_n500#" -115.109
+cap "VDD" "X1/X1/XR17/a_n415_n1322#" 50.4206
+cap "GND" "X4/IN" 89.4758
+cap "X1/X1/XR17/a_n285_n1192#" "X1/X1/XR17/a_n415_n1322#" -394.671
+cap "X1/X1/XR17/a_n285_n1192#" "GND" -10.5993
+cap "X1/X1/XR17/a_n285_n1192#" "X1/X1/XM4/a_n945_n188#" 7.6695
+cap "X4/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 0.88673
+cap "X4/IN" "X1/X1/XR17/a_n285_n1192#" 185.933
+cap "X1/X1/XR17/a_n285_n1192#" "X1/X1/XR17/a_n415_n1322#" 298.528
+cap "X5/IN" "X4/IN" 44.333
+cap "X4/XC3/m4_n651_n500#" "X4/IN" -46.5146
+cap "X4/XC3/m4_n651_n500#" "X1/X1/XR17/a_n415_n1322#" 70.3498
+cap "X4/IN" "GND" 306.069
+cap "X1/X1/XR17/a_n415_n1322#" "X1/X1/XM4/a_n989_n100#" 1.52706
+cap "X4/XC3/m4_n651_n500#" "X1/X1/XR17/a_n285_n1192#" 507.521
+cap "X1/X1/GND" "X1/X1/XR17/a_n415_n1322#" 100.708
+cap "X4/IN" "X4/XC2/m4_n651_n300#" -8.83551
+cap "X1/X1/GND" "X4/IN" 75.88
+cap "GND" "X1/X1/XR17/a_n285_n1192#" -32.5047
+cap "X4/XC3/m4_n651_n500#" "GND" 29.2158
+cap "X1/X1/BIAS" "X1/X1/XR17/a_n415_n1322#" 4.44119
+cap "X1/X1/GND" "X1/X1/XR17/a_n285_n1192#" -10.9335
+cap "X4/XC3/m4_n651_n500#" "X1/X1/GND" 18.5231
+cap "X1/X1/XR17/a_n285_n1192#" "X4/XC2/m4_n651_n300#" 283.799
+cap "GND" "X4/XC2/m4_n651_n300#" 8.29238
+cap "X1/X1/GND" "X1/X1/XM4/a_n989_n100#" 14.0825
+cap "X1/X1/XR17/a_n285_n1192#" "X5/ctrll5" 4.62123
+cap "X1/X1/BIAS" "X1/X1/XR17/a_n285_n1192#" 18.7048
+cap "X5/XC2/m4_n651_n300#" "X4/XC2/m4_n651_n300#" 0.88673
+cap "X4/XC3/m4_n651_n500#" "X1/X1/BIAS" -65.2741
+cap "X1/X1/GND" "X1/X1/BIAS" 0.914252
+cap "X1/X1/BIAS" "X4/XC2/m4_n651_n300#" -151.367
+cap "X1/X1/BIAS" "X5/ctrll5" 0.566803
+cap "X1/X1/VDD" "X4/XM5/a_n225_n100#" 239.055
+cap "X5/IN" "X4/XC3/m4_n651_n500#" 46.3835
+cap "X1/X1/SUB" "X4/XM5/a_n317_n100#" 1.83607
+cap "X1/X1/VDD" "X1/X1/GND" 0.515124
+cap "X1/X1/XM4/a_n989_n100#" "X1/X1/BIAS" -0.151908
+cap "X4/XC3/m4_n651_n500#" "X1/X1/GND" -1546.68
+cap "X4/XM5/a_n225_n100#" "X1/X1/GND" 805.545
+cap "X1/X1/BIAS" "X5/ctrll5" 9.68539
+cap "X5/XC2/m4_n651_n300#" "X4/XC2/m4_n651_n300#" 19.0671
+cap "X1/X1/XM4/a_n989_n100#" "X5/ctrll5" 4.74992
+cap "X1/X1/SUB" "X1/X1/BIAS" 2.04822
+cap "X1/X1/VDD" "X5/XC2/m4_n651_n300#" -1435.45
+cap "X1/X1/XM4/a_n989_n100#" "X1/X1/SUB" 3.36313
+cap "X4/XC3/m4_n651_n500#" "X5/XC2/m4_n651_n300#" 27.302
+cap "X1/X1/BIAS" "X4/XC2/m4_n651_n300#" -519.018
+cap "GND" "X4/XC2/m4_n651_n300#" 8.29238
+cap "X4/XM5/a_n225_n100#" "X5/XC2/m4_n651_n300#" 48.0138
+cap "X1/X1/VDD" "X5/XC3/m4_n651_n500#" -581.758
+cap "X1/X1/VDD" "X1/X1/BIAS" 38.51
+cap "X4/XC3/m4_n651_n500#" "X1/X1/BIAS" -5104.13
+cap "X4/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 73.329
+cap "X1/X1/VDD" "X5/ctrll5" 0.570379
+cap "X4/XC3/m4_n651_n500#" "GND" 29.2158
+cap "X5/XC3/m4_n651_n500#" "X4/XM5/a_n225_n100#" 169.698
+cap "X1/X1/XM4/a_n989_n100#" "X4/XC3/m4_n651_n500#" 998.129
+cap "X1/X1/BIAS" "X4/XM5/a_n225_n100#" 18.8072
+cap "X1/X1/XM4/a_n989_n100#" "X4/XM5/a_n225_n100#" 1.78465
+cap "X5/XC3/m4_n651_n500#" "X1/X1/GND" -514.564
+cap "X1/X1/SUB" "X4/XC3/m4_n651_n500#" -253.108
+cap "X1/X1/BIAS" "X1/X1/GND" 238.199
+cap "X1/X1/XM4/a_n989_n100#" "X1/X1/GND" 13.9361
+cap "X1/X1/VDD" "X4/XC2/m4_n651_n300#" -127.491
+cap "X5/IN" "X4/XC2/m4_n651_n300#" 13.1651
+cap "X1/X1/SUB" "X1/X1/GND" 17.7008
+cap "X4/XM5/a_n317_n100#" "X1/X1/BIAS" 2.35191
+cap "X4/XC3/m4_n651_n500#" "X1/X1/VDD" 196.075
+cap "X1/X1/XM4/a_n989_n100#" "X4/XM5/a_n317_n100#" 0.355455
+cap "X5/IN" "X1/X1/VDD" -233.462
+cap "X1/X1/VDD" "X1/X1/SUB" -0.144337
+cap "X5/IN" "X4/XC2/m4_n651_n300#" 13.1651
+cap "X4/XC2/m4_n651_n300#" "X5/XC2/m4_n651_n300#" 9.08563
+cap "X5/XC3/m4_n651_n500#" "X1/X1/SUB" 90.6152
+cap "X1/X1/VDD" "X5/XM5/a_n225_n100#" -148.805
+cap "X4/XM5/a_n225_n100#" "X5/XC2/m4_n651_n300#" 21.3558
+cap "X5/XC3/m4_n651_n500#" "X4/XM5/a_n225_n100#" 75.491
+cap "X5/IN" "X4/IN" 44.333
+cap "X5/IN" "X1/X1/GND" 179.527
+cap "X5/IN" "X5/XC2/m4_n651_n300#" 24.4203
+cap "X5/XC3/m4_n651_n500#" "X1/X1/GND" 144.306
+cap "X1/X1/VDD" "X5/XC2/m4_n651_n300#" 1213.65
+cap "X1/X1/VDD" "X5/IN" 87.8442
+cap "X5/XC3/m4_n651_n500#" "X5/IN" 68.9613
+cap "X5/XC2/m4_n651_n300#" "X10/IN" 13.1651
+cap "X5/IN" "X10/IN" 44.333
+cap "X5/XC3/m4_n651_n500#" "X1/X1/VDD" 433.144
+cap "X5/XC3/m4_n651_n500#" "X10/IN" 46.3835
+cap "X1/X1/SUB" "X5/XM5/a_n317_n100#" 0.35309
+cap "X5/IN" "X4/XC3/m4_n651_n500#" 46.3835
+cap "X4/XC3/m4_n651_n500#" "X5/XC2/m4_n651_n300#" 12.7509
+cap "X10/XC3/m4_n651_n500#" "X5/XC3/m4_n651_n500#" 32.9122
+cap "X5/XC3/m4_n651_n500#" "X4/XC3/m4_n651_n500#" 34.7241
+cap "X10/XC2/m4_n651_n300#" "X5/XC2/m4_n651_n300#" 9.53354
+cap "X1/X1/VDD" "X5/ctrll5" 9.66151
+cap "X1/X1/SUB" "X1/X1/GND" -0.0113404
+cap "X5/XC3/m4_n651_n500#" "X10/XC2/m4_n651_n300#" 10.4849
+cap "X1/X4/XM4/a_n989_n100#" "X10/XC3/m4_n651_n500#" 858.358
+cap "X5/XM5/a_n225_n100#" "X1/X4/SUB" 157.97
+cap "X1/X4/BIAS" "X1/X4/GND" -0.541924
+cap "X11/IN" "X10/IN" 44.333
+cap "X5/IN" "X10/IN" 44.333
+cap "X1/X4/VDD" "X10/XC2/m4_n651_n300#" -46.8946
+cap "X1/X4/GND" "X11/XC3/m4_n651_n500#" -301.465
+cap "X1/X4/XM4/a_n989_n100#" "X10/IN" 5.80541
+cap "X1/X4/BIAS" "X10/XC3/m4_n651_n500#" 31.7032
+cap "X1/X4/VDD" "X10/XC3/m4_n651_n500#" -192.759
+cap "X5/XM5/a_n225_n100#" "X10/XC2/m4_n651_n300#" 48.0138
+cap "X5/XM5/a_n225_n100#" "X1/X4/GND" 274.934
+cap "X11/XC3/m4_n651_n500#" "X10/XC3/m4_n651_n500#" 0.88673
+cap "X1/X4/BIAS" "X10/IN" 24.3935
+cap "X1/X4/VDD" "X10/IN" 118.195
+cap "X5/XM5/a_n225_n100#" "X10/XC3/m4_n651_n500#" 169.698
+cap "X1/X4/XM4/a_n989_n100#" "X5/ctrll5" 3.14172
+cap "X5/XC3/m4_n651_n500#" "X10/XC2/m4_n651_n300#" 27.302
+cap "X5/XC3/m4_n651_n500#" "X1/X4/GND" -264.87
+cap "X1/X4/BIAS" "X5/ctrll5" 6.88625
+cap "X1/X4/VDD" "X5/ctrll5" 3.03814
+cap "X5/XC3/m4_n651_n500#" "X10/XC3/m4_n651_n500#" 52.8121
+cap "X1/X4/SUB" "X1/X4/GND" -0.0485596
+cap "X5/XC3/m4_n651_n500#" "X10/IN" 46.3835
+cap "X5/XC2/m4_n651_n300#" "X10/XC2/m4_n651_n300#" 9.53354
+cap "X1/X4/SUB" "X10/XC3/m4_n651_n500#" 27.9285
+cap "X1/X4/VDD" "X5/XM5/a_n225_n100#" 417.843
+cap "X10/IN" "X5/XC2/m4_n651_n300#" 13.1651
+cap "X11/XC2/m4_n651_n300#" "X10/XC2/m4_n651_n300#" 0.88673
+cap "X1/X4/GND" "X10/XC3/m4_n651_n500#" -100.655
+cap "X5/XM5/a_n317_n100#" "X1/X4/SUB" 1.48298
+cap "X10/IN" "X10/XC2/m4_n651_n300#" 24.4203
+cap "X1/X4/GND" "X10/IN" 154.686
+cap "X1/X4/VDD" "X5/XC3/m4_n651_n500#" -120.93
+cap "X10/IN" "X10/XC3/m4_n651_n500#" 68.9613
+cap "X1/X4/BIAS" "X1/X4/SUB" -1.42751
+cap "X1/X4/VDD" "X1/X4/SUB" -0.190779
+cap "X11/XC3/m4_n651_n500#" "X10/XC3/m4_n651_n500#" 73.329
+cap "X5/XC3/m4_n651_n500#" "X10/XC3/m4_n651_n500#" 17.2973
+cap "X1/X4/VDD" "X10/XC3/m4_n651_n500#" 560.735
+cap "X1/X4/VDD" "X1/X4/SUB" -0.331045
+cap "X1/X4/BIAS" "X10/XC3/m4_n651_n500#" -840.489
+cap "X1/X4/BIAS" "X1/X4/SUB" -0.615959
+cap "X5/XC3/m4_n651_n500#" "X10/XC2/m4_n651_n300#" 5.58748
+cap "X1/X4/GND" "X10/XM5/a_n225_n100#" 311.645
+cap "X1/X4/VDD" "X10/XC2/m4_n651_n300#" -7.16609
+cap "X1/X4/SUB" "X10/XC3/m4_n651_n500#" -194.817
+cap "X11/XC3/m4_n651_n500#" "X1/X4/GND" 80.3061
+cap "X1/X4/XM4/a_n989_n100#" "X5/ctrll5" 1.60821
+cap "X11/XC2/m4_n651_n300#" "X10/XM5/a_n225_n100#" 48.0138
+cap "X1/X4/GND" "X1/X4/BIAS" -0.243473
+cap "X5/XM5/a_n225_n100#" "X10/XC3/m4_n651_n500#" 24.0012
+cap "X11/IN" "X1/X4/VDD" -15.8688
+cap "X1/X4/GND" "X10/XC3/m4_n651_n500#" -889.653
+cap "X1/X4/SUB" "X10/XM5/a_n317_n100#" 1.83607
+cap "X11/XC2/m4_n651_n300#" "X1/X4/VDD" -3.38641
+cap "X1/X4/VDD" "X5/ctrll5" 6.63502
+cap "X1/X4/GND" "X1/X4/SUB" -0.0493443
+cap "X1/X4/BIAS" "X5/ctrll5" 3.36594
+cap "X11/IN" "X10/XC3/m4_n651_n500#" 46.3835
+cap "X5/XM5/a_n225_n100#" "X10/XC2/m4_n651_n300#" 6.78558
+cap "X11/XC2/m4_n651_n300#" "X10/XC3/m4_n651_n500#" 27.302
+cap "X11/IN" "X10/XC2/m4_n651_n300#" 13.1651
+cap "X11/XC2/m4_n651_n300#" "X10/XC2/m4_n651_n300#" 19.0671
+cap "X11/XC3/m4_n651_n500#" "X10/XM5/a_n225_n100#" 169.698
+cap "X10/XC2/m4_n651_n300#" "X5/XC2/m4_n651_n300#" 4.74808
+cap "X1/X4/VDD" "X10/XM5/a_n225_n100#" 509.511
+cap "X1/X4/XM4/a_n989_n100#" "X10/XC3/m4_n651_n500#" -7731.33
+cap "X11/XC2/m4_n651_n300#" "X10/XC3/m4_n651_n500#" 12.7509
+cap "X11/IN" "X1/X4/VDD" 14.9167
+cap "X11/XC3/m4_n651_n500#" "X1/X4/BIAS" 129.861
+cap "X10/XM5/a_n225_n100#" "X11/XC3/m4_n651_n500#" 75.491
+cap "X11/IN" "X10/XC3/m4_n651_n500#" 46.3835
+cap "X10/IN" "X11/IN" 44.333
+cap "X11/IN" "X11/XC3/m4_n651_n500#" -86.8192
+cap "X11/XC3/m4_n651_n500#" "X1/X4/VDD" 43.152
+cap "X11/XC2/m4_n651_n300#" "X1/X4/BIAS" 55.7337
+cap "X11/XC3/m4_n651_n500#" "X1/X4/GND" 4.28199
+cap "X11/XC2/m4_n651_n300#" "X10/XC2/m4_n651_n300#" 9.08563
+cap "X11/XC3/m4_n651_n500#" "X10/XC3/m4_n651_n500#" 34.7241
+cap "X10/XM5/a_n225_n100#" "X11/XC2/m4_n651_n300#" 21.3558
+cap "X11/IN" "X11/XC2/m4_n651_n300#" -23.9884
+cap "X11/XC2/m4_n651_n300#" "X1/X4/VDD" 88.9402
+cap "X11/IN" "X1/X4/BIAS" 33.1912
+cap "X11/IN" "X10/XC2/m4_n651_n300#" 13.1651
+cap "bias_calc_0/XR19/a_n415_n1322#" "bias_calc_0/VDD" 6.6015
+cap "bias_calc_0/BIAS2V" "bias_calc_0/VDD" 1.0743
+cap "bias_calc_0/XR19/a_n285_760#" "bias_calc_0/VDD" 5.48522
+cap "bias_calc_0/XR19/a_n415_n1322#" "bias_calc_0/VDD" 0.454386
+cap "bias_calc_0/VDD" "bias_calc_0/XR19/a_n285_760#" 1.32893
+cap "bias_calc_0/VDD" "bias_calc_0/BIAS2V" 1.49468
+cap "X3/BIAS" "X3/SUB" 378.798
+cap "X3/X4/GND" "m1_50680_31080#" 704.6
+cap "X4/XC1/m4_n551_n300#" "GND" 19.4994
+cap "X3/X4/VDD" "X1/X1/XM4/a_n945_n188#" 0.289415
+cap "X4/XC2/m4_n651_n300#" "X3/X4/VDD" -114.944
+cap "X3/X4/VDD" "X4/XC3/c2_n551_n400#" -80.7643
+cap "GND" "X4/XC3/c2_n551_n400#" 89.4758
+cap "GND" "X3/X4/VDD" 7.79777
+cap "X3/X4/VDD" "X1/X1/XR17/a_n415_n1322#" 403.084
+cap "X4/XM3/a_n33_n100#" "GND" 12.771
+cap "X4/XM3/a_n33_n100#" "X5/XC2/m4_n651_n300#" 0.88673
+cap "X1/X1/BIAS" "X5/ctrll5" 0.566803
+cap "X4/m1_4820_n1420#" "X5/ctrll5" -0.00325358
+cap "GND" "X4/m1_4820_n1420#" 24.6981
+cap "X4/XM3/a_n33_n100#" "X4/XC3/c2_n551_n400#" -39.5943
+cap "X5/XC3/c2_n551_n400#" "X4/XC3/c2_n551_n400#" 8.41795
+cap "X1/X1/XR17/a_n415_n1322#" "X3/X4/VDD" 12.7827
+cap "X4/XC3/c2_n551_n400#" "X4/m1_4820_n1420#" -145.536
+cap "X3/X4/VDD" "X5/ctrll5" 4.62123
+cap "GND" "X3/X4/VDD" -0.431196
+cap "X1/X1/BIAS" "X4/XM3/a_n33_n100#" 17.2475
+cap "X4/XM3/a_n33_n100#" "X3/X4/VDD" 239.215
+cap "X1/X1/GND" "X3/X4/VDD" 0.43242
+cap "GND" "X4/XC3/c2_n551_n400#" 306.069
+cap "X1/X1/XR17/a_n415_n1322#" "X1/X1/GND" 229.072
+cap "X5/XC1/m4_n551_n300#" "X4/m1_4820_n1420#" 1.77346
+cap "X4/XM5/a_n225_n100#" "X1/X1/VDD" 57.798
+cap "X5/ctrll5" "X4/m1_4820_n1420#" 2.84395
+cap "X5/ctrll5" "X1/X1/BIAS" 9.68539
+cap "X1/X1/XR17/a_n415_n1322#" "X4/XM4/a_n81_n100#" 1.53995
+cap "X5/ctrll5" "X4/XM3/a_n33_n100#" -0.0290995
+cap "X4/XM4/a_n81_n100#" "X1/X1/VDD" 44.8246
+cap "X1/X1/XR17/a_n415_n1322#" "X4/m1_4820_n1420#" -1.30681
+cap "X1/X1/XR17/a_n415_n1322#" "X1/X1/BIAS" 17.9919
+cap "X5/ctrll5" "X5/ctrll4" -1.43259
+cap "X1/X1/BIAS" "X1/X1/VDD" 32.8111
+cap "X5/ctrll5" "X1/X1/XM4/a_159_n100#" 4.74992
+cap "X1/X1/XR17/a_n415_n1322#" "X4/XM3/a_n33_n100#" 57.9599
+cap "X1/X1/GND" "X1/X1/VDD" 0.515124
+cap "X4/XM3/a_n33_n100#" "X1/X1/VDD" -272.421
+cap "X1/X1/VDD" "X5/XC2/m4_n651_n300#" -40.2977
+cap "X4/XM5/a_n225_n100#" "X5/XC1/m4_n551_n300#" 122.069
+cap "X4/XM5/a_n225_n100#" "X4/XM4/a_n81_n100#" 79.6215
+cap "X5/XC3/c2_n551_n400#" "X4/m1_4820_n1420#" 83.8969
+cap "X1/X1/XM4/a_159_n100#" "X1/X1/XR17/a_n415_n1322#" 2.19152
+cap "X5/XC1/m4_n551_n300#" "X4/XM4/a_n81_n100#" 69.4118
+cap "GND" "X4/m1_4820_n1420#" 24.6981
+cap "X4/XM5/a_n225_n100#" "X4/m1_4820_n1420#" -35.3611
+cap "X5/XC3/c2_n551_n400#" "X4/XM3/a_n33_n100#" 20.2754
+cap "X4/XM5/a_n225_n100#" "X1/X1/BIAS" 69.7245
+cap "X5/ctrll5" "X1/X1/XR17/a_n415_n1322#" -0.38787
+cap "X5/ctrll5" "X5/ctrll3" -0.704687
+cap "X5/XC1/m4_n551_n300#" "X4/m1_4820_n1420#" 60.8535
+cap "X5/ctrll5" "X1/X1/VDD" 0.570379
+cap "GND" "X4/XM3/a_n33_n100#" 12.771
+cap "X4/XM5/a_n225_n100#" "X5/XC2/m4_n651_n300#" 94.4298
+cap "X4/m1_4820_n1420#" "X4/XM4/a_n81_n100#" 94.0947
+cap "X1/X1/GND" "X4/XM5/a_n225_n100#" 3.85923
+cap "X1/X1/BIAS" "X4/XM4/a_n81_n100#" 56.706
+cap "X5/XC1/m4_n551_n300#" "X4/XM3/a_n33_n100#" 48.4932
+cap "X4/XM4/a_n81_n100#" "X5/XC2/m4_n651_n300#" 42.1098
+cap "X1/X1/XM4/a_159_n100#" "X4/XM5/a_n225_n100#" 0.466677
+cap "X4/XM3/a_n33_n100#" "X4/m1_4820_n1420#" 60.8827
+cap "X1/X1/BIAS" "X5/XC2/m4_n651_n300#" -64.3687
+cap "X1/X1/BIAS" "X4/XM3/a_n33_n100#" -370.88
+cap "X5/ctrll5" "X4/XM5/a_n225_n100#" 41.3005
+cap "X4/XM3/a_n33_n100#" "X5/XC2/m4_n651_n300#" 29.4192
+cap "X5/ctrll5" "X5/XC1/m4_n551_n300#" 3.62215
+cap "X5/ctrll5" "X4/XM4/a_n81_n100#" 1.18001
+cap "X5/XC3/c2_n551_n400#" "X1/X1/VDD" -35.8774
+cap "X1/X1/XR17/a_n415_n1322#" "X4/XM5/a_n225_n100#" 26.5612
+cap "X4/XM5/a_n225_n100#" "X5/m1_4820_n1420#" 54.2945
+cap "X4/XM1/a_n175_n274#" "X5/XM3/a_n33_n100#" 59.831
+cap "X5/XM5/a_n225_n100#" "X5/XM4/a_n81_n100#" -262.07
+cap "X4/XM1/a_n175_n274#" "X4/XM5/a_n225_n100#" 8.09189
+cap "X5/XC3/c2_n551_n400#" "X4/XC3/c2_n551_n400#" 8.41795
+cap "X5/XM4/a_n81_n100#" "X5/ctrll5" -58.8293
+cap "X1/X1/BIAS" "X10/XC3/c2_n551_n400#" -105.045
+cap "X1/X1/VDD" "X5/XM4/a_n81_n100#" -53.4649
+cap "X5/XM5/a_n225_n100#" "X5/m1_4820_n1420#" 6.2556
+cap "X10/XC1/m4_n551_n300#" "X5/XM4/a_n81_n100#" 26.6566
+cap "X4/XM4/a_n81_n100#" "X5/XM3/a_n33_n100#" 19.6667
+cap "X5/m1_4820_n1420#" "X5/ctrll5" 36.8724
+cap "X5/ctrll4" "X5/ctrll5" -0.303882
+cap "X1/X1/BIAS" "X10/XC2/m4_n651_n300#" -149.499
+cap "X1/X1/BIAS" "X5/XM4/a_n81_n100#" -40.4134
+cap "X4/XM1/a_n175_n274#" "X5/ctrll5" -0.369124
+cap "X5/XC3/c2_n551_n400#" "X10/XC3/c2_n551_n400#" 8.41795
+cap "X10/XC3/c2_n551_n400#" "X5/m1_4820_n1420#" 38.4368
+cap "X10/XC2/m4_n651_n300#" "X5/XM4/a_n81_n100#" 16.1717
+cap "X5/XM3/a_n33_n100#" "X4/XM5/a_n225_n100#" 53.3133
+cap "X10/XC1/m4_n551_n300#" "X5/m1_4820_n1420#" 37.1701
+cap "X4/XM1/a_n175_n274#" "X1/X1/VDD" 11.1862
+cap "X5/XC3/c2_n551_n400#" "X4/XM3/a_n33_n100#" 20.2754
+cap "X4/XM1/a_n175_n274#" "X1/X1/BIAS" 13.0133
+cap "X5/m1_4820_n1420#" "X5/XM4/a_n81_n100#" -47.4248
+cap "X4/XM3/a_n33_n100#" "X5/m1_4820_n1420#" 23.107
+cap "X4/XM1/a_n175_n274#" "X5/XM4/a_n81_n100#" -231.667
+cap "X5/XM3/a_n33_n100#" "X5/ctrll5" -0.000833203
+cap "X5/XC3/c2_n551_n400#" "X5/m1_4820_n1420#" -134.237
+cap "X5/XM3/a_n33_n100#" "X10/XC3/c2_n551_n400#" 20.2754
+cap "X1/X1/VDD" "X5/XM3/a_n33_n100#" 405.354
+cap "X4/XM1/a_n175_n274#" "X5/m1_4820_n1420#" -0.705417
+cap "X5/XM3/a_n33_n100#" "X10/XC1/m4_n551_n300#" 24.2466
+cap "X1/X1/BIAS" "X5/XM3/a_n33_n100#" -10.3123
+cap "X5/XM3/a_n33_n100#" "X10/XC2/m4_n651_n300#" 14.7096
+cap "X4/XM3/a_n33_n100#" "X5/XM3/a_n33_n100#" 14.0183
+cap "X4/XM4/a_n81_n100#" "X5/m1_4820_n1420#" 32.4176
+cap "X1/X1/VDD" "X5/XM5/a_n225_n100#" -29.138
+cap "X5/XC3/c2_n551_n400#" "X5/XM3/a_n33_n100#" 11.6121
+cap "X5/XM3/a_n33_n100#" "X5/m1_4820_n1420#" 60.8802
+cap "X1/X1/VDD" "X5/ctrll5" 9.66151
+cap "X5/XC3/c2_n551_n400#" "X4/m1_4820_n1420#" 83.8969
+cap "X5/m1_4820_n1420#" "X4/m1_4820_n1420#" 42.5006
+cap "X5/XM3/a_n33_n100#" "X10/m1_4820_n1420#" 24.2466
+cap "X1/X4/BIAS" "X5/XM5/a_n225_n100#" 70.1521
+cap "X1/X4/BIAS" "X5/ctrll5" 6.88625
+cap "X11/XC2/m4_n651_n300#" "X10/XM3/a_n33_n100#" 0.88673
+cap "X5/XM3/a_n33_n100#" "X10/XM3/a_n33_n100#" 14.7096
+cap "X1/X4/BIAS" "X1/X4/VDD" -5.36708
+cap "X5/ctrll5" "X5/XM5/a_n225_n100#" 42.8713
+cap "X10/XC3/c2_n551_n400#" "X10/m1_4820_n1420#" -134.237
+cap "X1/X4/BIAS" "X5/XM4/a_n81_n100#" -5.14177
+cap "X1/X4/BIAS" "X1/X1/XR16/a_n415_n1322#" 2.65085
+cap "X5/XM5/a_n225_n100#" "X5/m1_4820_n1420#" -35.1914
+cap "X5/XM5/a_n225_n100#" "X1/X4/VDD" 67.0361
+cap "X5/ctrll5" "X5/m1_4820_n1420#" 104.938
+cap "X10/XC3/c2_n551_n400#" "X10/XM3/a_n33_n100#" 11.6121
+cap "X5/ctrll5" "X1/X4/VDD" 3.03814
+cap "X5/XM4/a_n81_n100#" "X5/XM5/a_n225_n100#" 79.9032
+cap "X10/XC3/c2_n551_n400#" "X5/XM3/a_n33_n100#" 20.2754
+cap "X5/XM4/a_n81_n100#" "X5/ctrll5" 144.544
+cap "X1/X1/XR16/a_n415_n1322#" "X5/XM5/a_n225_n100#" 8.42492
+cap "X5/ctrll5" "X1/X1/XR16/a_n415_n1322#" 1316.11
+cap "X5/XM4/a_n81_n100#" "X5/m1_4820_n1420#" 94.0947
+cap "X5/XM4/a_n81_n100#" "X1/X4/VDD" 180.812
+cap "X1/X4/BIAS" "X10/XM3/a_n33_n100#" 170.865
+cap "X1/X1/XR16/a_n415_n1322#" "X1/X4/VDD" 2.27868
+cap "X11/XC1/m4_n551_n300#" "X10/m1_4820_n1420#" 1.77346
+cap "X5/XM5/a_n225_n100#" "X10/m1_4820_n1420#" 122.069
+cap "X5/XM4/a_n81_n100#" "X1/X1/XR16/a_n415_n1322#" -0.736229
+cap "X5/ctrll5" "X10/m1_4820_n1420#" 3.49446
+cap "X5/XM5/a_n225_n100#" "X10/XM3/a_n33_n100#" 94.4298
+cap "X5/ctrll5" "X5/ctrll4" -1.845
+cap "X5/m1_4820_n1420#" "X10/m1_4820_n1420#" 43.118
+cap "X5/XM4/a_n81_n100#" "X10/m1_4820_n1420#" 69.4118
+cap "X1/X4/VDD" "X10/XM3/a_n33_n100#" 179.102
+cap "X10/XC3/c2_n551_n400#" "X5/XC3/c2_n551_n400#" 8.41795
+cap "X5/ctrll5" "X5/ctrll3" -1.025
+cap "X5/XM4/a_n81_n100#" "X10/XM3/a_n33_n100#" 42.1098
+cap "X5/ctrll5" "X1/X4/XM4/a_159_n100#" 3.14172
+cap "X10/XC3/c2_n551_n400#" "X5/m1_4820_n1420#" 167.704
+cap "X10/XC3/c2_n551_n400#" "X11/XC3/c2_n551_n400#" 8.41795
+cap "X1/X4/GND" "X5/XM5/a_n225_n100#" 3.85923
+cap "X5/ctrll4" "X5/ctrll5" -1.51941
+cap "X5/m1_4820_n1420#" "X10/m1_4820_n1420#" 25.3826
+cap "X1/X4/BIAS" "X1/X4/VDD" -1.935
+cap "X1/X4/BIAS" "X5/ctrll5" 3.36594
+cap "X1/X4/XR17/a_n415_n1322#" "X1/X4/VDD" 9.9951
+cap "X1/X4/XR17/a_n415_n1322#" "X5/ctrll5" -0.812709
+cap "X11/XC1/m4_n551_n300#" "X10/XM4/a_n81_n100#" 69.4118
+cap "X10/XM5/a_n225_n100#" "X10/m1_4820_n1420#" -35.2035
+cap "X10/XM5/a_n225_n100#" "X1/X4/GND" 3.95441
+cap "X10/XM4/a_n81_n100#" "X1/X4/VDD" 45.1606
+cap "X10/XM5/a_n225_n100#" "X1/X4/BIAS" 70.9987
+cap "X5/ctrll3" "X5/ctrll5" -0.576562
+cap "X10/XM5/a_n225_n100#" "X11/XC2/m4_n651_n300#" 94.4298
+cap "X5/ctrll5" "X10/XM4/a_n81_n100#" 1.1999
+cap "X10/XM5/a_n225_n100#" "X1/X4/XR17/a_n415_n1322#" 8.42492
+cap "X10/XM3/a_n33_n100#" "X5/XM5/a_n225_n100#" 30.8406
+cap "X10/XM3/a_n33_n100#" "X11/XC3/c2_n551_n400#" 20.2754
+cap "X5/XM5/a_n225_n100#" "X10/m1_4820_n1420#" 17.2515
+cap "X11/XC3/c2_n551_n400#" "X10/m1_4820_n1420#" 83.8969
+cap "X10/XM3/a_n33_n100#" "X10/m1_4820_n1420#" 60.8802
+cap "X1/X4/XM4/a_159_n100#" "X5/ctrll5" 1.60821
+cap "X10/XM5/a_n225_n100#" "X10/XM4/a_n81_n100#" 79.8832
+cap "X10/XM3/a_n33_n100#" "X1/X4/BIAS" -52.456
+cap "X1/X4/XR17/a_n415_n1322#" "X5/XM5/a_n225_n100#" 8.09189
+cap "X10/XM3/a_n33_n100#" "X11/XC2/m4_n651_n300#" 29.4192
+cap "X1/X4/BIAS" "X11/XC3/c2_n551_n400#" -32.7921
+cap "X5/ctrll5" "X11/XC1/m4_n551_n300#" 3.62663
+cap "X1/X4/XR17/a_n415_n1322#" "X10/XM3/a_n33_n100#" 59.6049
+cap "X5/ctrll5" "X1/X4/VDD" 6.63502
+cap "X1/X4/XR17/a_n415_n1322#" "X10/m1_4820_n1420#" -0.768949
+cap "X10/XM3/a_n33_n100#" "X5/XM3/a_n33_n100#" 7.32469
+cap "X5/XM3/a_n33_n100#" "X10/m1_4820_n1420#" 12.0737
+cap "X1/X4/BIAS" "X11/XC2/m4_n651_n300#" -33.8049
+cap "X10/XM5/a_n225_n100#" "X11/XC1/m4_n551_n300#" 122.069
+cap "X1/X4/XR17/a_n415_n1322#" "X1/X4/BIAS" 15.64
+cap "X10/XM4/a_n81_n100#" "X10/m1_4820_n1420#" 94.0947
+cap "X10/XM5/a_n225_n100#" "X1/X4/VDD" 73.0645
+cap "X10/XM5/a_n225_n100#" "X5/ctrll5" 42.78
+cap "X1/X4/BIAS" "X10/XM4/a_n81_n100#" 54.6841
+cap "X11/XC2/m4_n651_n300#" "X10/XM4/a_n81_n100#" 42.1098
+cap "X1/X4/XR17/a_n415_n1322#" "X10/XM4/a_n81_n100#" -0.911973
+cap "X10/XM3/a_n33_n100#" "X5/XM4/a_n81_n100#" 8.61798
+cap "X10/XM3/a_n33_n100#" "X11/XC1/m4_n551_n300#" 48.4932
+cap "X5/XM4/a_n81_n100#" "X10/m1_4820_n1420#" 14.2055
+cap "X11/XC1/m4_n551_n300#" "X10/m1_4820_n1420#" 60.8535
+cap "X10/XM3/a_n33_n100#" "X1/X4/VDD" 262.581
+cap "X10/XM3/a_n33_n100#" "X5/ctrll5" -0.00932799
+cap "X5/ctrll5" "X10/m1_4820_n1420#" 112.735
+cap "X11/XC3/c2_n551_n400#" "X10/XC3/c2_n551_n400#" 8.41795
+cap "X11/m1_4820_n1420#" "X11/XC3/c2_n551_n400#" -134.237
+cap "X11/XM3/a_n33_n100#" "X10/XM4/a_n81_n100#" 19.6667
+cap "CTRL1" "X1/X4/XM1/a_n1091_n274#" 0.733598
+cap "X1/X4/XM1/a_n1091_n274#" "X11/ctrll5" 67.7761
+cap "X11/XC3/c2_n551_n400#" "X10/m1_4820_n1420#" 83.8969
+cap "X11/ctrll2" "X1/X4/XM1/a_n1091_n274#" 0.882775
+cap "X11/m1_4820_n1420#" "X11/ctrll5" 131.308
+cap "X11/ctrll4" "X11/ctrll5" 14.3328
+cap "X11/XM3/a_n33_n100#" "X11/XC3/c2_n551_n400#" -37.0855
+cap "X1/X4/BIAS" "X11/XM3/a_n33_n100#" 90.2452
+cap "X10/XM3/a_n33_n100#" "X11/XC3/c2_n551_n400#" 20.2754
+cap "X11/XM3/a_n33_n100#" "X11/ctrll5" -0.00012557
+cap "X11/m1_4820_n1420#" "X1/X4/XM1/a_n1091_n274#" -12.5904
+cap "X11/ctrll4" "X1/X4/XM1/a_n1091_n274#" 1.49797
+cap "X11/m1_4820_n1420#" "X10/m1_4820_n1420#" 42.5006
+cap "X11/ctrll3" "X11/ctrll5" 10.7587
+cap "X11/XM3/a_n33_n100#" "X1/X4/XM1/a_n1091_n274#" -0.268679
+cap "X11/XM3/a_n33_n100#" "X11/m1_4820_n1420#" -0.00251052
+cap "X10/XM5/a_n225_n100#" "X1/X4/XM1/a_n1091_n274#" 8.09189
+cap "X11/m1_4820_n1420#" "X10/XM5/a_n225_n100#" 54.2945
+cap "X11/XM4/a_n81_n100#" "X1/X4/XM1/a_n1091_n274#" -17.1993
+cap "X11/m1_4820_n1420#" "X10/XM3/a_n33_n100#" 23.107
+cap "CTRL1" "X11/ctrll5" 7.2936
+cap "X10/XM4/a_n81_n100#" "X11/m1_4820_n1420#" 32.4176
+cap "X11/ctrll3" "X1/X4/XM1/a_n1091_n274#" 1.10259
+cap "X11/ctrll2" "X11/ctrll5" 8.71005
+cap "X11/XM3/a_n33_n100#" "X10/XM5/a_n225_n100#" 53.3133
+cap "X11/XM3/a_n33_n100#" "X10/XM3/a_n33_n100#" 14.0183
+cap "X11/XM5/a_n225_n100#" "X1/X4/XR16/a_n415_n1322#" 32.1421
+cap "X1/X4/XR16/a_n415_n1322#" "X11/ctrll3" 10.0047
+cap "X11/XM5/a_n225_n100#" "X11/ctrll3" 8.56607
+cap "X11/ctrll2" "X11/ctrll5" 28.6758
+cap "X1/X4/XR16/a_n415_n1322#" "X11/ctrll4" 14.3159
+cap "X1/X4/XR16/a_n415_n1322#" "X11/XM4/a_n81_n100#" 6.72914
+cap "X11/XM5/a_n225_n100#" "X11/ctrll4" 12.5139
+cap "CTRL1" "X11/ctrll5" 8.30618
+cap "X1/X4/XR16/a_n415_n1322#" "X11/ctrll2" 7.79575
+cap "X1/X4/XR16/a_n415_n1322#" "X11/ctrll5" 1722.87
+cap "X11/XM5/a_n225_n100#" "X11/ctrll2" 6.60138
+cap "X11/XM5/a_n225_n100#" "X11/ctrll5" 48.4505
+cap "X11/ctrll3" "X11/ctrll5" 37.2619
+cap "X1/X4/XR16/a_n415_n1322#" "CTRL1" 3.18208
+cap "X11/m1_4820_n1420#" "X11/ctrll5" 136.906
+cap "X11/XM5/a_n225_n100#" "CTRL1" 2.67491
+cap "X11/XM4/a_n81_n100#" "X11/ctrll5" 187.022
+cap "X11/ctrll4" "X11/ctrll5" 55.4958
+cap "CTRL1" "X11/XM5/a_n225_n100#" 2.67491
+cap "X11/ctrll5" "CTRL1" 14.8662
+cap "X11/XM5/a_n317_n100#" "CTRL1" 3.18208
+cap "X3/X1/VDD" "X3/X1/XR1/a_n703_n3602#" 7.01954
+cap "m1_46210_32690#" "X3/X1/XR1/a_n703_n3602#" 378.798
+cap "X3/OUT180" "X3/X1/VDD" 162.094
+cap "X3/X1/VDD" "X3/X1/XR1/a_n703_n3602#" 22.5699
+cap "X3/X1/XR1/a_n703_n3602#" "VDD" 36.4397
+cap "X3/OUT0" "VDD" 243.319
+cap "output_buffer_0/XR3/a_n703_n2202#" "VDD" 12.3852
+cap "output_buffer_0/BIAS" "output_buffer_0/XR3/a_n703_n2202#" 704.6
+cap "output_buffer_0/BIAS" "VDD" -10.7975
+cap "output_buffer_0/XR3/a_n703_n2202#" "X3/X4/VDD" 21.2216
+cap "X3/X1/XR2/a_n703_n3602#" "X3/X4/VDD" 1166.96
+cap "X4/XC2/c2_n551_n200#" "X4/GND" 45.6966
+cap "X3/X4/XR1/a_n703_n3602#" "X1/X1/VDD" 344.056
+cap "X4/GND" "X4/XM1/a_n73_n100#" 19.4994
+cap "X4/GND" "X1/X1/VDD" -32.1746
+cap "X4/XM1/a_n73_n100#" "X4/GND" 35.9535
+cap "X4/XC2/c2_n551_n200#" "X4/GND" 195.472
+cap "X4/XM1/a_n73_n100#" "X4/XC2/c2_n551_n200#" -135.805
+cap "X4/XM1/a_n73_n100#" "X5/XC6/m4_n551_n300#" 1.77346
+cap "X4/XM5/a_n225_n100#" "X5/GND" 3.01397
+cap "X5/ctrll3" "X5/ctrll5" -0.704687
+cap "X5/ctrll4" "X5/XM1/a_n73_n100#" 4.03186
+cap "X4/XM1/a_n73_n100#" "X5/XM1/a_n73_n100#" 35.4709
+cap "X4/XM4/a_n81_n100#" "X1/X1/BIAS" 3.63429
+cap "X5/m1_4820_n890#" "X4/XM5/a_n225_n100#" 4.62167
+cap "X4/XM5/a_n225_n100#" "X5/XM1/a_n73_n100#" 2.23793
+cap "X5/GND" "X5/XM1/a_n73_n100#" 0.789004
+cap "X5/ctrll3" "X4/XM3/a_n33_n100#" 14.8767
+cap "X5/ctrll4" "X5/ctrll2" -1.22425
+cap "X4/XM2/a_15_n100#" "X5/XC2/c2_n551_n200#" 84.9956
+cap "X5/ctrll3" "X5/ctrll4" -4.17736
+cap "X5/ctrll3" "X5/ctrll1" -1.09821
+cap "X5/ctrll5" "X5/ctrll4" -1.43259
+cap "X5/ctrll3" "X5/GND" -0.0124387
+cap "X4/XM1/a_n73_n100#" "X5/XC2/c2_n551_n200#" 22.154
+cap "X4/XM2/a_15_n100#" "X4/XM3/a_n33_n100#" -0.194139
+cap "X4/XM4/a_n81_n100#" "X4/XM2/a_15_n100#" -11.7473
+cap "X4/XM4/a_n81_n100#" "X5/ctrll4" 44.3366
+cap "X5/GND" "X4/XM3/a_n33_n100#" 86.5121
+cap "X4/XM4/a_n81_n100#" "X5/GND" 25.7374
+cap "X4/XM5/a_n225_n100#" "X4/XM2/a_15_n100#" -5.19848
+cap "X4/XM4/a_n81_n100#" "X4/XM5/a_n225_n100#" -0.0021211
+cap "X4/XM2/a_15_n100#" "X5/GND" -0.00479267
+cap "X5/ctrll3" "X5/ctrll2" -2.88281
+cap "X5/m1_4820_n890#" "X4/XM3/a_n33_n100#" 8.64948
+cap "X5/XM1/a_n73_n100#" "X4/XM3/a_n33_n100#" 69.0731
+cap "X4/XM1/a_n73_n100#" "X5/ctrll4" 10.8456
+cap "X5/m1_4820_n890#" "X4/XM4/a_n81_n100#" 11.0133
+cap "X4/XM4/a_n81_n100#" "X5/XM1/a_n73_n100#" 117.108
+cap "X5/ctrll1" "X5/ctrll4" -0.787028
+cap "X4/XM2/a_15_n100#" "X5/XM1/a_n73_n100#" 25.4672
+cap "X5/GND" "X5/ctrll4" -0.0122756
+cap "X4/XM1/a_n73_n100#" "X5/GND" 44.7651
+cap "X5/XC2/c2_n551_n200#" "X4/XM2/a_15_n100#" 84.9956
+cap "X5/XM3/a_n33_n100#" "output_buffer_0/GND" 8.28199
+cap "X5/ctrll3" "X5/GND" -0.0450144
+cap "X4/XM3/a_n33_n100#" "X5/XM1/a_n73_n100#" 43.687
+cap "X4/XM4/a_n81_n100#" "X5/XM1/a_n73_n100#" 52.9759
+cap "X5/ctrll1" "X5/ctrll4" -0.116119
+cap "X5/XM1/a_n73_n100#" "X4/XM1/a_n73_n100#" 17.118
+cap "X5/XC2/c2_n551_n200#" "X4/XM1/a_n73_n100#" 22.154
+cap "X4/XM3/a_n33_n100#" "X5/XM3/a_n33_n100#" 8.64948
+cap "X5/XM4/a_n81_n100#" "X5/ctrll4" -71.1917
+cap "X5/GND" "X5/XM3/a_n33_n100#" 31.059
+cap "X4/XM4/a_n81_n100#" "X5/XM3/a_n33_n100#" 11.0133
+cap "X5/XM1/a_n73_n100#" "X5/ctrll4" 40.5905
+cap "X5/XM4/a_n81_n100#" "X10/XM1/a_n73_n100#" 5.29616
+cap "X5/XM5/a_n225_n100#" "X5/XM4/a_n81_n100#" 0.00743942
+cap "X5/XM1/a_n73_n100#" "X4/XM5/a_n225_n100#" 0.995399
+cap "X5/XM3/a_n33_n100#" "X5/ctrll4" 0.192011
+cap "X5/ctrll2" "X5/ctrll4" -0.068972
+cap "X5/XM1/a_n73_n100#" "X10/XM1/a_n73_n100#" 17.7355
+cap "X5/XM1/a_n73_n100#" "X10/XC2/c2_n551_n200#" 22.154
+cap "X4/XM5/a_n225_n100#" "X5/XM3/a_n33_n100#" 4.62167
+cap "X5/ctrll3" "X5/XM1/a_n73_n100#" -1.71466
+cap "X5/XM3/a_n33_n100#" "X10/XM1/a_n73_n100#" 28.433
+cap "X5/GND" "X4/XM4/a_n81_n100#" 7.37728
+cap "X4/XM3/a_n33_n100#" "X5/GND" 5.95311
+cap "X5/XC2/c2_n551_n200#" "X5/XM1/a_n73_n100#" -125.505
+cap "X5/ctrll3" "X5/XM3/a_n33_n100#" -69.9727
+cap "X5/XM4/a_n81_n100#" "X5/XM2/a_15_n100#" 8.92721
+cap "X5/XM4/a_n81_n100#" "output_buffer_0/GND" 0.134601
+cap "X5/GND" "X5/ctrll4" -0.0781752
+cap "X5/ctrll5" "X5/ctrll4" -0.303882
+cap "X5/XM1/a_n73_n100#" "output_buffer_0/GND" 15.4733
+cap "X5/GND" "X4/XM5/a_n225_n100#" 3.04255
+cap "X5/GND" "X5/XM4/a_n81_n100#" 0.00784023
+cap "X5/ctrll5" "X5/XM4/a_n81_n100#" 0.00083606
+cap "X5/XM1/a_n73_n100#" "X4/XM2/a_15_n100#" 25.4672
+cap "X10/XM3/a_n33_n100#" "X5/XM5/a_n225_n100#" 4.62167
+cap "X5/XM3/a_n33_n100#" "X10/XM3/a_n33_n100#" 8.64948
+cap "X10/XM1/a_n73_n100#" "X5/XM3/a_n33_n100#" 62.8379
+cap "X5/ctrll3" "X5/ctrll2" -2.30625
+cap "X10/XM1/a_n73_n100#" "X5/XM5/a_n225_n100#" 2.23793
+cap "X1/X4/BIAS" "X5/XM4/a_n81_n100#" 3.63663
+cap "X5/XM5/a_n225_n100#" "X5/XM2/a_15_n100#" -5.19848
+cap "X5/XM3/a_n33_n100#" "X5/XM2/a_15_n100#" -1.34411e-05
+cap "X5/ctrll3" "X5/ctrll4" -5.56981
+cap "X10/XM1/a_n73_n100#" "output_buffer_0/GND" 9.42422
+cap "X5/XM5/a_n225_n100#" "X5/XM4/a_n81_n100#" -0.0021211
+cap "X10/XM1/a_n73_n100#" "X10/XC2/c2_n551_n200#" -125.505
+cap "X5/ctrll4" "X5/ctrll1" -0.774126
+cap "output_buffer_0/GND" "X5/XM4/a_n81_n100#" 8.39011
+cap "X5/ctrll3" "X5/XM3/a_n33_n100#" 158.24
+cap "X10/XC2/c2_n551_n200#" "X5/XM2/a_15_n100#" 169.991
+cap "X5/ctrll3" "X5/ctrll1" -1.42768
+cap "X10/XC2/c2_n551_n200#" "X5/XM1/a_n73_n100#" 22.154
+cap "X5/GND" "X5/XM4/a_n81_n100#" 13.7283
+cap "X5/GND" "X5/XM2/a_15_n100#" -0.00479267
+cap "output_buffer_0/GND" "X5/XM3/a_n33_n100#" 13.6921
+cap "X5/ctrll4" "X5/GND" 1316.53
+cap "X10/XM1/a_n73_n100#" "X5/XM2/a_15_n100#" 25.4672
+cap "X10/XM3/a_n33_n100#" "X5/XM4/a_n81_n100#" 11.0133
+cap "X10/XM1/a_n73_n100#" "X5/XM4/a_n81_n100#" 118.378
+cap "X10/XM1/a_n73_n100#" "X5/XM1/a_n73_n100#" 17.7355
+cap "X10/XM1/a_n73_n100#" "X5/ctrll4" 4.03186
+cap "X5/ctrll3" "X5/GND" 1316.53
+cap "X5/ctrll4" "X5/ctrll5" -1.845
+cap "X10/XM1/a_n73_n100#" "X11/XC6/m4_n551_n300#" 1.77346
+cap "X5/XM4/a_n81_n100#" "X5/XM2/a_15_n100#" -11.7473
+cap "X5/GND" "X5/XM5/a_n225_n100#" 3.01397
+cap "X5/XM3/a_n33_n100#" "X5/GND" 12.9351
+cap "X5/ctrll4" "X5/ctrll2" -0.948364
+cap "X5/ctrll3" "X10/XM1/a_n73_n100#" -1.71466
+cap "X5/ctrll3" "X5/ctrll5" -1.025
+cap "X5/ctrll4" "X5/XM4/a_n81_n100#" 474.425
+cap "X5/XM4/a_n81_n100#" "X5/GND" 7.37728
+cap "X5/GND" "X5/XM3/a_n33_n100#" 5.95311
+cap "X5/ctrll3" "X10/XM3/a_n33_n100#" 14.8767
+cap "X10/XM3/a_n33_n100#" "X11/m1_4820_n890#" 8.64948
+cap "X10/XM2/a_15_n100#" "X10/XM5/a_n225_n100#" -5.19848
+cap "X10/XM4/a_n81_n100#" "X5/ctrll4" 44.3366
+cap "X10/XM4/a_n81_n100#" "X11/XM1/a_n73_n100#" 117.108
+cap "X10/XM4/a_n81_n100#" "GND" 8.52471
+cap "X5/ctrll3" "X5/GND" -0.0574531
+cap "X10/XM5/a_n225_n100#" "X5/GND" 3.01397
+cap "X10/XM4/a_n81_n100#" "X10/XM5/a_n225_n100#" -0.0021211
+cap "X10/XM4/a_n81_n100#" "X11/m1_4820_n890#" 11.0133
+cap "X5/XM5/a_n225_n100#" "X10/XM1/a_n73_n100#" 0.316277
+cap "X5/ctrll4" "X11/XM1/a_n73_n100#" 4.03186
+cap "X10/XM2/a_15_n100#" "X10/XM3/a_n33_n100#" -0.189784
+cap "GND" "X11/XM1/a_n73_n100#" 0.789004
+cap "X5/XM5/a_n225_n100#" "X10/XM3/a_n33_n100#" 4.62167
+cap "X5/ctrll5" "X5/ctrll4" -1.51941
+cap "X5/ctrll3" "X5/ctrll4" -3.89887
+cap "X10/XM5/a_n225_n100#" "X11/XM1/a_n73_n100#" 2.23793
+cap "X5/GND" "X10/XM3/a_n33_n100#" 58.1881
+cap "X10/XM2/a_15_n100#" "X5/GND" -0.00479267
+cap "X5/XM5/a_n225_n100#" "X5/GND" 3.04255
+cap "X10/XM4/a_n81_n100#" "X10/XM2/a_15_n100#" -11.7473
+cap "X5/ctrll5" "X5/ctrll3" -0.576562
+cap "X5/ctrll1" "X5/ctrll4" -0.916049
+cap "X10/XM1/a_n73_n100#" "X5/XM2/a_15_n100#" 25.4672
+cap "X10/XM1/a_n73_n100#" "X11/XC2/c2_n551_n200#" 22.154
+cap "X10/XM5/a_n225_n100#" "X11/m1_4820_n890#" 4.62167
+cap "X5/XM4/a_n81_n100#" "X10/XM1/a_n73_n100#" 17.7823
+cap "X10/XM1/a_n73_n100#" "X5/ctrll4" -26.4881
+cap "X10/XM1/a_n73_n100#" "X11/XM1/a_n73_n100#" 35.4709
+cap "X10/XM1/a_n73_n100#" "X5/XM3/a_n33_n100#" 26.749
+cap "X10/XM4/a_n81_n100#" "X5/GND" 13.7283
+cap "X5/ctrll2" "X5/ctrll4" -1.13804
+cap "X10/XM2/a_15_n100#" "X11/XC2/c2_n551_n200#" 84.9956
+cap "X5/XM4/a_n81_n100#" "X10/XM3/a_n33_n100#" 11.0133
+cap "X10/XM4/a_n81_n100#" "X1/X4/BIAS" 3.63429
+cap "X10/XM3/a_n33_n100#" "X5/ctrll4" 0.192011
+cap "X10/XM1/a_n73_n100#" "GND" 6.83804
+cap "X5/XM3/a_n33_n100#" "X10/XM3/a_n33_n100#" 8.64948
+cap "X5/ctrll1" "X5/ctrll3" -1.23
+cap "X10/XM2/a_15_n100#" "X11/XM1/a_n73_n100#" 25.4672
+cap "X10/XM3/a_n33_n100#" "X11/XM1/a_n73_n100#" 69.0731
+cap "GND" "X10/XM3/a_n33_n100#" 21.9741
+cap "X10/XM1/a_n73_n100#" "X5/ctrll3" 31.2436
+cap "X5/GND" "X5/ctrll4" -0.0904508
+cap "X5/ctrll2" "X5/ctrll3" -2.1525
+cap "X11/ctrll3" "X11/XM2/a_15_n100#" 0.0606183
+cap "X10/XM2/a_15_n100#" "X11/XM1/a_n73_n100#" 25.4672
+cap "GND" "X11/XM1/a_n73_n100#" 15.4733
+cap "X11/XM4/a_n81_n100#" "X11/ctrll4" -79.5872
+cap "X11/GND" "X11/ctrll2" 1.47129
+cap "X11/XC2/c2_n551_n200#" "X10/XM2/a_15_n100#" 84.9956
+cap "X11/GND" "X11/XM3/a_n33_n100#" -23.5834
+cap "X11/GND" "X11/ctrll3" 14.2116
+cap "X11/GND" "X10/XM4/a_n81_n100#" 7.37728
+cap "X11/GND" "X10/XM3/a_n33_n100#" 5.95311
+cap "X11/GND" "X11/ctrll4" 48.8417
+cap "GND" "X11/XM3/a_n33_n100#" 8.28199
+cap "X11/GND" "X11/ctrll1" 1.22266
+cap "X11/GND" "X10/XM5/a_n225_n100#" 3.04255
+cap "X11/ctrll3" "X11/XM1/a_n73_n100#" -1.71466
+cap "X10/XM3/a_n33_n100#" "X11/XM1/a_n73_n100#" 43.687
+cap "X11/XM1/a_n73_n100#" "X10/XM4/a_n81_n100#" 52.9759
+cap "X11/XM1/a_n73_n100#" "X11/ctrll4" 113.619
+cap "X11/XC2/c2_n551_n200#" "X11/XM1/a_n73_n100#" -125.505
+cap "X10/XM1/a_n73_n100#" "X11/XM1/a_n73_n100#" 17.118
+cap "X10/XM5/a_n225_n100#" "X11/XM1/a_n73_n100#" 0.995399
+cap "X11/GND" "X11/XM2/a_15_n100#" -14.3992
+cap "X11/ctrll3" "X11/ctrll2" 2.83021
+cap "X11/ctrll2" "X11/ctrll4" 5.84562
+cap "X11/ctrll3" "X11/XM3/a_n33_n100#" -78.6664
+cap "X10/XM4/a_n81_n100#" "X11/XM3/a_n33_n100#" 11.0133
+cap "X10/XM3/a_n33_n100#" "X11/XM3/a_n33_n100#" 8.64948
+cap "X11/ctrll4" "X11/XM3/a_n33_n100#" 0.192011
+cap "X11/ctrll3" "X11/ctrll4" 7.03158
+cap "X11/ctrll3" "X11/ctrll1" 2.66718
+cap "X11/ctrll1" "X11/ctrll4" 4.89913
+cap "X11/GND" "X11/XM4/a_n81_n100#" -11.0877
+cap "X11/XC2/c2_n551_n200#" "X10/XM1/a_n73_n100#" 22.154
+cap "X10/XM5/a_n225_n100#" "X11/XM3/a_n33_n100#" 4.62167
+cap "GND" "X11/XM4/a_n81_n100#" 0.134601
+cap "GND" "X11/XM3/a_n33_n100#" 13.6921
+cap "X11/ctrll4" "X11/ctrll1" 3.24172
+cap "X11/ctrll3" "X11/ctrll5" 3.98981
+cap "X11/XM3/a_n33_n100#" "X11/ctrll1" 1.0974
+cap "X11/ctrll5" "X11/XM5/a_n225_n100#" 0.935775
+cap "GND" "X11/XM4/a_n81_n100#" 8.39011
+cap "X11/XM4/a_n81_n100#" "X11/ctrll1" 2.1948
+cap "X11/GND" "X11/ctrll4" 1943.37
+cap "X11/ctrll3" "X11/ctrll2" 11.9764
+cap "X11/GND" "X11/XM3/a_n33_n100#" 16.0269
+cap "X11/XM5/a_n225_n100#" "X11/ctrll2" 1.52339
+cap "X11/ctrll5" "X11/ctrll1" 1.2496
+cap "X11/GND" "X11/XM4/a_n81_n100#" 15.3351
+cap "X11/ctrll3" "X11/XM2/a_15_n100#" -0.520321
+cap "X11/ctrll3" "X11/XM5/a_n225_n100#" 1.97679
+cap "X11/ctrll3" "X11/ctrll1" 3.27495
+cap "X11/GND" "X11/ctrll2" 12.984
+cap "X11/XM5/a_n225_n100#" "X11/ctrll1" 0.617286
+cap "X11/GND" "X11/ctrll3" 2138.75
+cap "X11/XM4/a_n81_n100#" "X11/ctrll4" 676.143
+cap "X11/GND" "X11/XM5/a_n225_n100#" 1.96349
+cap "X11/ctrll4" "X11/ctrll5" 6.14142
+cap "X11/GND" "X11/ctrll1" 5.30047
+cap "X11/ctrll4" "X11/ctrll2" 14.1947
+cap "X11/XM3/a_n33_n100#" "X11/ctrll2" 2.70826
+cap "X11/XM4/a_n81_n100#" "X11/ctrll2" 5.41651
+cap "X11/ctrll3" "X11/ctrll4" 15.1702
+cap "X11/ctrll4" "X11/XM2/a_15_n100#" 0.0214046
+cap "X11/XM3/a_n33_n100#" "X11/ctrll3" 245.5
+cap "X11/ctrll4" "X11/XM5/a_n225_n100#" 2.88783
+cap "X11/XM3/a_n33_n100#" "X11/XM2/a_15_n100#" -1.34411e-05
+cap "X11/ctrll5" "X11/ctrll2" 3.1365
+cap "X11/XM4/a_n81_n100#" "X11/ctrll3" 7.02857
+cap "X11/ctrll5" "X11/ctrll1" 1.2496
+cap "X11/GND" "X11/ctrll1" 5.30047
+cap "X11/ctrll4" "X11/ctrll1" 8.03945
+cap "X11/ctrll3" "X11/ctrll1" 6.13763
+cap "X11/XM4/a_n81_n100#" "X11/ctrll1" 2.1948
+cap "X11/XM3/a_n33_n100#" "X11/ctrll1" 1.0974
+cap "X11/XM5/a_n225_n100#" "X11/ctrll1" 0.617286
+cap "output_buffer_0/GND" "output_buffer_0/VDD" 0.541306
+cap "output_buffer_0/VDD" "output_buffer_0/GND" -235.461
+cap "output_buffer_0/XR2/a_n415_n1322#" "output_buffer_0/VDD" -53.8237
+cap "output_buffer_0/VDD" "output_buffer_0/BIAS" 482.461
+cap "output_buffer_0/XR2/a_n415_n1322#" "output_buffer_0/BIAS" 221.452
+cap "output_buffer_0/BIAS" "output_buffer_0/VDD" 6.95277
+cap "output_buffer_0/XR2/a_n285_760#" "output_buffer_0/XR2/a_n415_n1322#" 3.99736
+cap "output_buffer_0/VDD" "output_buffer_0/INB" 501.329
+cap "output_buffer_0/INB" "output_buffer_0/XR2/a_n415_n1322#" 29.4353
+cap "output_buffer_0/VDD" "output_buffer_0/XR2/a_n415_n1322#" 51.7107
+cap "X3/X1/VDD" "VDD" 545.265
+cap "VDD" "X3/X1/XR1/a_n703_n3602#" 36.4397
+cap "X3/X1/VDD" "output_buffer_0/OUTB" 8.11509
+cap "X3/X1/VDD" "X3/X1/XR1/a_n703_n3602#" -2.27886
+cap "X3/X1/VDD" "output_buffer_0/INA" 87.975
+cap "output_buffer_0/INA" "output_buffer_0/OUTB" 19.8899
+cap "output_buffer_0/INA" "X3/X1/XR1/a_n703_n3602#" -143.205
+cap "X3/X1/VDD" "output_buffer_0/XR3/a_n703_n2202#" -23.3291
+cap "output_buffer_0/XR3/a_n703_n2202#" "VDD" 26.0991
+cap "X3/X1/VDD" "output_buffer_0/BIAS" 415.058
+cap "output_buffer_0/INA" "VDD" 430.594
+cap "output_buffer_0/BIAS" "VDD" -58.102
+cap "X3/X1/VDD" "VDD" 495.269
+cap "output_buffer_0/INA" "output_buffer_0/XR3/a_n703_n2202#" -8.61382
+cap "output_buffer_0/XR3/a_n703_n2202#" "output_buffer_0/BIAS" 289.45
+cap "output_buffer_0/XR3/a_n703_n2202#" "output_buffer_0/VDD" 52.3181
+cap "output_buffer_0/VDD" "output_buffer_0/BIAS" 51.779
+cap "X3/X1/XR2/a_n703_n3602#" "output_buffer_0/VDD" 1719.55
+cap "X4/XM1/a_n73_n100#" "output_buffer_0/VDD" 3.22302
+cap "output_buffer_0/VDD" "X4/GND" 198.704
+cap "X4/GND" "X3/X4/XR1/a_n703_n3602#" 42.2835
+cap "X4/GND" "output_buffer_0/GND" 2.75526
+cap "X4/XM1/a_n73_n100#" "X4/GND" 6.36974
+cap "output_buffer_0/VDD" "X4/ctrll1" 0.912412
+cap "output_buffer_0/VDD" "X3/X4/XR1/a_n703_n3602#" 54.6959
+cap "X5/ctrll2" "X4/XM1/a_n73_n100#" -3.50131
+cap "X3/X4/VDD" "X5/ctrll1" 11.0486
+cap "X4/GND" "X4/XM1/a_n73_n100#" 121.205
+cap "X3/X4/VDD" "X4/GND" -572.993
+cap "X4/GND" "X5/ctrll1" -238.394
+cap "X3/X4/VDD" "X4/XM1/a_n73_n100#" 13.8515
+cap "X4/XC6/c2_n451_n200#" "X4/GND" 13.2936
+cap "X5/ctrll2" "X4/GND" -1.23374
+cap "X5/ctrll1" "X4/XM1/a_n73_n100#" -108.563
+cap "X4/XM2/a_15_n100#" "X5/ctrll1" -182.618
+cap "X5/ctrll4" "X5/ctrll2" -1.22425
+cap "X3/X4/VDD" "X5/ctrll1" 3.93829
+cap "X4/XM2/a_15_n100#" "X5/ctrll2" -6.85034
+cap "X5/ctrll2" "X5/XM1/a_n73_n100#" 2.00386
+cap "X4/XM2/a_15_n100#" "X5/GND" 262.079
+cap "X5/GND" "X5/XM1/a_n73_n100#" 10.4631
+cap "X5/ctrll3" "X5/ctrll1" -1.09821
+cap "X4/XM3/a_n33_n100#" "X5/GND" 34.8578
+cap "X4/XM1/a_n73_n100#" "X5/ctrll1" -0.0241201
+cap "X5/GND" "X3/X4/VDD" 12.7812
+cap "X5/ctrll2" "X5/ctrll1" 1.05163
+cap "X5/GND" "X5/ctrll1" -110.192
+cap "X4/XM2/a_15_n100#" "X5/XM1/a_n73_n100#" 37.032
+cap "X5/ctrll3" "X5/ctrll2" -2.88281
+cap "X5/ctrll4" "X5/ctrll1" -0.787028
+cap "X4/XM1/a_n73_n100#" "X5/ctrll2" -0.0153937
+cap "X4/XM1/a_n73_n100#" "X5/GND" 56.2266
+cap "X5/GND" "X5/ctrll2" 30.9611
+cap "X4/XM4/a_n81_n100#" "X5/GND" 16.3171
+cap "X5/XM1/a_n73_n100#" "X5/ctrll2" -6.09474
+cap "X5/XM1/a_n73_n100#" "X5/ctrll1" -120.903
+cap "X5/XM1/a_n73_n100#" "output_buffer_0/GND" 73.665
+cap "X10/XM1/a_n73_n100#" "X5/GND" 6.40472
+cap "X5/GND" "X4/XM2/a_15_n100#" 9.43138
+cap "X5/ctrll2" "X5/ctrll4" -0.068972
+cap "X5/ctrll1" "X5/ctrll4" -0.116119
+cap "X5/ctrll1" "X5/ctrll2" 11.6681
+cap "X5/XM1/a_n73_n100#" "X5/GND" 30.3735
+cap "X5/XM1/a_n73_n100#" "X4/XM2/a_15_n100#" 37.032
+cap "X5/GND" "X5/XM2/a_15_n100#" -106.565
+cap "X10/XM1/a_n73_n100#" "X5/ctrll2" 0.47556
+cap "X5/ctrll2" "X5/GND" -7.40002
+cap "X5/ctrll1" "X5/GND" -5.31919
+cap "output_buffer_0/GND" "X5/XM3/a_n33_n100#" 8.28199
+cap "X5/ctrll1" "X4/XM2/a_15_n100#" 1.607
+cap "X5/XM4/a_n81_n100#" "output_buffer_0/GND" 0.134601
+cap "X5/GND" "output_buffer_0/GND" -4.86976
+cap "X10/XM1/a_n73_n100#" "output_buffer_0/GND" 58.8872
+cap "X5/GND" "output_buffer_0/GND" -0.453729
+cap "output_buffer_0/GND" "X5/XM4/a_n81_n100#" 8.39011
+cap "X5/GND" "X5/ctrll1" 937.916
+cap "X10/XM1/a_n73_n100#" "X5/ctrll1" -109.412
+cap "X5/ctrll2" "X5/ctrll1" 0.0583849
+cap "output_buffer_0/GND" "X5/XM2/a_15_n100#" 51.726
+cap "X5/ctrll1" "X5/XM2/a_15_n100#" -109.336
+cap "X5/GND" "X5/XM3/a_n33_n100#" 7.03392
+cap "X5/ctrll3" "X5/ctrll2" -2.30625
+cap "X5/ctrll4" "X5/ctrll2" -0.948364
+cap "X10/XM1/a_n73_n100#" "X5/GND" 34.9012
+cap "X5/GND" "X5/XM4/a_n81_n100#" 4.30804
+cap "X5/ctrll3" "X5/ctrll1" -1.42768
+cap "X10/XM1/a_n73_n100#" "X5/ctrll2" 0.320602
+cap "X5/ctrll2" "X5/GND" 1753.54
+cap "output_buffer_0/GND" "X5/XM3/a_n33_n100#" 13.6921
+cap "X10/XM1/a_n73_n100#" "X5/XM2/a_15_n100#" 74.064
+cap "X5/GND" "X5/XM2/a_15_n100#" 109.046
+cap "X5/ctrll2" "X5/XM2/a_15_n100#" -9.98175
+cap "X5/ctrll4" "X5/ctrll1" -0.774126
+cap "X11/XM1/a_n73_n100#" "X5/ctrll2" 2.00386
+cap "X5/XM2/a_15_n100#" "X5/ctrll1" 1.16399
+cap "X5/ctrll1" "X10/XM1/a_n73_n100#" 81.3315
+cap "GND" "X5/GND" -8.10218
+cap "X5/ctrll1" "X5/ctrll3" -1.23
+cap "X5/ctrll2" "X5/GND" 821.772
+cap "X5/XM2/a_15_n100#" "X10/XM1/a_n73_n100#" 1.95549
+cap "X11/XM1/a_n73_n100#" "X10/XM2/a_15_n100#" 37.032
+cap "X5/ctrll2" "X5/ctrll4" -1.13804
+cap "GND" "X10/XM4/a_n81_n100#" 8.52471
+cap "X5/ctrll2" "X5/ctrll1" 4.04207
+cap "X10/XM2/a_15_n100#" "X5/GND" 100.126
+cap "GND" "X10/XM1/a_n73_n100#" 15.5668
+cap "X10/XM3/a_n33_n100#" "X5/GND" 7.03392
+cap "X5/ctrll2" "X10/XM1/a_n73_n100#" 29.8242
+cap "X11/XM1/a_n73_n100#" "X5/GND" 9.67414
+cap "X10/XM2/a_15_n100#" "X5/ctrll1" -109.779
+cap "X5/ctrll2" "X5/ctrll3" -2.1525
+cap "X10/XM4/a_n81_n100#" "X5/GND" 4.30804
+cap "X5/GND" "X5/ctrll1" 889.147
+cap "X5/ctrll1" "X5/ctrll4" -0.916049
+cap "GND" "X10/XM2/a_15_n100#" 51.726
+cap "X5/GND" "X5/XM2/a_15_n100#" 7.86268
+cap "X10/XM2/a_15_n100#" "X5/ctrll2" -6.85034
+cap "GND" "X10/XM3/a_n33_n100#" 21.9741
+cap "GND" "X11/XM1/a_n73_n100#" 0.789004
+cap "X5/GND" "X10/XM1/a_n73_n100#" 51.589
+cap "X11/ctrll1" "X10/XM2/a_15_n100#" 1.607
+cap "X11/XM1/a_n73_n100#" "GND" 73.665
+cap "X11/XM1/a_n73_n100#" "X10/XM2/a_15_n100#" 37.032
+cap "X11/ctrll2" "X11/ctrll4" -0.068972
+cap "X11/ctrll1" "X11/ctrll4" -0.0516084
+cap "X11/ctrll2" "X11/GND" 7.01701
+cap "X11/ctrll1" "X11/GND" 3.19065
+cap "GND" "X11/XM4/a_n81_n100#" 0.134601
+cap "X11/XM1/a_n73_n100#" "X11/GND" 30.3735
+cap "GND" "X11/XM3/a_n33_n100#" 8.28199
+cap "GND" "X11/GND" -4.86976
+cap "X11/XM2/a_15_n100#" "X11/GND" -9.89457
+cap "X10/XM2/a_15_n100#" "X11/GND" 9.43138
+cap "X11/ctrll1" "X11/ctrll2" 8.38623
+cap "X11/XM1/a_n73_n100#" "X11/ctrll2" -6.09474
+cap "X11/ctrll1" "X11/XM1/a_n73_n100#" -120.903
+cap "X11/ctrll2" "X11/ctrll3" -0.730313
+cap "X11/ctrll1" "X11/ctrll3" -0.3075
+cap "X11/ctrll1" "X11/GND" 2446.72
+cap "GND" "X11/XM3/a_n33_n100#" 13.6921
+cap "X11/ctrll3" "X11/ctrll2" -0.960938
+cap "X11/XM2/a_15_n100#" "GND" 51.726
+cap "X11/ctrll4" "X11/ctrll2" -0.431075
+cap "X11/XM2/a_15_n100#" "X11/ctrll2" -2.34078
+cap "GND" "X11/GND" -0.913219
+cap "X11/ctrll3" "X11/ctrll1" -0.988393
+cap "X11/XM2/a_15_n100#" "X11/GND" 17.3823
+cap "X11/GND" "X11/ctrll2" 2959.4
+cap "X11/ctrll1" "X11/ctrll4" -0.580594
+cap "X11/ctrll1" "X11/XM2/a_15_n100#" -50.0812
+cap "X11/ctrll1" "X11/ctrll2" -0.428785
+cap "X11/XM4/a_n81_n100#" "GND" 8.39011
+cap "X11/GND" "X11/ctrll1" 1.05919
+cap "X11/XM2/a_15_n100#" "X11/ctrll1" 1.0974
+cap "X11/ctrll2" "X11/ctrll1" 3.46622
+cap "output_buffer_0/VDD" "output_buffer_0/GND" -1.09472
+cap "output_buffer_0/VDD" "output_buffer_0/XM2/a_n1091_n274#" -3.05242
+cap "output_buffer_0/VDD" "output_buffer_0/GND" 14.4151
+cap "output_buffer_0/GND" "output_buffer_0/BIAS" 1.49143
+cap "output_buffer_0/GND" "output_buffer_0/VDD" -0.483927
+cap "output_buffer_0/XM2/a_n989_n100#" "output_buffer_0/BIAS" 1.87706
+cap "output_buffer_0/VDD" "output_buffer_0/BIAS" 2.89929
+cap "output_buffer_0/XM2/a_n1091_n274#" "output_buffer_0/VDD" 8.70234
+cap "output_buffer_0/XM2/a_n705_n100#" "output_buffer_0/BIAS" 0.437143
+cap "output_buffer_0/VDD" "output_buffer_0/BIAS" 4.26656
+cap "output_buffer_0/VDD" "output_buffer_0/XR2/a_n415_n1322#" 9.07733
+cap "output_buffer_0/XM2/a_n609_n100#" "output_buffer_0/BIAS" 0.93853
+cap "output_buffer_0/INB" "output_buffer_0/OUTB" 9.71669
+cap "output_buffer_0/BIAS" "output_buffer_0/INB" 3.55271e-15
+cap "output_buffer_0/XR2/a_n415_n1322#" "output_buffer_0/INB" -0.0675188
+cap "output_buffer_0/XR2/a_n285_760#" "output_buffer_0/XR2/a_n415_n1322#" 7.99471
+cap "output_buffer_0/BIAS" "output_buffer_0/INA" -1.12824
+cap "output_buffer_0/BIAS" "output_buffer_0/XR2/a_n415_n1322#" -0.019782
+cap "output_buffer_0/OUTB" "X3/X1/XR1/a_n703_n3602#" -1.24645
+cap "output_buffer_0/OUTB" "X3/X1/VDD" 8.11509
+cap "output_buffer_0/INB" "output_buffer_0/OUTB" 9.71669
+cap "output_buffer_0/OUTB" "output_buffer_0/INA" 66.7289
+cap "output_buffer_0/BIAS" "output_buffer_0/INA" -1.12824
+cap "output_buffer_0/INA" "X3/X1/XR1/a_n703_n3602#" -0.0442274
+cap "output_buffer_0/XR3/a_n703_n2202#" "output_buffer_0/BIAS" -0.318261
+cap "output_buffer_0/XR3/a_n703_n2202#" "X3/X1/VDD" 17.2331
+cap "output_buffer_0/XR3/a_n703_n2202#" "output_buffer_0/VDD" 17.2331
+cap "output_buffer_0/VDD" "X3/X1/XR2/a_n703_n3602#" 52.0245
+cap "GND" "X10/m1_4820_n890#" 12.3302
+cap "GND" "X10/XM1/a_n73_n100#" 1.60101
+cap "GND" "X10/XM2/a_15_n100#" 9.48744
+cap "X11/m1_4820_n890#" "GND" 4.64599
+cap "X11/XM1/a_n73_n100#" "GND" 10.6734
+cap "X11/m1_4820_n890#" "GND" 7.68423
+cap "GND" "X11/XM2/a_15_n100#" 9.48744
+cap "output_buffer_0/GND" "output_buffer_0/BIAS" 27.8186
+cap "output_buffer_0/GND" "output_buffer_0/XM2/a_n989_n100#" 22.1835
+cap "output_buffer_0/XM2/a_n989_n100#" "output_buffer_0/BIAS" 5.27038
+cap "output_buffer_0/XM2/a_n609_n100#" "output_buffer_0/BIAS" 1.6926
+cap "output_buffer_0/XM2/a_n705_n100#" "output_buffer_0/BIAS" 0.897178
+cap "output_buffer_0/XR2/a_n415_n1322#" "output_buffer_0/BIAS" -0.179595
+cap "output_buffer_0/XM2/a_n609_n100#" "output_buffer_0/XM2/a_n705_n100#" 11.0391
+cap "output_buffer_0/XM4/a_n1665_n100#" "GND" 2.75526
+merge "X11/GND" "X10/GND" -1927.15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34855937 -6480 0 0 -46076788 -21160 -71665653 -30356 -3709020 -10194 6101050 -16800 0 0
+merge "X10/GND" "X5/GND"
+merge "X5/GND" "output_buffer_0/GND"
+merge "output_buffer_0/GND" "X4/GND"
+merge "X4/GND" "X1/X1/SUB"
+merge "X1/X1/SUB" "X3/X4/XR1/a_n703_n3602#"
+merge "X3/X4/XR1/a_n703_n3602#" "X3/X1/SUB"
+merge "X3/X1/SUB" "li_55194_32310#"
+merge "li_55194_32310#" "X1/X1/GND"
+merge "X1/X1/GND" "X3/X4/GND"
+merge "X3/X4/GND" "X3/X1/GND"
+merge "X3/X1/GND" "X3/X5/GND"
+merge "X3/X5/GND" "li_52140_31175#"
+merge "li_52140_31175#" "X3/X5/XR18/a_n415_n4762#"
+merge "X3/X5/XR18/a_n415_n4762#" "li_36440_31120#"
+merge "li_36440_31120#" "X1/SUB"
+merge "X1/SUB" "X3/X4/XR2/a_n703_n3602#"
+merge "X3/X4/XR2/a_n703_n3602#" "X1/X1/XR17/a_n415_n1322#"
+merge "X1/X1/XR17/a_n415_n1322#" "li_55184_29702#"
+merge "li_55184_29702#" "X3/X4/SUB"
+merge "X3/X4/SUB" "X3/X3/SUB"
+merge "X3/X3/SUB" "X3/X2/SUB"
+merge "X3/X2/SUB" "li_55174_27882#"
+merge "li_55174_27882#" "X1/X2/SUB"
+merge "X1/X2/SUB" "X3/X2/XR2/a_n703_n3602#"
+merge "X3/X2/XR2/a_n703_n3602#" "X3/X2/GND"
+merge "X3/X2/GND" "X1/X2/GND"
+merge "X1/X2/GND" "X1/X2/XR17/a_n415_n1322#"
+merge "X1/X2/XR17/a_n415_n1322#" "li_55178_25280#"
+merge "li_55178_25280#" "X3/X3/GND"
+merge "X3/X3/GND" "X3/X2/XR1/a_n703_n3602#"
+merge "X3/X2/XR1/a_n703_n3602#" "li_52135_26050#"
+merge "li_52135_26050#" "bias_calc_0/XR20/a_n415_n1702#"
+merge "bias_calc_0/XR20/a_n415_n1702#" "X3/X6/GND"
+merge "X3/X6/GND" "X3/X6/XR21/a_n415_n4762#"
+merge "X3/X6/XR21/a_n415_n4762#" "bias_calc_0/SUB"
+merge "bias_calc_0/SUB" "li_34160_25810#"
+merge "li_34160_25810#" "li_33670_25540#"
+merge "li_33670_25540#" "X3/X6/XC2/m3_n2150_n3100#"
+merge "X3/X6/XC2/m3_n2150_n3100#" "bias_calc_0/GND"
+merge "bias_calc_0/GND" "bias_calc_0/XM40/a_n611_n274#"
+merge "bias_calc_0/XM40/a_n611_n274#" "li_32925_24370#"
+merge "li_32925_24370#" "X9/GND"
+merge "X9/GND" "X8/GND"
+merge "X8/GND" "X7/GND"
+merge "X7/GND" "X6/GND"
+merge "X6/GND" "GND"
+merge "X1/X4/OUTA" "X11/IN" -2090.65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4734800 -200 -2656635 -2112 0 0 7524800 -2090 0 0
+merge "X11/IN" "X3/I4A"
+merge "X3/I4A" "m3_61085_29785#"
+merge "m3_61085_29785#" "X1/X1/INB"
+merge "X1/X1/INB" "X1/S4A"
+merge "output_buffer_0/VSUBS" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/VSUBS" "X11/VSUBS"
+merge "X11/VSUBS" "X10/VSUBS"
+merge "X10/VSUBS" "X5/VSUBS"
+merge "X5/VSUBS" "X4/VSUBS"
+merge "X4/VSUBS" "X1/VSUBS"
+merge "X1/VSUBS" "bias_calc_0/VSUBS"
+merge "bias_calc_0/VSUBS" "X9/VSUBS"
+merge "X9/VSUBS" "X8/VSUBS"
+merge "X8/VSUBS" "X7/VSUBS"
+merge "X7/VSUBS" "X6/VSUBS"
+merge "X6/VSUBS" "X3/VSUBS"
+merge "X3/VSUBS" "VSUBS"
+merge "X3/I2B" "X3/X2/INB" 6777.91 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3330400 -220 2057200 -2306 -2928420 0 4300620 -1460 0 0
+merge "X3/X2/INB" "X1/S2B"
+merge "X1/S2B" "m3_56407_27820#"
+merge "m3_56407_27820#" "X1/X2/OUTB"
+merge "X1/X2/OUTB" "X6/IN"
+merge "X6/IN" "m3_55465_27385#"
+merge "X3/X2/INA" "X3/I2A" 4258.23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2107890 -210 10047690 -1820 0 0 -1083200 -1700 0 0
+merge "X3/I2A" "X1/S2A"
+merge "X1/S2A" "X1/X2/OUTA"
+merge "X1/X2/OUTA" "X7/IN"
+merge "X7/IN" "m3_57710_27380#"
+merge "X3/I3B" "X1/S3B" 14199.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1904000 -200 20902350 -1610 0 0 -4757275 -1300 0 0
+merge "X1/S3B" "X8/IN"
+merge "X8/IN" "X1/X3/OUTB"
+merge "X1/X3/OUTB" "m3_59620_27555#"
+merge "X10/ctrll3" "X11/ctrll3" -8523.15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -11988605 -19750 0 0 0 0 0 0 0 0 0 0
+merge "X11/ctrll3" "m1_61595_35305#"
+merge "m1_61595_35305#" "X4/ctrll3"
+merge "X4/ctrll3" "m1_59465_35305#"
+merge "m1_59465_35305#" "X5/ctrll3"
+merge "X5/ctrll3" "m1_57355_35305#"
+merge "m1_57355_35305#" "X8/ctrll3"
+merge "X8/ctrll3" "CTRL3"
+merge "CTRL3" "X9/ctrll3"
+merge "X9/ctrll3" "m1_61575_22265#"
+merge "m1_61575_22265#" "X6/ctrll3"
+merge "X6/ctrll3" "m1_59460_22265#"
+merge "m1_59460_22265#" "X7/ctrll3"
+merge "X7/ctrll3" "m1_57370_22265#"
+merge "output_buffer_0/BIAS" "X1/X1/BIAS" -5429.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -6897817 -7632 0 0 0 0 0 0 0 0 0 0
+merge "X1/X1/BIAS" "X1/X1/XM4/a_n945_n188#"
+merge "X1/X1/XM4/a_n945_n188#" "bias_calc_0/BIASOUT"
+merge "bias_calc_0/BIASOUT" "m1_46210_32690#"
+merge "m1_46210_32690#" "X3/BIAS"
+merge "X3/BIAS" "m1_36045_25020#"
+merge "m1_36045_25020#" "X3/X4/BIAS"
+merge "X3/X4/BIAS" "m1_55108_31074#"
+merge "m1_55108_31074#" "X3/X1/BIAS"
+merge "X3/X1/BIAS" "m1_50680_31080#"
+merge "X1/X1/OUTA" "X3/I1A" -5.00242 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5401300 -200 2375450 -2600 0 0 -2982800 -1710 0 0
+merge "X3/I1A" "X5/IN"
+merge "X5/IN" "m3_57735_29855#"
+merge "m3_57735_29855#" "m3_57480_29855#"
+merge "m3_57480_29855#" "X1/S1A"
+merge "X10/ctrll4" "X11/ctrll4" -12227.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -17303460 -19780 0 0 0 0 0 0 0 0 0 0
+merge "X11/ctrll4" "m1_61570_34715#"
+merge "m1_61570_34715#" "X4/ctrll4"
+merge "X4/ctrll4" "m1_59460_34715#"
+merge "m1_59460_34715#" "X5/ctrll4"
+merge "X5/ctrll4" "m1_57380_34715#"
+merge "m1_57380_34715#" "X8/ctrll4"
+merge "X8/ctrll4" "CTRL4"
+merge "CTRL4" "X9/ctrll4"
+merge "X9/ctrll4" "m1_61575_22855#"
+merge "m1_61575_22855#" "X6/ctrll4"
+merge "X6/ctrll4" "m1_59460_22855#"
+merge "m1_59460_22855#" "X7/ctrll4"
+merge "X7/ctrll4" "m1_57350_22855#"
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_93_n161#" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n35_n161#" -15483.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13599019 -1910 -14642085 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n35_n161#" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n163_n161#"
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n163_n161#" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_35_n64#"
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_35_n64#" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n221_n64#"
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n221_n64#" "bias_calc_0/BIAS2V"
+merge "bias_calc_0/BIAS2V" "m1_33455_32800#"
+merge "X1/X1/OUTB" "X3/I1B" 6893.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7330400 -200 6349800 -1610 -3110580 0 1341400 -1910 0 0
+merge "X3/I1B" "X1/S1B"
+merge "X1/S1B" "X4/IN"
+merge "X4/IN" "m3_55465_29875#"
+merge "X10/ctrll5" "X11/ctrll5" -11859.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -16486705 -14190 0 0 0 0 0 0 0 0 0 0
+merge "X11/ctrll5" "m1_61555_33805#"
+merge "m1_61555_33805#" "X4/ctrll5"
+merge "X4/ctrll5" "m1_59460_33805#"
+merge "m1_59460_33805#" "X5/ctrll5"
+merge "X5/ctrll5" "m1_57385_33805#"
+merge "m1_57385_33805#" "X8/ctrll5"
+merge "X8/ctrll5" "CTRL5"
+merge "CTRL5" "X9/ctrll5"
+merge "X9/ctrll5" "m1_61580_23765#"
+merge "m1_61580_23765#" "X6/ctrll5"
+merge "X6/ctrll5" "m1_59445_23765#"
+merge "m1_59445_23765#" "X7/ctrll5"
+merge "X7/ctrll5" "m1_57370_23765#"
+merge "output_buffer_0/INB" "X3/OUT180" -7159.61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5882780 -100 -4504700 0 -4296700 -860 0 0 0 0 0 0
+merge "X3/OUT180" "m1_47700_36500#"
+merge "X3/X6/VOP" "X3/VOP" -5121.02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1081350 -150 3531600 -18600 0 0 0 0 0 0 0 0
+merge "X3/VOP" "bias_calc_0/VOP"
+merge "bias_calc_0/VOP" "m1_35620_27495#"
+merge "X10/ctrll1" "X11/ctrll1" -2067.25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1278580 -25210 0 0 0 0 0 0 0 0 0 0
+merge "X11/ctrll1" "m1_61580_36205#"
+merge "m1_61580_36205#" "X4/ctrll1"
+merge "X4/ctrll1" "m1_59485_36205#"
+merge "m1_59485_36205#" "X5/ctrll1"
+merge "X5/ctrll1" "m1_57390_36205#"
+merge "m1_57390_36205#" "X8/ctrll1"
+merge "X8/ctrll1" "CTRL1"
+merge "CTRL1" "X9/ctrll1"
+merge "X9/ctrll1" "m1_61570_21365#"
+merge "m1_61570_21365#" "X6/ctrll1"
+merge "X6/ctrll1" "m1_59480_21365#"
+merge "m1_59480_21365#" "X7/ctrll1"
+merge "X7/ctrll1" "m1_57360_21365#"
+merge "output_buffer_0/VDD" "X3/X4/VDD" -24784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19733237 -868 1579073 -984 -38028689 -33218 -11939035 -4090 -17707620 -3030 29828810 -39601 0 0
+merge "X3/X4/VDD" "m2_55046_36460#"
+merge "m2_55046_36460#" "X3/X1/VDD"
+merge "X3/X1/VDD" "X3/m2_18710_20900#"
+merge "X3/m2_18710_20900#" "X1/X1/VDD"
+merge "X1/X1/VDD" "bias_calc_0/VDD"
+merge "bias_calc_0/VDD" "bias_calc_0/PSUB"
+merge "bias_calc_0/PSUB" "li_33260_31990#"
+merge "li_33260_31990#" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_163_n64#"
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_163_n64#" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n93_n64#"
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/a_n93_n64#" "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/w_n359_n284#"
+merge "sky130_fd_pr__pfet_01v8_lvt_75KH85_0/w_n359_n284#" "X1/X2/VDD"
+merge "X1/X2/VDD" "X3/X2/VDD"
+merge "X3/X2/VDD" "VDD"
+merge "X10/ctrll2" "X11/ctrll2" -18130.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -26192400 -19590 0 0 0 0 0 0 0 0 0 0
+merge "X11/ctrll2" "m1_61585_35845#"
+merge "m1_61585_35845#" "X4/ctrll2"
+merge "X4/ctrll2" "m1_59490_35845#"
+merge "m1_59490_35845#" "X5/ctrll2"
+merge "X5/ctrll2" "m1_57365_35845#"
+merge "m1_57365_35845#" "X8/ctrll2"
+merge "X8/ctrll2" "CTRL2"
+merge "CTRL2" "X9/ctrll2"
+merge "X9/ctrll2" "m1_61565_21725#"
+merge "m1_61565_21725#" "X6/ctrll2"
+merge "X6/ctrll2" "m1_59475_21725#"
+merge "m1_59475_21725#" "X7/ctrll2"
+merge "X7/ctrll2" "m1_57370_21725#"
+merge "X1/X2/BIAS" "X3/X2/BIAS" 1027.79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 985628 -760 0 0 0 0 0 0 0 0 0 0
+merge "X3/X2/BIAS" "m1_55094_26496#"
+merge "X3/I3A" "X1/S3A" -698.663 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2268000 -200 -3775780 -2092 0 0 9673340 -2010 0 0
+merge "X1/S3A" "X9/IN"
+merge "X9/IN" "X1/X3/OUTA"
+merge "X1/X3/OUTA" "m3_61090_27360#"
+merge "output_buffer_0/INA" "X3/OUT0" -688.563 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -897000 -810 0 0 592540 -860 0 0 0 0 0 0
+merge "X3/OUT0" "m1_48170_36500#"
+merge "X1/X4/OUTB" "X10/IN" 8928.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7330400 -200 6353230 -2100 0 0 -10078695 -1200 0 0
+merge "X10/IN" "X3/I4B"
+merge "X3/I4B" "m3_59300_29490#"
+merge "m3_59300_29490#" "X1/S4B"
+merge "X3/AMP" "bias_calc_0/AMP" -2466.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2636800 -230 0 0 0 0 -2765220 -828 0 0 0 0
+merge "bias_calc_0/AMP" "m1_35580_30580#"

mag/VCO.mag

diff --git a/mag/VCO.mag b/mag/VCO.mag
new file mode 100644
index 0000000..db8b1d0
--- /dev/null
+++ b/mag/VCO.mag
@@ -0,0 +1,686 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662920576
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+<< metal4 >>
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+rect 53610 21990 54670 22040
+rect 53610 21230 53680 21990
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+<< via4 >>
+rect 34230 36060 34590 36430
+rect 45040 36060 45430 36430
+rect 53690 35650 54350 36390
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+rect 56940 36660 57560 37160
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+rect 54840 26090 55200 26420
+rect 34550 24140 35760 24620
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+<< metal5 >>
+rect 54780 37160 57650 37240
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+rect 54550 22520 55250 22580
+rect 53610 21990 54670 22040
+rect 53610 21230 53680 21990
+rect 54610 21230 54670 21990
+rect 53610 21170 54670 21230
+use core_osc  X1
+timestamp 1662665761
+transform 1 0 46065 0 1 21045
+box 9175 3425 16085 12111
+use buffer_amp_vop  X3
+timestamp 1662863789
+transform 1 0 26070 0 1 10600
+box 10225 10400 29180 26030
+use cap_bank  X4
+timestamp 1662665204
+transform 1 0 52305 0 -1 34725
+box 3300 -1540 5112 5514
+use cap_bank  X5
+timestamp 1662665204
+transform 1 0 54405 0 -1 34725
+box 3300 -1540 5112 5514
+use cap_bank  X6
+timestamp 1662665204
+transform 1 0 52305 0 1 22905
+box 3300 -1540 5112 5514
+use cap_bank  X7
+timestamp 1662665204
+transform 1 0 54405 0 1 22905
+box 3300 -1540 5112 5514
+use cap_bank  X8
+timestamp 1662665204
+transform 1 0 56505 0 1 22905
+box 3300 -1540 5112 5514
+use cap_bank  X9
+timestamp 1662665204
+transform 1 0 58605 0 1 22905
+box 3300 -1540 5112 5514
+use cap_bank  X10
+timestamp 1662665204
+transform 1 0 56505 0 -1 34725
+box 3300 -1540 5112 5514
+use cap_bank  X11
+timestamp 1662665204
+transform 1 0 58605 0 -1 34725
+box 3300 -1540 5112 5514
+use bias_calc  bias_calc_0
+timestamp 1662665484
+transform 1 0 14295 0 1 25060
+box 16846 -965 21340 7275
+use output_buffer  output_buffer_0
+timestamp 1662517639
+transform 1 0 34825 0 1 39195
+box 8845 -1865 22825 2478
+use sky130_fd_pr__pfet_01v8_lvt_75KH85  sky130_fd_pr__pfet_01v8_lvt_75KH85_0
+timestamp 1662690363
+transform 1 0 33689 0 1 32864
+box -359 -284 359 284
+<< labels >>
+rlabel metal5 53630 21190 54080 36450 1 VDD
+rlabel metal5 36330 24100 37030 32510 1 GND
+rlabel metal2 60540 36070 61280 37200 1 GND
+port 1 n
+rlabel metal1 64850 21365 64910 36265 1 CTRL1
+rlabel metal1 64595 21725 64655 35905 1 CTRL2
+rlabel metal1 64345 22265 64405 35365 1 CTRL3
+rlabel metal1 64080 22855 64140 34775 1 CTRL4
+rlabel metal1 63845 23765 63905 33865 1 CTRL5
+<< end >>

mag/amp_dec.ext

diff --git a/mag/amp_dec.ext b/mag/amp_dec.ext
new file mode 100644
index 0000000..5705bdc
--- /dev/null
+++ b/mag/amp_dec.ext
@@ -0,0 +1,172 @@
+timestamp 1662519997
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__res_high_po_2p85_MXEQGY XR18 1 0 5451 0 1 5398
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM28 1 0 6899 0 -1 9820
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM27 1 0 7699 0 -1 9820
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM26 1 0 9299 0 -1 9820
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM25 1 0 8499 0 -1 9820
+use sky130_fd_pr__cap_mim_m3_1_4RCNTW XC1 1 0 8050 0 1 3700
+node "AMP" 0 528.823 6040 590 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 421200 2940 0 0 0 0
+node "GND" 0 1723.61 5100 700 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 367200 2440 499200 2840 507600 2960 0 0 0 0 0 0
+node "VDD" 8 2074.96 6760 9720 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104400 4480 1452900 10600 0 0 0 0 0 0 0 0
+node "IN4" 3 371.489 8970 9640 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76700 2680 0 0 0 0 0 0 0 0 0 0
+node "IN3" 3 365.046 8170 9640 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76700 2680 0 0 0 0 0 0 0 0 0 0
+node "IN2" 3 392.57 7370 9640 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76700 2680 0 0 0 0 0 0 0 0 0 0
+node "IN1" 3 426.806 6570 9640 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76700 2680 0 0 0 0 0 0 0 0 0 0
+node "m1_5160_9600#" 8 4252.16 5160 9600 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 409860 8760 1167200 9760 160000 1600 1448000 8040 0 0 0 0
+node "li_8790_9540#" 70 85.7645 8790 9540 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8800 520 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7990_9540#" 70 82.0136 7990 9540 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8800 520 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7190_9540#" 70 86.6137 7190 9540 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8800 520 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5840_9550#" 240 265.619 5840 9550 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30000 1580 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_8790_10060#" 70 85.7645 8790 10060 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8800 520 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7990_10060#" 70 82.0136 7990 10060 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8800 520 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7190_10060#" 70 85.7757 7190 10060 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8800 520 0 0 0 0 0 0 0 0 0 0 0 0
+node "SUB" 237 261.156 5840 10060 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29600 1560 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VDD" "li_7190_9540#" 50.1813
+cap "AMP" "GND" 305.532
+cap "IN3" "VDD" 704.391
+cap "m1_5160_9600#" "VDD" 8671.78
+cap "li_5840_9550#" "VDD" 23.3147
+cap "IN2" "VDD" 703.247
+cap "li_8790_10060#" "li_7190_10060#" 0.811594
+cap "VDD" "li_8790_9540#" 49.7277
+cap "li_7990_10060#" "li_8790_10060#" 1.93103
+cap "li_8790_10060#" "li_8790_9540#" 12.8333
+cap "VDD" "IN4" 690.91
+cap "li_7190_10060#" "li_7190_9540#" 12.8333
+cap "m1_5160_9600#" "IN3" 1018.3
+cap "li_5840_9550#" "li_7190_9540#" 1.4
+cap "li_7190_10060#" "SUB" 1.83607
+cap "li_8790_10060#" "IN4" 29.4168
+cap "IN3" "IN2" 31.2472
+cap "IN3" "li_7990_10060#" 26.2189
+cap "li_5840_9550#" "SUB" 44.0851
+cap "li_7190_9540#" "li_8790_9540#" 0.811594
+cap "li_5840_9550#" "m1_5160_9600#" 50.0122
+cap "li_7990_10060#" "SUB" 0.794326
+cap "IN1" "VDD" 682.627
+cap "m1_5160_9600#" "IN2" 1013.91
+cap "li_7990_10060#" "li_7190_10060#" 1.93103
+cap "IN2" "li_7190_10060#" 29.2558
+cap "VDD" "li_7990_9540#" 47.7241
+cap "IN3" "IN4" 31.2472
+cap "m1_5160_9600#" "IN4" 1000.55
+cap "IN2" "IN4" 12.7179
+cap "IN3" "IN1" 12.7179
+cap "li_7990_9540#" "li_7190_9540#" 1.93103
+cap "SUB" "IN1" 22.3694
+cap "m1_5160_9600#" "IN1" 986.456
+cap "li_5840_9550#" "li_7990_9540#" 0.6
+cap "IN2" "IN1" 31.2472
+cap "li_7990_10060#" "li_7990_9540#" 12.8333
+cap "li_7990_9540#" "li_8790_9540#" 1.93103
+cap "XR18/a_n415_n4762#" "XR18/a_n285_n4632#" 336.142
+cap "XC1/c1_n2050_n3000#" "XR18/a_n285_n4632#" -222.739
+cap "XR18/a_n285_n4632#" "XC1/c1_n2050_n3000#" -1031.76
+cap "XC1/m3_n2150_n3100#" "XC1/c1_n2050_n3000#" 89.8449
+cap "XC1/c1_n2050_n3000#" "XC1/m3_n2150_n3100#" -178.42
+cap "XM28/a_n323_n274#" "XM28/a_n129_n100#" 169.007
+cap "XM28/a_n323_n274#" "XM28/a_n177_n188#" 1.92636
+cap "XR18/a_n285_4200#" "XM28/a_n323_n274#" 92.3277
+cap "XR18/a_n285_4200#" "XM28/a_n129_n100#" 5.11794
+cap "XR18/a_n285_4200#" "XM28/a_n177_n188#" 1.70039
+cap "XR18/a_n285_4200#" "XM25/a_n177_n188#" -3.55271e-15
+cap "XM25/a_n177_n188#" "XM27/a_n177_n188#" 13.1119
+cap "XR18/a_n285_4200#" "XM27/a_n177_n188#" -13.0074
+cap "XM28/a_n323_n274#" "XM25/a_n177_n188#" 3.36406
+cap "XR18/a_n285_4200#" "XM28/a_n323_n274#" 205.678
+cap "XM28/a_n177_n188#" "XM28/a_n129_n100#" 4.57582
+cap "XM28/a_n323_n274#" "XM27/a_n177_n188#" 163.81
+cap "XM26/a_n177_n188#" "XM28/a_n129_n100#" -1.86077
+cap "XM28/a_n177_n188#" "XM25/a_n177_n188#" 7.12798
+cap "XR18/a_n285_4200#" "XM28/a_n177_n188#" -6.58875
+cap "XM25/a_n177_n188#" "XM28/a_n129_n100#" -5.88405
+cap "XR18/a_n285_4200#" "XM28/a_n129_n100#" -1019.83
+cap "XM28/a_n177_n188#" "XM27/a_n177_n188#" 37.4828
+cap "XM28/a_n177_n188#" "XM28/a_n323_n274#" 207.648
+cap "XM28/a_n129_n100#" "XM27/a_n177_n188#" -77.4189
+cap "XM28/a_n323_n274#" "XM28/a_n129_n100#" 326.212
+cap "XM26/a_n177_n188#" "XM27/a_n177_n188#" 3.94117
+cap "XM28/a_n221_n100#" "XM28/a_n129_n100#" -888.871
+cap "XM27/a_n177_n188#" "XM28/a_n177_n188#" 3.54635
+cap "XM28/a_n323_n274#" "XM27/a_n177_n188#" 11.6773
+cap "XM25/a_n177_n188#" "XM28/a_n177_n188#" 7.12798
+cap "XM28/a_n323_n274#" "XM25/a_n177_n188#" 167.756
+cap "XM27/a_n177_n188#" "XM28/a_n129_n100#" -851.627
+cap "XM27/a_n177_n188#" "XM28/a_n221_n100#" 0.795193
+cap "XM28/a_n323_n274#" "XM26/a_n177_n188#" 123.552
+cap "XM25/a_n177_n188#" "XM28/a_n129_n100#" -9.86675
+cap "XM25/a_n177_n188#" "XM28/a_n221_n100#" -21.8254
+cap "XM26/a_n177_n188#" "XM28/a_n129_n100#" -80.7013
+cap "XM28/a_n323_n274#" "XM28/a_n177_n188#" 3.36406
+cap "XM26/a_n177_n188#" "XM28/a_n221_n100#" -32.5351
+cap "XM27/a_n177_n188#" "XM25/a_n177_n188#" 27.0931
+cap "XM28/a_n177_n188#" "XM28/a_n129_n100#" -1.87681
+cap "XM28/a_n323_n274#" "XM28/a_n129_n100#" -306.993
+cap "XM28/a_n221_n100#" "XM28/a_n177_n188#" -4.44089e-16
+cap "XM27/a_n177_n188#" "XM26/a_n177_n188#" 5.30131
+cap "XM28/a_n323_n274#" "XM28/a_n221_n100#" 395.724
+cap "XM26/a_n177_n188#" "XM25/a_n177_n188#" 27.0931
+cap "XM27/a_n177_n188#" "XM26/a_n177_n188#" 0.794557
+cap "XM26/a_n177_n188#" "XM27/a_63_n100#" 265.023
+cap "XM27/a_n33_n100#" "XM27/a_63_n100#" -52.7844
+cap "XM27/a_n323_n274#" "XM25/a_n177_n188#" 1.82198
+cap "XM27/a_n323_n274#" "XM27/a_63_n100#" 341.707
+cap "XM25/a_n177_n188#" "XM27/a_63_n100#" -2.26781
+cap "XM27/a_n33_n100#" "XM26/a_n177_n188#" 258.589
+cap "XM27/a_n323_n274#" "XM26/a_n177_n188#" 5.38843
+cap "XM27/a_n323_n274#" "XM27/a_n33_n100#" 84.6138
+cap "XM26/a_n177_n188#" "XM27/a_n81_122#" 3.24101
+cap "XM26/a_n177_n188#" "XM25/a_n177_n188#" 13.7956
+merge "XM26/a_159_n100#" "XM25/a_159_n100#" 20628.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34739842 -7846 0 0 0 0 1217420 -5382 0 0 0 0
+merge "XM25/a_159_n100#" "XM25/a_n33_n100#"
+merge "XM25/a_n33_n100#" "XM25/a_n221_n100#"
+merge "XM25/a_n221_n100#" "XM26/a_n33_n100#"
+merge "XM26/a_n33_n100#" "XM26/a_n221_n100#"
+merge "XM26/a_n221_n100#" "XM27/a_159_n100#"
+merge "XM27/a_159_n100#" "XM27/a_n33_n100#"
+merge "XM27/a_n33_n100#" "XM27/a_n221_n100#"
+merge "XM27/a_n221_n100#" "XM28/a_159_n100#"
+merge "XM28/a_159_n100#" "XM28/a_n33_n100#"
+merge "XM28/a_n33_n100#" "XM28/a_n221_n100#"
+merge "XM28/a_n221_n100#" "XR18/a_n285_4200#"
+merge "XR18/a_n285_4200#" "XC1/c1_n2050_n3000#"
+merge "XC1/c1_n2050_n3000#" "m1_5160_9600#"
+merge "m1_5160_9600#" "AMP"
+merge "XM25/a_n323_n274#" "XM26/a_n323_n274#" -8837.55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -9033412 -2056 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM26/a_n323_n274#" "li_8790_9540#"
+merge "li_8790_9540#" "li_8790_10060#"
+merge "li_8790_10060#" "XM27/a_n323_n274#"
+merge "XM27/a_n323_n274#" "li_7990_9540#"
+merge "li_7990_9540#" "li_7990_10060#"
+merge "li_7990_10060#" "XM28/a_n323_n274#"
+merge "XM28/a_n323_n274#" "li_7190_9540#"
+merge "li_7190_9540#" "li_7190_10060#"
+merge "li_7190_10060#" "XC1/VSUBS"
+merge "XC1/VSUBS" "li_5840_9550#"
+merge "li_5840_9550#" "SUB"
+merge "SUB" "XR18/a_n415_n4762#"
+merge "XR18/a_n415_n4762#" "VSUBS"
+merge "XC1/m3_n2150_n3100#" "XR18/a_n285_n4632#" -3201.35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -134454 -1942 0 0 -8247000 -1360 0 0 0 0 0 0
+merge "XR18/a_n285_n4632#" "GND"
+merge "XM25/a_63_n100#" "XM25/a_n129_n100#" 12601.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18628900 -3936 0 0 0 0 0 0 0 0 0 0
+merge "XM25/a_n129_n100#" "XM26/a_63_n100#"
+merge "XM26/a_63_n100#" "XM26/a_n129_n100#"
+merge "XM26/a_n129_n100#" "XM27/a_63_n100#"
+merge "XM27/a_63_n100#" "XM27/a_n129_n100#"
+merge "XM27/a_n129_n100#" "XM28/a_63_n100#"
+merge "XM28/a_63_n100#" "XM28/a_n129_n100#"
+merge "XM28/a_n129_n100#" "VDD"
+merge "XM28/a_n81_122#" "XM28/a_n177_n188#" -12132.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -18757846 -1268 0 0 0 0 0 0 0 0 0 0
+merge "XM28/a_n177_n188#" "IN1"
+merge "XM25/a_n81_122#" "XM25/a_n177_n188#" -12184.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -18757846 -1268 0 0 0 0 0 0 0 0 0 0
+merge "XM25/a_n177_n188#" "IN3"
+merge "XM27/a_n81_122#" "XM27/a_n177_n188#" -20818.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -32225221 -1268 0 0 0 0 0 0 0 0 0 0
+merge "XM27/a_n177_n188#" "IN2"
+merge "XM26/a_n81_122#" "XM26/a_n177_n188#" -11119.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -17063201 -1268 0 0 0 0 0 0 0 0 0 0
+merge "XM26/a_n177_n188#" "IN4"

mag/amp_dec.mag

diff --git a/mag/amp_dec.mag b/mag/amp_dec.mag
new file mode 100644
index 0000000..85b6fa0
--- /dev/null
+++ b/mag/amp_dec.mag
@@ -0,0 +1,265 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662519997
+<< locali >>
+rect 5840 10060 6580 10100
+rect 7190 10060 7410 10100
+rect 7990 10060 8210 10100
+rect 8790 10060 9010 10100
+rect 5840 9550 6590 9590
+rect 7190 9540 7410 9580
+rect 7990 9540 8210 9580
+rect 8790 9540 9010 9580
+<< metal1 >>
+rect 5160 10000 5740 10040
+rect 5160 9640 5200 10000
+rect 5700 9640 5740 10000
+rect 6570 10010 6640 10130
+rect 7370 10010 7440 10130
+rect 8170 10010 8240 10130
+rect 8970 10010 9040 10130
+rect 6570 9950 6980 10010
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+rect 6570 9690 6640 9950
+rect 6670 9910 6750 9920
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+rect 6740 9850 6750 9910
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+rect 6680 9720 6730 9840
+rect 6780 9800 6830 9920
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+rect 6860 9850 6870 9910
+rect 6930 9850 6940 9910
+rect 6860 9840 6940 9850
+rect 6760 9790 6840 9800
+rect 6760 9730 6770 9790
+rect 6830 9730 6840 9790
+rect 6760 9720 6840 9730
+rect 6870 9720 6930 9840
+rect 6970 9810 7030 9920
+rect 7060 9910 7140 9920
+rect 7060 9850 7070 9910
+rect 7130 9850 7140 9910
+rect 7060 9840 7140 9850
+rect 7060 9830 7120 9840
+rect 6960 9800 7030 9810
+rect 6960 9790 7040 9800
+rect 6960 9730 6970 9790
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+rect 7070 9720 7120 9830
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+rect 7560 9730 7570 9790
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+rect 7760 9800 7830 9810
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+rect 8560 9800 8630 9810
+rect 8560 9790 8640 9800
+rect 8560 9730 8570 9790
+rect 8630 9730 8640 9790
+rect 8560 9720 8640 9730
+rect 8668 9720 8720 9830
+rect 8970 9690 9040 9950
+rect 9070 9910 9150 9920
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+rect 9070 9840 9150 9850
+rect 9080 9720 9130 9840
+rect 9180 9800 9230 9920
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+rect 9270 9720 9330 9840
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+rect 9360 9730 9370 9790
+rect 9430 9730 9440 9790
+rect 9360 9720 9440 9730
+rect 9468 9720 9520 9830
+rect 6570 9640 7080 9690
+rect 7370 9640 7880 9690
+rect 8170 9640 8680 9690
+rect 8970 9640 9480 9690
+rect 5160 9600 5740 9640
+rect 5100 1200 5780 1240
+rect 5100 740 5140 1200
+rect 5740 740 5780 1200
+rect 5100 700 5780 740
+<< via1 >>
+rect 5200 9640 5700 10000
+rect 6680 9850 6740 9910
+rect 6870 9850 6930 9910
+rect 6770 9730 6830 9790
+rect 7070 9850 7130 9910
+rect 6970 9730 7030 9790
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+rect 9080 9850 9140 9910
+rect 9270 9850 9330 9910
+rect 9170 9730 9230 9790
+rect 9470 9850 9530 9910
+rect 9370 9730 9430 9790
+rect 5140 740 5740 1200
+<< metal2 >>
+rect 7670 10040 7870 10060
+rect 8470 10040 8670 10060
+rect 9270 10040 9470 10060
+rect 5160 10000 9540 10040
+rect 5160 9640 5200 10000
+rect 5700 9680 6080 10000
+rect 6400 9910 9540 10000
+rect 6400 9850 6680 9910
+rect 6740 9850 6870 9910
+rect 6930 9850 7070 9910
+rect 7130 9850 7480 9910
+rect 7540 9850 7670 9910
+rect 7730 9850 7870 9910
+rect 7930 9850 8280 9910
+rect 8340 9850 8470 9910
+rect 8530 9850 8670 9910
+rect 8730 9850 9080 9910
+rect 9140 9850 9270 9910
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+rect 9530 9850 9540 9910
+rect 6400 9840 9540 9850
+rect 6400 9680 6440 9840
+rect 5700 9640 6440 9680
+rect 6540 9790 9570 9800
+rect 6540 9730 6770 9790
+rect 6830 9730 6970 9790
+rect 7030 9730 7570 9790
+rect 7630 9730 7770 9790
+rect 7830 9730 8370 9790
+rect 8430 9730 8570 9790
+rect 8630 9730 9170 9790
+rect 9230 9730 9370 9790
+rect 9430 9730 9570 9790
+rect 5160 9600 5740 9640
+rect 6540 9510 9570 9730
+rect 6540 9360 6830 9510
+rect 5000 9070 6830 9360
+rect 5000 1200 5780 1240
+rect 5000 740 5140 1200
+rect 5740 740 5780 1200
+rect 5000 600 5780 740
+<< via2 >>
+rect 6080 9680 6400 10000
+rect 5140 740 5740 1200
+<< metal3 >>
+rect 6040 10000 6440 10040
+rect 6040 9680 6080 10000
+rect 6400 9680 6440 10000
+rect 6040 9640 6440 9680
+rect 5100 1200 6040 1240
+rect 5100 740 5140 1200
+rect 5740 740 6040 1200
+rect 5100 700 6040 740
+<< via3 >>
+rect 6080 9680 6400 10000
+<< metal4 >>
+rect 6040 10000 6440 10040
+rect 6040 9680 6080 10000
+rect 6400 9680 6440 10000
+rect 6040 6420 6440 9680
+rect 6040 590 6430 1670
+use sky130_fd_pr__cap_mim_m3_1_4RCNTW  XC1
+timestamp 1662404926
+transform 1 0 8050 0 1 3700
+box -2150 -3100 2149 3100
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM25 
+timestamp 1662515274
+transform 1 0 8499 0 -1 9820
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM26
+timestamp 1662515274
+transform 1 0 9299 0 -1 9820
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM27
+timestamp 1662515274
+transform 1 0 7699 0 -1 9820
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM28
+timestamp 1662515274
+transform 1 0 6899 0 -1 9820
+box -359 -310 359 310
+use sky130_fd_pr__res_high_po_2p85_MXEQGY  XR18 
+timestamp 1662404926
+transform 1 0 5451 0 1 5398
+box -451 -4798 451 4798
+<< labels >>
+rlabel metal2 5000 600 5140 1240 1 GND
+rlabel metal1 6570 9950 6640 10130 1 IN1
+rlabel metal2 5000 9070 6830 9360 1 VDD
+rlabel metal1 7370 9640 7440 10130 1 IN2
+rlabel metal1 8170 9640 8240 10130 1 IN3
+rlabel metal1 8970 9640 9040 10130 1 IN4
+rlabel metal4 6040 590 6430 1670 1 AMP
+rlabel locali 5840 10060 6580 10100 1 SUB
+<< end >>

mag/bias_calc.ext

diff --git a/mag/bias_calc.ext b/mag/bias_calc.ext
new file mode 100644
index 0000000..60e07d7
--- /dev/null
+++ b/mag/bias_calc.ext
@@ -0,0 +1,1148 @@
+timestamp 1662665484
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_lvt_D3M934 XM2 0 1 18069 -1 0 6117
+use sky130_fd_pr__pfet_01v8_lvt_D3M934 XM36 0 1 17419 -1 0 6117
+use sky130_fd_pr__pfet_01v8_lvt_D3Z634 XM37 0 1 17819 -1 0 2297
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX XM39 1 0 17493 0 1 -340
+use sky130_fd_pr__pfet_01v8_lvt_D3M934 XM3 0 1 18719 -1 0 6117
+use sky130_fd_pr__pfet_01v8_lvt_D3Z634 XM38 0 1 18469 -1 0 2297
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX XM40 -1 0 18797 0 -1 -340
+use sky130_fd_pr__res_high_po_2p85_P79JE3 XR19 1 0 19491 0 1 5548
+use sky130_fd_pr__res_high_po_2p85_MM89SS XR20 1 0 19491 0 1 2448
+use sky130_fd_pr__pfet_01v8_lvt_D3M934 XM1 0 1 20269 -1 0 2877
+use sky130_fd_pr__pfet_01v8_lvt_D3M934 XM29 0 1 20269 -1 0 5127
+use sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4 XM30 0 1 21019 -1 0 3207
+use sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4 XM31 0 1 21019 -1 0 4807
+node "VOP" 7 756.118 20820 2435 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 192000 6520 0 0 0 0 0 0 0 0 0 0
+node "AMP" 7 808.666 20820 4180 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 192000 6520 0 0 0 0 0 0 0 0 0 0
+node "m1_20160_2025#" 26 2458.61 20160 2025 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 372582 16800 2213050 15340 0 0 0 0 0 0 0 0
+node "GND" 4 5405.49 16970 -440 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1854300 13720 1936500 8840 1821550 7580 0 0 0 0 0 0
+node "BIASOUT" 19 3514.12 18360 350 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 290247 12886 3447375 13800 0 0 0 0 0 0 0 0
+node "m1_18270_400#" 16 3900.21 18270 400 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 996068 21740 1639500 9970 0 0 0 0 0 0 0 0
+node "m1_17860_4190#" 0 18.1263 17860 4190 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3500 240 0 0 0 0 0 0 0 0 0 0
+node "m1_16980_n520#" 30 4904.53 16980 -520 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 539850 22560 3057000 11390 0 0 0 0 0 0 0 0
+node "VCTRL" 18 2023.51 17100 4310 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 524400 17600 0 0 0 0 0 0 0 0 0 0
+node "m1_19235_6325#" 4 2461.01 19235 6325 v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 262525 4800 1560750 9250 0 0 0 0 0 0 0 0
+node "VDD" 40 4485.8 17310 5130 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 538976 24000 3107100 23860 749850 8360 0 0 0 0 0 0
+node "m1_17310_5240#" 48 4663.88 17310 5240 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 758128 33000 5150200 25000 0 0 0 0 0 0 0 0
+node "BIAS2V" 0 4975.51 17220 5180 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1534300 50200 0 0 0 0 0 0 0 0 0 0
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+node "SUB" 253 279.948 19070 -100 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40050 1870 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_18070_n100#" 55 41.2588 18070 -100 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5250 370 0 0 0 0 0 0 0 0 0 0 0 0
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+node "li_18315_7170#" 50 0 18315 7170 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6200 390 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_17670_7175#" 50 25.8996 17670 7175 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6200 390 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_20550_2400#" 15438 1950 20550 2400 nw 0 0 0 0 650000 6900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_17930_210#" 10745 5266.8 17930 210 nw 0 0 0 0 1755600 9700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_17100_7240#" 4031 8782.05 17100 7240 nw 0 0 0 0 2927350 8710 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_18320_5030#" "li_18715_4315#" 4.08333
+cap "BIASOUT" "li_18070_245#" 9.78043
+cap "li_18070_n615#" "li_18070_245#" 5.09091
+cap "VCTRL" "GND" 144.33
+cap "BIASOUT" "m1_17310_5240#" 9645.71
+cap "m1_18270_400#" "m1_20160_2025#" 3454.13
+cap "li_18715_4315#" "li_18070_4315#" 74.7316
+cap "m1_20160_2025#" "m1_19235_6325#" 3579.18
+cap "w_20550_2400#" "li_20510_3935#" 145.39
+cap "BIASOUT" "BIAS2V" 28.1196
+cap "m1_20160_2025#" "li_20520_5545#" 24.7818
+cap "m1_16980_n520#" "VCTRL" 5445.37
+cap "VDD" "BIASOUT" 145.578
+cap "m1_18270_400#" "VCTRL" 1230.19
+cap "li_18715_4315#" "w_17100_7240#" 20.3607
+cap "li_18070_4315#" "w_17930_210#" 74.1009
+cap "BIAS2V" "m1_17310_5240#" 8495.77
+cap "VDD" "PSUB" 114.401
+cap "VDD" "m1_17310_5240#" 20384.5
+cap "li_18320_5030#" "m1_17310_5240#" 21.2082
+cap "VOP" "AMP" 12.8348
+cap "VOP" "GND" 84.7727
+cap "VDD" "BIAS2V" 13395.7
+cap "li_20520_5545#" "li_20510_3935#" 8.06339
+cap "li_18070_4315#" "m1_17310_5240#" 190.792
+cap "PSUB" "w_17100_7240#" 40.5605
+cap "w_17100_7240#" "m1_17310_5240#" 1823.68
+cap "m1_18270_400#" "VOP" 1724.65
+cap "VCTRL" "w_17930_210#" 735.28
+cap "li_18320_5030#" "li_18070_4315#" 12.307
+cap "BIAS2V" "w_17100_7240#" 2457.19
+cap "m1_20160_2025#" "BIASOUT" 85.092
+cap "VDD" "w_17100_7240#" 2613.92
+cap "li_18320_5030#" "w_17100_7240#" 45.9719
+cap "w_20550_2400#" "li_20515_2435#" 87.5173
+cap "VCTRL" "BIASOUT" 203.401
+cap "li_18715_4315#" "li_17670_5030#" 1.10112
+cap "m1_20160_2025#" "m1_17310_5240#" 51.2047
+cap "m1_20160_2025#" "BIAS2V" 4643.71
+cap "VCTRL" "m1_17310_5240#" 4612.53
+cap "VDD" "m1_20160_2025#" 11038.7
+cap "BIAS2V" "li_18315_7170#" 82.1037
+cap "m1_17860_4190#" "GND" 1.45276
+cap "VCTRL" "BIAS2V" 8.2
+cap "VCTRL" "VDD" 38.8308
+cap "m1_16980_n520#" "m1_17860_4190#" 54.983
+cap "li_18070_n100#" "SUB" 1.15294
+cap "m1_18270_400#" "m1_17860_4190#" 8.13971
+cap "li_17670_5030#" "m1_17310_5240#" 22.9477
+cap "li_18315_7170#" "w_17100_7240#" 81.272
+cap "GND" "AMP" 37.6307
+cap "li_18320_5030#" "li_17670_5030#" 2.26263
+cap "m1_16980_n520#" "li_18070_n100#" 8.16789
+cap "VOP" "BIAS2V" 342.136
+cap "m1_16980_n520#" "GND" 7475.99
+cap "li_18070_4315#" "li_17670_5030#" 5.7619
+cap "li_18715_4315#" "li_17535_4310#" 18.2183
+cap "VDD" "VOP" 50.6709
+cap "m1_18270_400#" "GND" 1414.74
+cap "li_17670_5030#" "w_17100_7240#" 40.2368
+cap "li_20520_5545#" "w_20550_2400#" 87.8495
+cap "m1_19235_6325#" "AMP" 1751.53
+cap "VDD" "li_19985_3930#" 41.5053
+cap "GND" "m1_19235_6325#" 17.701
+cap "m1_17860_4190#" "w_17930_210#" 9.61538
+cap "BIAS2V" "li_17670_7175#" 82.1037
+cap "m1_18270_400#" "m1_16980_n520#" 260.94
+cap "li_19370_n95#" "SUB" 96.0784
+cap "li_19370_n95#" "li_18070_n100#" 0.730435
+cap "m1_18270_400#" "m1_19235_6325#" 136.561
+cap "m1_20160_2025#" "li_20510_3935#" 121.326
+cap "m1_17860_4190#" "BIASOUT" 6.7507
+cap "li_19870_4105#" "li_19075_4105#" 6.07895
+cap "li_19370_n95#" "GND" 69.2115
+cap "li_17535_4310#" "m1_17310_5240#" 152.751
+cap "li_17670_7175#" "w_17100_7240#" 55.3724
+cap "m1_17860_4190#" "m1_17310_5240#" 106.993
+cap "VOP" "m1_20160_2025#" 1694.04
+cap "li_18320_5030#" "li_17535_4310#" 1.12
+cap "BIASOUT" "SUB" 263.002
+cap "m1_17860_4190#" "BIAS2V" 2.35532
+cap "BIASOUT" "li_18070_n100#" 7.94512
+cap "li_18070_n615#" "li_18070_n100#" 8.75
+cap "li_18070_245#" "SUB" 1.15294
+cap "m1_16980_n520#" "w_17930_210#" 143.421
+cap "BIASOUT" "GND" 5369.64
+cap "li_18070_n615#" "GND" 36.247
+cap "li_18070_245#" "li_18070_n100#" 13.5484
+cap "m1_18270_400#" "w_17930_210#" 892.195
+cap "li_18070_4315#" "li_17535_4310#" 74.2728
+cap "li_18315_7170#" "li_17670_7175#" 2
+cap "m1_16980_n520#" "BIASOUT" 2090.4
+cap "GND" "m1_17310_5240#" 141.548
+cap "m1_18270_400#" "BIASOUT" 5838.6
+cap "li_19985_3930#" "li_20510_3935#" 9.78507
+cap "BIAS2V" "AMP" 342.136
+cap "m1_16980_n520#" "li_18070_245#" 10.2779
+cap "GND" "BIAS2V" 532.033
+cap "li_21265_3940#" "li_20510_3935#" 9.82558
+cap "VDD" "AMP" 51.2314
+cap "VDD" "GND" 165.42
+cap "m1_20160_2025#" "li_20515_2435#" 25.9663
+cap "m1_16980_n520#" "m1_17310_5240#" 9680.19
+cap "m1_18270_400#" "m1_17310_5240#" 4816.8
+cap "PSUB" "m1_19235_6325#" 126.992
+cap "m1_19235_6325#" "m1_17310_5240#" 60.1019
+cap "m1_16980_n520#" "BIAS2V" 3.3874
+cap "m1_18270_400#" "BIAS2V" 118.854
+cap "m1_16980_n520#" "VDD" 12.88
+cap "li_19370_n95#" "BIASOUT" 67.4741
+cap "m1_18270_400#" "VDD" 164.795
+cap "VCTRL" "li_17535_4310#" 33.4975
+cap "BIAS2V" "m1_19235_6325#" 511.803
+cap "VDD" "m1_19235_6325#" 1064.5
+cap "li_21265_3940#" "li_19985_3930#" 2.92369
+cap "li_19370_n95#" "li_18070_245#" 0.852174
+cap "BIASOUT" "li_19075_4105#" 58.9461
+cap "m1_17860_4190#" "VCTRL" 108.65
+cap "li_20515_2435#" "li_20510_3935#" 8.18362
+cap "BIASOUT" "w_17930_210#" 10.5092
+cap "li_17670_5030#" "li_17535_4310#" 8.4
+cap "li_18070_245#" "w_17930_210#" 71.0514
+cap "m1_20160_2025#" "w_20550_2400#" 461.367
+cap "m1_20160_2025#" "AMP" 1681.12
+cap "m1_20160_2025#" "GND" 127.828
+cap "w_17930_210#" "m1_17310_5240#" 786.221
+cap "XM37/a_285_n197#" "w_17930_210#" 12.9862
+cap "XM38/a_285_n197#" "w_17930_210#" 3.92628
+cap "XM37/a_355_n100#" "w_17930_210#" 203.85
+cap "XM37/a_285_n197#" "XM39/a_n611_n274#" 17.8127
+cap "XM37/a_355_n100#" "XM39/a_n611_n274#" 422.831
+cap "XM37/a_285_n197#" "XM39/a_n509_n100#" 3.19476
+cap "XM39/a_n611_n274#" "w_17930_210#" 75.7973
+cap "XM37/a_355_n100#" "XM39/a_n509_n100#" -1908.16
+cap "XM39/a_n509_n100#" "w_17930_210#" 5.92531
+cap "XM37/a_355_n100#" "XM37/a_483_n100#" -63.525
+cap "XM37/a_483_n100#" "w_17930_210#" 3.55271e-15
+cap "XM39/a_n509_n100#" "XM39/a_n611_n274#" 358.908
+cap "XM39/a_n611_n274#" "XM37/a_483_n100#" 22.4002
+cap "XM37/a_355_n100#" "XM38/a_355_n100#" 311.02
+cap "XM39/a_n509_n100#" "XM37/a_483_n100#" 1.84732
+cap "w_17930_210#" "XM38/a_355_n100#" 2.50308
+cap "XM39/a_n611_n274#" "XM38/a_355_n100#" -649.559
+cap "XM39/a_n509_n100#" "XM38/a_355_n100#" 70.3684
+cap "XM37/a_285_n197#" "XM38/a_285_n197#" 4.12088
+cap "XM37/a_285_n197#" "XM37/a_355_n100#" 26.6238
+cap "XM38/a_355_n100#" "XM37/a_355_n100#" 174.599
+cap "XM38/a_355_n100#" "XM38/a_285_n197#" 13.1799
+cap "XM37/a_355_n100#" "XM37/a_483_n100#" 6.76624
+cap "w_17930_210#" "XM37/a_285_n197#" 0.953605
+cap "XM39/a_n611_n274#" "XM37/a_285_n197#" 0.966204
+cap "XM39/a_n509_n100#" "w_17930_210#" 5.92531
+cap "XM38/a_355_n100#" "XM37/a_285_n197#" -5.55112e-17
+cap "XM39/a_n509_n100#" "XM39/a_n611_n274#" -233.329
+cap "w_17930_210#" "XM39/a_n611_n274#" 96.6332
+cap "XM38/a_355_n100#" "XM39/a_n509_n100#" -1785.8
+cap "XM38/a_285_n197#" "XM37/a_355_n100#" 13.5378
+cap "XM39/a_n509_n100#" "XM37/a_483_n100#" 1.84732
+cap "XM38/a_355_n100#" "w_17930_210#" 164.275
+cap "w_17930_210#" "XM37/a_483_n100#" 8.88178e-16
+cap "XM38/a_355_n100#" "XM39/a_n611_n274#" 190.544
+cap "XM37/a_483_n100#" "XM39/a_n611_n274#" 22.4002
+cap "XM38/a_285_n197#" "XM37/a_285_n197#" 4.12088
+cap "XM38/a_355_n100#" "XM37/a_483_n100#" -70.6687
+cap "XM39/a_n509_n100#" "XM38/a_285_n197#" 3.37888
+cap "XM39/a_n509_n100#" "XM37/a_355_n100#" -995.088
+cap "XM38/a_285_n197#" "w_17930_210#" 9.23231
+cap "w_17930_210#" "XM37/a_355_n100#" 16.0235
+cap "XM37/a_355_n100#" "XM39/a_n611_n274#" 14.7052
+cap "XM38/a_285_n197#" "XM39/a_n611_n274#" 25.8208
+cap "XM38/a_n925_n100#" "XM37/a_n1053_n100#" -771.525
+cap "w_17930_210#" "XM37/a_n1053_n100#" 232.31
+cap "XM37/a_n925_n100#" "XM39/a_n509_n100#" 1.33726
+cap "XM37/a_n1123_n197#" "XM39/a_n509_n100#" 0.708758
+cap "XM37/a_n1123_n197#" "XM37/a_n925_n100#" 415.501
+cap "XM39/a_n611_n274#" "XM37/a_n925_n100#" 18.657
+cap "XM37/a_n1123_n197#" "XM39/a_n611_n274#" 30.265
+cap "XM38/a_n1123_n197#" "XM37/a_n925_n100#" 0.771671
+cap "XM38/a_n1123_n197#" "XM37/a_n1123_n197#" 112.758
+cap "XM38/a_n925_n100#" "XM37/a_n1123_n197#" 0.00151493
+cap "XM38/a_n925_n100#" "XM37/a_n925_n100#" 5.42159
+cap "w_17930_210#" "XM37/a_n925_n100#" 448.743
+cap "w_17930_210#" "XM37/a_n1123_n197#" 682.686
+cap "w_17930_210#" "XM39/a_n611_n274#" 63.3407
+cap "XM38/a_n1123_n197#" "w_17930_210#" 114.779
+cap "XM37/a_n1053_n100#" "XM39/a_n509_n100#" 1.84732
+cap "XM37/a_n1053_n100#" "XM37/a_n925_n100#" -1429.14
+cap "XM37/a_n1053_n100#" "XM37/a_n1123_n197#" 409.357
+cap "XM37/a_n1053_n100#" "XM39/a_n611_n274#" 25.2299
+cap "XM38/a_n925_n100#" "w_17930_210#" 12.0431
+cap "XM38/a_n1123_n197#" "XM37/a_n1053_n100#" -254.062
+cap "XM38/a_n925_n100#" "XM37/a_n1053_n100#" -1449.62
+cap "XM38/a_n1123_n197#" "XM1/w_n1127_n319#" 0.22006
+cap "XM37/a_n1123_n197#" "XM37/a_n1053_n100#" -1.06581e-14
+cap "XM1/w_n1127_n319#" "XM39/a_n611_n274#" 0.932253
+cap "XM37/a_n925_n100#" "XM37/a_n1053_n100#" 6.76624
+cap "XM38/a_n925_n100#" "XM37/a_n1123_n197#" 0.00151493
+cap "XM37/a_n1053_n100#" "XM39/a_n509_n100#" 1.84732
+cap "XM37/a_n925_n100#" "XM38/a_n925_n100#" 10.6967
+cap "XM37/a_n1053_n100#" "w_17930_210#" 52.4906
+cap "XM38/a_n925_n100#" "XM39/a_n509_n100#" 1.33726
+cap "XM38/a_n1123_n197#" "XM37/a_n1053_n100#" 408.044
+cap "XM37/a_n1053_n100#" "XM39/a_n611_n274#" 39.3619
+cap "XM38/a_n925_n100#" "w_17930_210#" 221.223
+cap "XM37/a_n1123_n197#" "w_17930_210#" 25.0568
+cap "XM38/a_n1123_n197#" "XM38/a_n925_n100#" 307.104
+cap "XM38/a_n925_n100#" "XM39/a_n611_n274#" 170.369
+cap "XM38/a_n1123_n197#" "XM37/a_n1123_n197#" 112.758
+cap "XM37/a_n925_n100#" "w_17930_210#" 2.99371
+cap "XM1/w_n1127_n319#" "XM37/a_n1053_n100#" 0.158528
+cap "XM37/a_n1123_n197#" "XM39/a_n611_n274#" 19.3834
+cap "XM38/a_n1123_n197#" "XM37/a_n925_n100#" 3.96892
+cap "XM38/a_n1123_n197#" "XM39/a_n509_n100#" -161.774
+cap "XM37/a_n925_n100#" "XM39/a_n611_n274#" 3.98957
+cap "XM39/a_n509_n100#" "XM39/a_n611_n274#" -13.4765
+cap "XM38/a_n1123_n197#" "w_17930_210#" 549.998
+cap "XM39/a_n611_n274#" "w_17930_210#" 212.185
+cap "XM38/a_n1123_n197#" "XM39/a_n611_n274#" 254.802
+cap "XM1/w_n1127_n319#" "w_17930_210#" 0.555916
+cap "XM1/w_n1127_n319#" "XM38/a_n1123_n197#" 0.22006
+cap "XM40/a_n611_n274#" "XM38/a_n1123_n197#" 88.6788
+cap "XM40/a_n611_n274#" "XM1/w_n1127_n319#" 18.7685
+cap "XM38/a_n925_n100#" "XM38/a_n1123_n197#" 0.338702
+cap "XM38/a_n1123_n197#" "XM38/a_n1053_n100#" 0.103846
+cap "XM1/w_n1127_n319#" "XM38/a_n1053_n100#" 0.158528
+cap "XM40/a_n611_n274#" "XM38/a_n1053_n100#" 1.46574
+cap "XM38/a_n925_n100#" "XM40/a_n611_n274#" 1.46574
+cap "XM1/w_n1127_n319#" "XM1/a_n477_n100#" 3.55271e-15
+cap "XM1/w_n1127_n319#" "XM1/a_n349_n100#" 6.66134e-15
+cap "XM38/a_n1123_n197#" "XM40/a_447_n100#" -1167.36
+cap "w_17930_210#" "XM38/a_n1123_n197#" 16.1325
+cap "XM1/w_n1127_n319#" "w_17930_210#" 0.555916
+cap "XM40/a_n611_n274#" "w_17930_210#" 13.1875
+cap "XM40/a_n611_n274#" "XM40/a_447_n100#" -178.287
+cap "XM1/w_n1127_n319#" "XM1/a_n547_n197#" 6.66134e-16
+cap "XM37/a_n1949_n100#" "XR19/a_n415_n1322#" 2.47702
+cap "XM37/a_n1891_n197#" "XM38/a_n1949_n100#" 4.26326e-14
+cap "XM37/w_n2087_n319#" "XM38/a_n1949_n100#" 14.4518
+cap "XM37/a_n1891_n197#" "XM37/w_n2087_n319#" 473.121
+cap "XR19/a_n415_n1322#" "XM37/a_n1891_n197#" 17.5128
+cap "XR19/a_n415_n1322#" "XM37/w_n2087_n319#" 56.035
+cap "XM38/a_n1891_n197#" "XM37/a_n1821_n100#" -263.503
+cap "XM37/a_n1949_n100#" "XM37/a_n1821_n100#" -1567.62
+cap "XM38/a_n1949_n100#" "XM37/a_n1821_n100#" -955.695
+cap "XM37/w_n2087_n319#" "XM37/a_n1821_n100#" 215.899
+cap "XM37/a_n1891_n197#" "XM37/a_n1821_n100#" 388.072
+cap "XR19/a_n415_n1322#" "XM37/a_n1821_n100#" 2.06418
+cap "XM38/a_n1891_n197#" "XM37/w_n2087_n319#" 103.166
+cap "XM38/a_n1891_n197#" "XM37/a_n1891_n197#" 108.28
+cap "XM37/a_n1891_n197#" "XR19/a_n285_n1192#" 7.10543e-15
+cap "XM37/a_n1949_n100#" "XM38/a_n1949_n100#" 6.46154
+cap "XM37/a_n1949_n100#" "XM37/w_n2087_n319#" 450.296
+cap "XM37/a_n1949_n100#" "XM37/a_n1891_n197#" 484.086
+cap "XR19/a_n285_n1192#" "XM30/a_n611_n197#" -7.10543e-15
+cap "XM37/w_n2087_n319#" "XM37/a_n1891_n197#" 25.0568
+cap "XM37/a_n1821_n100#" "XM38/a_n1949_n100#" -1577.72
+cap "XM1/a_n931_n197#" "XM38/a_n1891_n197#" 10.5577
+cap "XM1/a_n931_n197#" "XM37/w_n2087_n319#" 7.42964
+cap "XM38/a_n1891_n197#" "XM38/a_n1949_n100#" 397.76
+cap "XM37/a_n1891_n197#" "XM38/a_n1949_n100#" 7.10543e-15
+cap "XM37/w_n2087_n319#" "XM38/a_n1949_n100#" 386.217
+cap "XM37/a_n1821_n100#" "XR19/a_n415_n1322#" 13.3596
+cap "XM38/a_n1891_n197#" "XR19/a_n415_n1322#" 93.9941
+cap "XM37/a_n1891_n197#" "XR19/a_n415_n1322#" 17.5128
+cap "XM37/w_n2087_n319#" "XM1/a_n861_n100#" 2.02123
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+cap "XM30/a_n611_n197#" "XM1/a_n931_n197#" 57.5961
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+cap "XM31/a_n611_n197#" "XM1/a_n989_n100#" -1.42109e-14
+cap "XM31/a_n611_n197#" "XR20/a_n285_1140#" 1.64683
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+cap "XM31/a_n611_n197#" "XM30/a_n611_n197#" 103.17
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+cap "XM31/a_n611_n197#" "XM31/a_n541_n100#" 96.706
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mag/bias_calc.mag

diff --git a/mag/bias_calc.mag b/mag/bias_calc.mag
new file mode 100644
index 0000000..f30883a
--- /dev/null
+++ b/mag/bias_calc.mag
@@ -0,0 +1,1984 @@
+magic
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+rect 20290 2015 20300 2075
+rect 20370 2015 20590 2075
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+rect 18500 1620 18510 1690
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+rect 18570 1110 19100 1180
+rect 18500 920 19100 1110
+rect 18500 850 18510 920
+rect 18570 850 19100 920
+rect 19240 1280 21340 1310
+rect 19750 910 21340 1280
+rect 19240 880 21340 910
+rect 18500 670 19100 850
+rect 18500 600 18510 670
+rect 18570 600 19100 670
+rect 17190 340 17720 410
+rect 17780 340 17790 410
+rect 17190 285 17790 340
+rect 18500 410 19100 600
+rect 18500 340 18510 410
+rect 18570 340 19100 410
+rect 18500 285 19100 340
+rect 16970 -130 18090 285
+rect 16970 -185 17400 -130
+rect 17480 -135 17995 -130
+rect 17480 -185 17785 -135
+rect 16970 -190 17785 -185
+rect 17865 -185 17995 -135
+rect 18075 -185 18090 -130
+rect 17865 -190 18090 -185
+rect 16970 -250 18090 -190
+rect 16970 -305 17080 -250
+rect 17135 -305 17270 -250
+rect 17325 -305 17465 -250
+rect 17520 -305 17655 -250
+rect 17710 -305 17850 -250
+rect 17905 -305 18090 -250
+rect 16970 -315 18090 -305
+rect 18195 -40 20515 285
+rect 18195 -240 19315 -40
+rect 18195 -250 19320 -240
+rect 18195 -305 18385 -250
+rect 18440 -305 18580 -250
+rect 18635 -305 18770 -250
+rect 18825 -305 18965 -250
+rect 19020 -305 19155 -250
+rect 19210 -305 19320 -250
+rect 18195 -315 19320 -305
+rect 16965 -375 19765 -365
+rect 16965 -430 16980 -375
+rect 17035 -430 17175 -375
+rect 17230 -430 17370 -375
+rect 17425 -430 17560 -375
+rect 17615 -430 17750 -375
+rect 17805 -430 17945 -375
+rect 18000 -430 18290 -375
+rect 18345 -430 18485 -375
+rect 18540 -430 18675 -375
+rect 18730 -430 18865 -375
+rect 18920 -430 19060 -375
+rect 19115 -390 19255 -375
+rect 19310 -390 19765 -375
+rect 19115 -430 19230 -390
+rect 16965 -940 19230 -430
+rect 19730 -940 19765 -390
+rect 16965 -965 19765 -940
+<< via2 >>
+rect 17450 7150 17705 7265
+rect 18105 7150 18360 7265
+rect 18750 7150 19005 7265
+rect 19970 6120 20230 6135
+rect 19970 6060 20170 6120
+rect 20170 6060 20230 6120
+rect 19970 5925 20230 6060
+rect 19235 1840 19725 2215
+rect 19230 -430 19255 -390
+rect 19255 -430 19310 -390
+rect 19310 -430 19730 -390
+rect 19230 -940 19730 -430
+<< metal3 >>
+rect 17440 7265 20250 7275
+rect 17440 7150 17450 7265
+rect 17705 7150 18105 7265
+rect 18360 7150 18750 7265
+rect 19005 7150 20250 7265
+rect 17440 7140 20250 7150
+rect 19950 6135 20250 7140
+rect 19950 5925 19970 6135
+rect 20230 5925 20250 6135
+rect 19950 5905 20250 5925
+rect 19200 2215 19770 2255
+rect 19200 1840 19235 2215
+rect 19725 1840 19770 2215
+rect 19200 1805 19770 1840
+rect 19200 -390 19765 1805
+rect 19200 -940 19230 -390
+rect 19730 -940 19765 -390
+rect 19200 -965 19765 -940
+use sky130_fd_pr__pfet_01v8_lvt_D3M934  XM1
+timestamp 1662404926
+transform 0 1 20269 -1 0 2877
+box -1127 -319 1127 319
+use sky130_fd_pr__pfet_01v8_lvt_D3M934  XM2
+timestamp 1662404926
+transform 0 1 18069 -1 0 6117
+box -1127 -319 1127 319
+use sky130_fd_pr__pfet_01v8_lvt_D3M934  XM3
+timestamp 1662404926
+transform 0 1 18719 -1 0 6117
+box -1127 -319 1127 319
+use sky130_fd_pr__pfet_01v8_lvt_D3M934  XM29
+timestamp 1662404926
+transform 0 1 20269 -1 0 5127
+box -1127 -319 1127 319
+use sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4  XM30
+timestamp 1662404926
+transform 0 1 21019 -1 0 3207
+box -807 -319 807 319
+use sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4  XM31
+timestamp 1662404926
+transform 0 1 21019 -1 0 4807
+box -807 -319 807 319
+use sky130_fd_pr__pfet_01v8_lvt_D3M934  XM36
+timestamp 1662404926
+transform 0 1 17419 -1 0 6117
+box -1127 -319 1127 319
+use sky130_fd_pr__pfet_01v8_lvt_D3Z634  XM37
+timestamp 1662404926
+transform 0 1 17819 -1 0 2297
+box -2087 -319 2087 319
+use sky130_fd_pr__pfet_01v8_lvt_D3Z634  XM38
+timestamp 1662404926
+transform 0 1 18469 -1 0 2297
+box -2087 -319 2087 319
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX  XM39
+timestamp 1662404926
+transform 1 0 17493 0 1 -340
+box -647 -310 647 310
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX  XM40
+timestamp 1662404926
+transform -1 0 18797 0 -1 -340
+box -647 -310 647 310
+use sky130_fd_pr__res_high_po_2p85_P79JE3  XR19
+timestamp 1662404926
+transform 1 0 19491 0 1 5548
+box -451 -1358 451 1358
+use sky130_fd_pr__res_high_po_2p85_MM89SS  XR20
+timestamp 1662404926
+transform 1 0 19491 0 1 2448
+box -451 -1738 451 1738
+<< labels >>
+rlabel metal1 20820 5520 21340 5580 1 AMP
+rlabel metal1 21020 2435 21340 2495 1 VOP
+rlabel metal3 18360 7140 18750 7275 1 VDD
+rlabel metal2 19060 -40 20515 285 1 BIASOUT
+rlabel locali 18970 6975 20025 7020 1 PSUB
+rlabel metal1 17220 7150 20470 7220 1 BIAS2V
+rlabel metal1 17100 4310 18020 4370 1 VCTRL
+rlabel metal2 16965 -965 19230 -430 1 GND
+rlabel locali 19070 -100 19115 790 1 SUB
+<< end >>

mag/buffer_amp.ext

diff --git a/mag/buffer_amp.ext b/mag/buffer_amp.ext
new file mode 100644
index 0000000..87fc244
--- /dev/null
+++ b/mag/buffer_amp.ext
@@ -0,0 +1,235 @@
+timestamp 1662405622
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__res_high_po_5p73_YZEQ6M XR2 1 0 8779 0 1 5038
+use sky130_fd_pr__res_high_po_5p73_YZEQ6M XR1 1 0 5739 0 1 5038
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX XM4 0 1 7610 -1 0 2547
+use sky130_fd_pr__nfet_01v8_lvt_648S5X XM3 0 1 7610 -1 0 1611
+use sky130_fd_pr__nfet_01v8_lvt_648S5X XM2 0 1 6910 -1 0 1611
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX XM1 0 -1 6910 -1 0 2547
+node "INA" 2 194.122 7430 1400 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37500 1600 0 0 0 0 0 0 0 0 0 0
+node "INB" 2 224.4 6730 1400 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37500 1600 0 0 0 0 0 0 0 0 0 0
+node "OUTA" 1 2076.95 7510 1505 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 509350 3720 509350 3720 794925 4850 0 0 0 0 0 0
+node "OUTB" 1 2584.84 5165 1565 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 517250 3740 517250 3740 803600 4870 0 0 0 0 0 0
+node "m1_6810_1630#" 10 1404.35 6810 1630 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158240 6650 821100 7430 0 0 0 0 0 0 0 0
+node "GND" 11 3914.6 6810 2035 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143450 6560 2760000 14600 0 0 0 0 0 0 0 0
+node "BIAS" 18 3007.31 5000 3125 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 510000 17120 0 0 0 0 0 0 0 0 0 0
+node "VDD" 2 4231.39 5155 8075 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1009200 6380 1988800 9920 0 0 0 0 0 0 0 0
+node "li_7850_1435#" 99 89.4468 7850 1435 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "SUB" 99 84.722 7145 1435 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_6405_1435#" 99 92.4174 6405 1435 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7830_1750#" 99 46.3014 7830 1750 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7145_1750#" 99 39.3624 7145 1750 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_6410_1750#" 99 46.0211 6410 1750 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7840_1935#" 99 92.2893 7840 1935 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7135_1935#" 99 88.9125 7135 1935 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_6410_1935#" 99 96.1379 6410 1935 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7840_3125#" 99 127.02 7840 3125 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_7100_3125#" 99 122.457 7100 3125 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_6405_3125#" 99 130.396 6405 3125 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9450 610 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_7135_1935#" "SUB" 15.6559
+cap "li_7135_1935#" "m1_6810_1630#" 51.6985
+cap "li_7830_1750#" "li_7840_3125#" 5.43284
+cap "li_6405_3125#" "li_6410_1750#" 5.53731
+cap "li_7100_3125#" "li_6405_3125#" 2.30588
+cap "li_7145_1750#" "SUB" 27
+cap "li_7145_1750#" "m1_6810_1630#" 25.2312
+cap "BIAS" "li_6405_3125#" 85.4247
+cap "li_6405_1435#" "SUB" 2.08511
+cap "li_7850_1435#" "li_7830_1750#" 25
+cap "INA" "BIAS" 7.67431
+cap "GND" "BIAS" 3826.69
+cap "BIAS" "m1_6810_1630#" 2376.37
+cap "INB" "OUTA" 16.4835
+cap "OUTB" "li_6405_1435#" 35.9158
+cap "li_7850_1435#" "OUTA" 34.8152
+cap "OUTB" "BIAS" 42.5278
+cap "GND" "li_6405_3125#" 18.9112
+cap "INA" "GND" 46.5002
+cap "li_7135_1935#" "li_6410_1935#" 2.15385
+cap "INA" "m1_6810_1630#" 117.091
+cap "GND" "m1_6810_1630#" 7097.51
+cap "li_7145_1750#" "li_7830_1750#" 2.36145
+cap "li_7100_3125#" "li_7840_3125#" 2.08511
+cap "li_7830_1750#" "li_6410_1750#" 0.852174
+cap "INA" "OUTB" 16.4835
+cap "OUTB" "GND" 99.6142
+cap "BIAS" "li_7840_3125#" 82.6012
+cap "OUTB" "m1_6810_1630#" 484.985
+cap "INB" "BIAS" 7.67431
+cap "li_7850_1435#" "li_6405_1435#" 0.834043
+cap "li_6410_1935#" "li_6410_1750#" 50.4
+cap "li_6405_1435#" "li_6410_1935#" 15.957
+cap "li_7840_3125#" "li_7840_1935#" 6.54545
+cap "li_7830_1750#" "li_7840_1935#" 48.5333
+cap "li_7840_3125#" "li_6405_3125#" 0.841202
+cap "OUTA" "BIAS" 42.1976
+cap "li_7850_1435#" "li_7840_1935#" 15.6559
+cap "li_7135_1935#" "li_7145_1750#" 48.5333
+cap "li_6410_1935#" "li_7840_1935#" 0.844828
+cap "GND" "li_7840_3125#" 19.413
+cap "li_7100_3125#" "li_7135_1935#" 5.69697
+cap "INA" "INB" 56.225
+cap "INB" "GND" 46.5002
+cap "INB" "m1_6810_1630#" 117.091
+cap "li_6410_1935#" "li_6405_3125#" 6.42424
+cap "li_7850_1435#" "SUB" 2.25287
+cap "li_7145_1750#" "li_6410_1750#" 2.10753
+cap "OUTB" "INB" 505.5
+cap "li_7100_3125#" "li_7145_1750#" 4.70149
+cap "li_7135_1935#" "li_7840_1935#" 2.25287
+cap "li_6405_1435#" "li_6410_1750#" 26.5
+cap "INA" "OUTA" 493.111
+cap "OUTA" "GND" 99.4546
+cap "OUTA" "m1_6810_1630#" 484.985
+cap "li_7100_3125#" "BIAS" 78.9898
+cap "OUTB" "OUTA" 36.1683
+cap "XM2/a_n33_n188#" "XR1/a_n573_n3472#" 3.42445
+cap "XM3/a_15_n100#" "XR1/a_n573_n3472#" 0.211055
+cap "XM4/a_n417_n100#" "XR1/a_n573_n3472#" 1.36222
+cap "XR1/a_n703_n3602#" "XR1/a_n573_n3472#" -77.0603
+cap "XM3/a_n33_n188#" "XR1/a_n573_n3472#" 1.46406
+cap "XM2/a_n33_n188#" "XM4/a_n417_n100#" -17.8249
+cap "XR1/a_n573_n3472#" "XM4/a_n417_n100#" -142.801
+cap "XR2/a_n703_n3602#" "XM4/a_n465_n188#" 224.833
+cap "XM4/a_n465_n188#" "XM3/a_n33_n188#" 34.5191
+cap "XR2/a_n703_n3602#" "XM4/a_n509_n100#" 354.196
+cap "XM2/a_n33_n188#" "XM4/a_n465_n188#" 34.5191
+cap "XR1/a_n573_n3472#" "XM4/a_n509_n100#" 38.1918
+cap "XR2/a_n703_n3602#" "XR2/a_n573_n3472#" -648.299
+cap "XR2/a_n573_n3472#" "XM3/a_n33_n188#" -10.6846
+cap "XR1/a_n573_n3472#" "XR2/a_n573_n3472#" 2.35742
+cap "XR2/a_n573_n3472#" "XM2/a_n33_n188#" 2.09152
+cap "XM4/a_n465_n188#" "XM4/a_n417_n100#" 194.057
+cap "XR2/a_n703_n3602#" "XM3/a_n33_n188#" 135.61
+cap "XM4/a_n509_n100#" "XM4/a_n417_n100#" -2717.3
+cap "XR2/a_n703_n3602#" "XM2/a_n33_n188#" 141.964
+cap "XR1/a_n573_n3472#" "XR2/a_n703_n3602#" -454.135
+cap "XR1/a_n573_n3472#" "XM3/a_n33_n188#" 2.08917
+cap "XM2/a_n33_n188#" "XM3/a_n33_n188#" 18.6759
+cap "XR2/a_n573_n3472#" "XM4/a_n417_n100#" -142.797
+cap "XR1/a_n573_n3472#" "XM2/a_n33_n188#" -9.57346
+cap "XM4/a_n509_n100#" "XM4/a_n465_n188#" 204.174
+cap "XR2/a_n573_n3472#" "XM4/a_n509_n100#" 38.1918
+cap "XR2/a_n703_n3602#" "XM4/a_n417_n100#" 577.423
+cap "XM4/a_n417_n100#" "XM3/a_n33_n188#" -17.8249
+cap "XR2/a_n703_n3602#" "XM3/a_n33_n188#" 4.67266
+cap "XR2/a_n703_n3602#" "XM4/a_n509_n100#" 143.274
+cap "XR2/a_n573_n3472#" "XM2/a_n33_n188#" 1.46642
+cap "XR2/a_n573_n3472#" "XM2/a_15_n100#" 0.211409
+cap "XM4/a_n417_n100#" "XR2/a_n573_n3472#" 1.36681
+cap "XR2/a_n703_n3602#" "XM4/a_n465_n188#" 32.3745
+cap "XR2/a_n703_n3602#" "XM2/a_n33_n188#" 3.69843
+cap "XM4/a_n509_n100#" "XM4/a_n465_n188#" -123.63
+cap "XR2/a_n703_n3602#" "XM2/a_15_n100#" 2.97498
+cap "XR2/a_n573_n3472#" "XM3/a_n33_n188#" 3.4381
+cap "XR2/a_n703_n3602#" "XM4/a_n417_n100#" -692.196
+cap "XR2/a_n703_n3602#" "XR2/a_n573_n3472#" 37.3519
+cap "XR2/a_n573_n3472#" "XR2/a_n703_n3602#" 129.394
+cap "XR2/a_n573_n3472#" "XM3/a_n33_n188#" 0.0461533
+cap "XR1/a_n703_n3602#" "XM4/a_n509_n100#" 113.573
+cap "XR1/a_n703_n3602#" "XM4/a_n465_n188#" 46.5609
+cap "XR2/a_n703_n3602#" "XM2/a_n33_n188#" 0.643243
+cap "XR1/a_n573_n3472#" "XM4/a_n417_n100#" 2.18947
+cap "XR1/a_n573_n3472#" "XM4/a_n509_n100#" 4.40188
+cap "XM3/a_n33_n188#" "XM4/a_n465_n188#" 1.0411
+cap "XR2/a_n703_n3602#" "XM4/a_n509_n100#" 182.157
+cap "XR2/a_n703_n3602#" "XM4/a_n417_n100#" 96.7964
+cap "XR2/a_n703_n3602#" "XR2/a_n573_n3472#" 1.89091
+cap "XR2/a_n703_n3602#" "XM4/a_n465_n188#" 573.704
+cap "XM3/a_n33_n188#" "XR2/a_n703_n3602#" 0.643243
+cap "XM2/a_n33_n188#" "XM4/a_n465_n188#" 1.0411
+cap "XR2/a_n703_n3602#" "XR1/a_n573_n3472#" 1.89091
+cap "XM4/a_n509_n100#" "XM4/a_n417_n100#" -916.964
+cap "XR2/a_n573_n3472#" "XM4/a_n417_n100#" 2.18947
+cap "XM4/a_n509_n100#" "XR2/a_n573_n3472#" 4.40188
+cap "XM4/a_n509_n100#" "XM4/a_n465_n188#" 63.7459
+cap "XM4/a_n465_n188#" "XM4/a_n417_n100#" 9.21841
+cap "XR2/a_n703_n3602#" "XM4/a_n509_n100#" 84.9781
+cap "XR2/a_n703_n3602#" "XM4/a_n417_n100#" 2.33251
+cap "XM4/a_n465_n188#" "XM4/a_n509_n100#" -17.7632
+cap "XR2/a_n703_n3602#" "XM4/a_n465_n188#" 883.236
+cap "XR2/a_n703_n3602#" "XM4/a_447_n100#" 113.689
+cap "XR2/a_n703_n3602#" "XM4/a_n369_122#" 46.4307
+cap "XR1/a_n573_3040#" "XR1/a_n703_n3602#" 88.9666
+cap "XR1/a_n703_n3602#" "XR2/a_n573_3040#" 58.5132
+cap "XR2/a_n573_3040#" "XR1/a_n703_n3602#" 88.9666
+cap "XR2/a_n703_n3602#" "XR2/a_n573_3040#" 58.5132
+cap "XR1/a_n573_3040#" "XR1/a_n703_n3602#" 34.9006
+cap "XR1/a_n703_n3602#" "XR2/a_n573_3040#" 24.7504
+cap "XR2/a_n573_3040#" "XR1/a_n703_n3602#" 34.9006
+cap "XR2/a_n703_n3602#" "XR2/a_n573_3040#" 24.7504
+merge "XM1/a_399_122#" "XM1/a_303_n188#" -20824.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -30662440 -4160 0 0 0 0 0 0 0 0 0 0
+merge "XM1/a_303_n188#" "XM1/a_207_122#"
+merge "XM1/a_207_122#" "XM1/a_111_n188#"
+merge "XM1/a_111_n188#" "XM1/a_15_122#"
+merge "XM1/a_15_122#" "XM1/a_n81_n188#"
+merge "XM1/a_n81_n188#" "XM1/a_n177_122#"
+merge "XM1/a_n177_122#" "XM1/a_n273_n188#"
+merge "XM1/a_n273_n188#" "XM1/a_n369_122#"
+merge "XM1/a_n369_122#" "XM1/a_n465_n188#"
+merge "XM1/a_n465_n188#" "XM4/a_399_122#"
+merge "XM4/a_399_122#" "XM4/a_303_n188#"
+merge "XM4/a_303_n188#" "XM4/a_207_122#"
+merge "XM4/a_207_122#" "XM4/a_111_n188#"
+merge "XM4/a_111_n188#" "XM4/a_15_122#"
+merge "XM4/a_15_122#" "XM4/a_n81_n188#"
+merge "XM4/a_n81_n188#" "XM4/a_n177_122#"
+merge "XM4/a_n177_122#" "XM4/a_n273_n188#"
+merge "XM4/a_n273_n188#" "XM4/a_n369_122#"
+merge "XM4/a_n369_122#" "XM4/a_n465_n188#"
+merge "XM4/a_n465_n188#" "BIAS"
+merge "XM1/a_351_n100#" "XM1/a_159_n100#" 2460.23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8833920 -5904 -7375650 0 0 0 0 0 0 0 0 0
+merge "XM1/a_159_n100#" "XM1/a_n33_n100#"
+merge "XM1/a_n33_n100#" "XM1/a_n225_n100#"
+merge "XM1/a_n225_n100#" "XM1/a_n417_n100#"
+merge "XM1/a_n417_n100#" "XM2/a_n73_n100#"
+merge "XM2/a_n73_n100#" "XM3/a_n73_n100#"
+merge "XM3/a_n73_n100#" "XM4/a_351_n100#"
+merge "XM4/a_351_n100#" "XM4/a_159_n100#"
+merge "XM4/a_159_n100#" "XM4/a_n33_n100#"
+merge "XM4/a_n33_n100#" "XM4/a_n225_n100#"
+merge "XM4/a_n225_n100#" "XM4/a_n417_n100#"
+merge "XM4/a_n417_n100#" "m1_6810_1630#"
+merge "XR2/a_n703_n3602#" "XM1/a_n611_n274#" 2196.74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3895084 -3814 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM1/a_n611_n274#" "XM2/a_n175_n274#"
+merge "XM2/a_n175_n274#" "XM3/a_n175_n274#"
+merge "XM3/a_n175_n274#" "li_7850_1435#"
+merge "li_7850_1435#" "SUB"
+merge "SUB" "li_7830_1750#"
+merge "li_7830_1750#" "li_7145_1750#"
+merge "li_7145_1750#" "XM4/a_n611_n274#"
+merge "XM4/a_n611_n274#" "li_7840_1935#"
+merge "li_7840_1935#" "li_7135_1935#"
+merge "li_7135_1935#" "li_7840_3125#"
+merge "li_7840_3125#" "li_7100_3125#"
+merge "li_7100_3125#" "XR1/a_n703_n3602#"
+merge "XR1/a_n703_n3602#" "VSUBS"
+merge "VSUBS" "li_6405_1435#"
+merge "li_6405_1435#" "li_6410_1750#"
+merge "li_6410_1750#" "li_6410_1935#"
+merge "li_6410_1935#" "li_6405_3125#"
+merge "XR2/a_n573_n3472#" "XM3/a_15_n100#" 5641.67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2779952 -3586 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_15_n100#" "OUTA"
+merge "XM1/a_447_n100#" "XM1/a_255_n100#" -33522.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -29459460 -5904 -31019900 -1040 0 0 0 0 0 0 0 0
+merge "XM1/a_255_n100#" "XM1/a_63_n100#"
+merge "XM1/a_63_n100#" "XM1/a_n129_n100#"
+merge "XM1/a_n129_n100#" "XM1/a_n321_n100#"
+merge "XM1/a_n321_n100#" "XM1/a_n509_n100#"
+merge "XM1/a_n509_n100#" "XM4/a_447_n100#"
+merge "XM4/a_447_n100#" "XM4/a_255_n100#"
+merge "XM4/a_255_n100#" "XM4/a_63_n100#"
+merge "XM4/a_63_n100#" "XM4/a_n129_n100#"
+merge "XM4/a_n129_n100#" "XM4/a_n321_n100#"
+merge "XM4/a_n321_n100#" "XM4/a_n509_n100#"
+merge "XM4/a_n509_n100#" "GND"
+merge "XM2/a_15_n100#" "XR1/a_n573_n3472#" 1836.22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2219496 -3586 0 0 0 0 0 0 0 0 0 0
+merge "XR1/a_n573_n3472#" "OUTB"
+merge "XR2/a_n573_3040#" "XR1/a_n573_3040#" 3479.19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7347108 -6188 0 0 0 0 0 0 0 0 0 0
+merge "XR1/a_n573_3040#" "VDD"
+merge "XM3/a_n33_n188#" "INA" -2972.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4481660 -416 0 0 0 0 0 0 0 0 0 0
+merge "XM2/a_n33_n188#" "INB" -1967.25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2920880 -416 0 0 0 0 0 0 0 0 0 0

mag/buffer_amp.mag

diff --git a/mag/buffer_amp.mag b/mag/buffer_amp.mag
new file mode 100644
index 0000000..efa1e86
--- /dev/null
+++ b/mag/buffer_amp.mag
@@ -0,0 +1,375 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662405622
+<< pwell >>
+rect 7710 2035 7715 2140
+<< locali >>
+rect 6405 3125 6675 3160
+rect 7100 3125 7370 3160
+rect 7840 3125 8110 3160
+rect 6410 1935 6680 1970
+rect 7135 1935 7405 1970
+rect 7840 1935 8110 1970
+rect 6410 1750 6680 1785
+rect 7145 1750 7415 1785
+rect 7830 1750 8100 1785
+rect 6405 1435 6675 1470
+rect 7145 1435 7415 1470
+rect 7850 1435 8120 1470
+<< metal1 >>
+rect 5155 8490 6315 8510
+rect 5155 8095 5175 8490
+rect 6295 8095 6315 8490
+rect 5155 8075 6315 8095
+rect 8200 8490 9360 8510
+rect 8200 8095 8220 8490
+rect 9340 8095 9360 8490
+rect 8200 8075 9360 8095
+rect 5000 3125 9520 3185
+rect 6720 2085 6780 3125
+rect 6810 3050 6895 3060
+rect 6810 2995 6820 3050
+rect 6885 3000 7010 3050
+rect 6885 2995 6895 3000
+rect 6810 2990 6895 2995
+rect 6930 2965 7010 2970
+rect 6930 2956 6940 2965
+rect 6810 2910 6940 2956
+rect 7000 2910 7010 2965
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+rect 7580 2376 7590 2385
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+rect 7510 2130 7590 2135
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+rect 6810 2040 6820 2095
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+rect 7625 2095 7710 2105
+rect 7625 2090 7635 2095
+rect 6885 2040 7015 2090
+rect 7505 2040 7635 2090
+rect 7700 2040 7710 2095
+rect 7740 2085 7800 3125
+rect 6810 2035 6895 2040
+rect 7625 2035 7710 2040
+rect 5165 1980 6315 2000
+rect 5165 1585 5185 1980
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+rect 6810 1515 6820 1580
+rect 7000 1515 7010 1580
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+rect 7040 1450 7090 1645
+rect 6730 1400 7090 1450
+rect 7430 1450 7480 1645
+rect 7510 1640 7520 1715
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+rect 7700 1515 7710 1580
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+rect 7740 1450 7790 1645
+rect 8205 1585 8225 1980
+rect 9335 1585 9350 1980
+rect 8205 1565 9350 1585
+rect 7430 1400 7790 1450
+<< via1 >>
+rect 5175 8095 6295 8490
+rect 8220 8095 9340 8490
+rect 6820 2995 6885 3050
+rect 6940 2910 7000 2965
+rect 6820 2810 6885 2865
+rect 6940 2715 7000 2770
+rect 6820 2615 6885 2670
+rect 6940 2525 7000 2580
+rect 6820 2425 6885 2480
+rect 6940 2330 7000 2385
+rect 6820 2230 6885 2285
+rect 6940 2140 7000 2195
+rect 7635 2995 7700 3050
+rect 7520 2910 7580 2965
+rect 7635 2810 7700 2865
+rect 7520 2715 7580 2770
+rect 7635 2615 7700 2670
+rect 7520 2525 7580 2580
+rect 7635 2425 7700 2480
+rect 7520 2330 7580 2385
+rect 7635 2230 7700 2285
+rect 7520 2140 7580 2195
+rect 6820 2040 6885 2095
+rect 7635 2040 7700 2095
+rect 5185 1585 6295 1980
+rect 6820 1640 7000 1715
+rect 6820 1515 7000 1580
+rect 7520 1640 7700 1715
+rect 7520 1515 7700 1580
+rect 8225 1585 9335 1980
+<< metal2 >>
+rect 5000 8490 9520 8510
+rect 5000 8095 5175 8490
+rect 6295 8095 8220 8490
+rect 9340 8095 9520 8490
+rect 5000 8070 9520 8095
+rect 5000 3225 9520 3625
+rect 6495 3050 6895 3225
+rect 6495 2995 6820 3050
+rect 6885 2995 6895 3050
+rect 6495 2865 6895 2995
+rect 7040 2975 7480 3065
+rect 7625 3050 8025 3225
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+rect 7700 2995 8025 3050
+rect 6930 2965 7590 2975
+rect 6930 2910 6940 2965
+rect 7000 2910 7520 2965
+rect 7580 2910 7590 2965
+rect 6930 2900 7590 2910
+rect 6495 2810 6820 2865
+rect 6885 2810 6895 2865
+rect 6495 2670 6895 2810
+rect 7040 2780 7480 2900
+rect 7625 2865 8025 2995
+rect 7625 2810 7635 2865
+rect 7700 2810 8025 2865
+rect 6930 2770 7590 2780
+rect 6930 2715 6940 2770
+rect 7000 2715 7520 2770
+rect 7580 2715 7590 2770
+rect 6930 2705 7590 2715
+rect 6495 2615 6820 2670
+rect 6885 2615 6895 2670
+rect 6495 2480 6895 2615
+rect 7040 2590 7480 2705
+rect 7625 2670 8025 2810
+rect 7625 2615 7635 2670
+rect 7700 2615 8025 2670
+rect 6930 2580 7590 2590
+rect 6930 2525 6940 2580
+rect 7000 2525 7520 2580
+rect 7580 2525 7590 2580
+rect 6930 2515 7590 2525
+rect 6495 2425 6820 2480
+rect 6885 2425 6895 2480
+rect 6495 2285 6895 2425
+rect 7040 2395 7480 2515
+rect 7625 2480 8025 2615
+rect 7625 2425 7635 2480
+rect 7700 2425 8025 2480
+rect 6930 2385 7590 2395
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+rect 7000 2330 7520 2385
+rect 7580 2330 7590 2385
+rect 6930 2320 7590 2330
+rect 6495 2230 6820 2285
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+rect 6495 2095 6895 2230
+rect 7040 2205 7480 2320
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+rect 7700 2230 8025 2285
+rect 6930 2195 7590 2205
+rect 6930 2140 6940 2195
+rect 7000 2140 7520 2195
+rect 7580 2140 7590 2195
+rect 6930 2130 7590 2140
+rect 6495 2040 6820 2095
+rect 6885 2040 6895 2095
+rect 6495 2035 6895 2040
+rect 5165 1980 6315 2000
+rect 5165 1585 5185 1980
+rect 6295 1585 6315 1980
+rect 7040 1870 7480 2130
+rect 7625 2095 8025 2230
+rect 7625 2040 7635 2095
+rect 7700 2040 8025 2095
+rect 7625 2035 8025 2040
+rect 8205 1980 9350 2000
+rect 6715 1720 7805 1870
+rect 6715 1715 7105 1720
+rect 6715 1685 6820 1715
+rect 6810 1640 6820 1685
+rect 7000 1685 7105 1715
+rect 7415 1715 7805 1720
+rect 7415 1685 7520 1715
+rect 7000 1640 7010 1685
+rect 6810 1630 7010 1640
+rect 7510 1640 7520 1685
+rect 7700 1685 7805 1715
+rect 7700 1640 7710 1685
+rect 7510 1630 7710 1640
+rect 5165 1565 6315 1585
+rect 6810 1580 7010 1590
+rect 6810 1515 6820 1580
+rect 7000 1515 7010 1580
+rect 6810 1505 7010 1515
+rect 7510 1580 7710 1590
+rect 7510 1515 7520 1580
+rect 7700 1515 7710 1580
+rect 8205 1585 8225 1980
+rect 9335 1585 9350 1980
+rect 8205 1570 9350 1585
+rect 7510 1505 7710 1515
+<< via2 >>
+rect 5185 1585 6295 1980
+rect 6820 1515 7000 1580
+rect 7520 1515 7700 1580
+rect 8225 1585 9335 1980
+<< metal3 >>
+rect 5165 1980 6315 2000
+rect 5165 1585 5185 1980
+rect 6295 1590 6315 1980
+rect 8205 1980 9350 1995
+rect 8205 1590 8225 1980
+rect 6295 1585 7010 1590
+rect 5165 1580 7010 1585
+rect 5165 1515 6820 1580
+rect 7000 1515 7010 1580
+rect 5165 1410 7010 1515
+rect 7510 1585 8225 1590
+rect 9335 1585 9350 1980
+rect 7510 1580 9350 1585
+rect 7510 1515 7520 1580
+rect 7700 1515 9350 1580
+rect 7510 1410 9350 1515
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX  XM1
+timestamp 1662404926
+transform 0 -1 6910 -1 0 2547
+box -647 -310 647 310
+use sky130_fd_pr__nfet_01v8_lvt_648S5X  XM2
+timestamp 1662404926
+transform 0 1 6910 -1 0 1611
+box -211 -310 211 310
+use sky130_fd_pr__nfet_01v8_lvt_648S5X  XM3
+timestamp 1662404926
+transform 0 1 7610 -1 0 1611
+box -211 -310 211 310
+use sky130_fd_pr__nfet_01v8_lvt_9DHFGX  XM4
+timestamp 1662404926
+transform 0 1 7610 -1 0 2547
+box -647 -310 647 310
+use sky130_fd_pr__res_high_po_5p73_YZEQ6M  XR1
+timestamp 1662404926
+transform 1 0 5739 0 1 5038
+box -739 -3638 739 3638
+use sky130_fd_pr__res_high_po_5p73_YZEQ6M  XR2
+timestamp 1662404926
+transform 1 0 8779 0 1 5038
+box -739 -3638 739 3638
+<< labels >>
+rlabel metal1 7430 1400 7790 1450 1 INA
+rlabel metal1 6730 1400 7090 1450 1 INB
+rlabel metal1 5000 3125 9520 3185 1 BIAS
+rlabel metal2 5000 3225 9520 3625 1 GND
+rlabel metal2 6295 8075 8220 8510 1 VDD
+rlabel metal3 5165 1410 6820 1585 1 OUTB
+rlabel metal3 7700 1410 9350 1585 1 OUTA
+rlabel locali 7145 1435 7415 1470 1 SUB
+<< end >>

mag/buffer_amp_vop.ext

diff --git a/mag/buffer_amp_vop.ext b/mag/buffer_amp_vop.ext
new file mode 100644
index 0000000..d2b2be0
--- /dev/null
+++ b/mag/buffer_amp_vop.ext
@@ -0,0 +1,1143 @@
+timestamp 1662863789
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use vop_dec X6 0 1 9830 -1 0 21409
+use amp_dec X5 0 1 9640 -1 0 26439
+use buffer_amp X4 1 0 19660 0 1 17350
+use buffer_amp X3 1 0 15140 0 -1 19081
+use buffer_amp X2 1 0 19660 0 -1 19081
+use buffer_amp X1 1 0 15140 0 1 17350
+node "AMP" 0 33.3541 10225 20205 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1625 180 0 0 0 0
+node "OUT90" 1 3730.37 23350 10410 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2181000 15140 0 0 0 0 0 0
+node "OUT270" 1 3565.59 21150 10400 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2181000 15140 0 0 0 0 0 0
+node "m3_10348_15604#" 0 602.568 10348 15604 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 580592 3264 0 0 0 0 0 0
+node "m3_19820_13570#" 3 4691.79 19820 13570 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3226900 30226 0 0 0 0 0 0
+node "OUT0" 1 3763.09 23350 18760 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2181000 15140 0 0 0 0 0 0
+node "OUT180" 1 3730.36 21150 18760 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2181000 15140 0 0 0 0 0 0
+node "GND" 2 4220.47 20640 12820 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1214900 6880 2076000 11180 0 0 0 0 0 0
+node "VDD" 2 2194.66 19520 10570 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1344200 9160 0 0 0 0 0 0 0 0
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mag/buffer_amp_vop.mag

diff --git a/mag/buffer_amp_vop.mag b/mag/buffer_amp_vop.mag
new file mode 100644
index 0000000..0401df1
--- /dev/null
+++ b/mag/buffer_amp_vop.mag
@@ -0,0 +1,259 @@
+magic
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+magscale 1 2
+timestamp 1662863789
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+rect 21660 18650 22760 18670
+rect 21660 18580 21680 18650
+rect 21750 18580 22760 18650
+rect 21660 18560 22760 18580
+rect 25635 18330 25835 18939
+rect 27680 18330 27880 18934
+rect 19870 18100 27880 18330
+rect 17540 16990 17840 17020
+rect 17540 16760 17610 16990
+rect 17790 16760 17840 16990
+rect 10348 15604 10872 16712
+rect 17540 14390 17840 16760
+rect 17540 14150 17610 14390
+rect 17810 14150 17840 14390
+rect 17540 14130 17840 14150
+rect 19870 13970 20070 18100
+rect 21660 17900 22760 17920
+rect 21660 17830 21680 17900
+rect 21750 17830 22760 17900
+rect 21660 17810 22760 17830
+rect 20130 17470 20400 17490
+rect 20130 17400 20150 17470
+rect 20220 17400 20400 17470
+rect 20130 17380 20400 17400
+rect 19820 13570 20070 13970
+rect 15850 13200 21040 13220
+rect 15850 12840 20660 13200
+rect 21010 12840 21040 13200
+rect 15850 12820 21040 12840
+rect 21150 10400 21450 17670
+rect 22650 17570 22760 17810
+rect 23350 10410 23650 17680
+rect 25635 17490 25835 18100
+rect 27680 17630 27880 18100
+<< metal4 >>
+rect 10225 20205 10250 20270
+use buffer_amp  X1
+timestamp 1662405622
+transform 1 0 15140 0 1 17350
+box 5000 1400 9520 8676
+use buffer_amp  X2
+timestamp 1662405622
+transform 1 0 19660 0 -1 19081
+box 5000 1400 9520 8676
+use buffer_amp  X3
+timestamp 1662405622
+transform 1 0 15140 0 -1 19081
+box 5000 1400 9520 8676
+use buffer_amp  X4
+timestamp 1662405622
+transform 1 0 19660 0 1 17350
+box 5000 1400 9520 8676
+use amp_dec  X5
+timestamp 1662519997
+transform 0 1 9640 -1 0 26439
+box 5000 590 10199 10196
+use vop_dec  X6
+timestamp 1662515827
+transform 0 1 9830 -1 0 21409
+box 5600 400 10899 9996
+<< labels >>
+rlabel metal2 10240 16000 19660 16430 1 VOP
+rlabel metal3 15850 12820 20660 13220 1 GND
+rlabel metal1 10230 13380 20140 13450 1 BIAS
+rlabel metal3 21150 18760 21450 26030 1 OUT180
+rlabel metal3 23350 18760 23650 26030 1 OUT0
+rlabel metal3 21150 10400 21450 17670 1 OUT270
+rlabel metal3 23350 10410 23650 17680 1 OUT90
+rlabel locali 19760 21370 20200 21410 1 SUB
+rlabel metal1 10240 22090 20210 22160 1 BIAS
+rlabel space 10230 20009 11310 20399 1 AMP
+rlabel metal4 10225 20205 10250 20270 1 AMP
+rlabel metal2 26730 18620 29180 18720 1 I4B
+rlabel metal2 27430 18490 29180 18590 1 I4A
+rlabel metal2 22210 18360 29180 18460 1 I1B
+rlabel metal2 22910 18230 29180 18330 1 I1A
+rlabel metal2 26740 18100 29180 18200 1 I3B
+rlabel metal2 27440 17970 29180 18070 1 I3A
+rlabel metal2 22920 17840 29180 17940 1 I2A
+rlabel metal2 22220 17710 29180 17810 1 I2B
+rlabel metal2 19520 10570 19820 14420 1 VDD
+<< end >>

mag/cap_bank.ext

diff --git a/mag/cap_bank.ext b/mag/cap_bank.ext
new file mode 100644
index 0000000..f60930a
--- /dev/null
+++ b/mag/cap_bank.ext
@@ -0,0 +1,357 @@
+timestamp 1662665204
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__cap_mim_m3_2_FJFAMD XC6 1 0 3851 0 1 -229
+use sky130_fd_pr__nfet_01v8_lvt_648S5X XM1 0 1 4010 -1 0 -1329
+use sky130_fd_pr__nfet_01v8_lvt_648S5X XM2 0 1 4800 -1 0 -1329
+use sky130_fd_pr__nfet_01v8_lvt_DJ7QE5 XM3 0 -1 4800 1 0 -847
+use sky130_fd_pr__nfet_01v8_lvt_BX7S53 XM4 0 1 4800 -1 0 -279
+use sky130_fd_pr__nfet_01v8_lvt_B6HS5D XM5 0 1 4800 -1 0 485
+use sky130_fd_pr__cap_mim_m3_2_WCTBV5 XC1 1 0 3851 0 1 701
+use sky130_fd_pr__cap_mim_m3_2_WCTZRP XC2 1 0 3951 0 1 1631
+use sky130_fd_pr__cap_mim_m3_2_3ZFDVT XC3 1 0 3951 0 1 2761
+use sky130_fd_pr__cap_mim_m3_2_VCH7EQ XC4 0 1 4611 1 0 4541
+node "IN" 0 3005.1 3380 -420 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3898000 13720 0 0
+node "m1_4820_n1420#" 1 504.976 4820 -1420 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6400 320 93600 1240 57600 1040 115200 1360 1091200 6620 0 0
+node "m1_4610_n1360#" 0 11.031 4610 -1360 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4200 260 0 0 0 0 0 0 0 0 0 0
+node "ctrll1" 4 551.037 3300 -1540 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120000 4120 0 0 0 0 0 0 0 0 0 0
+node "m1_3820_n1360#" 0 31.8294 3820 -1360 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4200 260 0 0 0 0 0 0 0 0 0 0
+node "m1_3910_n1320#" 1 566.026 3910 -1320 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11920 560 93600 1240 61200 1060 363600 2740 0 0 0 0
+node "ctrll2" 4 350.884 3300 -1180 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119400 4100 0 0 0 0 0 0 0 0 0 0
+node "m1_4820_n890#" 1 949.676 4820 -890 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6400 320 133100 1500 68800 1180 673300 7200 0 0 0 0
+node "ctrll3" 4 608 3300 -640 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 145200 4640 0 0 0 0 0 0 0 0 0 0
+node "m1_4820_n460#" 2 949.739 4820 -460 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12800 640 165000 1720 88000 1420 720000 7680 0 0 0 0
+node "ctrll4" 5 747.462 3300 -50 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 145800 4980 0 0 0 0 0 0 0 0 0 0
+node "m1_4700_270#" 4 2051.68 4700 270 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37200 1680 248100 2300 137600 2040 689280 8936 0 0 0 0
+node "ctrll5" 6 1162.94 3300 860 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 181200 6160 0 0 0 0 0 0 0 0 0 0
+node "li_4250_n1505#" 113 94.4717 4250 -1505 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10850 690 0 0 0 0 0 0 0 0 0 0 0 0
+node "GND" 65 1192.6 4250 -1355 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21700 760 103020 4880 808200 6360 0 0 0 0 0 0 0 0
+node "li_5040_n1185#" 53 60.524 5040 -1185 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5075 360 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4250_n1190#" 154 132.772 4250 -1190 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14700 910 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5040_n655#" 53 53.9541 5040 -655 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5075 360 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4525_n660#" 53 56.4427 4525 -660 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5075 360 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_5040_n40#" 53 60.6435 5040 -40 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5075 360 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4525_n40#" 53 61.7446 4525 -40 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5075 360 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_4250_n1190#" "ctrll2" 118.791
+cap "li_5040_n40#" "li_4525_n40#" 8.45833
+cap "ctrll3" "m1_3910_n1320#" 74.6566
+cap "li_4525_n660#" "ctrll3" 32.4402
+cap "m1_3910_n1320#" "ctrll1" 347.217
+cap "m1_4610_n1360#" "m1_3910_n1320#" 2.04259
+cap "li_5040_n655#" "li_4525_n660#" 8.16667
+cap "GND" "m1_4820_n460#" 740.254
+cap "m1_4820_n460#" "ctrll2" 7.94567
+cap "ctrll3" "m1_4820_n890#" 367.831
+cap "li_5040_n1185#" "ctrll2" 28.6554
+cap "li_5040_n655#" "m1_4820_n890#" 4.26797
+cap "ctrll1" "m1_4820_n890#" 5.00339
+cap "ctrll4" "m1_4820_n460#" 414.554
+cap "m1_4820_n1420#" "m1_4700_270#" 891.337
+cap "li_4525_n660#" "li_4525_n40#" 2.06316
+cap "m1_3820_n1360#" "ctrll3" 3.40615
+cap "m1_3820_n1360#" "ctrll1" 28.3846
+cap "m1_4820_n1420#" "ctrll5" 44.2096
+cap "m1_4610_n1360#" "m1_3820_n1360#" 3.53836
+cap "GND" "ctrll3" 546.659
+cap "m1_4700_270#" "ctrll5" 1037.94
+cap "m1_3910_n1320#" "m1_4820_n890#" 80.0714
+cap "GND" "ctrll1" 751.211
+cap "m1_4610_n1360#" "GND" 82.3064
+cap "ctrll3" "ctrll2" 150.538
+cap "ctrll1" "ctrll2" 249.986
+cap "m1_4610_n1360#" "ctrll2" 30.0619
+cap "ctrll4" "li_5040_n40#" 26.2137
+cap "m1_3820_n1360#" "m1_3910_n1320#" 85.5477
+cap "m1_4820_n1420#" "IN" 193.693
+cap "ctrll4" "ctrll3" 138.886
+cap "m1_4700_270#" "IN" 497.963
+cap "ctrll4" "ctrll1" 47.8078
+cap "GND" "m1_3910_n1320#" 738.836
+cap "ctrll4" "m1_4610_n1360#" 2.51591
+cap "GND" "li_4525_n40#" 22.729
+cap "GND" "li_4525_n660#" 22.5204
+cap "m1_3910_n1320#" "ctrll2" 344.919
+cap "IN" "ctrll5" 72.5383
+cap "GND" "m1_4820_n890#" 1034.91
+cap "ctrll4" "m1_3910_n1320#" 6.13414
+cap "ctrll4" "li_4525_n40#" 27.1524
+cap "ctrll2" "m1_4820_n890#" 12.8348
+cap "m1_4820_n1420#" "m1_4820_n460#" 1426.41
+cap "GND" "m1_3820_n1360#" 21.5611
+cap "m1_4700_270#" "m1_4820_n460#" 3111.27
+cap "m1_4820_n1420#" "li_5040_n1185#" 8.11316
+cap "ctrll4" "m1_4820_n890#" 17.9675
+cap "m1_3820_n1360#" "ctrll2" 22.5873
+cap "ctrll5" "m1_4820_n460#" 23.1958
+cap "li_4250_n1505#" "li_4250_n1190#" 31
+cap "GND" "ctrll2" 590.664
+cap "ctrll4" "m1_3820_n1360#" 1.78548
+cap "m1_4820_n1420#" "li_5040_n40#" 3.12854
+cap "ctrll4" "GND" 746.375
+cap "m1_4820_n1420#" "ctrll3" 19.5467
+cap "m1_4700_270#" "li_5040_n40#" 35.5431
+cap "m1_4700_270#" "ctrll3" 21.9375
+cap "m1_4820_n1420#" "li_5040_n655#" 1.25142
+cap "m1_4820_n1420#" "ctrll1" 389.799
+cap "m1_4820_n1420#" "m1_4610_n1360#" 4.92
+cap "ctrll4" "ctrll2" 64.133
+cap "ctrll5" "ctrll3" 48.6247
+cap "li_4250_n1190#" "li_5040_n1185#" 8.16667
+cap "m1_4610_n1360#" "ctrll5" 1.39245
+cap "m1_4820_n1420#" "m1_3910_n1320#" 68.4958
+cap "li_4250_n1505#" "ctrll1" 97.923
+cap "m1_4820_n1420#" "m1_4820_n890#" 1582.8
+cap "m1_4700_270#" "m1_4820_n890#" 444.855
+cap "m1_4820_n1420#" "m1_3820_n1360#" 0.785106
+cap "ctrll5" "m1_4820_n890#" 26.9404
+cap "li_4250_n1505#" "li_4525_n40#" 0.685315
+cap "li_4250_n1505#" "li_4525_n660#" 1.20988
+cap "m1_4820_n1420#" "GND" 580.437
+cap "m1_4820_n460#" "li_5040_n40#" 0.397451
+cap "ctrll3" "m1_4820_n460#" 34.1226
+cap "m1_4700_270#" "GND" 2549.09
+cap "li_5040_n40#" "li_5040_n1185#" 0.98
+cap "m1_4820_n1420#" "ctrll2" 247.817
+cap "m1_4820_n460#" "ctrll1" 5.33379
+cap "li_5040_n655#" "m1_4820_n460#" 23.3545
+cap "li_4250_n1190#" "li_4525_n40#" 0.975124
+cap "li_4525_n660#" "li_4250_n1190#" 2.54545
+cap "li_5040_n655#" "li_5040_n1185#" 2.54545
+cap "m1_4700_270#" "ctrll2" 10.0352
+cap "ctrll5" "GND" 1131.19
+cap "m1_4820_n1420#" "ctrll4" 6.18597
+cap "ctrll4" "m1_4700_270#" 57.6403
+cap "ctrll5" "ctrll2" 3.22382
+cap "m1_3910_n1320#" "m1_4820_n460#" 5.53125
+cap "ctrll4" "ctrll5" 92.0704
+cap "li_4250_n1505#" "GND" 84.36
+cap "li_5040_n655#" "li_5040_n40#" 2.08511
+cap "li_5040_n655#" "ctrll3" 32.4402
+cap "ctrll3" "ctrll1" 82.8643
+cap "m1_4610_n1360#" "ctrll3" 4.81304
+cap "m1_4610_n1360#" "ctrll1" 24.75
+cap "m1_4820_n460#" "m1_4820_n890#" 3146.56
+cap "GND" "li_4250_n1190#" 121.028
+cap "li_5040_n1185#" "m1_4820_n890#" 13.5527
+cap "ctrll4" "IN" 61.188
+cap "XM2/a_15_n100#" "XM2/a_n33_n188#" 0.3075
+cap "XM3/a_15_122#" "XM1/a_n175_n274#" -103.4
+cap "XM3/a_n33_n100#" "XM1/a_n175_n274#" -50.5437
+cap "XM2/a_n33_n188#" "XM5/a_n273_n188#" 0.143394
+cap "XM2/a_15_n100#" "XM1/a_n175_n274#" -47.1816
+cap "XM4/a_n81_n100#" "XM3/a_n33_n100#" 0.479619
+cap "XM4/a_n81_n100#" "XM2/a_15_n100#" 0.223354
+cap "XM4/a_n129_n188#" "XM1/a_n33_n188#" -3.55271e-15
+cap "XM1/a_n175_n274#" "XM5/a_n273_n188#" 3.72281
+cap "XC6/m4_n551_n300#" "XM1/a_n33_n188#" 2.65371
+cap "XC6/m4_n551_n300#" "XC6/c2_n451_n200#" 73.681
+cap "XM5/a_n225_n100#" "XM1/a_n175_n274#" 1.2736
+cap "XM3/a_15_122#" "XM3/a_n33_n100#" 0.597647
+cap "XM4/a_n129_n188#" "XM2/a_n33_n188#" 5.43037
+cap "XC6/m4_n551_n300#" "XM2/a_n33_n188#" -0.175658
+cap "XM4/a_n81_n100#" "XM5/a_n225_n100#" 0.459188
+cap "XM2/a_n33_n188#" "XM1/a_n33_n188#" 12.951
+cap "XM2/a_15_n100#" "XM3/a_n33_n100#" 0.227642
+cap "XM3/a_15_122#" "XM5/a_n273_n188#" 4.49189
+cap "XC6/m4_n551_n300#" "XM1/a_n175_n274#" -75.76
+cap "XM4/a_n129_n188#" "XM1/a_n175_n274#" 14.4842
+cap "XM1/a_n33_n188#" "XM1/a_n175_n274#" 179.577
+cap "XM4/a_n81_n100#" "XC6/m4_n551_n300#" 33.6496
+cap "XM4/a_n81_n100#" "XM4/a_n129_n188#" 22.9395
+cap "XM3/a_n33_n100#" "XM5/a_n225_n100#" 0.13136
+cap "XM2/a_n33_n188#" "XM1/a_n175_n274#" 204.523
+cap "XM3/a_15_122#" "XC6/m4_n551_n300#" -1.66718
+cap "XM3/a_15_122#" "XM4/a_n129_n188#" 14.3714
+cap "XM3/a_15_122#" "XM1/a_n33_n188#" -7.10543e-15
+cap "XM3/a_n33_n100#" "XC6/m4_n551_n300#" 208.435
+cap "XM4/a_n81_n100#" "XM1/a_n175_n274#" -93.693
+cap "XM2/a_15_n100#" "XC6/m4_n551_n300#" 55.192
+cap "XM2/a_15_n100#" "XM1/a_n33_n188#" 0.887984
+cap "XM3/a_15_122#" "XM2/a_n33_n188#" 6.31974
+cap "XM2/a_15_n100#" "XC6/c2_n451_n200#" 0.0542872
+cap "XM4/a_n129_n188#" "XM5/a_n273_n188#" 14.4613
+cap "XM2/a_15_n100#" "XM1/a_n33_n188#" 50.6018
+cap "XM3/a_n33_n100#" "XM4/a_n129_n188#" 2.86047
+cap "XM1/a_n175_n274#" "XM4/a_n129_n188#" -60.5298
+cap "XM4/a_n129_n188#" "XM2/a_n33_n188#" 3.35126
+cap "XM1/a_n175_n274#" "XM3/a_15_122#" -543.683
+cap "XM3/a_15_122#" "XM2/a_n33_n188#" 7.45069
+cap "XM3/a_n33_n100#" "XM3/a_15_122#" 13.4269
+cap "XM2/a_15_n100#" "XC6/c2_n451_n200#" 0.0542872
+cap "XM1/a_n175_n274#" "XC6/m4_n551_n300#" 1.32633
+cap "XM2/a_n33_n188#" "XC6/m4_n551_n300#" 0.101942
+cap "XM2/a_15_n100#" "XM4/a_n81_n100#" -67.0432
+cap "XM4/a_n81_n100#" "XM1/a_n33_n188#" 7.89414
+cap "XM5/a_n273_n188#" "XM4/a_n81_n100#" 3.83018
+cap "XM1/a_n175_n274#" "XM2/a_n33_n188#" -506.981
+cap "XM1/a_n175_n274#" "XM3/a_n33_n100#" 260.352
+cap "XM3/a_n33_n100#" "XM2/a_n33_n188#" 17.712
+cap "XM2/a_15_n100#" "XM4/a_n129_n188#" 1.70308
+cap "XM2/a_15_n100#" "XM3/a_15_122#" 5.47884
+cap "XM4/a_n129_n188#" "XM5/a_n273_n188#" 10.7514
+cap "XM5/a_n225_n100#" "XM4/a_n81_n100#" 41.9326
+cap "XM3/a_15_122#" "XM5/a_n273_n188#" 4.49189
+cap "XM2/a_15_n100#" "XC6/m4_n551_n300#" 55.192
+cap "XM4/a_n129_n188#" "XM4/a_n81_n100#" 92.2188
+cap "XM3/a_15_122#" "XM4/a_n81_n100#" 46.6276
+cap "XM2/a_15_n100#" "XM1/a_n175_n274#" 287.705
+cap "XM3/a_n33_n100#" "XM1/a_n33_n188#" 7.25902
+cap "XM1/a_n175_n274#" "XM1/a_n33_n188#" -564.037
+cap "XM2/a_15_n100#" "XM3/a_n33_n100#" 20.8348
+cap "XM2/a_n33_n188#" "XM1/a_n33_n188#" 2.8076
+cap "XM2/a_15_n100#" "XM2/a_n33_n188#" 27.9164
+cap "XM4/a_n81_n100#" "XC6/m4_n551_n300#" 33.6496
+cap "XM1/a_n175_n274#" "XM5/a_n273_n188#" 7.68044
+cap "XM2/a_n33_n188#" "XM5/a_n273_n188#" 0.80878
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mag/cap_bank.mag

diff --git a/mag/cap_bank.mag b/mag/cap_bank.mag
new file mode 100644
index 0000000..7000552
--- /dev/null
+++ b/mag/cap_bank.mag
@@ -0,0 +1,347 @@
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+rect 4820 -1410 4830 -1350
+rect 4890 -1410 4950 -1350
+rect 4820 -1480 4950 -1410
+rect 5050 -1480 5080 -1180
+rect 4820 -1510 5080 -1480
+<< via2 >>
+rect 4980 90 5080 910
+rect 4980 -530 5080 -30
+rect 4980 -1030 5080 -650
+rect 3760 -1470 3880 -1180
+rect 4950 -1480 5050 -1180
+<< metal3 >>
+rect 4950 910 5110 920
+rect 4950 90 4980 910
+rect 5080 90 5110 910
+rect 4950 60 5110 90
+rect 4950 -30 5110 0
+rect 4950 -530 4980 -30
+rect 5080 -530 5110 -30
+rect 4950 -550 5110 -530
+rect 4950 -650 5110 -630
+rect 4950 -1030 4980 -650
+rect 5080 -1030 5110 -650
+rect 4950 -1060 5110 -1030
+rect 3730 -1180 3900 -1150
+rect 3730 -1470 3760 -1180
+rect 3880 -1470 3900 -1180
+rect 3730 -1510 3900 -1470
+rect 4920 -1180 5080 -1150
+rect 4920 -1480 4950 -1180
+rect 5050 -1480 5080 -1180
+rect 4920 -1510 5080 -1480
+<< via3 >>
+rect 4980 90 5080 910
+rect 4980 -530 5080 -30
+rect 4980 -1030 5080 -650
+rect 3760 -1470 3880 -1180
+rect 4950 -1480 5050 -1180
+<< metal4 >>
+rect 4370 2260 4890 2540
+rect 3730 -1180 4090 -500
+rect 4510 -630 4670 1930
+rect 4730 0 4890 2260
+rect 4950 910 5110 4368
+rect 4950 90 4980 910
+rect 5080 90 5110 910
+rect 4950 60 5110 90
+rect 4730 -30 5110 0
+rect 4730 -530 4980 -30
+rect 5080 -530 5110 -30
+rect 4730 -560 5110 -530
+rect 4510 -650 5110 -630
+rect 4510 -1030 4980 -650
+rect 5080 -1030 5110 -650
+rect 4510 -1060 5110 -1030
+rect 4510 -1070 5080 -1060
+rect 3730 -1470 3760 -1180
+rect 3880 -1470 4090 -1180
+rect 3730 -1510 4090 -1470
+rect 4760 -1180 5080 -1150
+rect 4760 -1480 4810 -1180
+rect 5050 -1480 5080 -1180
+rect 4760 -1510 5080 -1480
+<< via4 >>
+rect 4810 -1480 4950 -1180
+rect 4950 -1480 5050 -1180
+<< metal5 >>
+rect 3380 3710 4990 4830
+rect 3380 3700 4930 3710
+rect 3380 1430 3970 3700
+rect 3380 -420 3780 1430
+rect 4280 400 5080 1000
+rect 4760 -1180 5080 400
+rect 4760 -1480 4810 -1180
+rect 5050 -1480 5080 -1180
+rect 4760 -1510 5080 -1480
+use sky130_fd_pr__cap_mim_m3_2_WCTBV5  XC1
+timestamp 1660521579
+transform 1 0 3851 0 1 701
+box -551 -301 573 301
+use sky130_fd_pr__cap_mim_m3_2_WCTZRP  XC2
+timestamp 1660420676
+transform 1 0 3951 0 1 1631
+box -651 -301 673 301
+use sky130_fd_pr__cap_mim_m3_2_3ZFDVT  XC3
+timestamp 1660420676
+transform 1 0 3951 0 1 2761
+box -651 -501 673 501
+use sky130_fd_pr__cap_mim_m3_2_VCH7EQ  XC4
+timestamp 1660420676
+transform 0 1 4611 1 0 4541
+box -951 -501 973 501
+use sky130_fd_pr__cap_mim_m3_2_FJFAMD  XC6
+timestamp 1660420676
+transform 1 0 3851 0 1 -229
+box -551 -301 573 301
+use sky130_fd_pr__nfet_01v8_lvt_648S5X  XM1
+timestamp 1662404926
+transform 0 1 4010 -1 0 -1329
+box -211 -310 211 310
+use sky130_fd_pr__nfet_01v8_lvt_648S5X  XM2
+timestamp 1662404926
+transform 0 1 4800 -1 0 -1329
+box -211 -310 211 310
+use sky130_fd_pr__nfet_01v8_lvt_DJ7QE5  XM3
+timestamp 1660420676
+transform 0 -1 4800 1 0 -847
+box -263 -310 263 310
+use sky130_fd_pr__nfet_01v8_lvt_BX7S53  XM4
+timestamp 1660420676
+transform 0 1 4800 -1 0 -279
+box -311 -310 311 310
+use sky130_fd_pr__nfet_01v8_lvt_B6HS5D  XM5
+timestamp 1660420676
+transform 0 1 4800 -1 0 485
+box -455 -310 455 310
+<< labels >>
+rlabel metal2 4100 -1510 4710 -1150 1 GND
+rlabel metal5 3380 3700 4930 4830 1 IN
+rlabel metal1 3300 -1540 5110 -1480 1 ctrll1
+rlabel metal1 3300 -1180 5110 -1120 1 ctrll2
+rlabel metal1 3300 -640 5110 -580 1 ctrll3
+rlabel metal1 3300 -50 5110 10 1 ctrll4
+rlabel metal1 3300 860 5110 920 1 ctrll5
+<< end >>

mag/comp.out

diff --git a/mag/comp.out b/mag/comp.out
new file mode 100644
index 0000000..3a28fe9
--- /dev/null
+++ b/mag/comp.out
@@ -0,0 +1,3049 @@
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8_lvt is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8_lvt is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8_lvt     |Circuit 2: sky130_fd_pr__nfet_01v8_lvt     
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+4                                          |4                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8_lvt and sky130_fd_pr__nfet_01v8_lvt are equivalent.
+Warning: Equate pins:  cell sky130_fd_pr__res_high_po_2p85 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__res_high_po_2p85 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__res_high_po_2p85  |Circuit 2: sky130_fd_pr__res_high_po_2p85  
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__res_high_po_2p85 and sky130_fd_pr__res_high_po_2p85 are equivalent.
+Warning: Equate pins:  cell sky130_fd_pr__res_high_po_5p73 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__res_high_po_5p73 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__res_high_po_5p73  |Circuit 2: sky130_fd_pr__res_high_po_5p73  
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__res_high_po_5p73 and sky130_fd_pr__res_high_po_5p73 are equivalent.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__cap_mim_m3_1      |Circuit 2: sky130_fd_pr__cap_mim_m3_1      
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__cap_mim_m3_1 and sky130_fd_pr__cap_mim_m3_1 are equivalent.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__cap_mim_m3_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__cap_mim_m3_2      |Circuit 2: sky130_fd_pr__cap_mim_m3_2      
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__cap_mim_m3_2 and sky130_fd_pr__cap_mim_m3_2 are equivalent.
+Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8_lvt is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8_lvt is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8_lvt     |Circuit 2: sky130_fd_pr__pfet_01v8_lvt     
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+4                                          |4                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8_lvt and sky130_fd_pr__pfet_01v8_lvt are equivalent.
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_YTLFGX in circuit core_osc_amp (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_HNLS5R in circuit core_osc_amp (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_P79JE3 in circuit core_osc_amp (0)(2 instances)
+
+Class core_osc_amp (0):  Merged 45 parallel devices.
+Class core_osc_amp (1):  Merged 1 parallel devices.
+Subcircuit summary:
+Circuit 1: core_osc_amp                    |Circuit 2: core_osc_amp                    
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8_lvt (48->3)        |sky130_fd_pr__nfet_01v8_lvt (4->3)         
+sky130_fd_pr__res_high_po_2p85 (2)         |sky130_fd_pr__res_high_po_2p85 (2)         
+Number of devices: 5                       |Number of devices: 5                       
+Number of nets: 9                          |Number of nets: 9                          
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: core_osc_amp                    |Circuit 2: core_osc_amp                    
+-------------------------------------------|-------------------------------------------
+OUTB                                       |OUTB                                       
+OUTA                                       |OUTA                                       
+VDD                                        |VDD                                        
+SUB                                        |SUB                                        
+INB                                        |INB                                        
+INA                                        |INA                                        
+BIAS                                       |BIAS                                       
+GND                                        |GND                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes core_osc_amp and core_osc_amp are equivalent.
+Flattening unmatched subcell sky130_fd_pr__res_high_po_5p73_YZEQ6M in circuit buffer_amp (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_9DHFGX in circuit buffer_amp (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_648S5X in circuit buffer_amp (0)(2 instances)
+
+Class buffer_amp (0):  Merged 19 parallel devices.
+Class buffer_amp (1):  Merged 1 parallel devices.
+Subcircuit summary:
+Circuit 1: buffer_amp                      |Circuit 2: buffer_amp                      
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__res_high_po_5p73 (2)         |sky130_fd_pr__res_high_po_5p73 (2)         
+sky130_fd_pr__nfet_01v8_lvt (22->3)        |sky130_fd_pr__nfet_01v8_lvt (4->3)         
+Number of devices: 5                       |Number of devices: 5                       
+Number of nets: 9                          |Number of nets: 9                          
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: buffer_amp                      |Circuit 2: buffer_amp                      
+-------------------------------------------|-------------------------------------------
+BIAS                                       |BIAS                                       
+GND                                        |GND                                        
+INA                                        |INA                                        
+INB                                        |INB                                        
+SUB                                        |SUB                                        
+OUTA                                       |OUTA                                       
+OUTB                                       |OUTB                                       
+VDD                                        |VDD                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes buffer_amp and buffer_amp are equivalent.
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_HNLS5R in circuit amp_dec (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_MXEQGY in circuit amp_dec (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_4RCNTW in circuit amp_dec (0)(1 instance)
+
+Class amp_dec (0):  Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: amp_dec                         |Circuit 2: amp_dec                         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8_lvt (16->4)        |sky130_fd_pr__nfet_01v8_lvt (4)            
+sky130_fd_pr__res_high_po_2p85 (1)         |sky130_fd_pr__res_high_po_2p85 (1)         
+sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
+Number of devices: 6                       |Number of devices: 6                       
+Number of nets: 8                          |Number of nets: 8                          
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: amp_dec                         |Circuit 2: amp_dec                         
+-------------------------------------------|-------------------------------------------
+GND                                        |GND                                        
+IN1                                        |IN1                                        
+IN2                                        |IN2                                        
+IN3                                        |IN3                                        
+IN4                                        |IN4                                        
+VDD                                        |VDD                                        
+SUB                                        |SUB                                        
+AMP                                        |AMP                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes amp_dec and amp_dec are equivalent.
+Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_MXEQGY in circuit vop_dec (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_1_4RCNTW in circuit vop_dec (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_6BNFGK in circuit vop_dec (0)(1 instance)
+
+Class vop_dec (0):  Merged 11 parallel devices.
+Subcircuit summary:
+Circuit 1: vop_dec                         |Circuit 2: vop_dec                         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__res_high_po_2p85 (1)         |sky130_fd_pr__res_high_po_2p85 (1)         
+sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
+sky130_fd_pr__nfet_01v8_lvt (12->1)        |sky130_fd_pr__nfet_01v8_lvt (1)            
+Number of devices: 3                       |Number of devices: 3                       
+Number of nets: 5                          |Number of nets: 5                          
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: vop_dec                         |Circuit 2: vop_dec                         
+-------------------------------------------|-------------------------------------------
+VDD                                        |VDD                                        
+IN                                         |IN                                         
+VOP                                        |VOP                                        
+SUB                                        |SUB                                        
+GND                                        |GND                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes vop_dec and vop_dec are equivalent.
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_648S5X in circuit cap_bank (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_DJ7QE5 in circuit cap_bank (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_BX7S53 in circuit cap_bank (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_B6HS5D in circuit cap_bank (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_WCTBV5 in circuit cap_bank (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_WCTZRP in circuit cap_bank (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_3ZFDVT in circuit cap_bank (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_VCH7EQ in circuit cap_bank (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__cap_mim_m3_2_FJFAMD in circuit cap_bank (0)(1 instance)
+
+Class cap_bank (0):  Merged 8 parallel devices.
+Subcircuit summary:
+Circuit 1: cap_bank                        |Circuit 2: cap_bank                        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8_lvt (13->5)        |sky130_fd_pr__nfet_01v8_lvt (5)            
+sky130_fd_pr__cap_mim_m3_2 (5)             |sky130_fd_pr__cap_mim_m3_2 (5)             
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 12                         |Number of nets: 12                         
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: cap_bank                        |Circuit 2: cap_bank                        
+-------------------------------------------|-------------------------------------------
+IN                                         |IN                                         
+GND                                        |GND                                        
+ctrll5                                     |ctrll5                                     
+ctrll4                                     |ctrll4                                     
+ctrll3                                     |ctrll3                                     
+ctrll2                                     |ctrll2                                     
+ctrll1                                     |ctrll1                                     
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes cap_bank and cap_bank are equivalent.
+Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_P79JE3 in circuit output_buffer (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__res_high_po_5p73_W59YBA in circuit output_buffer (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_YTLFGX in circuit output_buffer (0)(4 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_LELFGX in circuit output_buffer (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_HNLS5R in circuit output_buffer (0)(2 instances)
+
+Class output_buffer (0):  Merged 202 parallel devices.
+Class output_buffer (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: output_buffer                   |Circuit 2: output_buffer                   
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__res_high_po_2p85 (2)         |sky130_fd_pr__res_high_po_2p85 (2)         
+sky130_fd_pr__res_high_po_5p73 (2)         |sky130_fd_pr__res_high_po_5p73 (2)         
+sky130_fd_pr__nfet_01v8_lvt (208->6)       |sky130_fd_pr__nfet_01v8_lvt (8->6)         
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 12                         |Number of nets: 12                         
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: output_buffer                   |Circuit 2: output_buffer                   
+-------------------------------------------|-------------------------------------------
+INA                                        |INA                                        
+INB                                        |INB                                        
+OUTA                                       |OUTA                                       
+OUTB                                       |OUTB                                       
+BIAS                                       |BIAS                                       
+GND                                        |GND                                        
+SUB                                        |SUB                                        
+VDD                                        |VDD                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes output_buffer and output_buffer are equivalent.
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_D3M934 in circuit bias_calc (0)(5 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_D3Z634 in circuit bias_calc (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_lvt_9DHFGX in circuit bias_calc (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_MM89SS in circuit bias_calc (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__res_high_po_2p85_P79JE3 in circuit bias_calc (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4 in circuit bias_calc (0)(2 instances)
+
+Class bias_calc (0):  Merged 167 parallel devices.
+Class bias_calc (1):  Merged 3 parallel devices.
+Subcircuit summary:
+Circuit 1: bias_calc                       |Circuit 2: bias_calc                       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_lvt (155->6)       |sky130_fd_pr__pfet_01v8_lvt (9->6)         
+sky130_fd_pr__nfet_01v8_lvt (20->2)        |sky130_fd_pr__nfet_01v8_lvt (2)            
+sky130_fd_pr__res_high_po_2p85 (2)         |sky130_fd_pr__res_high_po_2p85 (2)         
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 14                         |Number of nets: 14                         
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: bias_calc                       |Circuit 2: bias_calc                       
+-------------------------------------------|-------------------------------------------
+GND                                        |GND                                        
+SUB                                        |SUB                                        
+VOP                                        |VOP                                        
+AMP                                        |AMP                                        
+VCTRL                                      |VCTRL                                      
+PSUB                                       |PSUB                                       
+BIAS2V                                     |BIAS2V                                     
+VDD                                        |VDD                                        
+BIASOUT                                    |BIASOUT                                    
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes bias_calc and bias_calc are equivalent.
+
+Subcircuit summary:
+Circuit 1: core_osc                        |Circuit 2: core_osc                        
+-------------------------------------------|-------------------------------------------
+core_osc_amp (4)                           |core_osc_amp (4)                           
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 12                         |Number of nets: 12                         
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: core_osc                        |Circuit 2: core_osc                        
+-------------------------------------------|-------------------------------------------
+BIAS                                       |BIAS                                       
+VDD                                        |VDD                                        
+GND                                        |GND                                        
+SUB                                        |SUB                                        
+S4B                                        |S4B                                        
+S4A                                        |S4A                                        
+S2A                                        |S2A                                        
+S1A                                        |S1A                                        
+S3A                                        |S3A                                        
+S2B                                        |S2B                                        
+S1B                                        |S1B                                        
+S3B                                        |S3B                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes core_osc and core_osc are equivalent.
+
+Subcircuit summary:
+Circuit 1: buffer_amp_vop                  |Circuit 2: buffer_amp_vop                  
+-------------------------------------------|-------------------------------------------
+buffer_amp (4)                             |buffer_amp (4)                             
+amp_dec (1)                                |amp_dec (1)                                
+vop_dec (1)                                |vop_dec (1)                                
+Number of devices: 6                       |Number of devices: 6                       
+Number of nets: 19                         |Number of nets: 19                         
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: buffer_amp_vop                  |Circuit 2: buffer_amp_vop                  
+-------------------------------------------|-------------------------------------------
+OUT0                                       |OUT0                                       
+OUT180                                     |OUT180                                     
+BIAS                                       |BIAS                                       
+VDD                                        |VDD                                        
+GND                                        |GND                                        
+SUB                                        |SUB                                        
+I2A                                        |I2A                                        
+I4A                                        |I4A                                        
+I2B                                        |I2B                                        
+I4B                                        |I4B                                        
+I3A                                        |I3A                                        
+I1A                                        |I1A                                        
+I3B                                        |I3B                                        
+I1B                                        |I1B                                        
+AMP                                        |AMP                                        
+VOP                                        |VOP                                        
+(no matching pin)                          |OUT90                                      
+(no matching pin)                          |OUT270                                     
+---------------------------------------------------------------------------------------
+Cell pin lists for buffer_amp_vop and buffer_amp_vop altered to match.
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_lvt_75KH85 in circuit VCO (0)(1 instance)
+
+Class VCO (0):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: VCO                             |Circuit 2: VCO                             
+-------------------------------------------|-------------------------------------------
+cap_bank (8)                               |cap_bank (8)                               
+output_buffer (1)                          |output_buffer (1)                          
+bias_calc (1)                              |bias_calc (1)                              
+sky130_fd_pr__pfet_01v8_lvt (3->1)         |sky130_fd_pr__pfet_01v8_lvt (1)            
+core_osc (1)                               |core_osc (1)                               
+buffer_amp_vop (1)                         |buffer_amp_vop (1)                         
+Number of devices: 13                      |Number of devices: 13                      
+Number of nets: 26                         |Number of nets: 26                         
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: VCO                             |Circuit 2: VCO                             
+-------------------------------------------|-------------------------------------------
+bias_calc_0/VCTRL                          |VCTRL **Mismatch**                         
+output_buffer_0/OUTA                       |OUTA **Mismatch**                          
+output_buffer_0/OUTB                       |OUTB **Mismatch**                          
+VDD                                        |VDD                                        
+GND                                        |GND                                        
+bias_calc_0/BIAS2V                         |REF **Mismatch**                           
+CTRL1                                      |CTRL1                                      
+CTRL2                                      |CTRL2                                      
+CTRL3                                      |CTRL3                                      
+CTRL4                                      |CTRL4                                      
+CTRL5                                      |CTRL5                                      
+---------------------------------------------------------------------------------------
+Cell pin lists for VCO and VCO altered to match.
+
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[9]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[100]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[101]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[102]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[103]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[104]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[105]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[106]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[107]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[108]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[109]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[110]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[111]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[112]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[113]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[114]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[115]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[116]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[117]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[118]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[119]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[120]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[121]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[122]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[123]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[124]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[125]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[126]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[127]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[16]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[17]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[18]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[27]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[28]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[29]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[2]
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+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[37]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[38]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[39]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[40]
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+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[50]
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+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[68]
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+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[70]
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+Cell user_analog_project_wrapper (0) disconnected node: la_data_out[100]
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+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
+Flattening instances of VCO in cell user_analog_project_wrapper (0) makes a better match
+Making another compare attempt.
+
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[9]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[100]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[101]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[102]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[103]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[104]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[105]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[106]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[107]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[108]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[109]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[110]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[111]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[112]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[113]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[114]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[115]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[116]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[117]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[118]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[119]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[120]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[121]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[122]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[123]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[124]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[125]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[126]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[127]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[16]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[17]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[18]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[27]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[28]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[29]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[30]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[31]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[32]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[33]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[34]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[35]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[36]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[37]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[38]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[39]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[40]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[41]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[42]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[43]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[44]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[45]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[46]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[47]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[48]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[49]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[50]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[51]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[52]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[53]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[54]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[55]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[56]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[57]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[58]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[59]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[60]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[61]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[62]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[63]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[64]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[65]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[66]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[67]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[68]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[69]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[70]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[71]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[72]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[73]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[74]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[75]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[76]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[77]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[78]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[79]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[80]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[81]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[82]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[83]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[84]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[85]
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+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_cyc_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
+Flattening instances of core_osc in cell user_analog_project_wrapper (0) makes a better match
+Flattening instances of cap_bank in cell user_analog_project_wrapper (0) makes a better match
+Flattening instances of buffer_amp_vop in cell user_analog_project_wrapper (0) makes a better match
+Flattening instances of output_buffer in cell user_analog_project_wrapper (0) makes a better match
+Making another compare attempt.
+
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_oeb[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_out[9]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[100]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[101]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[102]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[103]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[104]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[105]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[106]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[107]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[108]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[109]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[110]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[111]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[112]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[113]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[114]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[115]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[116]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[117]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[118]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[119]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[120]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[121]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[122]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[123]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[124]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[125]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[126]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[127]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[16]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[17]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[18]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[27]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[28]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[29]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[30]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[31]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[32]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[33]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[34]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[35]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[36]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[37]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[38]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[39]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[40]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[41]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[42]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[43]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[44]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[45]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[46]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[47]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[48]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[49]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[50]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[51]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[52]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[53]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[54]
+Cell user_analog_project_wrapper (0) disconnected node: la_data_in[55]
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+Cell user_analog_project_wrapper (0) disconnected node: vssd2
+Cell user_analog_project_wrapper (0) disconnected node: wb_clk_i
+Cell user_analog_project_wrapper (0) disconnected node: wb_rst_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_ack_o
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_adr_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_cyc_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_i[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[10]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[11]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[12]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[13]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[14]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[15]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[16]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[17]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[18]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[19]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[20]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[21]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[22]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[23]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[24]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[25]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[26]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[27]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[28]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[29]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[30]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[31]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[4]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[5]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[6]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[7]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[8]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_dat_o[9]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[0]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[1]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[2]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_sel_i[3]
+Cell user_analog_project_wrapper (0) disconnected node: wbs_stb_i
+Cell user_analog_project_wrapper (0) disconnected node: wbs_we_i
+Equate pins:  cell user_analog_project_wrapper and/or ../xschem/user_analog_project_wrapper.spice has no elements.
+
+Subcircuit pins:
+Circuit 1: user_analog_project_wrapper     |Circuit 2: ../xschem/user_analog_project_w 
+-------------------------------------------|-------------------------------------------
+gpio_analog[0]                             |(no matching pin)                          
+gpio_analog[10]                            |(no matching pin)                          
+gpio_analog[11]                            |(no matching pin)                          
+gpio_analog[12]                            |(no matching pin)                          
+gpio_analog[13]                            |(no matching pin)                          
+gpio_analog[14]                            |(no matching pin)                          
+gpio_analog[15]                            |(no matching pin)                          
+gpio_analog[16]                            |(no matching pin)                          
+gpio_analog[17]                            |(no matching pin)                          
+gpio_analog[1]                             |(no matching pin)                          
+gpio_analog[2]                             |(no matching pin)                          
+gpio_analog[3]                             |(no matching pin)                          
+gpio_analog[4]                             |(no matching pin)                          
+gpio_analog[5]                             |(no matching pin)                          
+gpio_analog[6]                             |(no matching pin)                          
+gpio_analog[7]                             |(no matching pin)                          
+gpio_analog[8]                             |(no matching pin)                          
+gpio_analog[9]                             |(no matching pin)                          
+gpio_noesd[0]                              |(no matching pin)                          
+gpio_noesd[10]                             |(no matching pin)                          
+gpio_noesd[11]                             |(no matching pin)                          
+gpio_noesd[12]                             |(no matching pin)                          
+gpio_noesd[13]                             |(no matching pin)                          
+gpio_noesd[14]                             |(no matching pin)                          
+gpio_noesd[15]                             |(no matching pin)                          
+gpio_noesd[16]                             |(no matching pin)                          
+gpio_noesd[17]                             |(no matching pin)                          
+gpio_noesd[1]                              |(no matching pin)                          
+gpio_noesd[2]                              |(no matching pin)                          
+gpio_noesd[3]                              |(no matching pin)                          
+gpio_noesd[4]                              |(no matching pin)                          
+gpio_noesd[5]                              |(no matching pin)                          
+gpio_noesd[6]                              |(no matching pin)                          
+gpio_noesd[7]                              |(no matching pin)                          
+gpio_noesd[8]                              |(no matching pin)                          
+gpio_noesd[9]                              |(no matching pin)                          
+io_analog[0]                               |(no matching pin)                          
+io_analog[1]                               |(no matching pin)                          
+io_analog[2]                               |(no matching pin)                          
+io_analog[3]                               |(no matching pin)                          
+io_analog[7]                               |(no matching pin)                          
+io_analog[8]                               |(no matching pin)                          
+io_analog[9]                               |(no matching pin)                          
+io_analog[4]                               |(no matching pin)                          
+io_analog[5]                               |(no matching pin)                          
+io_analog[6]                               |(no matching pin)                          
+io_clamp_high[0]                           |(no matching pin)                          
+io_clamp_high[1]                           |(no matching pin)                          
+io_clamp_high[2]                           |(no matching pin)                          
+io_clamp_low[0]                            |(no matching pin)                          
+io_clamp_low[1]                            |(no matching pin)                          
+io_clamp_low[2]                            |(no matching pin)                          
+io_in[0]                                   |(no matching pin)                          
+io_in[10]                                  |(no matching pin)                          
+io_in[11]                                  |(no matching pin)                          
+io_in[12]                                  |(no matching pin)                          
+io_in[13]                                  |(no matching pin)                          
+io_in[14]                                  |(no matching pin)                          
+io_in[15]                                  |(no matching pin)                          
+io_in[16]                                  |(no matching pin)                          
+io_in[17]                                  |(no matching pin)                          
+io_in[18]                                  |(no matching pin)                          
+io_in[19]                                  |(no matching pin)                          
+io_in[1]                                   |(no matching pin)                          
+io_in[20]                                  |(no matching pin)                          
+io_in[21]                                  |(no matching pin)                          
+io_in[22]                                  |(no matching pin)                          
+io_in[23]                                  |(no matching pin)                          
+io_in[24]                                  |(no matching pin)                          
+io_in[25]                                  |(no matching pin)                          
+io_in[26]                                  |(no matching pin)                          
+io_in[2]                                   |(no matching pin)                          
+io_in[3]                                   |(no matching pin)                          
+io_in[4]                                   |(no matching pin)                          
+io_in[5]                                   |(no matching pin)                          
+io_in[6]                                   |(no matching pin)                          
+io_in[7]                                   |(no matching pin)                          
+io_in[8]                                   |(no matching pin)                          
+io_in[9]                                   |(no matching pin)                          
+io_in_3v3[0]                               |(no matching pin)                          
+io_in_3v3[10]                              |(no matching pin)                          
+io_in_3v3[11]                              |(no matching pin)                          
+io_in_3v3[12]                              |(no matching pin)                          
+io_in_3v3[13]                              |(no matching pin)                          
+io_in_3v3[14]                              |(no matching pin)                          
+io_in_3v3[15]                              |(no matching pin)                          
+io_in_3v3[16]                              |(no matching pin)                          
+io_in_3v3[17]                              |(no matching pin)                          
+io_in_3v3[18]                              |(no matching pin)                          
+io_in_3v3[19]                              |(no matching pin)                          
+io_in_3v3[1]                               |(no matching pin)                          
+io_in_3v3[20]                              |(no matching pin)                          
+io_in_3v3[21]                              |(no matching pin)                          
+io_in_3v3[22]                              |(no matching pin)                          
+io_in_3v3[23]                              |(no matching pin)                          
+io_in_3v3[24]                              |(no matching pin)                          
+io_in_3v3[25]                              |(no matching pin)                          
+io_in_3v3[26]                              |(no matching pin)                          
+io_in_3v3[2]                               |(no matching pin)                          
+io_in_3v3[3]                               |(no matching pin)                          
+io_in_3v3[4]                               |(no matching pin)                          
+io_in_3v3[5]                               |(no matching pin)                          
+io_in_3v3[6]                               |(no matching pin)                          
+io_in_3v3[7]                               |(no matching pin)                          
+io_in_3v3[8]                               |(no matching pin)                          
+io_in_3v3[9]                               |(no matching pin)                          
+io_oeb[0]                                  |(no matching pin)                          
+io_oeb[10]                                 |(no matching pin)                          
+io_oeb[11]                                 |(no matching pin)                          
+io_oeb[12]                                 |(no matching pin)                          
+io_oeb[13]                                 |(no matching pin)                          
+io_oeb[14]                                 |(no matching pin)                          
+io_oeb[15]                                 |(no matching pin)                          
+io_oeb[16]                                 |(no matching pin)                          
+io_oeb[17]                                 |(no matching pin)                          
+io_oeb[18]                                 |(no matching pin)                          
+io_oeb[19]                                 |(no matching pin)                          
+io_oeb[1]                                  |(no matching pin)                          
+io_oeb[20]                                 |(no matching pin)                          
+io_oeb[21]                                 |(no matching pin)                          
+io_oeb[22]                                 |(no matching pin)                          
+io_oeb[23]                                 |(no matching pin)                          
+io_oeb[24]                                 |(no matching pin)                          
+io_oeb[25]                                 |(no matching pin)                          
+io_oeb[26]                                 |(no matching pin)                          
+io_oeb[2]                                  |(no matching pin)                          
+io_oeb[3]                                  |(no matching pin)                          
+io_oeb[4]                                  |(no matching pin)                          
+io_oeb[5]                                  |(no matching pin)                          
+io_oeb[6]                                  |(no matching pin)                          
+io_oeb[7]                                  |(no matching pin)                          
+io_oeb[8]                                  |(no matching pin)                          
+io_oeb[9]                                  |(no matching pin)                          
+io_out[0]                                  |(no matching pin)                          
+io_out[10]                                 |(no matching pin)                          
+io_out[11]                                 |(no matching pin)                          
+io_out[12]                                 |(no matching pin)                          
+io_out[13]                                 |(no matching pin)                          
+io_out[14]                                 |(no matching pin)                          
+io_out[15]                                 |(no matching pin)                          
+io_out[16]                                 |(no matching pin)                          
+io_out[17]                                 |(no matching pin)                          
+io_out[18]                                 |(no matching pin)                          
+io_out[19]                                 |(no matching pin)                          
+io_out[1]                                  |(no matching pin)                          
+io_out[20]                                 |(no matching pin)                          
+io_out[21]                                 |(no matching pin)                          
+io_out[22]                                 |(no matching pin)                          
+io_out[23]                                 |(no matching pin)                          
+io_out[24]                                 |(no matching pin)                          
+io_out[25]                                 |(no matching pin)                          
+io_out[26]                                 |(no matching pin)                          
+io_out[2]                                  |(no matching pin)                          
+io_out[3]                                  |(no matching pin)                          
+io_out[4]                                  |(no matching pin)                          
+io_out[5]                                  |(no matching pin)                          
+io_out[6]                                  |(no matching pin)                          
+io_out[7]                                  |(no matching pin)                          
+io_out[8]                                  |(no matching pin)                          
+io_out[9]                                  |(no matching pin)                          
+la_data_in[0]                              |(no matching pin)                          
+la_data_in[100]                            |(no matching pin)                          
+la_data_in[101]                            |(no matching pin)                          
+la_data_in[102]                            |(no matching pin)                          
+la_data_in[103]                            |(no matching pin)                          
+la_data_in[104]                            |(no matching pin)                          
+la_data_in[105]                            |(no matching pin)                          
+la_data_in[106]                            |(no matching pin)                          
+la_data_in[107]                            |(no matching pin)                          
+la_data_in[108]                            |(no matching pin)                          
+la_data_in[109]                            |(no matching pin)                          
+la_data_in[10]                             |(no matching pin)                          
+la_data_in[110]                            |(no matching pin)                          
+la_data_in[111]                            |(no matching pin)                          
+la_data_in[112]                            |(no matching pin)                          
+la_data_in[113]                            |(no matching pin)                          
+la_data_in[114]                            |(no matching pin)                          
+la_data_in[115]                            |(no matching pin)                          
+la_data_in[116]                            |(no matching pin)                          
+la_data_in[117]                            |(no matching pin)                          
+la_data_in[118]                            |(no matching pin)                          
+la_data_in[119]                            |(no matching pin)                          
+la_data_in[11]                             |(no matching pin)                          
+la_data_in[120]                            |(no matching pin)                          
+la_data_in[121]                            |(no matching pin)                          
+la_data_in[122]                            |(no matching pin)                          
+la_data_in[123]                            |(no matching pin)                          
+la_data_in[124]                            |(no matching pin)                          
+la_data_in[125]                            |(no matching pin)                          
+la_data_in[126]                            |(no matching pin)                          
+la_data_in[127]                            |(no matching pin)                          
+la_data_in[12]                             |(no matching pin)                          
+la_data_in[13]                             |(no matching pin)                          
+la_data_in[14]                             |(no matching pin)                          
+la_data_in[15]                             |(no matching pin)                          
+la_data_in[16]                             |(no matching pin)                          
+la_data_in[17]                             |(no matching pin)                          
+la_data_in[18]                             |(no matching pin)                          
+la_data_in[19]                             |(no matching pin)                          
+la_data_in[1]                              |(no matching pin)                          
+la_data_in[20]                             |(no matching pin)                          
+la_data_in[21]                             |(no matching pin)                          
+la_data_in[22]                             |(no matching pin)                          
+la_data_in[23]                             |(no matching pin)                          
+la_data_in[24]                             |(no matching pin)                          
+la_data_in[25]                             |(no matching pin)                          
+la_data_in[26]                             |(no matching pin)                          
+la_data_in[27]                             |(no matching pin)                          
+la_data_in[28]                             |(no matching pin)                          
+la_data_in[29]                             |(no matching pin)                          
+la_data_in[2]                              |(no matching pin)                          
+la_data_in[30]                             |(no matching pin)                          
+la_data_in[31]                             |(no matching pin)                          
+la_data_in[32]                             |(no matching pin)                          
+la_data_in[33]                             |(no matching pin)                          
+la_data_in[34]                             |(no matching pin)                          
+la_data_in[35]                             |(no matching pin)                          
+la_data_in[36]                             |(no matching pin)                          
+la_data_in[37]                             |(no matching pin)                          
+la_data_in[38]                             |(no matching pin)                          
+la_data_in[39]                             |(no matching pin)                          
+la_data_in[3]                              |(no matching pin)                          
+la_data_in[40]                             |(no matching pin)                          
+la_data_in[41]                             |(no matching pin)                          
+la_data_in[42]                             |(no matching pin)                          
+la_data_in[43]                             |(no matching pin)                          
+la_data_in[44]                             |(no matching pin)                          
+la_data_in[45]                             |(no matching pin)                          
+la_data_in[46]                             |(no matching pin)                          
+la_data_in[47]                             |(no matching pin)                          
+la_data_in[48]                             |(no matching pin)                          
+la_data_in[49]                             |(no matching pin)                          
+la_data_in[4]                              |(no matching pin)                          
+la_data_in[50]                             |(no matching pin)                          
+la_data_in[51]                             |(no matching pin)                          
+la_data_in[52]                             |(no matching pin)                          
+la_data_in[53]                             |(no matching pin)                          
+la_data_in[54]                             |(no matching pin)                          
+la_data_in[55]                             |(no matching pin)                          
+la_data_in[56]                             |(no matching pin)                          
+la_data_in[57]                             |(no matching pin)                          
+la_data_in[58]                             |(no matching pin)                          
+la_data_in[59]                             |(no matching pin)                          
+la_data_in[5]                              |(no matching pin)                          
+la_data_in[60]                             |(no matching pin)                          
+la_data_in[61]                             |(no matching pin)                          
+la_data_in[62]                             |(no matching pin)                          
+la_data_in[63]                             |(no matching pin)                          
+la_data_in[64]                             |(no matching pin)                          
+la_data_in[65]                             |(no matching pin)                          
+la_data_in[66]                             |(no matching pin)                          
+la_data_in[67]                             |(no matching pin)                          
+la_data_in[68]                             |(no matching pin)                          
+la_data_in[69]                             |(no matching pin)                          
+la_data_in[6]                              |(no matching pin)                          
+la_data_in[70]                             |(no matching pin)                          
+la_data_in[71]                             |(no matching pin)                          
+la_data_in[72]                             |(no matching pin)                          
+la_data_in[73]                             |(no matching pin)                          
+la_data_in[74]                             |(no matching pin)                          
+la_data_in[75]                             |(no matching pin)                          
+la_data_in[76]                             |(no matching pin)                          
+la_data_in[77]                             |(no matching pin)                          
+la_data_in[78]                             |(no matching pin)                          
+la_data_in[79]                             |(no matching pin)                          
+la_data_in[7]                              |(no matching pin)                          
+la_data_in[80]                             |(no matching pin)                          
+la_data_in[81]                             |(no matching pin)                          
+la_data_in[82]                             |(no matching pin)                          
+la_data_in[83]                             |(no matching pin)                          
+la_data_in[84]                             |(no matching pin)                          
+la_data_in[85]                             |(no matching pin)                          
+la_data_in[86]                             |(no matching pin)                          
+la_data_in[87]                             |(no matching pin)                          
+la_data_in[88]                             |(no matching pin)                          
+la_data_in[89]                             |(no matching pin)                          
+la_data_in[8]                              |(no matching pin)                          
+la_data_in[90]                             |(no matching pin)                          
+la_data_in[91]                             |(no matching pin)                          
+la_data_in[92]                             |(no matching pin)                          
+la_data_in[93]                             |(no matching pin)                          
+la_data_in[94]                             |(no matching pin)                          
+la_data_in[95]                             |(no matching pin)                          
+la_data_in[96]                             |(no matching pin)                          
+la_data_in[97]                             |(no matching pin)                          
+la_data_in[98]                             |(no matching pin)                          
+la_data_in[99]                             |(no matching pin)                          
+la_data_in[9]                              |(no matching pin)                          
+la_data_out[0]                             |(no matching pin)                          
+la_data_out[100]                           |(no matching pin)                          
+la_data_out[101]                           |(no matching pin)                          
+la_data_out[102]                           |(no matching pin)                          
+la_data_out[103]                           |(no matching pin)                          
+la_data_out[104]                           |(no matching pin)                          
+la_data_out[105]                           |(no matching pin)                          
+la_data_out[106]                           |(no matching pin)                          
+la_data_out[107]                           |(no matching pin)                          
+la_data_out[108]                           |(no matching pin)                          
+la_data_out[109]                           |(no matching pin)                          
+la_data_out[10]                            |(no matching pin)                          
+la_data_out[110]                           |(no matching pin)                          
+la_data_out[111]                           |(no matching pin)                          
+la_data_out[112]                           |(no matching pin)                          
+la_data_out[113]                           |(no matching pin)                          
+la_data_out[114]                           |(no matching pin)                          
+la_data_out[115]                           |(no matching pin)                          
+la_data_out[116]                           |(no matching pin)                          
+la_data_out[117]                           |(no matching pin)                          
+la_data_out[118]                           |(no matching pin)                          
+la_data_out[119]                           |(no matching pin)                          
+la_data_out[11]                            |(no matching pin)                          
+la_data_out[120]                           |(no matching pin)                          
+la_data_out[121]                           |(no matching pin)                          
+la_data_out[122]                           |(no matching pin)                          
+la_data_out[123]                           |(no matching pin)                          
+la_data_out[124]                           |(no matching pin)                          
+la_data_out[125]                           |(no matching pin)                          
+la_data_out[126]                           |(no matching pin)                          
+la_data_out[127]                           |(no matching pin)                          
+la_data_out[12]                            |(no matching pin)                          
+la_data_out[13]                            |(no matching pin)                          
+la_data_out[14]                            |(no matching pin)                          
+la_data_out[15]                            |(no matching pin)                          
+la_data_out[16]                            |(no matching pin)                          
+la_data_out[17]                            |(no matching pin)                          
+la_data_out[18]                            |(no matching pin)                          
+la_data_out[19]                            |(no matching pin)                          
+la_data_out[1]                             |(no matching pin)                          
+la_data_out[20]                            |(no matching pin)                          
+la_data_out[21]                            |(no matching pin)                          
+la_data_out[22]                            |(no matching pin)                          
+la_data_out[23]                            |(no matching pin)                          
+la_data_out[24]                            |(no matching pin)                          
+la_data_out[25]                            |(no matching pin)                          
+la_data_out[26]                            |(no matching pin)                          
+la_data_out[27]                            |(no matching pin)                          
+la_data_out[28]                            |(no matching pin)                          
+la_data_out[29]                            |(no matching pin)                          
+la_data_out[2]                             |(no matching pin)                          
+la_data_out[30]                            |(no matching pin)                          
+la_data_out[31]                            |(no matching pin)                          
+la_data_out[32]                            |(no matching pin)                          
+la_data_out[33]                            |(no matching pin)                          
+la_data_out[34]                            |(no matching pin)                          
+la_data_out[35]                            |(no matching pin)                          
+la_data_out[36]                            |(no matching pin)                          
+la_data_out[37]                            |(no matching pin)                          
+la_data_out[38]                            |(no matching pin)                          
+la_data_out[39]                            |(no matching pin)                          
+la_data_out[3]                             |(no matching pin)                          
+la_data_out[40]                            |(no matching pin)                          
+la_data_out[41]                            |(no matching pin)                          
+la_data_out[42]                            |(no matching pin)                          
+la_data_out[43]                            |(no matching pin)                          
+la_data_out[44]                            |(no matching pin)                          
+la_data_out[45]                            |(no matching pin)                          
+la_data_out[46]                            |(no matching pin)                          
+la_data_out[47]                            |(no matching pin)                          
+la_data_out[48]                            |(no matching pin)                          
+la_data_out[49]                            |(no matching pin)                          
+la_data_out[4]                             |(no matching pin)                          
+la_data_out[50]                            |(no matching pin)                          
+la_data_out[51]                            |(no matching pin)                          
+la_data_out[52]                            |(no matching pin)                          
+la_data_out[53]                            |(no matching pin)                          
+la_data_out[54]                            |(no matching pin)                          
+la_data_out[55]                            |(no matching pin)                          
+la_data_out[56]                            |(no matching pin)                          
+la_data_out[57]                            |(no matching pin)                          
+la_data_out[58]                            |(no matching pin)                          
+la_data_out[59]                            |(no matching pin)                          
+la_data_out[5]                             |(no matching pin)                          
+la_data_out[60]                            |(no matching pin)                          
+la_data_out[61]                            |(no matching pin)                          
+la_data_out[62]                            |(no matching pin)                          
+la_data_out[63]                            |(no matching pin)                          
+la_data_out[64]                            |(no matching pin)                          
+la_data_out[65]                            |(no matching pin)                          
+la_data_out[66]                            |(no matching pin)                          
+la_data_out[67]                            |(no matching pin)                          
+la_data_out[68]                            |(no matching pin)                          
+la_data_out[69]                            |(no matching pin)                          
+la_data_out[6]                             |(no matching pin)                          
+la_data_out[70]                            |(no matching pin)                          
+la_data_out[71]                            |(no matching pin)                          
+la_data_out[72]                            |(no matching pin)                          
+la_data_out[73]                            |(no matching pin)                          
+la_data_out[74]                            |(no matching pin)                          
+la_data_out[75]                            |(no matching pin)                          
+la_data_out[76]                            |(no matching pin)                          
+la_data_out[77]                            |(no matching pin)                          
+la_data_out[78]                            |(no matching pin)                          
+la_data_out[79]                            |(no matching pin)                          
+la_data_out[7]                             |(no matching pin)                          
+la_data_out[80]                            |(no matching pin)                          
+la_data_out[81]                            |(no matching pin)                          
+la_data_out[82]                            |(no matching pin)                          
+la_data_out[83]                            |(no matching pin)                          
+la_data_out[84]                            |(no matching pin)                          
+la_data_out[85]                            |(no matching pin)                          
+la_data_out[86]                            |(no matching pin)                          
+la_data_out[87]                            |(no matching pin)                          
+la_data_out[88]                            |(no matching pin)                          
+la_data_out[89]                            |(no matching pin)                          
+la_data_out[8]                             |(no matching pin)                          
+la_data_out[90]                            |(no matching pin)                          
+la_data_out[91]                            |(no matching pin)                          
+la_data_out[92]                            |(no matching pin)                          
+la_data_out[93]                            |(no matching pin)                          
+la_data_out[94]                            |(no matching pin)                          
+la_data_out[95]                            |(no matching pin)                          
+la_data_out[96]                            |(no matching pin)                          
+la_data_out[97]                            |(no matching pin)                          
+la_data_out[98]                            |(no matching pin)                          
+la_data_out[99]                            |(no matching pin)                          
+la_data_out[9]                             |(no matching pin)                          
+la_oenb[0]                                 |(no matching pin)                          
+la_oenb[100]                               |(no matching pin)                          
+la_oenb[101]                               |(no matching pin)                          
+la_oenb[102]                               |(no matching pin)                          
+la_oenb[103]                               |(no matching pin)                          
+la_oenb[104]                               |(no matching pin)                          
+la_oenb[105]                               |(no matching pin)                          
+la_oenb[106]                               |(no matching pin)                          
+la_oenb[107]                               |(no matching pin)                          
+la_oenb[108]                               |(no matching pin)                          
+la_oenb[109]                               |(no matching pin)                          
+la_oenb[10]                                |(no matching pin)                          
+la_oenb[110]                               |(no matching pin)                          
+la_oenb[111]                               |(no matching pin)                          
+la_oenb[112]                               |(no matching pin)                          
+la_oenb[113]                               |(no matching pin)                          
+la_oenb[114]                               |(no matching pin)                          
+la_oenb[115]                               |(no matching pin)                          
+la_oenb[116]                               |(no matching pin)                          
+la_oenb[117]                               |(no matching pin)                          
+la_oenb[118]                               |(no matching pin)                          
+la_oenb[119]                               |(no matching pin)                          
+la_oenb[11]                                |(no matching pin)                          
+la_oenb[120]                               |(no matching pin)                          
+la_oenb[121]                               |(no matching pin)                          
+la_oenb[122]                               |(no matching pin)                          
+la_oenb[123]                               |(no matching pin)                          
+la_oenb[124]                               |(no matching pin)                          
+la_oenb[125]                               |(no matching pin)                          
+la_oenb[126]                               |(no matching pin)                          
+la_oenb[127]                               |(no matching pin)                          
+la_oenb[12]                                |(no matching pin)                          
+la_oenb[13]                                |(no matching pin)                          
+la_oenb[14]                                |(no matching pin)                          
+la_oenb[15]                                |(no matching pin)                          
+la_oenb[16]                                |(no matching pin)                          
+la_oenb[17]                                |(no matching pin)                          
+la_oenb[18]                                |(no matching pin)                          
+la_oenb[19]                                |(no matching pin)                          
+la_oenb[1]                                 |(no matching pin)                          
+la_oenb[20]                                |(no matching pin)                          
+la_oenb[21]                                |(no matching pin)                          
+la_oenb[22]                                |(no matching pin)                          
+la_oenb[23]                                |(no matching pin)                          
+la_oenb[24]                                |(no matching pin)                          
+la_oenb[25]                                |(no matching pin)                          
+la_oenb[26]                                |(no matching pin)                          
+la_oenb[27]                                |(no matching pin)                          
+la_oenb[28]                                |(no matching pin)                          
+la_oenb[29]                                |(no matching pin)                          
+la_oenb[2]                                 |(no matching pin)                          
+la_oenb[30]                                |(no matching pin)                          
+la_oenb[31]                                |(no matching pin)                          
+la_oenb[32]                                |(no matching pin)                          
+la_oenb[33]                                |(no matching pin)                          
+la_oenb[34]                                |(no matching pin)                          
+la_oenb[35]                                |(no matching pin)                          
+la_oenb[36]                                |(no matching pin)                          
+la_oenb[37]                                |(no matching pin)                          
+la_oenb[38]                                |(no matching pin)                          
+la_oenb[39]                                |(no matching pin)                          
+la_oenb[3]                                 |(no matching pin)                          
+la_oenb[40]                                |(no matching pin)                          
+la_oenb[41]                                |(no matching pin)                          
+la_oenb[42]                                |(no matching pin)                          
+la_oenb[43]                                |(no matching pin)                          
+la_oenb[44]                                |(no matching pin)                          
+la_oenb[45]                                |(no matching pin)                          
+la_oenb[46]                                |(no matching pin)                          
+la_oenb[47]                                |(no matching pin)                          
+la_oenb[48]                                |(no matching pin)                          
+la_oenb[49]                                |(no matching pin)                          
+la_oenb[4]                                 |(no matching pin)                          
+la_oenb[50]                                |(no matching pin)                          
+la_oenb[51]                                |(no matching pin)                          
+la_oenb[52]                                |(no matching pin)                          
+la_oenb[53]                                |(no matching pin)                          
+la_oenb[54]                                |(no matching pin)                          
+la_oenb[55]                                |(no matching pin)                          
+la_oenb[56]                                |(no matching pin)                          
+la_oenb[57]                                |(no matching pin)                          
+la_oenb[58]                                |(no matching pin)                          
+la_oenb[59]                                |(no matching pin)                          
+la_oenb[5]                                 |(no matching pin)                          
+la_oenb[60]                                |(no matching pin)                          
+la_oenb[61]                                |(no matching pin)                          
+la_oenb[62]                                |(no matching pin)                          
+la_oenb[63]                                |(no matching pin)                          
+la_oenb[64]                                |(no matching pin)                          
+la_oenb[65]                                |(no matching pin)                          
+la_oenb[66]                                |(no matching pin)                          
+la_oenb[67]                                |(no matching pin)                          
+la_oenb[68]                                |(no matching pin)                          
+la_oenb[69]                                |(no matching pin)                          
+la_oenb[6]                                 |(no matching pin)                          
+la_oenb[70]                                |(no matching pin)                          
+la_oenb[71]                                |(no matching pin)                          
+la_oenb[72]                                |(no matching pin)                          
+la_oenb[73]                                |(no matching pin)                          
+la_oenb[74]                                |(no matching pin)                          
+la_oenb[75]                                |(no matching pin)                          
+la_oenb[76]                                |(no matching pin)                          
+la_oenb[77]                                |(no matching pin)                          
+la_oenb[78]                                |(no matching pin)                          
+la_oenb[79]                                |(no matching pin)                          
+la_oenb[7]                                 |(no matching pin)                          
+la_oenb[80]                                |(no matching pin)                          
+la_oenb[81]                                |(no matching pin)                          
+la_oenb[82]                                |(no matching pin)                          
+la_oenb[83]                                |(no matching pin)                          
+la_oenb[84]                                |(no matching pin)                          
+la_oenb[85]                                |(no matching pin)                          
+la_oenb[86]                                |(no matching pin)                          
+la_oenb[87]                                |(no matching pin)                          
+la_oenb[88]                                |(no matching pin)                          
+la_oenb[89]                                |(no matching pin)                          
+la_oenb[8]                                 |(no matching pin)                          
+la_oenb[90]                                |(no matching pin)                          
+la_oenb[91]                                |(no matching pin)                          
+la_oenb[92]                                |(no matching pin)                          
+la_oenb[93]                                |(no matching pin)                          
+la_oenb[94]                                |(no matching pin)                          
+la_oenb[95]                                |(no matching pin)                          
+la_oenb[96]                                |(no matching pin)                          
+la_oenb[97]                                |(no matching pin)                          
+la_oenb[98]                                |(no matching pin)                          
+la_oenb[99]                                |(no matching pin)                          
+la_oenb[9]                                 |(no matching pin)                          
+user_clock2                                |(no matching pin)                          
+user_irq[0]                                |(no matching pin)                          
+user_irq[1]                                |(no matching pin)                          
+user_irq[2]                                |(no matching pin)                          
+vccd1                                      |(no matching pin)                          
+vccd2                                      |(no matching pin)                          
+vdda1                                      |(no matching pin)                          
+vdda2                                      |(no matching pin)                          
+vssa1                                      |(no matching pin)                          
+vssa2                                      |(no matching pin)                          
+vssd1                                      |(no matching pin)                          
+vssd2                                      |(no matching pin)                          
+wb_clk_i                                   |(no matching pin)                          
+wb_rst_i                                   |(no matching pin)                          
+wbs_ack_o                                  |(no matching pin)                          
+wbs_adr_i[0]                               |(no matching pin)                          
+wbs_adr_i[10]                              |(no matching pin)                          
+wbs_adr_i[11]                              |(no matching pin)                          
+wbs_adr_i[12]                              |(no matching pin)                          
+wbs_adr_i[13]                              |(no matching pin)                          
+wbs_adr_i[14]                              |(no matching pin)                          
+wbs_adr_i[15]                              |(no matching pin)                          
+wbs_adr_i[16]                              |(no matching pin)                          
+wbs_adr_i[17]                              |(no matching pin)                          
+wbs_adr_i[18]                              |(no matching pin)                          
+wbs_adr_i[19]                              |(no matching pin)                          
+wbs_adr_i[1]                               |(no matching pin)                          
+wbs_adr_i[20]                              |(no matching pin)                          
+wbs_adr_i[21]                              |(no matching pin)                          
+wbs_adr_i[22]                              |(no matching pin)                          
+wbs_adr_i[23]                              |(no matching pin)                          
+wbs_adr_i[24]                              |(no matching pin)                          
+wbs_adr_i[25]                              |(no matching pin)                          
+wbs_adr_i[26]                              |(no matching pin)                          
+wbs_adr_i[27]                              |(no matching pin)                          
+wbs_adr_i[28]                              |(no matching pin)                          
+wbs_adr_i[29]                              |(no matching pin)                          
+wbs_adr_i[2]                               |(no matching pin)                          
+wbs_adr_i[30]                              |(no matching pin)                          
+wbs_adr_i[31]                              |(no matching pin)                          
+wbs_adr_i[3]                               |(no matching pin)                          
+wbs_adr_i[4]                               |(no matching pin)                          
+wbs_adr_i[5]                               |(no matching pin)                          
+wbs_adr_i[6]                               |(no matching pin)                          
+wbs_adr_i[7]                               |(no matching pin)                          
+wbs_adr_i[8]                               |(no matching pin)                          
+wbs_adr_i[9]                               |(no matching pin)                          
+wbs_cyc_i                                  |(no matching pin)                          
+wbs_dat_i[0]                               |(no matching pin)                          
+wbs_dat_i[10]                              |(no matching pin)                          
+wbs_dat_i[11]                              |(no matching pin)                          
+wbs_dat_i[12]                              |(no matching pin)                          
+wbs_dat_i[13]                              |(no matching pin)                          
+wbs_dat_i[14]                              |(no matching pin)                          
+wbs_dat_i[15]                              |(no matching pin)                          
+wbs_dat_i[16]                              |(no matching pin)                          
+wbs_dat_i[17]                              |(no matching pin)                          
+wbs_dat_i[18]                              |(no matching pin)                          
+wbs_dat_i[19]                              |(no matching pin)                          
+wbs_dat_i[1]                               |(no matching pin)                          
+wbs_dat_i[20]                              |(no matching pin)                          
+wbs_dat_i[21]                              |(no matching pin)                          
+wbs_dat_i[22]                              |(no matching pin)                          
+wbs_dat_i[23]                              |(no matching pin)                          
+wbs_dat_i[24]                              |(no matching pin)                          
+wbs_dat_i[25]                              |(no matching pin)                          
+wbs_dat_i[26]                              |(no matching pin)                          
+wbs_dat_i[27]                              |(no matching pin)                          
+wbs_dat_i[28]                              |(no matching pin)                          
+wbs_dat_i[29]                              |(no matching pin)                          
+wbs_dat_i[2]                               |(no matching pin)                          
+wbs_dat_i[30]                              |(no matching pin)                          
+wbs_dat_i[31]                              |(no matching pin)                          
+wbs_dat_i[3]                               |(no matching pin)                          
+wbs_dat_i[4]                               |(no matching pin)                          
+wbs_dat_i[5]                               |(no matching pin)                          
+wbs_dat_i[6]                               |(no matching pin)                          
+wbs_dat_i[7]                               |(no matching pin)                          
+wbs_dat_i[8]                               |(no matching pin)                          
+wbs_dat_i[9]                               |(no matching pin)                          
+wbs_dat_o[0]                               |(no matching pin)                          
+wbs_dat_o[10]                              |(no matching pin)                          
+wbs_dat_o[11]                              |(no matching pin)                          
+wbs_dat_o[12]                              |(no matching pin)                          
+wbs_dat_o[13]                              |(no matching pin)                          
+wbs_dat_o[14]                              |(no matching pin)                          
+wbs_dat_o[15]                              |(no matching pin)                          
+wbs_dat_o[16]                              |(no matching pin)                          
+wbs_dat_o[17]                              |(no matching pin)                          
+wbs_dat_o[18]                              |(no matching pin)                          
+wbs_dat_o[19]                              |(no matching pin)                          
+wbs_dat_o[1]                               |(no matching pin)                          
+wbs_dat_o[20]                              |(no matching pin)                          
+wbs_dat_o[21]                              |(no matching pin)                          
+wbs_dat_o[22]                              |(no matching pin)                          
+wbs_dat_o[23]                              |(no matching pin)                          
+wbs_dat_o[24]                              |(no matching pin)                          
+wbs_dat_o[25]                              |(no matching pin)                          
+wbs_dat_o[26]                              |(no matching pin)                          
+wbs_dat_o[27]                              |(no matching pin)                          
+wbs_dat_o[28]                              |(no matching pin)                          
+wbs_dat_o[29]                              |(no matching pin)                          
+wbs_dat_o[2]                               |(no matching pin)                          
+wbs_dat_o[30]                              |(no matching pin)                          
+wbs_dat_o[31]                              |(no matching pin)                          
+wbs_dat_o[3]                               |(no matching pin)                          
+wbs_dat_o[4]                               |(no matching pin)                          
+wbs_dat_o[5]                               |(no matching pin)                          
+wbs_dat_o[6]                               |(no matching pin)                          
+wbs_dat_o[7]                               |(no matching pin)                          
+wbs_dat_o[8]                               |(no matching pin)                          
+wbs_dat_o[9]                               |(no matching pin)                          
+wbs_sel_i[0]                               |(no matching pin)                          
+wbs_sel_i[1]                               |(no matching pin)                          
+wbs_sel_i[2]                               |(no matching pin)                          
+wbs_sel_i[3]                               |(no matching pin)                          
+wbs_stb_i                                  |(no matching pin)                          
+wbs_we_i                                   |(no matching pin)                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes user_analog_project_wrapper and ../xschem/user_analog_project_wrapper.spice are equivalent.
+Cells failed matching, or top level cell failed pin matching.

mag/core_osc.ext

diff --git a/mag/core_osc.ext b/mag/core_osc.ext
new file mode 100644
index 0000000..959b026
--- /dev/null
+++ b/mag/core_osc.ext
@@ -0,0 +1,963 @@
+timestamp 1662665761
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use core_osc_amp X4 -1 0 18162 0 -1 12340
+use core_osc_amp X3 -1 0 18162 0 1 3195
+use core_osc_amp X2 -1 0 14762 0 1 3195
+use core_osc_amp X1 -1 0 14762 0 -1 12340
+node "m3_12355_3530#" 1 562.393 12355 3530 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 213200 4520 0 0 0 0 0 0
+node "m3_12355_3940#" 1 156.226 12355 3940 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76050 2470 0 0 0 0 0 0
+node "m3_12355_4075#" 0 417.75 12355 4075 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 193050 2670 0 0 0 0 0 0
+node "m3_12350_11295#" 0 575.73 12350 11295 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 357000 2980 0 0 0 0 0 0
+node "m3_12355_11705#" 0 257.293 12355 11705 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 1440 0 0 0 0 0 0
+node "m2_12350_3425#" 2 554.254 12350 3425 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 96375 2720 0 0 0 0 0 0 0 0
+node "S2B" 9 1779.34 9175 7265 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 635625 13140 100500 2410 0 0 0 0 0 0
+node "S2A" 9 803.179 9180 7395 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 671500 13720 70500 1610 0 0 0 0 0 0
+node "S1A" 9 1162.84 9185 7785 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 663900 13670 103200 2740 0 0 0 0 0 0
+node "S1B" 9 1284.67 9185 7915 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 665100 13700 104400 2770 0 0 0 0 0 0
+node "S3A" 9 862.772 9185 7525 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 664700 13690 103600 2750 0 0 0 0 0 0
+node "S3B" 9 1058.04 9185 7655 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 662300 13770 105200 2790 0 0 0 0 0 0
+node "S4A" 9 1447.21 9185 8045 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 676000 13720 69500 1590 0 0 0 0 0 0
+node "S4B" 9 2672.78 9185 8175 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 636500 13130 104500 2490 0 0 0 0 0 0
+node "GND" 15 1806.38 15810 11390 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 480325 14910 26400 1000 0 0 0 0 0 0
+node "VDD" 16 726.332 15910 3685 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 532300 16490 39150 1440 0 0 0 0 0 0
+node "BIAS" 18 2224.46 15730 3425 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 607650 18650 0 0 0 0 0 0 0 0
+node "m2_12280_12036#" 4 901.625 12280 12036 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 160125 4420 0 0 0 0 0 0 0 0
+node "li_12290_4230#" 139 181.204 12290 4230 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13300 830 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_12290_6840#" 139 181.204 12290 6840 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13300 830 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_14750_7140#" 402 547.35 14750 7140 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50200 2590 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_13575_7140#" 402 547.35 13575 7140 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50200 2590 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_11345_7140#" 402 546.795 11345 7140 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50200 2590 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_10175_7140#" 402 546.795 10175 7140 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50200 2590 0 0 0 0 0 0 0 0 0 0 0 0
+node "SUB" 139 181.204 12290 8660 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13300 830 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_12290_11270#" 139 181.204 12290 11270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13300 830 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "S2B" 60.1538
+cap "S1A" "S3B" 8762.77
+cap "S2B" "li_11345_7140#" 32.5038
+cap "S3A" "S4B" 636.8
+cap "S1A" "S2B" 786.258
+cap "li_12290_11270#" "m3_12350_11295#" 103.617
+cap "li_10175_7140#" "S4A" 30.9223
+cap "GND" "BIAS" 2225.55
+cap "GND" "S1B" 60.1538
+cap "li_14750_7140#" "S3B" 27.9467
+cap "li_10175_7140#" "S3A" 26.7961
+cap "S1B" "li_11345_7140#" 29.9989
+cap "S1A" "BIAS" 15.0385
+cap "li_14750_7140#" "S2B" 33.9122
+cap "li_13575_7140#" "S2A" 25.8554
+cap "S1A" "S1B" 8841.26
+cap "S1B" "li_14750_7140#" 30.0225
+cap "S2A" "S3B" 1711.39
+cap "li_13575_7140#" "S4B" 39.7011
+cap "S2A" "S2B" 8502.34
+cap "VDD" "S3B" 23.697
+cap "VDD" "S2B" 23.697
+cap "S2A" "BIAS" 15.0385
+cap "S1B" "S2A" 715.64
+cap "S1A" "GND" 60.1538
+cap "VDD" "BIAS" 10654.7
+cap "S1B" "VDD" 23.697
+cap "S3B" "S4B" 808.692
+cap "S1A" "li_11345_7140#" 28.9965
+cap "S4A" "S3A" 886.699
+cap "S2B" "S4B" 291.802
+cap "li_10175_7140#" "S3B" 27.9231
+cap "BIAS" "S4B" 15.0385
+cap "S1A" "li_14750_7140#" 29.0201
+cap "li_10175_7140#" "S2B" 32.5038
+cap "S1B" "S4B" 1709.72
+cap "li_12290_4230#" "m3_12355_4075#" 102.046
+cap "S1B" "li_10175_7140#" 29.9989
+cap "GND" "S2A" 64.9579
+cap "m3_12355_11705#" "m3_12350_11295#" 214.582
+cap "S2A" "li_11345_7140#" 25.8318
+cap "GND" "VDD" 8282.65
+cap "li_13575_7140#" "S4A" 30.9425
+cap "S1A" "S2A" 1004.66
+cap "li_13575_7140#" "S3A" 26.8197
+cap "S1A" "VDD" 23.697
+cap "S2A" "li_14750_7140#" 25.7441
+cap "GND" "S4B" 60.1538
+cap "S3B" "S4A" 1017.62
+cap "li_11345_7140#" "S4B" 39.6774
+cap "m3_12355_3530#" "m3_12355_4075#" 325.119
+cap "S2B" "S4A" 362.538
+cap "S3B" "S3A" 8835.27
+cap "S1A" "S4B" 974.233
+cap "m3_12355_4075#" "m3_12355_3940#" 939.343
+cap "S2B" "S3A" 1665.72
+cap "li_10175_7140#" "li_11345_7140#" 31.0973
+cap "BIAS" "S4A" 15.0385
+cap "S1A" "li_10175_7140#" 28.9965
+cap "li_14750_7140#" "S4B" 39.7011
+cap "S1B" "S4A" 8666.2
+cap "BIAS" "S3A" 17.7877
+cap "S2A" "VDD" 28.1941
+cap "S1B" "S3A" 1086
+cap "m3_12355_3530#" "m3_12355_3940#" 674.138
+cap "S2A" "S4B" 363.112
+cap "li_13575_7140#" "S3B" 27.9467
+cap "VDD" "S4B" 23.697
+cap "li_13575_7140#" "S2B" 32.5275
+cap "S2A" "li_10175_7140#" 25.8318
+cap "GND" "S4A" 60.1538
+cap "li_11345_7140#" "S4A" 30.9189
+cap "li_13575_7140#" "S1B" 30.0225
+cap "GND" "S3A" 63.3972
+cap "S1A" "S4A" 1704.7
+cap "li_11345_7140#" "S3A" 26.7961
+cap "S3B" "S2B" 962.828
+cap "S1A" "S3A" 1800.16
+cap "li_14750_7140#" "S4A" 30.9425
+cap "li_10175_7140#" "S4B" 40.8972
+cap "BIAS" "S3B" 15.0385
+cap "li_14750_7140#" "S3A" 26.8197
+cap "S1B" "S3B" 1806.23
+cap "BIAS" "S2B" 15.0385
+cap "S1B" "S2B" 666.306
+cap "S1B" "BIAS" 15.0385
+cap "S2A" "S4A" 467.423
+cap "m2_12280_12036#" "BIAS" 2.19197
+cap "VDD" "S4A" 23.697
+cap "S2A" "S3A" 8656.21
+cap "S1A" "li_13575_7140#" 29.0201
+cap "VDD" "S3A" 26.6666
+cap "li_13575_7140#" "li_14750_7140#" 30.9604
+cap "GND" "S3B" 60.1538
+cap "S3B" "li_11345_7140#" 27.9231
+cap "S4A" "S4B" 8530.78
+cap "X3/VDD" "X3/GND" -35.8973
+cap "X2/BIAS" "X3/GND" 76.0032
+cap "X3/GND" "X2/XM4/a_927_n100#" 5.21705
+cap "X3/VDD" "X2/BIAS" 52.0438
+cap "X3/VDD" "X2/XM4/a_927_n100#" 2.16497
+cap "X3/XR17/a_n415_n1322#" "X3/GND" 9.0081
+cap "X3/VDD" "X3/XR17/a_n415_n1322#" 51.6066
+cap "X2/BIAS" "X3/XR17/a_n415_n1322#" 5.2985
+cap "X3/XR17/a_n415_n1322#" "X2/XM4/a_927_n100#" 1.00563
+cap "X3/XR17/a_n415_n1322#" "X3/GND" -76.9881
+cap "X3/VDD" "X3/GND" 740.481
+cap "X3/XR17/a_n415_n1322#" "X3/BIAS" 4.05617
+cap "X3/VDD" "X3/BIAS" 791.605
+cap "X3/VDD" "X3/XM4/a_927_n100#" 2.16397
+cap "X3/XR17/a_n415_n1322#" "X3/XM4/a_927_n100#" 1.00422
+cap "X3/XR17/a_n415_n1322#" "X3/VDD" 115.764
+cap "X2/XM4/a_927_n100#" "X3/XR17/a_n415_n1322#" 1.00563
+cap "X2/XM4/a_927_n100#" "X3/VDD" 2.16497
+cap "X3/BIAS" "X3/SUB" 5.67679
+cap "X3/GND" "X3/VDD" 5.57248
+cap "X3/BIAS" "X3/XM4/a_927_n100#" 26.1549
+cap "X3/SUB" "X3/XM4/a_927_n100#" 1.00422
+cap "X3/BIAS" "X3/GND" 113.713
+cap "X3/GND" "X3/SUB" 554.306
+cap "X3/GND" "X3/XM4/a_927_n100#" 3.82756
+cap "X3/BIAS" "X3/VDD" 101.564
+cap "X3/VDD" "X3/SUB" 9.26947
+cap "X3/VDD" "X3/XM4/a_927_n100#" 5.7235
+cap "X3/XM4/a_927_n100#" "X3/BIAS" 3.33749
+cap "X3/GND" "X3/BIAS" 25.3102
+cap "X3/VDD" "X3/BIAS" 149.978
+cap "X3/XM4/a_927_n100#" "X3/GND" 3.82756
+cap "X3/XM4/a_927_n100#" "X3/VDD" 3.55952
+cap "X3/VDD" "X3/GND" 69.4296
+cap "X3/SUB" "X3/GND" 1745.28
+cap "X3/VDD" "X3/SUB" -4.69306
+cap "X2/INB" "X2/XM4/a_831_n100#" 2.4172
+cap "X2/BIAS" "X2/OUTA" 1.20184
+cap "X2/INA" "X2/XM4/a_831_n100#" 1.25321
+cap "X2/XM4/a_927_n100#" "S3A" 2.77071
+cap "S3A" "X2/XM4/a_831_n100#" 2.81593
+cap "X2/XM4/a_927_n100#" "X2/OUTA" 3.03842
+cap "X2/BIAS" "S3B" 0.990709
+cap "X2/OUTA" "X2/XM4/a_831_n100#" 4.36973
+cap "X2/BIAS" "X2/OUTB" 1.34518
+cap "X2/XM4/a_927_n100#" "S3B" 1.34607
+cap "S3B" "X2/XM4/a_831_n100#" 1.36713
+cap "X2/OUTB" "X2/XM4/a_927_n100#" 4.7142
+cap "X2/BIAS" "S3A" 1.08611
+cap "X2/OUTB" "X2/XM4/a_831_n100#" 4.846
+cap "X2/OUTA" "X2/BIAS" 1.20184
+cap "X3/GND" "X2/OUTB" 4.846
+cap "X2/XM4/a_927_n100#" "X2/OUTB" 4.7142
+cap "S3B" "X3/GND" 1.36713
+cap "S3B" "X2/XM4/a_927_n100#" 1.34607
+cap "X2/BIAS" "X2/OUTB" 1.34518
+cap "S3B" "X2/BIAS" 0.990709
+cap "S3A" "X2/XM4/a_927_n100#" 2.77071
+cap "S3A" "X3/GND" 2.81593
+cap "S3A" "X2/BIAS" 1.08611
+cap "X3/XR17/a_n415_n1322#" "X3/GND" 19.7666
+cap "X2/XM4/a_927_n100#" "X3/XR17/a_n415_n1322#" 2.34648
+cap "X2/XM4/a_927_n100#" "X3/GND" 2.00168
+cap "X3/XR17/a_n415_n1322#" "X2/BIAS" 4.80473
+cap "X2/INA" "X3/GND" 3.67041
+cap "X2/XM4/a_927_n100#" "X2/OUTA" 3.03842
+cap "X2/OUTA" "X3/GND" 4.36973
+cap "X2/XM4/a_927_n100#" "X3/XM3/a_n323_n274#" 2.34648
+cap "X3/BIAS" "X3/XM3/a_n323_n274#" 9.60287
+cap "X3/XM3/a_n323_n274#" "X3/GND" 5.35984
+cap "X3/XM4/a_927_n100#" "X3/XM3/a_n323_n274#" 2.34341
+cap "X3/XM4/a_927_n100#" "X3/GND" 8.68562
+cap "X3/VDD" "X3/BIAS" 39.7271
+cap "X3/BIAS" "X3/GND" 61.4524
+cap "X3/XM4/a_927_n100#" "X3/OUTB" 2.69213
+cap "X3/OUTA" "X3/XM4/a_927_n100#" 5.54143
+cap "X3/XM4/a_927_n100#" "X3/INB" 6.37539
+cap "X3/INA" "X3/GND" 8.73946
+cap "X3/BIAS" "X3/OUTB" 1.98142
+cap "X3/SUB" "X3/GND" 2.67815
+cap "X3/OUTA" "X3/BIAS" 2.17222
+cap "X3/BIAS" "X3/INB" 2.69037
+cap "X3/XM4/a_927_n100#" "X3/BIAS" 246.808
+cap "X3/VDD" "X3/GND" 9.71475
+cap "X3/INA" "X3/XM4/a_927_n100#" 6.07683
+cap "X3/SUB" "X3/XM4/a_927_n100#" 2.34341
+cap "X3/GND" "S1A" 2.50641
+cap "X3/INA" "X3/BIAS" 2.40369
+cap "X3/SUB" "X3/BIAS" 4.79814
+cap "X3/GND" "X3/OUTB" 2.73427
+cap "X3/OUTA" "X3/GND" 5.63185
+cap "X3/GND" "X3/INB" 6.0575
+cap "X3/VDD" "X3/XM4/a_927_n100#" 8.07738
+cap "X3/BIAS" "X3/VDD" 39.7271
+cap "X3/VDD" "X3/GND" 9.71475
+cap "X3/VDD" "X3/XM4/a_927_n100#" 8.07738
+cap "X3/BIAS" "X3/GND" 52.0182
+cap "X3/BIAS" "X3/XM4/a_927_n100#" 7.57354
+cap "X3/GND" "X3/XM4/a_927_n100#" 8.68562
+cap "S3A" "X2/XM4/a_543_n100#" 19.6153
+cap "X2/XM4/a_639_n100#" "X2/INA" 1.25723
+cap "X1/INA" "X2/XM4/a_543_n100#" 3.47233
+cap "X1/XM3/a_n129_n100#" "X2/XM4/a_543_n100#" 5.47505
+cap "S3A" "X2/XM3/a_n323_n274#" 6.64129
+cap "X2/INB" "X2/XM4/a_543_n100#" 9.01944
+cap "X2/INA" "X2/OUTB" 17.8971
+cap "X2/XM4/a_639_n100#" "X2/OUTB" 6.74397
+cap "X1/XM3/a_n129_n100#" "X2/XM3/a_n323_n274#" 3.933
+cap "X1/INB" "X2/OUTB" 24.2898
+cap "X2/XM4/a_639_n100#" "X2/OUTA" 6.05501
+cap "X2/INB" "X2/XM3/a_n323_n274#" -42.4686
+cap "X2/XM4/a_639_n100#" "S3B" 1.37193
+cap "X1/INB" "X2/OUTA" 8.24655
+cap "X2/OUTB" "X2/OUTA" 69.118
+cap "X2/XM4/a_n945_n188#" "X2/OUTB" 1.34518
+cap "S3B" "X2/OUTB" 20.773
+cap "X2/XM4/a_543_n100#" "X2/XM3/a_n323_n274#" 3.933
+cap "X2/XM4/a_n945_n188#" "X2/OUTA" 1.20184
+cap "X2/XM4/a_639_n100#" "S3A" 4.33139
+cap "X2/OUTB" "S3A" 49.6441
+cap "X1/INB" "S3A" 9.78906
+cap "X2/XM4/a_639_n100#" "X2/INB" 5.48293
+cap "X2/INA" "X2/INB" 8.03225
+cap "X1/INA" "X2/OUTB" 12.8756
+cap "X1/XM3/a_n129_n100#" "X2/OUTB" 7.68612
+cap "X2/XM4/a_n945_n188#" "S3A" 1.08611
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+cap "BIAS" "X4/XM1/a_n945_n188#" 16.2282
+cap "X4/XM3/a_n129_n100#" "X4/GND" 8.39119
+cap "X4/VDD" "X4/GND" 7.60612
+cap "X4/OUTA" "X4/GND" 33.4408
+cap "X4/VDD" "X4/XM1/a_n945_n188#" 32.0977
+cap "X4/XM3/a_n129_n100#" "BIAS" 7.31681
+cap "X4/OUTA" "BIAS" 18.0248
+cap "X4/XM1/a_n945_n188#" "X4/GND" 34.7046
+cap "X4/SUB" "X4/GND" 0.032408
+cap "X1/BIAS" "X4/XR17/a_n415_n1322#" 7.16478
+cap "X4/GND" "X4/XR17/a_n415_n1322#" 13.5455
+cap "X1/XM4/a_n989_n100#" "X4/VDD" 2.16497
+cap "X1/BIAS" "X4/GND" 91.7387
+cap "X1/XM4/a_n989_n100#" "X4/XR17/a_n415_n1322#" 1.34085
+cap "X4/XR17/a_n415_n1322#" "X4/VDD" 51.8367
+cap "X1/XM4/a_n989_n100#" "X4/GND" 5.50886
+cap "X1/BIAS" "X4/VDD" 36.9065
+cap "X4/GND" "X4/VDD" 34.033
+cap "X4/VDD" "X4/BIAS" 43.7832
+cap "X4/VDD" "X4/XM4/a_n989_n100#" 2.16397
+cap "X4/VDD" "X1/XM4/a_n989_n100#" 2.16497
+cap "X4/VDD" "X4/GND" 901.149
+cap "X4/VDD" "X4/XR17/a_n415_n1322#" 115.764
+cap "X4/BIAS" "X4/XR17/a_n415_n1322#" 5.46342
+cap "X4/XR17/a_n415_n1322#" "X4/XM4/a_n989_n100#" 1.33896
+cap "X1/XM4/a_n989_n100#" "X4/XR17/a_n415_n1322#" 1.34085
+cap "X4/GND" "X4/XR17/a_n415_n1322#" -77.2189
+cap "X4/BIAS" "X4/VDD" 89.2917
+cap "X4/SUB" "X4/XM4/a_n989_n100#" 1.33896
+cap "X4/BIAS" "X4/SUB" 7.5143
+cap "X4/GND" "X4/XM4/a_n989_n100#" 5.37331
+cap "X4/SUB" "X4/VDD" 9.26947
+cap "X4/BIAS" "X4/GND" 150.57
+cap "X4/GND" "X4/VDD" 85.0809
+cap "X4/SUB" "X4/GND" 554.976
+cap "X4/BIAS" "X4/XM4/a_n989_n100#" 76.4442
+cap "X4/VDD" "X4/XM4/a_n989_n100#" 7.161
+cap "X4/XM4/a_n989_n100#" "X4/GND" 5.37331
+cap "X4/VDD" "X4/GND" 79.9258
+cap "X4/XM4/a_n989_n100#" "X4/VDD" 4.99702
+cap "X4/GND" "X4/BIAS" 37.5488
+cap "X4/GND" "X4/SUB" 1745.28
+cap "X4/XM4/a_n989_n100#" "X4/BIAS" 4.68533
+cap "X4/VDD" "X4/BIAS" 140.867
+cap "X4/VDD" "X4/SUB" -4.69306
+cap "X4/VDD" "X1/BIAS" 14.4104
+cap "X4/VDD" "X4/GND" -51.313
+cap "X4/VDD" "X4/BIAS" 723.857
+cap "X4/VDD" "X4/BIAS" 13.6404
+cap "X4/BIAS" "X4/VDD" 16.9313
+merge "X4/VSUBS" "X1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "X1/VSUBS" "X3/VSUBS"
+merge "X3/VSUBS" "X2/VSUBS"
+merge "X2/VSUBS" "VSUBS"
+merge "X1/GND" "X4/GND" -1260.52 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2758000 -5600 -32942165 -2708 0 0 0 0 0 0
+merge "X4/GND" "m3_12350_11295#"
+merge "m3_12350_11295#" "X2/GND"
+merge "X2/GND" "GND"
+merge "GND" "X3/GND"
+merge "X3/GND" "m3_12355_3940#"
+merge "m3_12355_3940#" "m3_12355_4075#"
+merge "X1/VDD" "X4/VDD" -1561.39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3038000 -5600 -13810715 -5988 0 0 0 0 0 0
+merge "X4/VDD" "m3_12355_11705#"
+merge "m3_12355_11705#" "X2/VDD"
+merge "X2/VDD" "VDD"
+merge "VDD" "X3/VDD"
+merge "X3/VDD" "m3_12355_3530#"
+merge "X3/INA" "X2/OUTA" 1156.41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12023200 -146 -14983700 -210 0 0 0 0 0 0
+merge "X2/OUTA" "S2A"
+merge "X2/XR16/a_n415_n1322#" "li_12290_11270#" 953.663 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1972034 -2304 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_12290_11270#" "X4/SUB"
+merge "X4/SUB" "X2/XM2/a_n323_n274#"
+merge "X2/XM2/a_n323_n274#" "X1/SUB"
+merge "X1/SUB" "X4/XM3/a_n323_n274#"
+merge "X4/XM3/a_n323_n274#" "X1/XR16/a_n415_n1322#"
+merge "X1/XR16/a_n415_n1322#" "X1/XM3/a_n323_n274#"
+merge "X1/XM3/a_n323_n274#" "X4/XR17/a_n415_n1322#"
+merge "X4/XR17/a_n415_n1322#" "SUB"
+merge "SUB" "X3/XM3/a_n323_n274#"
+merge "X3/XM3/a_n323_n274#" "li_14750_7140#"
+merge "li_14750_7140#" "li_13575_7140#"
+merge "li_13575_7140#" "X3/SUB"
+merge "X3/SUB" "X2/XM3/a_n323_n274#"
+merge "X2/XM3/a_n323_n274#" "li_11345_7140#"
+merge "li_11345_7140#" "li_10175_7140#"
+merge "li_10175_7140#" "li_12290_6840#"
+merge "li_12290_6840#" "X2/SUB"
+merge "X2/SUB" "X3/XR17/a_n415_n1322#"
+merge "X3/XR17/a_n415_n1322#" "li_12290_4230#"
+merge "X3/INB" "X2/OUTB" -287.632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500 -160 5400 -210 0 0 0 0 0 0
+merge "X2/OUTB" "S2B"
+merge "X4/BIAS" "X1/BIAS" 713.753 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -317395 -11194 0 0 0 0 0 0 0 0
+merge "X1/BIAS" "m2_12280_12036#"
+merge "m2_12280_12036#" "X3/BIAS"
+merge "X3/BIAS" "BIAS"
+merge "BIAS" "X2/BIAS"
+merge "X2/BIAS" "m2_12350_3425#"
+merge "X4/OUTA" "X1/INB" 238.546 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24000 -230 230800 -800 0 0 0 0 0 0
+merge "X1/INB" "S4A"
+merge "X4/OUTB" "X1/INA" -652.787 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1194000 -2280 96000 -280 0 0 0 0 0 0
+merge "X1/INA" "S4B"
+merge "X4/INA" "X3/OUTA" 886.656 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2957100 -8774 24800 -180 0 0 0 0 0 0
+merge "X3/OUTA" "S3A"
+merge "X4/INB" "X3/OUTB" 1265.58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2986880 -6066 74400 -220 0 0 0 0 0 0
+merge "X3/OUTB" "S3B"
+merge "X1/OUTA" "X2/INA" 1961.43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6575320 -5144 12400 -170 0 0 0 0 0 0
+merge "X2/INA" "S1A"
+merge "X1/OUTB" "X2/INB" 43.1088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3767200 -7976 7600 -200 0 0 0 0 0 0
+merge "X2/INB" "S1B"

mag/core_osc.mag

diff --git a/mag/core_osc.mag b/mag/core_osc.mag
new file mode 100644
index 0000000..6fad4f8
--- /dev/null
+++ b/mag/core_osc.mag
@@ -0,0 +1,239 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662665761
+<< locali >>
+rect 12290 11270 12670 11305
+rect 12290 8660 12670 8695
+rect 10175 7140 10215 8395
+rect 11345 7140 11385 8395
+rect 13575 7140 13615 8395
+rect 14750 7140 14790 8395
+rect 12290 6840 12670 6875
+rect 12290 4230 12670 4265
+<< metal2 >>
+rect 12280 12036 14415 12111
+rect 15735 12035 16085 12110
+rect 15910 11825 15990 11835
+rect 15910 11765 15920 11825
+rect 15980 11765 15990 11825
+rect 15910 11750 15990 11765
+rect 15810 11460 15890 11470
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+rect 15810 11390 15890 11400
+rect 9185 8265 10505 8275
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+rect 9185 8175 10505 8185
+rect 10575 8145 10675 8330
+rect 11130 8275 11230 8325
+rect 13625 8320 13630 8380
+rect 13625 8315 13635 8320
+rect 14660 8370 14740 8395
+rect 13695 8315 13705 8320
+rect 13625 8305 13705 8315
+rect 14660 8310 14670 8370
+rect 14730 8310 14740 8370
+rect 14660 8305 14740 8310
+rect 10765 8265 15760 8275
+rect 10765 8185 10775 8265
+rect 10845 8185 12780 8265
+rect 12860 8185 15760 8265
+rect 10765 8175 15760 8185
+rect 9185 8140 15760 8145
+rect 9185 8055 14850 8140
+rect 14930 8055 15760 8140
+rect 9185 8045 15760 8055
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+rect 10225 7225 10305 7235
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+rect 10295 7165 10305 7225
+rect 10225 7140 10305 7165
+rect 11260 7225 11340 7235
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+rect 11330 7165 11340 7225
+rect 13755 7210 13830 7265
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+rect 14460 7355 15760 7365
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+rect 11260 7155 11340 7165
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+rect 15885 4115 15890 4175
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+rect 15925 3770 15990 11750
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+rect 15910 3700 15920 3760
+rect 15980 3700 15990 3760
+rect 15910 3685 15990 3700
+rect 16020 3500 16085 12035
+rect 12350 3425 13635 3500
+rect 15730 3425 16085 3500
+<< via2 >>
+rect 15920 11765 15980 11825
+rect 15820 11400 15880 11460
+rect 10425 8185 10495 8265
+rect 13635 8315 13695 8375
+rect 14670 8310 14730 8370
+rect 10775 8185 10845 8265
+rect 12780 8185 12860 8265
+rect 14850 8055 14930 8140
+rect 10235 7925 10295 8005
+rect 11270 7795 11330 7875
+rect 13635 7665 13695 7745
+rect 14670 7535 14730 7615
+rect 12100 7405 12190 7485
+rect 9845 7275 9925 7355
+rect 14120 7275 14180 7355
+rect 10235 7165 10295 7225
+rect 11270 7165 11330 7225
+rect 14470 7275 14530 7355
+rect 15825 4115 15885 4175
+rect 15920 3700 15980 3760
+<< metal3 >>
+rect 12355 11705 12775 12005
+rect 15735 11825 15990 11835
+rect 15735 11775 15920 11825
+rect 15910 11765 15920 11775
+rect 15980 11765 15990 11825
+rect 15910 11750 15990 11765
+rect 12350 11295 13540 11595
+rect 15710 11460 15890 11470
+rect 15710 11400 15820 11460
+rect 15880 11400 15890 11460
+rect 15710 11390 15890 11400
+rect 10225 8005 10305 8460
+rect 10415 8265 10855 8275
+rect 10415 8185 10425 8265
+rect 10495 8185 10775 8265
+rect 10845 8185 10855 8265
+rect 10415 8175 10855 8185
+rect 10225 7925 10235 8005
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+rect 9835 7355 9935 7365
+rect 9835 7275 9845 7355
+rect 9925 7275 9935 7355
+rect 9835 6790 9935 7275
+rect 10225 7225 10305 7925
+rect 10225 7165 10235 7225
+rect 10295 7165 10305 7225
+rect 10225 7155 10305 7165
+rect 11260 7875 11340 8445
+rect 12770 8265 12870 8780
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+rect 12860 8185 12870 8265
+rect 12770 8175 12870 8185
+rect 13625 8375 13705 8380
+rect 13625 8315 13635 8375
+rect 13695 8315 13705 8375
+rect 11260 7795 11270 7875
+rect 11330 7795 11340 7875
+rect 11260 7225 11340 7795
+rect 13625 7745 13705 8315
+rect 13625 7665 13635 7745
+rect 13695 7665 13705 7745
+rect 11260 7165 11270 7225
+rect 11330 7165 11340 7225
+rect 11260 7155 11340 7165
+rect 12095 7485 12195 7495
+rect 12095 7405 12100 7485
+rect 12190 7405 12195 7485
+rect 12095 6790 12195 7405
+rect 13625 7065 13705 7665
+rect 14660 8370 14740 8380
+rect 14660 8310 14670 8370
+rect 14730 8310 14740 8370
+rect 14660 7615 14740 8310
+rect 14840 8140 14940 8740
+rect 14840 8055 14850 8140
+rect 14930 8055 14940 8140
+rect 14840 8045 14940 8055
+rect 14660 7535 14670 7615
+rect 14730 7535 14740 7615
+rect 14110 7355 14540 7365
+rect 14110 7275 14120 7355
+rect 14180 7275 14470 7355
+rect 14530 7275 14540 7355
+rect 14110 7265 14540 7275
+rect 14660 7085 14740 7535
+rect 12355 4075 13525 4240
+rect 15725 4175 15890 4180
+rect 15725 4120 15825 4175
+rect 15750 4115 15825 4120
+rect 15885 4115 15890 4175
+rect 15750 4105 15890 4115
+rect 12355 3940 13525 4005
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+rect 12355 3550 12787 3810
+rect 13317 3550 13525 3810
+rect 15910 3760 15990 3770
+rect 15910 3755 15920 3760
+rect 15695 3700 15920 3755
+rect 15980 3700 15990 3760
+rect 15695 3685 15990 3700
+rect 12355 3530 13525 3550
+use core_osc_amp  X1
+timestamp 1662515374
+transform -1 0 14762 0 -1 12340
+box 2396 230 5562 4020
+use core_osc_amp  X2
+timestamp 1662515374
+transform -1 0 14762 0 1 3195
+box 2396 230 5562 4020
+use core_osc_amp  X3
+timestamp 1662515374
+transform -1 0 18162 0 1 3195
+box 2396 230 5562 4020
+use core_osc_amp  X4
+timestamp 1662515374
+transform -1 0 18162 0 -1 12340
+box 2396 230 5562 4020
+<< labels >>
+rlabel metal2 9185 8045 14850 8145 1 S4A
+rlabel metal2 9185 7915 10235 8015 1 S1B
+rlabel metal2 9185 7785 11270 7885 1 S1A
+rlabel metal2 9185 7655 13635 7755 1 S3B
+rlabel metal2 9185 7525 14670 7625 1 S3A
+rlabel metal2 9180 7395 12100 7495 1 S2A
+rlabel metal2 9175 7265 9845 7365 1 S2B
+rlabel metal2 14930 8045 15760 8145 1 S4A
+rlabel metal2 10295 7915 15760 8015 1 S1B
+rlabel metal2 11330 7785 15760 7885 1 S1A
+rlabel metal2 13695 7655 15760 7755 1 S3B
+rlabel metal2 14730 7525 15760 7625 1 S3A
+rlabel metal2 12190 7395 15760 7495 1 S2A
+rlabel metal2 14530 7265 15760 7365 1 S2B
+rlabel metal2 9185 8175 10425 8275 1 S4B
+rlabel metal2 12860 8175 15760 8275 1 S4B
+rlabel metal2 16020 3425 16085 12110 1 BIAS
+rlabel metal2 15925 3760 15990 11765 1 VDD
+rlabel metal2 15825 4175 15890 11400 1 GND
+rlabel locali 12290 8660 12670 8695 1 SUB
+<< end >>

mag/core_osc_amp.ext

diff --git a/mag/core_osc_amp.ext b/mag/core_osc_amp.ext
new file mode 100644
index 0000000..c50bb7e
--- /dev/null
+++ b/mag/core_osc_amp.ext
@@ -0,0 +1,291 @@
+timestamp 1662515374
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__res_high_po_2p85_P79JE3 XR17 1 0 5111 0 1 2358
+use sky130_fd_pr__res_high_po_2p85_P79JE3 XR16 1 0 2851 0 1 2358
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX XM4 0 1 4310 -1 0 2127
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM3 0 1 4310 -1 0 3659
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM2 0 -1 3650 -1 0 3659
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX XM1 0 -1 3650 -1 0 2127
+node "VDD" 2 3443.46 2565 1165 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 495900 4020 1442100 7340 898500 6590 0 0 0 0 0 0
+node "GND" 58 3806.79 3550 1220 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 185492 16832 169850 7400 1944000 13560 0 0 0 0 0 0
+node "BIAS" 42 4361.78 3425 1175 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 304000 14000 977625 26220 0 0 0 0 0 0 0 0
+node "INB" 4 520.692 4085 3570 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30400 1400 97125 2740 0 0 0 0 0 0 0 0
+node "m1_3550_1144#" 71 3513.16 3550 1144 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 235144 20868 233100 9900 1638375 6980 0 0 0 0 0 0
+node "INA" 4 601.026 3425 3475 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30400 1400 97125 2740 0 0 0 0 0 0 0 0
+node "m1_3640_3828#" 4 72.5393 3640 3828 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1728 508 0 0 0 0 0 0 0 0 0 0
+node "OUTB" 2 1772.59 4325 3420 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 229225 2880 272925 3160 509530 3672 0 0 0 0 0 0
+node "OUTA" 3 1884.45 2585 3140 v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 232801 3888 272925 3160 508620 3668 0 0 0 0 0 0
+node "li_4580_1035#" 46 65.615 4580 1035 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3920_1035#" 46 62.034 3920 1035 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3265_1035#" 46 68.597 3265 1035 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+node "SUB" 73 102.118 2435 2260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7000 470 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4550_3185#" 57 52.981 4550 3185 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5425 380 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3890_3185#" 66 60.4421 3890 3185 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6300 430 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3260_3185#" 46 45.9552 3260 3185 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4580_3335#" 46 24.5119 4580 3335 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3920_3335#" 46 28.1391 3920 3335 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3260_3335#" 46 28.8793 3260 3335 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_4580_3650#" 55 61.5831 4580 3650 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5250 370 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3265_3645#" 42 50.3901 3265 3645 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4025 300 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_3915_3945#" 46 60.3451 3915 3945 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4375 320 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "OUTB" "VDD" 27.3619
+cap "OUTB" "m1_3550_1144#" 662.182
+cap "li_3890_3185#" "m1_3550_1144#" 23.5106
+cap "li_4580_3335#" "li_4550_3185#" 30.4348
+cap "GND" "li_4580_1035#" 19.6371
+cap "li_3890_3185#" "li_4550_3185#" 2.04167
+cap "OUTB" "li_4580_3335#" 9.85692
+cap "li_3920_3335#" "m1_3550_1144#" 11.2009
+cap "INB" "OUTA" 40.0632
+cap "INA" "OUTA" 901.803
+cap "li_4550_3185#" "li_3260_3185#" 0.841202
+cap "INB" "BIAS" 96.5434
+cap "VDD" "OUTA" 27.3619
+cap "li_3265_3645#" "li_3260_3185#" 7.57647
+cap "INA" "BIAS" 96.5434
+cap "m1_3550_1144#" "OUTA" 2183.18
+cap "GND" "m1_3640_3828#" 56.8458
+cap "li_4580_1035#" "li_3265_1035#" 0.823529
+cap "li_4580_3335#" "li_3920_3335#" 1.83178
+cap "VDD" "BIAS" 2094.1
+cap "m1_3550_1144#" "BIAS" 6038.81
+cap "li_3890_3185#" "li_3260_3185#" 1.94059
+cap "li_3890_3185#" "li_3920_3335#" 30.4348
+cap "li_3265_3645#" "OUTA" 18.0902
+cap "OUTB" "OUTA" 93.23
+cap "li_3920_1035#" "li_4580_1035#" 1.83178
+cap "li_3260_3335#" "li_3265_3645#" 11.7091
+cap "INB" "m1_3640_3828#" 1.87254
+cap "GND" "li_3265_1035#" 38.1285
+cap "li_4580_3335#" "li_3260_3335#" 0.820084
+cap "INA" "m1_3640_3828#" 20.91
+cap "m1_3640_3828#" "m1_3550_1144#" 295.785
+cap "INB" "GND" 13.4786
+cap "GND" "INA" 13.4786
+cap "li_3260_3335#" "li_3260_3185#" 30.4348
+cap "li_3915_3945#" "li_3890_3185#" 4.82759
+cap "VDD" "GND" 2185.65
+cap "li_3260_3335#" "li_3920_3335#" 1.83178
+cap "li_4550_3185#" "li_4580_3650#" 8.13953
+cap "GND" "m1_3550_1144#" 24477.7
+cap "li_3265_3645#" "li_4580_3650#" 0.7
+cap "li_4580_3335#" "li_4580_3650#" 12.5
+cap "OUTB" "m1_3640_3828#" 2.952
+cap "li_3260_3335#" "OUTA" 11.4751
+cap "li_3915_3945#" "li_3920_3335#" 5.84348
+cap "GND" "li_3920_1035#" 12.7681
+cap "OUTB" "li_4580_3650#" 18.0978
+cap "OUTB" "GND" 251.81
+cap "INB" "INA" 187.588
+cap "m1_3640_3828#" "OUTA" 223.22
+cap "li_3920_1035#" "li_3265_1035#" 1.84906
+cap "INB" "m1_3550_1144#" 551.763
+cap "INA" "m1_3550_1144#" 597.238
+cap "VDD" "m1_3550_1144#" 195.789
+cap "GND" "OUTA" 452.084
+cap "GND" "BIAS" 6699.22
+cap "INB" "OUTB" 805.878
+cap "OUTB" "INA" 37.8519
+cap "XR17/a_n415_n1322#" "XM4/a_n897_n100#" -18.6057
+cap "XM4/a_n945_n188#" "XM4/a_n989_n100#" -453.699
+cap "XM4/a_n945_n188#" "XR17/a_n285_n1192#" 83.827
+cap "XM4/a_n989_n100#" "XR17/a_n285_n1192#" -0.477436
+cap "XR16/a_n285_760#" "XR17/a_n285_n1192#" -6.2925
+cap "XM4/a_n945_n188#" "XR17/a_n415_n1322#" 106.276
+cap "XM4/a_n989_n100#" "XR17/a_n415_n1322#" 24.5411
+cap "XM4/a_n945_n188#" "XM4/a_n897_n100#" 239.717
+cap "XR17/a_n285_n1192#" "XR17/a_n415_n1322#" 231.458
+cap "XM4/a_n989_n100#" "XM4/a_n897_n100#" -2553.11
+cap "XR17/a_n285_n1192#" "XM4/a_n897_n100#" 0.151916
+cap "XM4/a_n945_n188#" "XM4/a_n897_n100#" -253.315
+cap "XM4/a_n897_n100#" "XR17/a_n415_n1322#" -509.581
+cap "XR17/a_n285_n1192#" "XR17/a_n285_760#" -4.16793
+cap "XM4/a_n989_n100#" "XM4/a_n897_n100#" -1881.11
+cap "XM4/a_n945_n188#" "XR17/a_n285_n1192#" 99.4133
+cap "XR17/a_n285_n1192#" "XR17/a_n415_n1322#" 131.279
+cap "XM4/a_n989_n100#" "XR17/a_n285_n1192#" -0.505947
+cap "XM4/a_n897_n100#" "XR17/a_n285_n1192#" 0.129373
+cap "XM4/a_n945_n188#" "XR17/a_n415_n1322#" 158.733
+cap "XM4/a_n989_n100#" "XM4/a_n945_n188#" 129.814
+cap "XM4/a_n989_n100#" "XR17/a_n415_n1322#" 155.654
+cap "XR17/a_n285_n1192#" "XM4/a_n989_n100#" 0.038471
+cap "XR17/a_n285_760#" "XR17/a_n285_n1192#" -2.12457
+cap "XM4/a_n897_n100#" "XR17/a_n415_n1322#" 0.883117
+cap "XM4/a_n945_n188#" "XR17/a_n415_n1322#" 4.11683
+cap "XM4/a_n989_n100#" "XR17/a_n415_n1322#" 1.32468
+cap "XM4/a_n945_n188#" "XR17/a_n285_n1192#" 1.77093
+cap "XR17/a_n285_n1192#" "XR17/a_n415_n1322#" -36.4084
+cap "XM4/a_n945_n188#" "XM4/a_n897_n100#" 528.331
+cap "XM4/a_n897_n100#" "XR16/a_n285_760#" -34.8651
+cap "XM4/a_n989_n100#" "XR17/a_n415_n1322#" 89.0013
+cap "XM4/a_n945_n188#" "XR17/a_n415_n1322#" 215.633
+cap "XM4/a_n897_n100#" "XR17/a_n415_n1322#" 244.579
+cap "XM4/a_n989_n100#" "XM4/a_n945_n188#" -1460.14
+cap "XM4/a_n989_n100#" "XR16/a_n285_760#" -18.7921
+cap "XM4/a_n989_n100#" "XM4/a_n897_n100#" -8236.84
+cap "XM2/a_n177_n188#" "XM4/a_n945_n188#" 27.3588
+cap "XM4/a_n945_n188#" "XM3/a_n177_n188#" 28.8752
+cap "XM4/a_n945_n188#" "XM2/a_n177_n188#" 1.51637
+cap "XM4/a_n989_n100#" "XM4/a_n897_n100#" -5843.61
+cap "XM4/a_n945_n188#" "XR17/a_n415_n1322#" 369.764
+cap "XM4/a_n945_n188#" "XM4/a_n989_n100#" 28.0744
+cap "XM4/a_n989_n100#" "XR17/a_n285_760#" 55.7543
+cap "XM4/a_n989_n100#" "XR17/a_n415_n1322#" 403.497
+cap "XM4/a_n945_n188#" "XM4/a_n897_n100#" 302.243
+cap "XM4/a_n897_n100#" "XR17/a_n285_760#" 93.695
+cap "XM4/a_n897_n100#" "XR17/a_n415_n1322#" 258.042
+cap "XR17/a_n415_n1322#" "XM4/a_n945_n188#" 11.5862
+cap "XM4/a_n897_n100#" "XR17/a_n415_n1322#" 3.53247
+cap "XM4/a_n989_n100#" "XR17/a_n415_n1322#" 3.09091
+cap "XM4/a_n1091_n274#" "XM1/a_n897_n100#" 50.5008
+cap "XM2/a_n177_n188#" "XM3/a_n177_n188#" 28.39
+cap "XM2/a_n177_n188#" "XR17/a_n285_760#" 4.65154
+cap "XR16/a_n285_760#" "XM4/a_n989_n100#" -1164.16
+cap "XM4/a_n1091_n274#" "XR16/a_n285_760#" 259.099
+cap "XM1/a_n945_n188#" "XM4/a_n989_n100#" 33.3149
+cap "XM1/a_n945_n188#" "XM4/a_n1091_n274#" 5.98745
+cap "XM4/a_n1091_n274#" "XM1/a_n945_n188#" 9.23431
+cap "XM4/a_n945_n188#" "XM1/a_n945_n188#" 2.13648
+cap "XM4/a_n945_n188#" "XM4/a_n989_n100#" -105.963
+cap "XM4/a_n1091_n274#" "XM4/a_n989_n100#" -289.911
+cap "XR16/a_n285_760#" "XM3/a_n177_n188#" 3.00767
+cap "XM4/a_n945_n188#" "XM4/a_n1091_n274#" 1.482
+cap "XR16/a_n285_760#" "XR17/a_n285_760#" 1.70312
+cap "XM2/a_n177_n188#" "XR16/a_n285_760#" 144.513
+cap "XR16/a_n285_760#" "XM1/a_n897_n100#" -34.8651
+cap "XM2/a_n177_n188#" "XM1/a_n945_n188#" 15.0065
+cap "XM2/a_n177_n188#" "XM1/a_n945_n188#" 17.4397
+cap "XM4/a_n989_n100#" "XM3/a_n177_n188#" -556.552
+cap "XM4/a_n989_n100#" "XR17/a_n285_760#" -1608.6
+cap "XM4/a_n1091_n274#" "XM3/a_n177_n188#" 6.16017
+cap "XM2/a_n177_n188#" "XM4/a_n989_n100#" 91.3371
+cap "XM4/a_n1091_n274#" "XR17/a_n285_760#" 8.0551
+cap "XM2/a_n177_n188#" "XM4/a_n1091_n274#" 123.265
+cap "XM1/a_n945_n188#" "XM1/a_n897_n100#" 22.3751
+cap "XM1/a_n897_n100#" "XM4/a_n989_n100#" -260.897
+cap "XR16/a_n285_760#" "XR16/a_n285_n1192#" -6.2925
+cap "XR16/a_n285_760#" "XR17/a_n285_760#" 1.70312
+cap "XM2/a_n177_n188#" "XR17/a_n285_760#" 7.82703
+cap "XM4/a_n1091_n274#" "XR17/a_n285_760#" 248.868
+cap "XM4/a_n945_n188#" "XM4/a_n989_n100#" 38.3784
+cap "XM4/a_n945_n188#" "XM3/a_n177_n188#" 22.3096
+cap "XM4/a_n1091_n274#" "XM4/a_n897_n100#" 50.8347
+cap "XM4/a_n1091_n274#" "XM1/a_n945_n188#" 17.1786
+cap "XM1/a_n945_n188#" "XM2/a_n177_n188#" 4.86988
+cap "XM4/a_n945_n188#" "XM3/a_n177_n188#" 15.0065
+cap "XM4/a_n1091_n274#" "XR16/a_n285_760#" 21.6607
+cap "XR16/a_n285_760#" "XM2/a_n177_n188#" -11.4596
+cap "XM4/a_n1091_n274#" "XM2/a_n177_n188#" -103.206
+cap "XM3/a_n177_n188#" "XM4/a_n989_n100#" 150.121
+cap "XM4/a_n989_n100#" "XR17/a_n285_760#" 561.143
+cap "XM4/a_n945_n188#" "XM4/a_n897_n100#" 15.5215
+cap "XM4/a_n945_n188#" "XM1/a_n945_n188#" 6.2356
+cap "XM3/a_n177_n188#" "XR17/a_n285_760#" 149.124
+cap "XM1/a_n945_n188#" "XM1/a_n897_n100#" -0.572981
+cap "XM4/a_n1091_n274#" "XM4/a_n945_n188#" 19.0426
+cap "XM4/a_n897_n100#" "XM4/a_n989_n100#" -195.641
+cap "XM1/a_n945_n188#" "XM4/a_n989_n100#" -30.6469
+cap "XM4/a_n1091_n274#" "XM4/a_n945_n188#" 5.98745
+cap "XR16/a_n285_760#" "XM4/a_n989_n100#" 0.294604
+cap "XM4/a_n1091_n274#" "XM4/a_n989_n100#" 279.439
+cap "XM2/a_n177_n188#" "XM4/a_n989_n100#" -75.7322
+cap "XR17/a_n285_760#" "XR17/a_n285_n1192#" -4.16793
+cap "XM4/a_n897_n100#" "XR17/a_n285_760#" 93.695
+cap "XM3/a_n177_n188#" "XM2/a_n177_n188#" 56.0087
+cap "XR16/a_n285_760#" "XM3/a_n177_n188#" 3.00767
+cap "XM4/a_n1091_n274#" "XM3/a_n177_n188#" 172.353
+cap "XM4/a_n1091_n274#" "XM4/a_n989_n100#" 0.883117
+cap "XM4/a_n1091_n274#" "XM4/a_n945_n188#" 0.445455
+cap "XM4/a_n1091_n274#" "XM3/a_n177_n188#" 1.61485
+cap "XR17/a_n285_760#" "XR17/a_n285_n1192#" -2.12457
+cap "XR17/a_n285_760#" "XM2/a_n221_n100#" -1.50884
+cap "XR17/a_n285_760#" "XM4/a_n989_n100#" 0.176919
+cap "XR17/a_n285_760#" "XM4/a_n1091_n274#" 7.76504
+cap "XR17/a_n285_760#" "XM3/a_n177_n188#" -1.05397
+merge "XM2/a_63_n100#" "XM2/a_n129_n100#" -18599.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -38273723 -18860 0 0 0 0 0 0 0 0 0 0
+merge "XM2/a_n129_n100#" "XM3/a_63_n100#"
+merge "XM3/a_63_n100#" "XM3/a_n129_n100#"
+merge "XM3/a_n129_n100#" "XM1/a_927_n100#"
+merge "XM1/a_927_n100#" "XM1/a_735_n100#"
+merge "XM1/a_735_n100#" "XM1/a_543_n100#"
+merge "XM1/a_543_n100#" "XM1/a_351_n100#"
+merge "XM1/a_351_n100#" "XM1/a_159_n100#"
+merge "XM1/a_159_n100#" "XM1/a_n33_n100#"
+merge "XM1/a_n33_n100#" "XM1/a_n225_n100#"
+merge "XM1/a_n225_n100#" "XM1/a_n417_n100#"
+merge "XM1/a_n417_n100#" "XM1/a_n609_n100#"
+merge "XM1/a_n609_n100#" "XM1/a_n801_n100#"
+merge "XM1/a_n801_n100#" "XM1/a_n989_n100#"
+merge "XM1/a_n989_n100#" "XM4/a_927_n100#"
+merge "XM4/a_927_n100#" "XM4/a_735_n100#"
+merge "XM4/a_735_n100#" "XM4/a_543_n100#"
+merge "XM4/a_543_n100#" "XM4/a_351_n100#"
+merge "XM4/a_351_n100#" "XM4/a_159_n100#"
+merge "XM4/a_159_n100#" "XM4/a_n33_n100#"
+merge "XM4/a_n33_n100#" "XM4/a_n225_n100#"
+merge "XM4/a_n225_n100#" "XM4/a_n417_n100#"
+merge "XM4/a_n417_n100#" "XM4/a_n609_n100#"
+merge "XM4/a_n609_n100#" "XM4/a_n801_n100#"
+merge "XM4/a_n801_n100#" "XM4/a_n989_n100#"
+merge "XM4/a_n989_n100#" "m1_3550_1144#"
+merge "XM2/a_n323_n274#" "XM3/a_n323_n274#" 1060.32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2702286 -2630 0 0 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_n323_n274#" "li_3920_3335#"
+merge "li_3920_3335#" "li_3915_3945#"
+merge "li_3915_3945#" "XM1/a_n1091_n274#"
+merge "XM1/a_n1091_n274#" "li_3265_3645#"
+merge "li_3265_3645#" "li_3260_3335#"
+merge "li_3260_3335#" "li_4580_3650#"
+merge "li_4580_3650#" "li_4580_3335#"
+merge "li_4580_3335#" "XM4/a_n1091_n274#"
+merge "XM4/a_n1091_n274#" "li_3920_1035#"
+merge "li_3920_1035#" "li_3890_3185#"
+merge "li_3890_3185#" "XR16/a_n415_n1322#"
+merge "XR16/a_n415_n1322#" "li_3265_1035#"
+merge "li_3265_1035#" "li_3260_3185#"
+merge "li_3260_3185#" "SUB"
+merge "SUB" "XR17/a_n415_n1322#"
+merge "XR17/a_n415_n1322#" "VSUBS"
+merge "VSUBS" "li_4580_1035#"
+merge "li_4580_1035#" "li_4550_3185#"
+merge "XM3/a_159_n100#" "XM3/a_n33_n100#" 8832.13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12823730 -2626 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_n33_n100#" "XM3/a_n221_n100#"
+merge "XM3/a_n221_n100#" "XR17/a_n285_760#"
+merge "XR17/a_n285_760#" "OUTB"
+merge "XM2/a_159_n100#" "XM2/a_n33_n100#" -337.354 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1369430 -4142 0 0 0 0 0 0 0 0 0 0
+merge "XM2/a_n33_n100#" "XM2/a_n221_n100#"
+merge "XM2/a_n221_n100#" "m1_3640_3828#"
+merge "m1_3640_3828#" "XR16/a_n285_760#"
+merge "XR16/a_n285_760#" "OUTA"
+merge "XM1/a_831_n100#" "XM1/a_639_n100#" -36250.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -54533340 -15272 0 0 0 0 0 0 0 0 0 0
+merge "XM1/a_639_n100#" "XM1/a_447_n100#"
+merge "XM1/a_447_n100#" "XM1/a_255_n100#"
+merge "XM1/a_255_n100#" "XM1/a_63_n100#"
+merge "XM1/a_63_n100#" "XM1/a_n129_n100#"
+merge "XM1/a_n129_n100#" "XM1/a_n321_n100#"
+merge "XM1/a_n321_n100#" "XM1/a_n513_n100#"
+merge "XM1/a_n513_n100#" "XM1/a_n705_n100#"
+merge "XM1/a_n705_n100#" "XM1/a_n897_n100#"
+merge "XM1/a_n897_n100#" "XM4/a_831_n100#"
+merge "XM4/a_831_n100#" "XM4/a_639_n100#"
+merge "XM4/a_639_n100#" "XM4/a_447_n100#"
+merge "XM4/a_447_n100#" "XM4/a_255_n100#"
+merge "XM4/a_255_n100#" "XM4/a_63_n100#"
+merge "XM4/a_63_n100#" "XM4/a_n129_n100#"
+merge "XM4/a_n129_n100#" "XM4/a_n321_n100#"
+merge "XM4/a_n321_n100#" "XM4/a_n513_n100#"
+merge "XM4/a_n513_n100#" "XM4/a_n705_n100#"
+merge "XM4/a_n705_n100#" "XM4/a_n897_n100#"
+merge "XM4/a_n897_n100#" "GND"
+merge "XR16/a_n285_n1192#" "XR17/a_n285_n1192#" -9176.73 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8660776 -3884 -8906500 0 0 0 0 0 0 0 0 0
+merge "XR17/a_n285_n1192#" "VDD"
+merge "XM3/a_n81_122#" "XM3/a_n177_n188#" 949.075 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1534280 -950 0 0 0 0 0 0 0 0 0 0
+merge "XM3/a_n177_n188#" "INB"
+merge "XM1/a_n945_n188#" "XM4/a_n945_n188#" 31905.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52393450 -10036 0 0 0 0 0 0 0 0 0 0
+merge "XM4/a_n945_n188#" "BIAS"
+merge "XM2/a_n81_122#" "XM2/a_n177_n188#" 418.146 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 552415 -950 0 0 0 0 0 0 0 0 0 0
+merge "XM2/a_n177_n188#" "INA"

mag/core_osc_amp.mag

diff --git a/mag/core_osc_amp.mag b/mag/core_osc_amp.mag
new file mode 100644
index 0000000..3c8add2
--- /dev/null
+++ b/mag/core_osc_amp.mag
@@ -0,0 +1,1468 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662515374
+<< pwell >>
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+<< locali >>
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+rect 3920 1035 4045 1070
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+<< metal1 >>
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+rect 3680 3060 3690 3125
+rect 3760 3080 3800 3125
+rect 3875 3125 4280 3155
+rect 4825 3140 4845 3300
+rect 5375 3140 5396 3530
+rect 3875 3080 4200 3125
+rect 3760 3060 4200 3080
+rect 4270 3060 4280 3125
+rect 3680 2925 4280 3060
+rect 3680 2860 3690 2925
+rect 3760 2860 4200 2925
+rect 4270 2860 4280 2925
+rect 3680 2735 4280 2860
+rect 3680 2675 3690 2735
+rect 3760 2675 4200 2735
+rect 4270 2675 4280 2735
+rect 3680 2540 4280 2675
+rect 3680 2480 3690 2540
+rect 3760 2480 4200 2540
+rect 4270 2480 4280 2540
+rect 3680 2350 4280 2480
+rect 3680 2290 3690 2350
+rect 3760 2290 4200 2350
+rect 4270 2290 4280 2350
+rect 3680 2160 4280 2290
+rect 3680 2095 3690 2160
+rect 3760 2095 4200 2160
+rect 4270 2095 4280 2160
+rect 3680 1970 4280 2095
+rect 3680 1905 3690 1970
+rect 3760 1905 4200 1970
+rect 4270 1905 4280 1970
+rect 3680 1775 4280 1905
+rect 3680 1710 3690 1775
+rect 3760 1710 4200 1775
+rect 4270 1710 4280 1775
+rect 3680 1585 4280 1710
+rect 3680 1520 3690 1585
+rect 3760 1520 4200 1585
+rect 4270 1520 4280 1585
+rect 3680 1390 4280 1520
+rect 3680 1325 3690 1390
+rect 3760 1325 4200 1390
+rect 4270 1325 4280 1390
+rect 3680 1200 4280 1325
+rect 3680 1130 3690 1200
+rect 3760 1130 4200 1200
+rect 4270 1130 4280 1200
+rect 3680 1105 4280 1130
+rect 4340 3025 4640 3140
+rect 4825 3120 5396 3140
+rect 4340 2960 4350 3025
+rect 4420 2960 4640 3025
+rect 4340 2830 4640 2960
+rect 4340 2765 4350 2830
+rect 4420 2765 4640 2830
+rect 4340 2640 4640 2765
+rect 4340 2575 4350 2640
+rect 4420 2575 4640 2640
+rect 4340 2445 4640 2575
+rect 4340 2385 4350 2445
+rect 4420 2385 4640 2445
+rect 4340 2255 4640 2385
+rect 4340 2190 4350 2255
+rect 4420 2190 4640 2255
+rect 4340 2065 4640 2190
+rect 4340 2000 4350 2065
+rect 4420 2000 4640 2065
+rect 4340 1870 4640 2000
+rect 4340 1805 4350 1870
+rect 4420 1805 4640 1870
+rect 4340 1680 4640 1805
+rect 4340 1615 4350 1680
+rect 4420 1615 4640 1680
+rect 4340 1485 4640 1615
+rect 4340 1420 4350 1485
+rect 4420 1420 4640 1485
+rect 4340 1295 4640 1420
+rect 4340 1230 4350 1295
+rect 4420 1230 4640 1295
+rect 4340 1045 4640 1230
+rect 2400 745 4640 1045
+rect 2400 695 2700 745
+rect 2400 615 5395 635
+rect 2400 610 4845 615
+rect 2400 355 2585 610
+rect 3115 355 4845 610
+rect 5375 355 5395 615
+rect 2400 335 5395 355
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX  XM1
+timestamp 1662510845
+transform 0 -1 3650 -1 0 2127
+box -1127 -310 1127 310
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM2
+timestamp 1662515274
+transform 0 -1 3650 -1 0 3659
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM3
+timestamp 1662515274
+transform 0 1 4310 -1 0 3659
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX  XM4
+timestamp 1662510845
+transform 0 1 4310 -1 0 2127
+box -1127 -310 1127 310
+use sky130_fd_pr__res_high_po_2p85_P79JE3  XR16
+timestamp 1662404926
+transform 1 0 2851 0 1 2358
+box -451 -1358 451 1358
+use sky130_fd_pr__res_high_po_2p85_P79JE3  XR17
+timestamp 1662404926
+transform 1 0 5111 0 1 2358
+box -451 -1358 451 1358
+<< labels >>
+flabel metal2 3622 4000 3622 4000 1 FreeMono 2 0 0 0 INA
+flabel metal2 4308 3992 4308 3992 1 FreeMono 2 0 0 0 INB
+flabel metal3 2466 480 2466 480 1 FreeMono 2 0 0 0 VDD
+flabel metal2 2472 260 2472 260 1 FreeMono 2 0 0 0 BIAS
+rlabel metal2 2400 230 2514 304 1 BIAS
+rlabel space 2398 336 2496 632 1 VDD
+rlabel space 2396 700 2542 1048 1 GND
+rlabel space 2430 2258 2468 2466 1 SUB
+rlabel metal2 2400 230 4535 305 0 BIAS
+rlabel metal3 2400 335 2585 635 0 VDD
+rlabel metal3 2400 695 2700 1045 0 GND
+rlabel metal2 3425 3945 3875 4020 1 INA
+rlabel metal2 4085 3945 4535 4020 1 INB
+rlabel locali 2435 2260 2470 2460 1 SUB
+rlabel metal3 2566 3552 3136 3598 1 OUTA
+rlabel metal3 4340 3530 5395 3600 1 OUTB
+<< end >>

mag/example_por.mag

diff --git a/mag/example_por.mag b/mag/example_por.mag
deleted file mode 100644
index 1b8c9ba..0000000
--- a/mag/example_por.mag
+++ /dev/null
@@ -1,603 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1620310959
-<< nwell >>
-rect 70 7344 6652 7795
-rect 7401 6799 10893 7301
-<< pwell >>
-rect 463 6569 519 6579
-rect 2635 5816 2853 6026
-<< mvpsubdiff >>
-rect 7438 7387 10856 7455
-<< mvnsubdiff >>
-rect 7467 7201 10827 7235
-<< locali >>
-rect 41 8275 183 8288
-rect 41 8190 57 8275
-rect 169 8190 183 8275
-rect 41 7451 183 8190
-rect 6891 8273 7134 8286
-rect 6891 8112 6936 8273
-rect 7117 8112 7134 8273
-rect 6891 7455 7134 8112
-rect 3043 7451 7134 7455
-rect 41 7435 7134 7451
-rect 41 7305 6927 7435
-rect 35 6388 121 7179
-rect 3043 7022 6927 7305
-rect 7110 7322 7134 7435
-rect 7110 7201 10829 7322
-rect 7110 7022 7134 7201
-rect 3043 7005 7134 7022
-rect 2907 6693 7134 6838
-rect 2907 6388 3220 6693
-rect 35 6320 3220 6388
-rect 35 6318 505 6320
-rect 35 6192 48 6318
-rect 286 6192 505 6318
-rect 35 6191 505 6192
-rect 2951 6253 3220 6320
-rect 6116 6388 7134 6693
-rect 6116 6253 10860 6388
-rect 2951 6191 10860 6253
-rect 35 6143 10860 6191
-rect 35 5813 689 6143
-rect 1006 5813 1393 6029
-rect 1778 5813 2165 6029
-rect 2550 6015 2937 6029
-rect 2550 5829 2648 6015
-rect 2840 5829 2937 6015
-rect 2550 5813 2937 5829
-rect 3322 5813 3709 6029
-rect 4094 5813 4481 6029
-rect 4866 5813 5253 6029
-rect 5638 5813 6025 6029
-rect 6410 5813 6797 6029
-rect 7182 5813 7569 6029
-rect 7954 5813 8341 6029
-rect 8726 5813 9113 6029
-rect 9498 5813 9885 6029
-rect 10656 5813 10837 6029
-rect 51 165 234 381
-rect 619 165 1006 381
-rect 1391 165 1778 381
-rect 2163 165 2550 381
-rect 2935 165 3322 381
-rect 3707 165 4094 381
-rect 4479 165 4866 381
-rect 5251 165 5638 381
-rect 6023 165 6410 381
-rect 6795 165 7182 381
-rect 7567 165 7954 381
-rect 8339 165 8726 381
-rect 9111 165 9498 381
-rect 9883 165 10270 381
-rect 10655 165 10835 381
-<< viali >>
-rect 57 8190 169 8275
-rect 6936 8112 7117 8273
-rect 9224 7854 9270 8060
-rect 7604 7754 7807 7801
-rect 9459 7754 9796 7801
-rect 10785 7683 10819 7879
-rect 6927 7022 7110 7435
-rect 7870 6775 8128 6834
-rect 48 6192 286 6318
-rect 505 6191 2951 6320
-rect 3220 6253 6116 6693
-rect 8439 6684 8506 6878
-rect 8650 6720 8853 6767
-rect 10270 6735 10316 6896
-rect 2648 5829 2840 6015
-rect 10202 5598 10340 6030
-<< metal1 >>
-rect 40 8275 7133 8286
-rect 40 8190 57 8275
-rect 169 8273 7133 8275
-rect 169 8269 6936 8273
-rect 624 8260 6936 8269
-rect 624 8201 1026 8260
-rect 169 8193 1026 8201
-rect 7117 8209 7133 8273
-rect 7284 8252 10841 8278
-rect 169 8190 6936 8193
-rect 40 8179 6936 8190
-rect 218 8110 376 8127
-rect 218 8038 436 8110
-rect 709 8082 719 8144
-rect 801 8129 818 8144
-rect 801 8085 2498 8129
-rect 2829 8085 2990 8129
-rect 801 8082 818 8085
-rect 218 8024 282 8038
-rect 218 7641 313 8024
-rect 375 7641 436 8038
-rect 521 7788 567 8040
-rect 627 7892 2821 8028
-rect 502 7653 2537 7788
-rect 218 7568 436 7641
-rect 521 7597 567 7653
-rect 709 7597 719 7606
-rect 218 7554 375 7568
-rect 218 7501 282 7554
-rect 521 7553 719 7597
-rect 709 7544 719 7553
-rect 801 7597 818 7606
-rect 2866 7597 2944 8085
-rect 2993 7658 3300 7804
-rect 801 7556 2990 7597
-rect 801 7553 2922 7556
-rect 801 7544 818 7553
-rect 3360 7501 3433 8122
-rect 3699 8082 3959 8128
-rect 3486 7636 3556 8035
-rect 218 7453 3433 7501
-rect 218 7248 282 7453
-rect 3497 7344 3556 7636
-rect 185 7121 282 7248
-rect 2382 7274 3556 7344
-rect 3699 7642 3781 8082
-rect 4283 8081 5747 8125
-rect 6083 8081 6237 8125
-rect 6910 8112 6936 8179
-rect 7117 8112 7134 8209
-rect 7284 8153 7318 8252
-rect 10802 8153 10841 8252
-rect 7284 8125 10841 8153
-rect 3988 7805 4025 8041
-rect 4109 7872 6071 8033
-rect 3966 7645 5802 7805
-rect 3699 7600 3773 7642
-rect 3699 7554 3958 7600
-rect 3988 7597 4025 7645
-rect 6126 7597 6188 8081
-rect 6249 7884 6537 8029
-rect 6249 7690 6262 7884
-rect 3699 7501 3773 7554
-rect 3988 7553 6239 7597
-rect 6612 7501 6674 8112
-rect 3699 7453 6674 7501
-rect 185 6969 263 7121
-rect 2382 7074 2452 7274
-rect 3699 7165 3773 7453
-rect 2265 7047 2275 7074
-rect 185 6573 282 6969
-rect 25 6318 301 6326
-rect 25 6192 48 6318
-rect 286 6192 301 6318
-rect 25 6185 301 6192
-rect 25 5348 133 6185
-rect 345 5944 399 7033
-rect 781 7003 2275 7047
-rect 2351 7047 2452 7074
-rect 2767 7074 3773 7165
-rect 2351 7003 2738 7047
-rect 463 6745 634 6972
-rect 2382 6952 2452 7003
-rect 721 6815 2452 6952
-rect 463 6579 2560 6745
-rect 463 6569 634 6579
-rect 505 6326 634 6569
-rect 2629 6533 2693 7003
-rect 2767 6949 2842 7074
-rect 6752 7065 6823 8044
-rect 6910 7435 7134 8112
-rect 9218 8060 9276 8072
-rect 9218 7854 9224 8060
-rect 9270 8051 9276 8060
-rect 10128 8051 10138 8053
-rect 9270 8001 10138 8051
-rect 9270 7854 9276 8001
-rect 10128 7999 10138 8001
-rect 10290 7999 10300 8053
-rect 9218 7842 9276 7854
-rect 10779 7879 10825 7891
-rect 7592 7801 8339 7807
-rect 7592 7754 7604 7801
-rect 7807 7754 8339 7801
-rect 7592 7748 8339 7754
-rect 8519 7801 9808 7807
-rect 8519 7754 9459 7801
-rect 9796 7754 9808 7801
-rect 8519 7748 9808 7754
-rect 10779 7728 10785 7879
-rect 10819 7728 10825 7879
-rect 10743 7674 10753 7728
-rect 10905 7674 10915 7728
-rect 10779 7671 10825 7674
-rect 2756 6573 2842 6949
-rect 6407 7036 6825 7065
-rect 3167 6819 6174 6842
-rect 3167 6693 4331 6819
-rect 5278 6693 6174 6819
-rect 781 6489 2275 6533
-rect 2265 6460 2275 6489
-rect 2350 6460 2360 6533
-rect 2585 6489 2739 6533
-rect 3167 6326 3220 6693
-rect 493 6320 3220 6326
-rect 493 6191 505 6320
-rect 2951 6253 3220 6320
-rect 6116 6531 6174 6693
-rect 6407 6623 6432 7036
-rect 6803 6840 6825 7036
-rect 6910 7022 6927 7435
-rect 7110 7324 7134 7435
-rect 7279 7543 10836 7570
-rect 7279 7449 7306 7543
-rect 8343 7449 8618 7543
-rect 10649 7449 10836 7543
-rect 7279 7417 10836 7449
-rect 7110 7299 10832 7324
-rect 7110 7124 7171 7299
-rect 8320 7124 8602 7299
-rect 10750 7124 10832 7299
-rect 7110 7094 10832 7124
-rect 7110 7022 7134 7094
-rect 10516 7093 10832 7094
-rect 6910 6994 7134 7022
-rect 10264 6896 10322 6908
-rect 8433 6878 8512 6890
-rect 6803 6834 8140 6840
-rect 6803 6775 7870 6834
-rect 8128 6775 8140 6834
-rect 6803 6769 8140 6775
-rect 6803 6623 6825 6769
-rect 8429 6684 8439 6878
-rect 8506 6773 8516 6878
-rect 8506 6767 8865 6773
-rect 8506 6720 8650 6767
-rect 8853 6720 8865 6767
-rect 10264 6735 10270 6896
-rect 10316 6834 10322 6896
-rect 10316 6765 10507 6834
-rect 10672 6765 10682 6834
-rect 10316 6735 10322 6765
-rect 10264 6723 10322 6735
-rect 8506 6714 8865 6720
-rect 8506 6684 8516 6714
-rect 8433 6672 8512 6684
-rect 6407 6600 6825 6623
-rect 6116 6319 10827 6531
-rect 6116 6253 6174 6319
-rect 2951 6237 6174 6253
-rect 10221 6260 10716 6270
-rect 2951 6191 6175 6237
-rect 493 6185 6175 6191
-rect 10221 6187 10233 6260
-rect 10700 6187 10716 6260
-rect 10221 6176 10716 6187
-rect 10221 6045 10315 6176
-rect 10187 6030 10353 6045
-rect 2635 6015 2853 6026
-rect 2635 5944 2648 6015
-rect 345 5890 2648 5944
-rect 2635 5829 2648 5890
-rect 2840 5829 2853 6015
-rect 2635 5816 2853 5829
-rect 10187 5598 10202 6030
-rect 10340 5598 10353 6030
-rect 10187 5582 10353 5598
-rect 10805 5348 10867 6079
-rect 25 4748 10867 5348
-rect 25 4348 133 4748
-rect 10805 4348 10867 4748
-rect 25 3748 10867 4348
-rect 25 3348 133 3748
-rect 10805 3348 10867 3748
-rect 25 2748 10867 3348
-rect 25 2348 133 2748
-rect 10805 2348 10867 2748
-rect 25 1748 10867 2348
-rect 25 1348 133 1748
-rect 10805 1348 10867 1748
-rect 25 748 10867 1348
-rect 25 99 133 748
-rect 10805 99 10867 748
-rect 25 11 10867 99
-<< via1 >>
-rect 60 8201 169 8269
-rect 169 8201 624 8269
-rect 1026 8193 6936 8260
-rect 6936 8193 7093 8260
-rect 719 8082 801 8144
-rect 719 7544 801 7606
-rect 7318 8153 10802 8252
-rect 2275 7003 2351 7074
-rect 10138 7999 10290 8053
-rect 8339 7748 8519 7807
-rect 10753 7683 10785 7728
-rect 10785 7683 10819 7728
-rect 10819 7683 10905 7728
-rect 10753 7674 10905 7683
-rect 4331 6693 5278 6819
-rect 2275 6460 2350 6533
-rect 4331 6270 5278 6693
-rect 6432 6623 6803 7036
-rect 7306 7449 8343 7543
-rect 8618 7449 10649 7543
-rect 7171 7124 8320 7299
-rect 8602 7124 10750 7299
-rect 8439 6684 8506 6878
-rect 10507 6765 10672 6834
-rect 10233 6187 10700 6260
-<< metal2 >>
-rect 985 8286 7132 8287
-rect 38 8269 7132 8286
-rect 38 8201 60 8269
-rect 624 8261 7132 8269
-rect 38 8104 77 8201
-rect 634 8187 886 8261
-rect 7091 8260 7132 8261
-rect 7093 8193 7132 8260
-rect 634 8104 654 8187
-rect 38 8061 654 8104
-rect 719 8144 801 8154
-rect 719 8072 801 8082
-rect 866 8104 886 8187
-rect 7091 8104 7132 8193
-rect 7284 8252 10841 8278
-rect 7284 8153 7318 8252
-rect 10802 8153 10841 8252
-rect 7284 8125 10841 8153
-rect 729 7616 785 8072
-rect 866 8060 7132 8104
-rect 10138 8056 10290 8066
-rect 10138 7986 10290 7996
-rect 8339 7807 8519 7817
-rect 8339 7738 8519 7748
-rect 719 7606 801 7616
-rect 719 7534 801 7544
-rect 7279 7543 8374 7570
-rect 7279 7449 7306 7543
-rect 8343 7449 8374 7543
-rect 7279 7417 8374 7449
-rect 7141 7299 8355 7324
-rect 7141 7124 7171 7299
-rect 8320 7124 8355 7299
-rect 7141 7094 8355 7124
-rect 2275 7074 2351 7084
-rect 2275 6993 2351 7003
-rect 6407 7036 6825 7065
-rect 2288 6543 2340 6993
-rect 4308 6849 5298 6868
-rect 2275 6533 2350 6543
-rect 2275 6450 2350 6460
-rect 4308 6270 4331 6849
-rect 5278 6270 5298 6849
-rect 6407 6623 6432 7036
-rect 6803 6623 6825 7036
-rect 8443 6888 8500 7738
-rect 10753 7731 10905 7741
-rect 10753 7661 10905 7671
-rect 8588 7543 10667 7570
-rect 8587 7449 8618 7543
-rect 10649 7449 10667 7543
-rect 8588 7417 10667 7449
-rect 8567 7299 10798 7324
-rect 8567 7124 8602 7299
-rect 10750 7124 10798 7299
-rect 8567 7094 10798 7124
-rect 8439 6878 8506 6888
-rect 8439 6674 8506 6684
-rect 6407 6600 6825 6623
-rect 4308 6249 5298 6270
-rect 10221 6270 10431 7094
-rect 10498 6765 10507 6834
-rect 10672 6765 10757 6834
-rect 10909 6765 10918 6834
-rect 10221 6260 10716 6270
-rect 10221 6187 10233 6260
-rect 10700 6187 10716 6260
-rect 10221 6176 10716 6187
-<< via2 >>
-rect 77 8201 624 8261
-rect 624 8201 634 8261
-rect 77 8104 634 8201
-rect 886 8260 7091 8261
-rect 886 8193 1026 8260
-rect 1026 8193 7091 8260
-rect 886 8104 7091 8193
-rect 7318 8153 10802 8252
-rect 10138 8053 10290 8056
-rect 10138 7999 10290 8053
-rect 10138 7996 10290 7999
-rect 7306 7449 8343 7543
-rect 4331 6819 5278 6849
-rect 4331 6522 5278 6819
-rect 6432 6623 6803 7036
-rect 10753 7728 10905 7731
-rect 10753 7674 10905 7728
-rect 10753 7671 10905 7674
-rect 8618 7449 10649 7543
-rect 10757 6765 10909 6834
-<< metal3 >>
-rect 38 8261 7126 8283
-rect 38 8244 77 8261
-rect 634 8244 886 8261
-rect 38 8000 73 8244
-rect 7091 8104 7126 8261
-rect 7284 8252 10841 8278
-rect 7284 8153 7318 8252
-rect 10802 8153 10841 8252
-rect 7284 8125 10841 8153
-rect 7073 8000 7126 8104
-rect 38 7965 7126 8000
-rect 10128 8056 10295 8064
-rect 10128 7996 10138 8056
-rect 10290 7996 10431 8056
-rect 10128 7991 10295 7996
-rect 10371 7916 10431 7996
-rect 10371 7856 11343 7916
-rect 10743 7731 10910 7739
-rect 10743 7671 10753 7731
-rect 10905 7671 10910 7731
-rect 10743 7666 10910 7671
-rect 7279 7543 10667 7570
-rect 7279 7449 7306 7543
-rect 10649 7449 10667 7543
-rect 10792 7551 10852 7666
-rect 10792 7491 11344 7551
-rect 7279 7417 10667 7449
-rect 4111 7277 5299 7317
-rect 4111 6849 4350 7277
-rect 5268 6849 5299 7277
-rect 4111 6522 4331 6849
-rect 5278 6522 5299 6849
-rect 6408 7036 6825 7065
-rect 6408 6623 6432 7036
-rect 6803 6623 6825 7036
-rect 10747 6834 10918 6840
-rect 10747 6765 10757 6834
-rect 10909 6765 11342 6834
-rect 10747 6758 10918 6765
-rect 6408 6600 6825 6623
-rect 4111 6494 5299 6522
-rect 4111 6251 4307 6494
-<< via3 >>
-rect 73 8104 77 8244
-rect 77 8104 634 8244
-rect 634 8104 886 8244
-rect 886 8104 7073 8244
-rect 7318 8153 10802 8252
-rect 73 8000 7073 8104
-rect 7306 7449 8343 7543
-rect 8343 7449 8618 7543
-rect 8618 7449 10649 7543
-rect 4350 6849 5268 7277
-rect 4350 6558 5268 6849
-rect 6432 6623 6803 7036
-<< metal4 >>
-rect 38 8244 7126 8283
-rect 38 8000 73 8244
-rect 7073 8000 7126 8244
-rect 38 7965 7126 8000
-rect 7241 8252 11180 8291
-rect 7241 8153 7318 8252
-rect 10802 8153 11180 8252
-rect 7241 7962 11180 8153
-rect 10843 7755 11178 7774
-rect 38 7543 10667 7655
-rect 38 7449 7306 7543
-rect 10649 7449 10667 7543
-rect 38 7277 10667 7449
-rect 38 7255 4350 7277
-rect 3817 6558 4350 7255
-rect 5268 7255 10667 7277
-rect 5268 6558 5299 7255
-rect 10843 7074 10879 7755
-rect 6386 7036 10879 7074
-rect 6386 6623 6432 7036
-rect 6803 6623 10879 7036
-rect 6386 6615 10879 6623
-rect 11146 6615 11178 7755
-rect 6386 6591 11178 6615
-rect 3817 6522 5299 6558
-rect 3817 51 4011 6522
-rect 4101 51 4793 6251
-<< via4 >>
-rect 4350 6558 5268 7247
-rect 10879 6615 11146 7755
-<< metal5 >>
-rect 10851 7755 11171 7779
-rect 4313 7247 5299 7317
-rect 4313 6558 4350 7247
-rect 5268 6558 5299 7247
-rect 4313 6494 5299 6558
-rect 4507 6135 5299 6494
-rect 10851 6615 10879 7755
-rect 11146 6615 11171 7755
-rect 10851 6242 11171 6615
-use sky130_fd_pr__nfet_g5v0d10v5_TGFUGS  sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0
-timestamp 1606063140
-transform 1 0 1515 0 1 6769
-box -962 -458 962 458
-use sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC  sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1
-timestamp 1605994897
-transform -1 0 371 0 1 6769
-box -308 -458 308 458
-use sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ  sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0
-timestamp 1606063140
-transform 1 0 1657 0 1 7841
-box -1101 -497 1101 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3
-timestamp 1606063140
-transform 1 0 408 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__nfet_g5v0d10v5_PKVMTM  sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0
-timestamp 1606063140
-transform 1 0 2660 0 1 6770
-box -308 -458 308 458
-use sky130_fd_pr__pfet_g5v0d10v5_YUHPBG  sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0
-timestamp 1606063140
-transform 1 0 2906 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0
-timestamp 1606063140
-transform 1 0 3392 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1
-timestamp 1606063140
-transform 1 0 3878 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_YEUEBV  sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0
-timestamp 1606063140
-transform 1 0 5018 0 1 7841
-box -992 -497 992 497
-use sky130_fd_pr__pfet_g5v0d10v5_YUHPXE  sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0
-timestamp 1606063140
-transform 1 0 6158 0 1 7841
-box -338 -497 338 497
-use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB  sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2
-timestamp 1606063140
-transform 1 0 6644 0 1 7841
-box -338 -497 338 497
-use sky130_fd_sc_hvl__schmittbuf_1  sky130_fd_sc_hvl__schmittbuf_1_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 7467 0 1 6404
-box -66 -43 1122 897
-use sky130_fd_sc_hvl__buf_8  sky130_fd_sc_hvl__buf_8_1 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 7477 0 1 7438
-box -66 -43 1986 897
-use sky130_fd_sc_hvl__buf_8  sky130_fd_sc_hvl__buf_8_0
-timestamp 1619722500
-transform 1 0 8523 0 1 6404
-box -66 -43 1986 897
-use sky130_fd_sc_hvl__fill_4  sky130_fd_sc_hvl__fill_4_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 10443 0 1 6404
-box -66 -43 450 897
-use sky130_fd_sc_hvl__inv_8  sky130_fd_sc_hvl__inv_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1619722500
-transform 1 0 9397 0 1 7438
-box -66 -43 1506 897
-use sky130_fd_pr__res_xhigh_po_0p69_S5N9F3  sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0
-timestamp 1606074388
-transform 1 0 5446 0 1 3098
-box -5446 -3098 5446 3098
-use sky130_fd_pr__cap_mim_m3_2_W5U4AW  sky130_fd_pr__cap_mim_m3_2_W5U4AW_0
-timestamp 1606502073
-transform 1 0 7970 0 1 3151
-box -3179 -3101 3201 3101
-use sky130_fd_pr__cap_mim_m3_1_WRT4AW  sky130_fd_pr__cap_mim_m3_1_WRT4AW_0
-timestamp 1606502073
-transform -1 0 7027 0 1 3151
-box -3136 -3100 3136 3100
-<< labels >>
-flabel metal4 s 38 7965 73 8283 0 FreeSans 320 0 0 0 vdd3v3
-port 0 nsew
-flabel metal4 s 38 7255 232 7655 0 FreeSans 320 0 0 0 vss
-port 2 nsew
-flabel metal4 s 10974 7962 11180 8291 0 FreeSans 320 0 0 0 vdd1v8
-port 1 nsew
-flabel metal3 11189 7491 11344 7551 0 FreeSans 320 0 0 0 por_l
-port 4 nsew
-flabel metal3 11188 7856 11343 7916 0 FreeSans 320 0 0 0 porb_l
-port 5 nsew
-flabel metal3 10969 6765 11342 6834 0 FreeSans 320 0 0 0 porb_h
-port 3 nsew
-<< properties >>
-string FIXED_BBOX 0 0 11344 8338
-<< end >>

mag/output_buffer.ext

diff --git a/mag/output_buffer.ext b/mag/output_buffer.ext
new file mode 100644
index 0000000..e546145
--- /dev/null
+++ b/mag/output_buffer.ext
@@ -0,0 +1,930 @@
+timestamp 1662517639
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__res_high_po_2p85_P79JE3 XR2 0 1 11380 -1 0 -807
+use sky130_fd_pr__res_high_po_5p73_W59YBA XR3 0 1 15798 -1 0 -1101
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX XM1 1 0 10847 0 -1 650
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX XM2 1 0 10847 0 1 -10
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX XM32 1 0 14687 0 1 650
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX XM33 1 0 14687 0 -1 -10
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM42 1 0 12379 0 -1 650
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R XM43 1 0 12379 0 1 -10
+use sky130_fd_pr__res_high_po_2p85_P79JE3 XR1 0 1 11383 -1 0 1451
+use sky130_fd_pr__res_high_po_5p73_W59YBA XR29 0 1 15798 -1 0 1739
+use sky130_fd_pr__nfet_01v8_lvt_LELFGX XM3 1 0 18902 0 1 650
+use sky130_fd_pr__nfet_01v8_lvt_LELFGX XM4 1 0 18902 0 1 -10
+node "OUTB" 6 3375.4 13750 -1655 v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 537075 8460 583200 6690 1428450 7620 0 0 0 0 0 0
+node "m1_12140_n1090#" 11 2170.68 12140 -1090 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 496315 12330 537000 5460 0 0 0 0 0 0 0 0
+node "INB" 6 739.208 12190 -190 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156675 5810 0 0 0 0 0 0 0 0 0 0
+node "GND" 82 11166.5 16085 -110 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 681750 33000 450000 21000 7286725 31730 0 0 0 0 0 0
+node "m1_13690_15#" 113 8586.28 13690 15 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 950463 46244 630000 29400 4805550 17470 0 0 0 0 0 0
+node "BIAS" 0 6656.92 15855 -1840 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1312720 52580 0 0 0 0 0 0 0 0 0 0
+node "GND" 18 3885.89 9945 -110 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 238500 11000 2792750 15320 0 0 0 0 0 0 0 0
+node "m1_9850_15#" 23 2496.17 9850 15 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 334250 15400 1658250 6780 0 0 0 0 0 0 0 0
+node "INA" 9 1009.68 12190 780 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 184300 7410 0 0 0 0 0 0 0 0 0 0
+node "BIAS" 25 2648.88 9900 -190 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 500500 20120 0 0 0 0 0 0 0 0 0 0
+node "OUTA" 6 3731.37 13740 1190 v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 527950 8440 586750 6690 1409050 7590 0 0 0 0 0 0
+node "VDD" 2 2611.2 10205 -1080 v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 418700 3700 484500 3980 1354500 6920 0 0 0 0 0 0
+node "m1_12140_1165#" 11 2668.09 12140 1165 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 508125 12320 546175 5420 0 0 0 0 0 0 0 0
+node "VDD" 3 5442.57 17435 -1675 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 996150 6320 996150 6320 996150 6320 2354075 9160 0 0 0 0
+node "li_12675_n1220#" 299 367.548 12675 -1220 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37400 1950 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_17965_n435#" 59 97.8065 17965 -435 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7400 450 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_15740_n425#" 176 164.593 15740 -425 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16800 1030 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_12660_n430#" 675 555.784 12660 -430 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85600 4330 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_10055_n430#" 58 95.4538 10055 -430 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7200 440 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_11905_n430#" 154 171.571 11905 -430 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19175 1040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_21885_225#" 69 97.7246 21885 225 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6650 450 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_15910_230#" 66 54.5673 15910 230 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6300 430 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_15735_230#" 66 54.2485 15735 230 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6300 430 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_12665_225#" 679 658.61 12665 225 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85950 4350 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_12050_230#" 61 50.5407 12050 230 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_11905_235#" 61 73.5059 11905 235 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_9755_230#" 61 100.638 9755 230 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7600 460 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_17960_890#" 91 123.475 17960 890 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8750 570 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_15745_885#" 180 171.747 15745 885 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17125 1050 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_11900_885#" 168 178.095 11900 885 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17750 1040 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_12665_885#" 669 693.496 12665 885 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85200 4300 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_10060_880#" 84 114.555 10060 880 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8050 530 0 0 0 0 0 0 0 0 0 0 0 0
+node "SUB" 299 431.3 12675 1830 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37400 1950 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_14375_550#" 522 0 14375 550 ndif 0 0 0 0 0 0 0 0 9200 492 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_9850_15#" "m1_12140_n1090#" 1597.86
+cap "m1_12140_1165#" "VDD" 27.2599
+cap "li_11905_235#" "li_12665_225#" 7.18792
+cap "VDD" "m1_13690_15#" 1431.69
+cap "li_12665_885#" "m1_12140_1165#" 390.656
+cap "m1_9850_15#" "INB" 779.611
+cap "li_15745_885#" "li_15910_230#" 1.17588
+cap "GND" "m1_12140_1165#" 123.179
+cap "VDD" "li_17960_890#" 6.23895
+cap "BIAS" "m1_12140_1165#" 50.9793
+cap "GND" "BIAS" 12349.9
+cap "li_15735_230#" "li_15740_n425#" 1.76842
+cap "li_12665_225#" "INA" 80.4219
+cap "GND" "VDD" 1580.46
+cap "m1_12140_n1090#" "INA" 270.639
+cap "m1_9850_15#" "li_12050_230#" 30.3788
+cap "li_12675_n1220#" "li_12660_n430#" 63.5332
+cap "li_12665_885#" "SUB" 62.3644
+cap "INB" "INA" 297.391
+cap "li_11900_885#" "li_12050_230#" 2.4086
+cap "li_11905_235#" "li_12050_230#" 49.3333
+cap "GND" "li_17965_n435#" 37.5495
+cap "BIAS" "VDD" 189.741
+cap "BIAS" "li_11905_n430#" 109.405
+cap "li_15735_230#" "m1_13690_15#" 21.2158
+cap "m1_12140_n1090#" "BIAS" 20.6336
+cap "OUTA" "m1_9850_15#" 30.875
+cap "INB" "m1_12140_n1090#" 763.315
+cap "m1_9850_15#" "OUTB" 30.8811
+cap "li_12660_n430#" "li_11905_n430#" 16.652
+cap "BIAS" "GND" 5473.15
+cap "li_12665_885#" "li_12660_n430#" 79.8906
+cap "m1_9850_15#" "m1_12140_1165#" 1622.79
+cap "li_10055_n430#" "li_10060_880#" 0.867257
+cap "m1_9850_15#" "m1_13690_15#" 84.5942
+cap "li_15740_n425#" "li_15745_885#" 4.55744
+cap "a_14375_550#" "OUTA" 7.728
+cap "OUTA" "GND" 308.36
+cap "li_12665_225#" "li_12050_230#" 11.3745
+cap "li_15740_n425#" "li_15910_230#" 1.17895
+cap "GND" "OUTB" 309.59
+cap "m1_9850_15#" "VDD" 1239.56
+cap "GND" "m1_13690_15#" 45156.3
+cap "OUTA" "INA" 18.058
+cap "INA" "OUTB" 143.71
+cap "li_11900_885#" "li_11905_n430#" 4.58407
+cap "li_15740_n425#" "BIAS" 92.0874
+cap "li_11905_235#" "li_11905_n430#" 2.33333
+cap "m1_9850_15#" "GND" 15522.7
+cap "li_12665_885#" "li_11900_885#" 16.5238
+cap "m1_12140_1165#" "INA" 631.625
+cap "m1_13690_15#" "li_15910_230#" 21.3339
+cap "INA" "m1_13690_15#" 108.353
+cap "OUTA" "m1_12140_n1090#" 127.619
+cap "GND" "li_17960_890#" 45.0405
+cap "m1_12140_n1090#" "OUTB" 2024.54
+cap "li_12675_n1220#" "INA" 28.8436
+cap "OUTA" "BIAS" 80.2817
+cap "BIAS" "m1_9850_15#" 5577.5
+cap "BIAS" "OUTB" 80.4994
+cap "GND" "VDD" 2906.52
+cap "li_12675_n1220#" "li_12665_225#" 34.6976
+cap "INB" "OUTB" 79.2653
+cap "m1_12140_n1090#" "m1_12140_1165#" 659.532
+cap "m1_12140_n1090#" "m1_13690_15#" 2145.68
+cap "m1_12140_1165#" "BIAS" 17.2467
+cap "INB" "m1_12140_1165#" 39.5174
+cap "m1_13690_15#" "BIAS" 11616.9
+cap "li_11905_235#" "BIAS" 87.8764
+cap "INB" "m1_13690_15#" 64.9631
+cap "li_12675_n1220#" "INB" 40.9045
+cap "li_12665_885#" "li_12665_225#" 170.47
+cap "GND" "INA" 24.7213
+cap "m1_12140_n1090#" "VDD" 27.3138
+cap "SUB" "li_12665_225#" 34.5791
+cap "VDD" "BIAS" 228.873
+cap "BIAS" "INA" 73.7856
+cap "GND" "m1_12140_n1090#" 125.622
+cap "GND" "li_10060_880#" 31.7798
+cap "GND" "INB" 41.3441
+cap "li_12660_n430#" "INA" 62.2403
+cap "li_15735_230#" "li_15745_885#" 1.47368
+cap "li_17965_n435#" "li_17960_890#" 0.736842
+cap "BIAS" "m1_12140_n1090#" 178.053
+cap "li_12660_n430#" "li_12665_225#" 168.701
+cap "OUTA" "OUTB" 265.324
+cap "li_11905_235#" "m1_9850_15#" 26.2325
+cap "GND" "li_10055_n430#" 33.4322
+cap "BIAS" "INB" 84.1991
+cap "OUTA" "m1_12140_1165#" 2194.11
+cap "li_15735_230#" "li_15910_230#" 36
+cap "li_12660_n430#" "m1_12140_n1090#" 96.451
+cap "li_11905_235#" "li_11900_885#" 2.43478
+cap "OUTA" "m1_13690_15#" 7248.28
+cap "m1_12140_1165#" "OUTB" 128.137
+cap "m1_13690_15#" "OUTB" 7438.01
+cap "INB" "li_12660_n430#" 69.0945
+cap "li_11905_n430#" "li_12050_230#" 2.35789
+cap "m1_12140_1165#" "m1_13690_15#" 2064.22
+cap "m1_9850_15#" "INA" 704.917
+cap "XM1/a_n945_n188#" "XR2/a_n285_n1192#" 0.880055
+cap "XR2/a_n415_n1322#" "XM1/a_n897_n100#" 0.443203
+cap "XR2/a_n415_n1322#" "XM1/a_n989_n100#" 0.0521415
+cap "XR2/a_n285_n1192#" "XM1/a_n897_n100#" 0.515456
+cap "XR2/a_n285_n1192#" "XM1/a_n989_n100#" 0.0273414
+cap "XR2/a_n415_n1322#" "XR2/a_n285_n1192#" -149.108
+cap "XM1/a_n945_n188#" "XR2/a_n285_n1192#" 0.0808325
+cap "XR2/a_n415_n1322#" "XM2/a_n945_n188#" 0.918489
+cap "XM2/a_n945_n188#" "XR2/a_n285_n1192#" 0.420982
+cap "XR2/a_n415_n1322#" "XM2/a_n945_n188#" 0.585106
+cap "XM2/a_n945_n188#" "XR2/a_n285_n1192#" 1.36834
+cap "XR2/a_n285_n1192#" "XR2/a_n285_760#" -6.30136
+cap "XR2/a_n415_n1322#" "XM1/a_n989_n100#" 3.54562
+cap "XR2/a_n285_n1192#" "XM1/a_n989_n100#" 3.56978
+cap "XR2/a_n415_n1322#" "XM1/a_n945_n188#" 11.6701
+cap "XR2/a_n415_n1322#" "XM1/a_n897_n100#" 3.10242
+cap "XR2/a_n285_n1192#" "XM1/a_n945_n188#" 14.6694
+cap "XR2/a_n285_n1192#" "XM1/a_n897_n100#" 3.64362
+cap "XR2/a_n415_n1322#" "XR2/a_n285_n1192#" 115.851
+cap "XR2/a_n415_n1322#" "XM1/a_n945_n188#" 37.1986
+cap "XM2/a_n705_n100#" "XR2/a_n415_n1322#" 0.443203
+cap "XR2/a_n415_n1322#" "XM1/a_n801_n100#" 1.77281
+cap "XM43/a_n81_122#" "XR3/a_n573_n2072#" 0.906962
+cap "XR2/a_n415_n1322#" "XM43/a_n81_122#" 6.24054
+cap "XR2/a_n285_760#" "XR2/a_n285_n1192#" -6.30136
+cap "XR2/a_n415_n1322#" "XR3/a_n573_n2072#" 8.94141
+cap "XR2/a_n285_760#" "XM1/a_n945_n188#" 1.42109e-14
+cap "XR2/a_n285_n1192#" "XM1/a_n945_n188#" 0.499103
+cap "XR2/a_n285_760#" "XM32/a_n945_n188#" 0.891386
+cap "XR2/a_n285_760#" "XM1/a_n801_n100#" 4.07832
+cap "XR2/a_n285_760#" "XM43/a_n81_122#" 8.30654
+cap "XR2/a_n285_760#" "XR3/a_n573_n2072#" 14.212
+cap "XR2/a_n285_760#" "XR2/a_n415_n1322#" 111.946
+cap "XR2/a_n285_760#" "XM42/a_n177_n188#" 3.36939
+cap "XR3/a_n703_n2202#" "XM42/a_n177_n188#" 3.93833
+cap "XR3/a_n573_n2072#" "XR2/a_n285_760#" 27.1117
+cap "XR3/a_n573_n2072#" "XM43/a_n81_122#" 0.906962
+cap "XM42/a_n177_n188#" "XR3/a_n573_n2072#" 6.06332
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+cap "XM3/a_n1809_122#" "XM3/a_n1857_n100#" 951.454
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+cap "XM3/a_n1713_n188#" "XM4/a_n1857_n100#" 1.80803
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+cap "XR3/a_n703_n2202#" "XM3/a_n1761_n100#" 581.764
+cap "XM4/a_n1809_122#" "XM4/a_n1713_n188#" 0.720674
+cap "XM4/a_n1809_122#" "XM3/a_n1761_n100#" 663.827
+cap "XM3/a_n1809_122#" "XM4/a_n1857_n100#" 0.827311
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+merge "XM3/a_1359_n188#" "XM3/a_2607_122#"
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+merge "XM3/a_2415_122#" "XM3/a_2223_122#"
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+merge "XM4/a_975_n188#" "XM4/a_783_n188#"
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+merge "XM3/a_591_n188#" "XM3/a_399_n188#"
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+merge "XM3/a_15_n188#" "XM3/a_1263_122#"
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+merge "XM3/a_1071_122#" "XM3/a_879_122#"
+merge "XM3/a_879_122#" "XM3/a_687_122#"
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+merge "XM3/a_303_122#" "XM3/a_111_122#"
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+merge "XM3/a_n369_n188#" "XM3/a_n561_n188#"
+merge "XM3/a_n561_n188#" "XM3/a_n753_n188#"
+merge "XM3/a_n753_n188#" "XM3/a_n945_n188#"
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+merge "XM3/a_n1137_n188#" "XM3/a_n1329_n188#"
+merge "XM3/a_n1329_n188#" "XM3/a_n81_122#"
+merge "XM3/a_n81_122#" "XM3/a_n273_122#"
+merge "XM3/a_n273_122#" "XM3/a_n465_122#"
+merge "XM3/a_n465_122#" "XM3/a_n657_122#"
+merge "XM3/a_n657_122#" "XM3/a_n849_122#"
+merge "XM3/a_n849_122#" "XM3/a_n1041_122#"
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+merge "XM3/a_n1713_n188#" "XM3/a_n1905_n188#"
+merge "XM3/a_n1905_n188#" "XM3/a_n2097_n188#"
+merge "XM3/a_n2097_n188#" "XM3/a_n2289_n188#"
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+merge "XM3/a_n2481_n188#" "XM3/a_n2673_n188#"
+merge "XM3/a_n2673_n188#" "XM3/a_n1617_122#"
+merge "XM3/a_n1617_122#" "XM3/a_n1809_122#"
+merge "XM3/a_n1809_122#" "XM3/a_n2001_122#"
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+merge "XM3/a_n2385_122#" "XM3/a_n2577_122#"
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+merge "XM2/a_n945_n188#" "XM1/a_n945_n188#"
+merge "XM1/a_n945_n188#" "BIAS"
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+merge "XM3/a_2847_n100#" "XM4/a_2655_n100#"
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+merge "XM33/a_639_n100#" "XM33/a_447_n100#"
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+merge "XM33/a_255_n100#" "XM33/a_63_n100#"
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+merge "XM33/a_n129_n100#" "XM33/a_n321_n100#"
+merge "XM33/a_n321_n100#" "XM33/a_n513_n100#"
+merge "XM33/a_n513_n100#" "XM33/a_n705_n100#"
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+merge "XM32/a_831_n100#" "XM32/a_639_n100#"
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+merge "a_14375_550#" "XM32/a_n513_n100#"
+merge "XM32/a_n513_n100#" "XM32/a_n705_n100#"
+merge "XM32/a_n705_n100#" "XM32/a_n897_n100#"
+merge "XM32/a_n897_n100#" "OUTA"
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+merge "XM43/a_63_n100#" "XM43/a_n129_n100#"
+merge "XM43/a_n129_n100#" "XR2/a_n285_760#"
+merge "XR2/a_n285_760#" "m1_12140_n1090#"
+merge "XM42/a_n81_122#" "XM42/a_n177_n188#" -33392.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -51898640 -1256 0 0 0 0 0 0 0 0 0 0
+merge "XM42/a_n177_n188#" "INA"
+merge "XM43/a_n177_n188#" "XM43/a_n81_122#" -21051.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -32550168 -1266 0 0 0 0 0 0 0 0 0 0
+merge "XM43/a_n81_122#" "INB"

mag/output_buffer.mag

diff --git a/mag/output_buffer.mag b/mag/output_buffer.mag
new file mode 100644
index 0000000..9262185
--- /dev/null
+++ b/mag/output_buffer.mag
@@ -0,0 +1,3256 @@
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+rect 21625 35 21760 105
+rect 21820 35 21825 105
+rect 13680 25 21825 35
+rect 22025 -45 22825 765
+rect 10190 -1080 10205 -550
+rect 10600 -1080 10640 -550
+rect 10190 -1275 10640 -1080
+rect 13725 -55 15710 -45
+rect 13725 -125 13795 -55
+rect 13855 -125 13985 -55
+rect 14045 -125 14180 -55
+rect 14240 -125 14370 -55
+rect 14430 -125 14560 -55
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+rect 14815 -125 14945 -55
+rect 15005 -125 15140 -55
+rect 15200 -125 15330 -55
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+rect 15980 -125 16090 -55
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+rect 16535 -125 16665 -55
+rect 16725 -125 16860 -55
+rect 16920 -125 17045 -55
+rect 17105 -125 17245 -55
+rect 17305 -125 17430 -55
+rect 17490 -125 17625 -55
+rect 17685 -125 17820 -55
+rect 17880 -125 18005 -55
+rect 18065 -125 18200 -55
+rect 18260 -125 18390 -55
+rect 18450 -125 18585 -55
+rect 18645 -125 18775 -55
+rect 18835 -125 18970 -55
+rect 19030 -125 19160 -55
+rect 19220 -125 19355 -55
+rect 19415 -125 19545 -55
+rect 19605 -125 19740 -55
+rect 19800 -125 19930 -55
+rect 19990 -125 20120 -55
+rect 20180 -125 20315 -55
+rect 20375 -125 20505 -55
+rect 20565 -125 20700 -55
+rect 20760 -125 20890 -55
+rect 20950 -125 21080 -55
+rect 21140 -125 21275 -55
+rect 21335 -125 21465 -55
+rect 21525 -125 21655 -55
+rect 21715 -125 22825 -55
+rect 15980 -455 22825 -125
+rect 13725 -560 14160 -455
+rect 13725 -1655 13750 -560
+rect 14135 -1430 14160 -560
+rect 17435 -565 17870 -530
+rect 14135 -1655 14165 -1430
+rect 13725 -1680 14165 -1655
+rect 17435 -1655 17460 -565
+rect 17845 -1655 17870 -565
+rect 17435 -1675 17870 -1655
+rect 13730 -1865 14165 -1680
+rect 22025 -1795 22825 -455
+<< via3 >>
+rect 17455 1190 17840 2280
+rect 17460 -1655 17845 -565
+<< metal4 >>
+rect 17435 2280 18025 2310
+rect 17435 1190 17455 2280
+rect 17840 1190 18025 2280
+rect 17435 -565 18025 1190
+rect 17435 -1655 17460 -565
+rect 17845 -1655 18025 -565
+rect 17435 -1675 18025 -1655
+rect 17440 -1680 18025 -1675
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX  XM1 
+timestamp 1662510845
+transform 1 0 10847 0 -1 650
+box -1127 -310 1127 310
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX  XM2
+timestamp 1662510845
+transform 1 0 10847 0 1 -10
+box -1127 -310 1127 310
+use sky130_fd_pr__nfet_01v8_lvt_LELFGX  XM3
+timestamp 1662407989
+transform 1 0 18902 0 1 650
+box -3047 -310 3047 310
+use sky130_fd_pr__nfet_01v8_lvt_LELFGX  XM4
+timestamp 1662407989
+transform 1 0 18902 0 1 -10
+box -3047 -310 3047 310
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX  XM32
+timestamp 1662510845
+transform 1 0 14687 0 1 650
+box -1127 -310 1127 310
+use sky130_fd_pr__nfet_01v8_lvt_YTLFGX  XM33
+timestamp 1662510845
+transform 1 0 14687 0 -1 -10
+box -1127 -310 1127 310
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM42 
+timestamp 1662515274
+transform 1 0 12379 0 -1 650
+box -359 -310 359 310
+use sky130_fd_pr__nfet_01v8_lvt_HNLS5R  XM43
+timestamp 1662515274
+transform 1 0 12379 0 1 -10
+box -359 -310 359 310
+use sky130_fd_pr__res_high_po_2p85_P79JE3  XR1 
+timestamp 1662404926
+transform 0 1 11383 -1 0 1451
+box -451 -1358 451 1358
+use sky130_fd_pr__res_high_po_2p85_P79JE3  XR2
+timestamp 1662404926
+transform 0 1 11380 -1 0 -807
+box -451 -1358 451 1358
+use sky130_fd_pr__res_high_po_5p73_W59YBA  XR3
+timestamp 1662407989
+transform 0 1 15798 -1 0 -1101
+box -739 -2238 739 2238
+use sky130_fd_pr__res_high_po_5p73_W59YBA  XR29
+timestamp 1662407989
+transform 0 1 15798 -1 0 1739
+box -739 -2238 739 2238
+<< labels >>
+rlabel metal1 11925 -1260 11975 830 1 BIAS
+rlabel metal2 8845 -1300 9445 980 1 GND
+rlabel metal3 10190 -1275 10640 -1080 1 VDD
+rlabel metal1 12900 -1255 12955 175 1 INB
+rlabel metal1 13365 -1260 13415 520 1 INA
+rlabel metal3 22025 -1795 22825 -240 1 GND
+rlabel metal4 17440 -1680 18025 2310 1 VDD
+rlabel metal1 15855 -1840 15905 830 1 BIAS
+rlabel locali 12675 1830 13610 1870 1 SUB
+rlabel metal3 13725 2280 14160 2475 1 OUTA
+rlabel metal3 13730 -1865 14165 -1655 1 OUTB
+<< end >>

mag/sky130A-BindKeys

diff --git a/mag/sky130A-BindKeys b/mag/sky130A-BindKeys
new file mode 100755
index 0000000..b40844c
--- /dev/null
+++ b/mag/sky130A-BindKeys
@@ -0,0 +1,172 @@
+#
+# Cadence-compatibility bindings except where marked.
+#
+macro f  "view"	     ;# zoom to fit window
+macro ^z "zoom 0.5"  ;# zoom in
+macro Z  "zoom 2"    ;# zoom out
+macro B  "popstack"  ;# up hierarchy
+macro X  {pushstack [cellname list self]}	;# down hierarchy
+macro x  "edit"		;# down hierarchy, edit-in-place
+macro b  "select top cell ; edit"  ;# up hierarchy from edit-in-place
+macro p  "tool wire; magic::trackwire %W pick"	;# path
+macro ^r "redraw"
+macro ^f "unexpand"
+macro F  "expand"
+macro ^a "select area"
+macro ^d "select clear"
+macro k  "magic::measure"
+macro K  "magic::unmeasure"
+macro i  "magic::promptload getcell"
+macro l  "magic::update_texthelper ; wm deiconify .texthelper ; raise .texthelper"
+macro O  "magic::clock"
+macro <del> "magic::delete"
+
+# Toolkit parameter dialog
+macro q "magic::gencell {} ; raise .params"
+#
+# The following should be already implemented as existing Magic bindings
+#
+macro u "undo"
+macro U "redo"
+macro m "move"
+macro c "copy"
+#
+# Compatibility with Electric;  Cadence bindings are on function keys and
+# do not work through the VNC.
+macro ^s "magic::promptsave magic"	;# save dialog menu
+
+#
+# Bertrand's bindings follow except where marked.
+#
+macro < sideways
+macro ^ upsidedown
+#
+# Set grid at 1 micron
+#
+macro 0  "grid on ; grid 1l"	;# Grid at 0.5um (1 lambda)
+# macro ^f "feedback clear"	;# conflicts with Cadence binding
+#
+# Paint/Erase macros 
+#
+macro 1 "paint m1"
+macro ! "erase m1"
+macro 2 "paint m2"
+macro @ "erase m2"
+macro 3 "paint m3"
+macro # "erase m3"
+macro 4 "paint m4"
+macro $ "erase m4"
+macro 5 "paint mtp"
+macro % "erase mtp"
+
+macro 7 "paint poly"
+# macro & "erase poly"
+# macro p "paint pdiff"
+macro n "paint ndiff"
+# macro l "erase labels"
+macro P "erase pdiff"
+macro N "erase ndiff"
+macro y "drc check; drc why"
+macro ? "select area; what"
+
+macro / "expand toggle"
+macro ^w "writeall force"
+macro ^e "edit"
+# macro ^x "quit"
+
+macro z "findbox zoom"
+# "f" conflicts with Cadence "full view", so use control-i to select cells.
+# macro f "select cell"
+macro ^i "select cell"
+
+# Leave keypad bindings as-is, further down.  However, keypad
+# keys generally don't translate through the VNC session, so
+# use the following arrow key bindings:
+#
+#                         no shift  shift
+# arrows only -> Pan       10%      100%
+# with alt    -> Move      1 lambda 1 grid
+# with ctrl   -> Stretch   1 lambda 1 grid
+# 
+# Pan 10 percent of the window size with arrows
+# macro XK_Left  "scroll l .1 w"
+# macro XK_Up    "scroll u .1 w"
+# macro XK_Right "scroll r .1 w"
+# macro XK_Down  "scroll d .1 w"
+
+# Pan 100 percent of the window size with arrows
+# macro Shift_XK_Left  "scroll l 1 w"
+# macro Shift_XK_Up    "scroll u 1 w"
+# macro Shift_XK_Right "scroll r 1 w"
+# macro Shift_XK_Down  "scroll d 1 w"
+
+# move 0.05um with arrows
+# macro Alt_XK_Left          "move l 1l"
+# macro Alt_XK_Right         "move r 1l"
+# macro Alt_XK_Up            "move u 1l"
+# macro Alt_XK_Down          "move d 1l"
+
+# move 1 grid unit with arrows
+# macro Alt_Shift_XK_Left  "move l 1g"
+# macro Alt_Shift_XK_Right "move r 1g"
+# macro Alt_Shift_XK_Up    "move u 1g"
+# macro Alt_Shift_XK_Down  "move d 1g"
+
+# stretch 0.05um with arrows
+# macro Control_XK_Left          "stretch l 1l"
+# macro Control_XK_Right         "stretch r 1l"
+# macro Control_XK_Up            "stretch u 1l"
+# macro Control_XK_Down          "stretch d 1l"
+
+# stretch 1 grid unit with arrows
+# macro Control_Shift_XK_Left  "stretch l 1g"
+# macro Control_Shift_XK_Right "stretch r 1g"
+# macro Control_Shift_XK_Up    "stretch u 1g"
+# macro Control_Shift_XK_Down  "stretch d 1g"
+
+# shift mouse wheel bindings for right-left shift
+macro Shift_XK_Pointer_Button4 "scroll r .05 w"
+macro Shift_XK_Pointer_Button5 "scroll l .05 w"
+
+# control mouse wheel bindings for zoom in/out
+macro Control_XK_Pointer_Button4 "zoom 0.70711"
+macro Control_XK_Pointer_Button5 "zoom 1.41421"
+
+# Bertrand's original arrow macros
+# move 1 grid unit with arrows
+macro XK_Left          "move l 1g"
+macro XK_Right         "move r 1g"
+macro XK_Up            "move u 1g"
+macro XK_Down          "move d 1g"
+
+# move 0.05um with arrows
+macro Control_XK_Left  "move l 1l"
+macro Control_XK_Right "move r 1l"
+macro Control_XK_Up    "move u 1l"
+macro Control_XK_Down  "move d 1l"
+
+# stretch 1 grid unit with arrows
+macro Shift_XK_Left          "stretch l 1g"
+macro Shift_XK_Right         "stretch r 1g"
+macro Shift_XK_Up            "stretch u 1g"
+macro Shift_XK_Down          "stretch d 1g"
+
+# stretch 0.05um with arrows
+macro Control_Shift_XK_Left  "stretch l 1l"
+macro Control_Shift_XK_Right "stretch r 1l"
+macro Control_Shift_XK_Up    "stretch u 1l"
+macro Control_Shift_XK_Down  "stretch d 1l"
+
+# Restore pan function on Alt-key
+# Pan 10 percent of the window size with arrows
+macro Alt_XK_Left  "scroll l .1 w"
+macro Alt_XK_Up    "scroll u .1 w"
+macro Alt_XK_Right "scroll r .1 w"
+macro Alt_XK_Down  "scroll d .1 w"
+
+# Pan 100 percent of the window size with arrows
+macro Alt_Shift_XK_Left  "scroll l 1 w"
+macro Alt_Shift_XK_Up    "scroll u 1 w"
+macro Alt_Shift_XK_Right "scroll r 1 w"
+macro Alt_Shift_XK_Down  "scroll d 1 w"
+

mag/sky130A-GDS.tech

diff --git a/mag/sky130A-GDS.tech b/mag/sky130A-GDS.tech
new file mode 100755
index 0000000..fc274e1
--- /dev/null
+++ b/mag/sky130A-GDS.tech
@@ -0,0 +1,762 @@
+tech
+    format 32
+    sky130A-GDS
+end
+
+version
+    version 1.0.310-0-gd7faec2
+    description "SkyWater SKY130: Vendor GDS layers and supplementary DRC"
+    requires magic-8.3.124
+end
+
+planes
+ p1
+ p2
+ p3
+ p4
+ p5
+ p6
+ p7
+ p8
+ p9
+ p10
+ p11
+ p12
+ p13
+ p14
+ p15
+ p16
+ p17
+ p18
+ p19
+ p20
+ p21
+ p22
+ p23
+ p24
+ p25
+ p26
+ p27
+ p28
+ p29
+ p30
+ p31
+ p32
+ p33
+ p34
+ p35
+ p36
+ p37
+ p38
+ p39
+ p40
+ p41
+ p42
+ p43
+end
+
+types
+ p1  NWELL,l1
+ p1  NWELLT,l60
+ p1  NWELLP,l62
+ p2  DNWELL,l2
+ p3  DIFF,l3
+ p3  TAP,l4
+ p4  LVTN,l5
+ p4  HVTP,l6
+ p5  HVI,l7
+ p6  TUNM,l8
+ p7  POLY,l9
+ p7  POLYP,l63
+ p7  POLYT,l70
+ p8  NPC,l10
+ p9  PSDM,l11
+ p9  NSDM,l12
+ p10 LICON1,l13
+ p11 LI1,l14
+ p11 LI1T,l15
+ p11 LI1P,l16
+ p12 MCON,l17
+ p12 MET1,l18
+ p12 MET1T,l19
+ p12 MET1P,l20
+ p13 VIA1,l21
+ p13 MET2,l22
+ p13 MET2T,l23
+ p13 MET2P,l24
+ p14 VIA2,l25
+ p14 MET3,l26
+ p14 MET3T,l27
+ p14 MET3P,l28
+ p15 VIA3,l29
+ p15 MET4,l30
+ p15 MET4T,l31
+ p15 MET4P,l32
+ p16 VIA4,l33
+ p16 MET5,l34
+ p16 MET5T,l35
+ p16 MET5P,l36
+ p17 PAD,l37
+ p17 PADT,l38
+ p17 PADP,l39
+ p18 AREAID,l40
+ p19 TEXT,l41
+ p20 HVTR,l42
+ p21 NCM,l43
+ p22 RPM,l44
+ p23 NSM,l45
+ p24 RDL,l46
+ p25 VHVI,l47
+ p26 LDNTM,l48
+ p26 HVNTM,l49
+ p27 PMM,l50
+ p28 PNP,l51
+ p29 CAP,l52
+ p30 IND,l53
+ p31 PWRES,l54
+ p32 POLYRES,l55
+ p33 DIFFRES,l56
+ p34 DIODE,l57
+ p35 POLYM,l58
+ p36 COREID,l59
+ p37 PWELLT,l61
+ p37 PWELLP,l64
+ p38 CFOMDROP,l65
+ p39 CLI1MADD,l66
+ p40 CNTMADD,l67
+ p41 CP1MADD,l68
+ p42 BOUND,l69
+ p43 RERAM,l71
+end
+
+contact
+end
+
+styles
+    styletype	mos
+ l1   nwell
+ l2   cwell
+ l3   ndiffusion
+ l4   pdiffusion
+ l5   implant1
+ l6   implant2
+ l7   implant3
+ l8   subcircuit
+ l9    polysilicon
+ l10   implant4
+ l11   pdop_stripes
+ l12   ndop_stripes
+ l13   obsmetal1 contact_X'es
+ l14   metal1
+ l15   metal1
+ l16   metal1
+ l17   metal1 metal2 via1
+ l18   metal2
+ l19   metal2
+ l20   metal2
+ l21   metal2 metal3 via2
+ l22   metal3
+ l23   metal3
+ l24   metal3
+ l25   metal3 metal4 via3
+ l26   metal4
+ l27   metal4
+ l28   metal4
+ l29   metal4 metal5 via4
+ l30   metal5
+ l31   metal5
+ l32   metal5
+ l33   metal5 metal6 via5
+ l34   metal6
+ l35   metal6
+ l36   metal6
+ l37   overglass
+ l38   overglass
+ l39   overglass
+ l40   subcircuit
+ l41   comment
+ l42   implant1
+ l43   mim_top
+ l44   mim_bottom
+ l45   ntransistor_stripes
+ l46   metal7
+ l47   electrode
+ l48   nwell_field_implant
+ l49   hvndiff_mask
+ l50   poly_light
+ l51   mvpdiff
+ l52   mvndiff
+ l53   hvpdiff
+ l54   cwellnsc
+ l55   poly_resist poly_resist_stripes
+ l56   ptransistor_stripes
+ l57   hvpdiff_mask
+ l58   poly_resist
+ l59   subcircuit
+ l60   nwell
+ l61   pwell
+ l62   nwell
+ l63   polysilicon
+ l64   pwell
+ l65   implant1
+ l66   implant2
+ l67   implant3
+ l68   implant4
+ l69   subcircuit
+ l70   polysilicon
+ l71   electrode_stripes
+ error_p	error_waffle
+ error_s	error_waffle
+ error_ps	error_waffle
+end
+
+compose
+   paint  MCON    MET1  MCON
+   paint  VIA1    MET2  VIA1
+   paint  VIA2    MET3  VIA2
+   paint  VIA3    MET4  VIA3
+   paint  VIA4    MET5  VIA4
+
+   paint  MCON    MET1P  MCON
+   paint  VIA1    MET2P  VIA1
+   paint  VIA2    MET3P  VIA2
+   paint  VIA3    MET4P  VIA3
+   paint  VIA4    MET5P  VIA4
+
+   paint  MCON    MET1T  MCON
+   paint  VIA1    MET2T  VIA1
+   paint  VIA2    MET3T  VIA2
+   paint  VIA3    MET4T  VIA3
+   paint  VIA4    MET5T  VIA4
+end
+
+connect
+end
+
+cifoutput
+style gdsii
+  scalefactor 10 nanometers
+  options calma-permissive-labels
+  gridlimit 1
+
+ layer  NWELL NWELL,NWELLT,NWELLP
+ calma 64 20
+
+ layer NWELLT
+ labels NWELLT noport
+ calma 64 16
+
+ layer NWELLP
+ labels NWELLP port
+ calma 64 5
+
+ layer  DNWELL DNWELL
+ labels DNWELL 
+ calma 64 18
+
+ layer  DIFF DIFF
+ labels DIFF 
+ calma 65 20
+
+ layer  TAP TAP
+ labels TAP 
+ calma 65 44
+
+ layer  POLY POLY,POLYP,POLYT
+ calma 66 20
+
+ layer POLYT
+ labels POLYT noport
+ calma 66 16
+
+ layer POLYP
+ labels POLYP port
+ calma 66 5
+
+ layer  LVTN LVTN
+ labels LVTN 
+ calma 125 44
+
+ layer  HVTP HVTP
+ labels HVTP 
+ calma 78 44
+
+ layer  HVI HVI
+ labels HVI 
+ calma 75 20
+
+ layer  TUNM TUNM
+ labels TUNM 
+ calma 80 20
+
+ layer  NPC NPC
+ labels NPC 
+ calma 95 20
+
+ layer  PSDM PSDM
+ labels PSDM 
+ calma 94 20
+
+ layer  NSDM NSDM
+ labels NSDM 
+ calma 93 44
+
+ layer  LICON1 LICON1
+ labels LICON1 
+ calma 66 44
+
+ # Note: LICON1 not on LI1 plane, may not be coincident with LI1.
+ layer  LI1 LI1,LI1T,LI1P
+ calma 67 20
+
+ layer  LI1T
+ labels LI1T noport
+ calma 67 16
+
+ layer  LI1P
+ labels LI1P port
+ calma 67 5
+
+ layer  MET1 MET1,MET1T,MET1P,MCON
+ calma 68 20
+
+ layer  MET1T
+ labels MET1T noport
+ calma 68 16
+
+ layer  MET1P
+ labels MET1P port
+ calma 68 5
+
+ layer  MCON MCON
+ labels MCON 
+ calma 67 44
+
+ layer  MET2 MET2,MET2T,MET2P,VIA1
+ calma 69 20
+
+ layer  MET2T
+ labels MET2T noport
+ calma 69 16
+
+ layer  MET2P
+ labels MET2P port
+ calma 69 5
+
+ layer  VIA1 VIA1
+ labels VIA1 
+ calma 68 44
+
+ layer  RERAM RERAM
+ labels RERAM
+ calma 201 20
+
+ layer  MET3 MET3,MET3T,MET3P,VIA2
+ calma 70 20
+
+ layer  MET3T
+ labels MET3T noport
+ calma 70 16
+
+ layer  MET3P
+ labels MET3P port
+ calma 70 5
+
+ layer  VIA2 VIA2
+ labels VIA2 
+ calma 69 44
+
+ layer  MET4 MET4,MET4T,MET4P,VIA3
+ calma 71 20
+
+ layer  MET4T
+ labels MET4T noport
+ calma 71 16
+
+ layer  MET4P
+ labels MET4P port
+ calma 71 5
+
+ layer  VIA3 VIA3
+ labels VIA3 
+ calma 70 44
+
+ layer  MET5 MET5,MET5T,MET5P,VIA4
+ calma 72 20
+
+ layer  MET5T
+ labels MET5T noport
+ calma 72 16
+
+ layer  MET5P
+ labels MET5P port
+ calma 72 5
+
+ layer  VIA4 VIA4
+ labels VIA4 
+ calma 71 44
+
+ layer  PAD PAD,PADT,PADP
+ calma 76 20
+
+ layer  PADT
+ labels PADT noport
+ calma 76 16
+
+ layer  PADP
+ labels PADP port
+ calma 76 5
+
+ layer  AREAID AREAID
+ labels AREAID
+ calma 81 4
+
+ layer  TEXT TEXT
+ labels TEXT
+ calma 83 44
+
+ layer HVTR HVTR
+ labels HVTR
+ calma 18 20
+
+ layer NCM NCM
+ labels NCM
+ calma 92 44
+
+ layer RPM RPM
+ labels RPM
+ calma 86 20
+
+ layer NSM NSM
+ labels NSM
+ calma 61 20
+
+ layer RDL RDL
+ labels RDL
+ calma 74 20
+
+ layer VHVI VHVI
+ labels VHVI
+ calma 74 21
+
+ layer LDNTM LDNTM
+ labels LDNTM
+ calma 11 44
+
+ layer HVNTM HVNTM
+ labels HVNTM
+ calma 125 20
+
+ layer PMM PMM
+ labels PMM
+ calma 85 44
+
+ layer PNP PNP
+ labels PNP
+ calma 82 44
+
+ layer CAP CAP
+ labels CAP
+ calma 82 64
+
+ layer IND IND
+ labels IND
+ calma 82 24
+
+ layer PWRES PWRES
+ labels PWRES
+ calma 64 13
+
+ layer POLYRES POLYRES
+ labels POLYRES
+ calma 66 13
+
+ layer DIFFRES DIFFRES
+ labels DIFFRES
+ calma 65 13
+
+ layer DIODE DIODE
+ labels DIODE
+ calma 81 23
+
+ layer POLYM POLYM
+ labels POLYM
+ calma 66 83
+
+ layer COREID COREID
+ labels COREID
+ calma 81 2
+
+ layer PWELLT PWELLT
+ labels PWELLT noport
+ calma 122 16
+
+ layer PWELLP PWELLP
+ labels PWELLP port
+ calma 64 59
+
+ layer CFOMDROP CFOMDROP
+ labels CFOMDROP
+ calma 22 22
+
+ layer CLI1MADD CLI1MADD
+ labels CLI1MADD
+ calma 115 43
+
+ layer CNTMADD CNTMADD
+ labels CNTMADD
+ calma 22 21
+
+ layer CP1MADD CP1MADD
+ labels CP1MADD
+ calma 33 43
+
+ layer BOUND BOUND
+ labels BOUND
+ calma 235 4
+end
+
+cifinput
+style default
+ scalefactor 10 nanometers
+ layer l1  NWELL
+ layer l2  DNWELL
+ layer l3  DIFF
+ layer l4  TAP
+ layer l5  LVTN
+ layer l6  HVTP
+ layer l7  HVI
+ layer l8  TUNM
+ layer l9  POLY
+ layer l10 NPC
+ layer l11 PSDM
+ layer l12 NSDM
+ layer l13 LICON1
+ layer l14 LI1
+ layer l15 LI1T
+ layer l16 LI1P
+ layer l17 MCON
+ layer l18 MET1
+ layer l19 MET1T
+ layer l20 MET1P
+ layer l21 VIA1
+ layer l22 MET2
+ layer l23 MET2T
+ layer l24 MET2P
+ layer l25 VIA2
+ layer l26 MET3
+ layer l27 MET3T
+ layer l28 MET3P
+ layer l29 VIA3
+ layer l30 MET4
+ layer l31 MET4T
+ layer l32 MET4P
+ layer l33 VIA4
+ layer l34 MET5
+ layer l35 MET5T
+ layer l36 MET5P
+ layer l37 PAD
+ layer l38 PADT
+ layer l39 PADP
+ layer l40 AREAID
+ layer l41 TEXT
+ layer l42 HVTR
+ layer l43 NCM
+ layer l44 RPM
+ layer l45 NSM
+ layer l46 RDL
+ layer l47 VHVI
+ layer l48 LDNTM
+ layer l49 HVNTM
+ layer l50 PMM
+ layer l51 PNP
+ layer l52 CAP
+ layer l53 IND
+ layer l54 PWRES
+ layer l55 POLYRES
+ layer l56 DIFFRES
+ layer l57 DIODE
+ layer l58 POLYM
+ layer l59 COREID
+ layer l60 NWELLT
+ layer l61 PWELLT
+ layer l62 NWELLP
+ layer l63 POLYP
+ layer l64 PWELLP
+ layer l65 CFOMDROP
+ layer l66 CLI1MADD
+ layer l67 CNTMADD
+ layer l68 CP1MADD
+ layer l69 BOUND
+ layer l70 POLYT
+ layer l71 RERAM
+ calma NWELL  64 20
+ calma DNWELL 64 18
+ calma DIFF   65 20
+ calma TAP    65 44
+ calma LVTN  125 44
+ calma HVTP   78 44
+ calma HVI    75 20
+ calma TUNM   80 20
+ calma POLY   66 20
+ calma NPC    95 20
+ calma PSDM   94 20
+ calma NSDM   93 44
+ calma LICON1 66 44
+ calma LI1    67 20
+ calma LI1T   67 16
+ calma LI1P   67 5
+ calma MCON   67 44
+ calma MET1   68 20
+ calma MET1T  68 16
+ calma MET1P  68 5
+ calma VIA1   68 44
+ calma MET2   69 20
+ calma MET2T  69 16
+ calma MET2P  69 5
+ calma VIA2   69 44
+ calma MET3   70 20
+ calma MET3T  70 16
+ calma MET3P  70 5
+ calma VIA3   70 44
+ calma MET4   71 20
+ calma MET4T  71 16
+ calma MET4P  71 5
+ calma VIA4   71 44
+ calma MET5   72 20
+ calma MET5T  72 16
+ calma MET5P  72 5
+ calma PAD    76 20
+ calma PADT   76 16
+ calma PADP   76 5
+ calma AREAID 81 4
+ calma TEXT   83 44
+ calma HVTR   18 20
+ calma NCM    92 44
+ calma RPM    86 20
+ calma NSM    61 20
+ calma RDL    74 20
+ calma VHVI   74 21
+ calma LDNTM  11 44
+ calma HVNTM 125 20
+ calma PMM    85 44
+ calma PNP    82 44
+ calma CAP    82 64
+ calma IND    82 24
+ calma PWRES  64 13
+ calma POLYRES 66 13
+ calma DIFFRES 65 13
+ calma DIODE  81 23
+ calma POLYM  66 83
+ calma COREID 81 2
+ calma NWELLT  64 16
+ calma PWELLT 122 16
+ calma NWELLP  64 5
+ calma POLYP  66 5
+ calma PWELLP 64 59
+ calma CFOMDROP 22 22
+ calma CLI1MADD 115 43
+ calma CNTMADD  22 21
+ calma CP1MADD  33 43
+ calma BOUND  235 4
+ calma POLYT  66 16
+ calma RERAM 201 20
+end
+ 
+mzrouter
+end
+
+#---------------------------------------------------------------------
+# DRC style used to check DRC errors GDS layers directly.  Generally,
+# this covers rules not found in sky130A.tech
+#---------------------------------------------------------------------
+
+drc
+ scalefactor 10
+
+ # NPC rules
+
+ width NPC 270 "NPC width < %d (NPC.1)"
+ spacing NPC NPC 270 touching_ok "NPC to NPC spacing < %d (NPC.2)"
+ spacing NPC LICON 90 surround_ok "NPC to non-poly LICON spacing < %d (LICON.13)"
+ angles NPC 45 "Only 45 degree angles allowed on NPC (X.3)"
+ off_grid NPC 5 "NPC shape not on %d grid (X.1b)"
+
+ # HVTP rules
+
+ width HVTP 380 "HVTP width < %d (HVTP.1)"
+ spacing HVTP HVTP 700 touching_ok "HVTP to HVTP spacing < %d (HVTP.2)"
+ area HVTP 265000 380 "HVTP minimum area < %a (HVTP.5)"
+ angles HVTP 45 "Only 45 degree angles allowed on HVTP (X.3)"
+ off_grid HVTP 5 "HVTP shape not on %d grid (X.1b)"
+
+ # HVI rules
+
+ width HVI 600 "HVI width < %d (HVI.1)"
+ spacing HVI HVI 700 touching_ok "HVI to HVI spacing < %d (HVI.2)"
+ spacing HVI NWELL 700 surround_ok "HVI to NWELL spacint < %d (HVI.5)"
+ no_overlap HVI TUNM
+ off_grid HVI 5 "HVI shape not on %d grid (X.1b)"
+
+ # NSDM rules
+
+ width NSDM 380 "NSDM width < %d (NSDM.1)"
+ spacing NSDM NSDM 380 touching_ok "NSDM to NSDM spacing < %d (NSDM.2)"
+ angles NSDM 45 "Only 45 degree angles allowed on NSDM (X.3)"
+ off_grid NSDM 5 "NSDM shape not on %d grid (X.1b)"
+
+ # PSDM rules
+
+ width PSDM 380 "PSDM width < %d (PSDM.1)"
+ spacing PSDM PSDM 380 touching_ok "PSDM to PSDM spacing < %d (PSDM.2)"
+ angles PSDM 45 "Only 45 degree angles allowed on PSDM (X.3)"
+ off_grid PSDM 5 "PSDM shape not on %d grid (X.1b)"
+
+end
+
+extract
+style default
+ planeorder p1 0
+ planeorder p2 1
+ planeorder p3 2
+ planeorder p4 3
+ planeorder p5 4
+ planeorder p6 5
+ planeorder p7 6
+ planeorder p8 7
+ planeorder p9 8
+ planeorder p10 9
+ planeorder p11 10
+ planeorder p12 11
+ planeorder p13 12
+ planeorder p14 13
+ planeorder p15 14
+ planeorder p16 15
+ planeorder p17 16
+ planeorder p18 17
+ planeorder p19 18
+ planeorder p20 19
+ planeorder p21 20
+ planeorder p22 21
+ planeorder p23 22
+ planeorder p24 23
+ planeorder p25 24
+ planeorder p26 25
+ planeorder p27 26
+ planeorder p28 27
+ planeorder p29 28
+ planeorder p30 29
+ planeorder p31 30
+ planeorder p32 31
+ planeorder p33 32
+ planeorder p34 33
+ planeorder p35 34
+ planeorder p36 35
+ planeorder p37 36
+ planeorder p38 37
+ planeorder p39 38
+ planeorder p40 39
+ planeorder p41 40
+ planeorder p42 41
+ planeorder p43 42
+end

mag/sky130A.magicrc

diff --git a/mag/sky130A.magicrc b/mag/sky130A.magicrc
new file mode 100755
index 0000000..52d0ed8
--- /dev/null
+++ b/mag/sky130A.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch.  This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+    scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDK_ROOT
+# "file nativename" guards against a local PDK_ROOT with "~" in the name
+if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} {
+    set PDK_ROOT /foss/pdk
+}
+
+# loading technology
+tech load $PDK_ROOT/sky130A/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDK_ROOT/sky130A/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDK_ROOT/sky130A/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid 
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+   set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}]} {
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_pr
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_io
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_osu_sc
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+    addpath ${PDK_ROOT}/sky130A/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_pr/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_io/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_osu_sc/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+    addpath ${PDK_ROOT}/sky130A/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog.  This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space.  Defined in the PDK script.
+catch {magic::query_my_projects}

mag/sky130A.tcl

diff --git a/mag/sky130A.tcl b/mag/sky130A.tcl
new file mode 100755
index 0000000..ba595d8
--- /dev/null
+++ b/mag/sky130A.tcl
@@ -0,0 +1,7194 @@
+#-----------------------------------------------------
+# Magic/TCL design kit for SKYWATER sky130A
+#-----------------------------------------------------
+# Tim Edwards
+# Revision 1	ALPHA   9/10/2020
+#-----------------------------------------------------
+
+if {[catch {set TECHPATH $env(PDK_ROOT)}]} {
+    set TECHPATH /foss/pdk
+}
+if [catch {set PDKPATH}] {set PDKPATH ${TECHPATH}/sky130A}
+set PDKNAME sky130A
+# "sky130" is the namespace used for all devices
+set PDKNAMESPACE sky130
+puts stdout "Loading sky130A Device Generator Menu ..."
+
+# Initialize toolkit menus to the wrapper window
+
+global Opts
+namespace eval sky130 {}
+
+# Set the window callback
+if [catch {set Opts(callback)}] {set Opts(callback) ""}
+set Opts(callback) [subst {sky130::addtechmenu \$framename; $Opts(callback)}]
+
+# if {![info exists Opts(cmdentry)]} {set Opts(cmdentry) 1}
+
+# Set options specific to this PDK
+set Opts(hidelocked) 1
+set Opts(hidespecial) 0
+
+# Wrap the closewrapper procedure so that closing the last
+# window is equivalent to quitting.
+if {[info commands closewrapper] == "closewrapper"} {
+   rename closewrapper closewrapperonly
+   proc closewrapper { framename } {
+      if {[llength [windownames all]] <= 1} {
+         magic::quit
+      } else {
+         closewrapperonly $framename
+      }
+   }
+}
+
+# Remove maze router layers from the toolbar by locking them
+tech lock fence,magnet,rotate
+
+namespace eval sky130 {
+    namespace path {::tcl::mathop ::tcl::mathfunc}
+
+    set ruleset [dict create]
+
+    # Process DRC rules (magic style)
+
+    dict set ruleset poly_surround    0.08      ;# Poly surrounds contact
+    dict set ruleset diff_surround    0.06      ;# Diffusion surrounds contact
+    dict set ruleset gate_to_diffcont 0.145     ;# Gate to diffusion contact center
+    dict set ruleset gate_to_polycont 0.275     ;# Gate to poly contact center
+    dict set ruleset gate_extension   0.13      ;# Poly extension beyond gate
+    dict set ruleset diff_extension   0.29      ;# Diffusion extension beyond gate
+    dict set ruleset contact_size     0.17      ;# Minimum contact size
+    dict set ruleset via_size         0.17      ;# Minimum via size
+    dict set ruleset metal_surround   0.08      ;# Local interconnect overlaps contact
+    dict set ruleset sub_surround     0.18      ;# Sub/well surrounds diffusion
+    dict set ruleset diff_spacing     0.28      ;# Diffusion spacing rule
+    dict set ruleset poly_spacing     0.21      ;# Poly spacing rule
+    dict set ruleset diff_poly_space  0.075     ;# Diffusion to poly spacing rule
+    dict set ruleset diff_gate_space  0.20      ;# Diffusion to gate poly spacing rule
+    dict set ruleset metal_spacing    0.23      ;# Local interconnect spacing rule
+    dict set ruleset mmetal_spacing   0.14      ;# Metal spacing rule (above local interconnect)
+    dict set ruleset res_to_cont      0.20      ;# resistor to contact center
+    dict set ruleset res_diff_space   0.20      ;# resistor to guard ring
+}
+
+#-----------------------------------------------------
+# magic::addtechmenu
+#-----------------------------------------------------
+
+proc sky130::addtechmenu {framename} {
+   global Winopts Opts
+   
+   # Check for difference between magic 8.1.125 and earlier, and 8.1.126 and later
+   if {[catch {${framename}.titlebar cget -height}]} {
+      set layoutframe ${framename}.pane.top
+   } else {
+      set layoutframe ${framename}
+   }
+
+   # List of devices is long.  Divide into two sections for active and passive deivces
+   magic::add_toolkit_menu $layoutframe "Devices 1" pdk1
+
+   magic::add_toolkit_command $layoutframe "nmos (MOSFET)" \
+	    "magic::gencell sky130::sky130_fd_pr__nfet_01v8" pdk1
+   magic::add_toolkit_command $layoutframe "pmos (MOSFET)" \
+	    "magic::gencell sky130::sky130_fd_pr__pfet_01v8" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+   magic::add_toolkit_command $layoutframe "n-diode" \
+	    "magic::gencell sky130::sky130_fd_pr__diode_pw2nd_05v5" pdk1
+   magic::add_toolkit_command $layoutframe "p-diode" \
+	    "magic::gencell sky130::sky130_fd_pr__diode_pd2nw_05v5" pdk1
+   magic::add_toolkit_command $layoutframe "photodiode" \
+	    "magic::gencell sky130::sky130_fd_pr__photodiode" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+   magic::add_toolkit_command $layoutframe "MOS varactor" \
+	    "magic::gencell sky130::sky130_fd_pr__cap_var_lvt" pdk1
+   magic::add_toolkit_separator	$layoutframe pdk1
+
+   magic::add_toolkit_command $layoutframe "NPN 1.0 x 1.0" \
+	    "magic::gencell sky130::sky130_fd_pr__rf_npn_05v5_W1p00L1p00" pdk1
+   magic::add_toolkit_command $layoutframe "NPN 1.0 x 2.0" \
+	    "magic::gencell sky130::sky130_fd_pr__rf_npn_05v5_W1p00L2p00" pdk1
+   magic::add_toolkit_command $layoutframe "PNP 0.68 x 0.68" \
+	    "magic::gencell sky130::sky130_fd_pr__rf_pnp_05v5_W0p68L0p68" pdk1
+   magic::add_toolkit_command $layoutframe "PNP 3.4 x 3.4" \
+	    "magic::gencell sky130::sky130_fd_pr__rf_pnp_05v5_W3p40L3p40" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+
+   magic::add_toolkit_command $layoutframe "inductor 1" \
+	    "magic::gencell sky130::sky130_fd_pr__rf_test_coil1" pdk1
+   magic::add_toolkit_command $layoutframe "inductor 2" \
+	    "magic::gencell sky130::sky130_fd_pr__rf_test_coil2" pdk1
+   magic::add_toolkit_command $layoutframe "inductor 3" \
+	    "magic::gencell sky130::sky130_fd_pr__rf_test_coil3" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+
+   magic::add_toolkit_command $layoutframe "substrate contact (1.8V)" \
+	    "sky130::subconn_draw" pdk1
+   magic::add_toolkit_command $layoutframe "substrate contact (5.0V)" \
+	    "sky130::mvsubconn_draw" pdk1
+   magic::add_toolkit_command $layoutframe "deep n-well region" \
+	    "sky130::deep_nwell_draw" pdk1
+   magic::add_toolkit_command $layoutframe "mcon" \
+	    "sky130::mcon_draw" pdk1
+   magic::add_toolkit_command $layoutframe "via1" \
+	    "sky130::via1_draw" pdk1
+   magic::add_toolkit_command $layoutframe "via2" \
+	    "sky130::via2_draw" pdk1
+   magic::add_toolkit_command $layoutframe "via3" \
+	    "sky130::via3_draw" pdk1
+   magic::add_toolkit_command $layoutframe "via4" \
+	    "sky130::via4_draw" pdk1
+   
+
+   magic::add_toolkit_menu $layoutframe "Devices 2" pdk2
+
+   magic::add_toolkit_command $layoutframe "n-diff resistor (1.8V) - 120 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_nd" pdk2
+   magic::add_toolkit_command $layoutframe "p-diff resistor (1.8V) - 197 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_pd" pdk2
+   magic::add_toolkit_command $layoutframe "n-diff resistor (5.0V) - 114 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_nd__hv" pdk2
+   magic::add_toolkit_command $layoutframe "p-diff resistor (5.0V) - 191 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_pd__hv" pdk2
+
+   magic::add_toolkit_command $layoutframe "poly resistor - 48.2 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_po" pdk2
+   magic::add_toolkit_command $layoutframe "poly resistor - 319.8 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_high_po_0p35" pdk2
+   magic::add_toolkit_command $layoutframe "poly resistor - 2000 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_xhigh_po_0p35" pdk2
+   magic::add_toolkit_command $layoutframe "p-well resistor - 3050 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_iso_pw" pdk2
+   magic::add_toolkit_separator	$layoutframe pdk2
+
+   magic::add_toolkit_command $layoutframe "l1 metal resistor - 12.2 Ohm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_l1" pdk2
+   magic::add_toolkit_command $layoutframe "m1 metal resistor - 125 mOhm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_m1" pdk2
+   magic::add_toolkit_command $layoutframe "m2 metal resistor - 125 mOhm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_m2" pdk2
+   magic::add_toolkit_command $layoutframe "m3 metal resistor - 47 mOhm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_m3" pdk2
+   magic::add_toolkit_command $layoutframe "m4 metal resistor - 47 mOhm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_m4" pdk2
+   magic::add_toolkit_command $layoutframe "m5 metal resistor - 29 mOhm/sq" \
+	    "magic::gencell sky130::sky130_fd_pr__res_generic_m5" pdk2
+
+   magic::add_toolkit_command $layoutframe "MiM cap - 2fF/um^2 (metal3)" \
+	    "magic::gencell sky130::sky130_fd_pr__cap_mim_m3_1" pdk2
+   magic::add_toolkit_command $layoutframe "MiM cap - 2fF/um^2 (metal4)" \
+	    "magic::gencell sky130::sky130_fd_pr__cap_mim_m3_2" pdk2
+   magic::add_toolkit_separator	$layoutframe pdk2
+
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 m1-m4, li/m5 shield" \
+	    "magic::gencell sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 11.5x11.7 m1-m2" \
+	    "magic::gencell sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 8.6x7.8 m1-m2 l1 shield" \
+	    "magic::gencell sky130::sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1" pdk2
+   magic::add_toolkit_command $layoutframe "vpp 4.4x4.6 m1-m2 l1 shield" \
+	    "magic::gencell sky130::sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1" pdk2
+
+   # Additional DRC style for routing only---add this to the DRC menu
+   ${layoutframe}.titlebar.mbuttons.drc.toolmenu add command -label "DRC Routing" -command {drc style drc(routing)}
+
+   # Add SPICE import function to File menu
+   ${layoutframe}.titlebar.mbuttons.file.toolmenu insert 4 command -label "Import SPICE" -command {sky130::importspice}
+   ${layoutframe}.titlebar.mbuttons.file.toolmenu insert 4 separator
+
+   # Add command entry window by default if enabled
+   if {[info exists Opts(cmdentry)]} {
+      set Winopts(${framename},cmdentry) $Opts(cmdentry)
+   } else {
+      set Winopts(${framename},cmdentry) 0
+   }
+   if {$Winopts(${framename},cmdentry) == 1} {
+      addcommandentry $framename
+   }
+}
+
+#----------------------------------------------------------------
+# Menu callback function to read a SPICE netlist and generate an
+# initial layout using the SKYWATER sky130A gencells.
+#----------------------------------------------------------------
+
+proc sky130::importspice {} {
+   global CAD_ROOT
+
+   set Layoutfilename [ tk_getOpenFile -filetypes \
+	    {{SPICE {.spice .spc .spi .ckt .cir .sp \
+	    {.spice .spc .spi .ckt .cir .sp}}} {"All files" {*}}}]
+   if {$Layoutfilename != ""} {
+      magic::netlist_to_layout $Layoutfilename sky130
+   }
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mcon_draw {{dir default}} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.17} {
+      puts stderr "Mcon width must be at least 0.17um"
+      return
+   }
+   if {$h < 0.17} {
+      puts stderr "Mcon height must be at least 0.17um"
+      return
+   }
+   suspendall
+   paint mcon
+   pushbox
+   if {($w < $h) || ($dir == "vert")} {
+       box grow e 0.03um
+       box grow w 0.03um
+       box grow n 0.06um
+       box grow s 0.06um
+       paint m1
+   } else {
+       box grow n 0.03um
+       box grow s 0.03um
+       box grow e 0.06um
+       box grow w 0.06um
+       paint m1
+   }
+   popbox
+   resumeall
+}
+
+proc sky130::via1_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.26} {
+      puts stderr "Via1 width must be at least 0.26um"
+      return
+   }
+   if {$h < 0.26} {
+      puts stderr "Via1 height must be at least 0.26um"
+      return
+   }
+   suspendall
+   paint via1
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m2
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m1
+   box grow e -0.05um
+   box grow w -0.05um
+   resumeall
+}
+
+proc sky130::via2_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.28} {
+      puts stderr "Via2 width must be at least 0.28um"
+      return
+   }
+   if {$h < 0.28} {
+      puts stderr "Via2 height must be at least 0.28um"
+      return
+   }
+   suspendall
+   pushbox
+   paint via2
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m2
+   popbox
+   pushbox
+   box grow n 0.025um
+   box grow s 0.025um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m3
+   popbox
+   resumeall
+}
+
+proc sky130::via3_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.32} {
+      puts stderr "Via3 width must be at least 0.32um"
+      return
+   }
+   if {$h < 0.32} {
+      puts stderr "Via3 height must be at least 0.32um"
+      return
+   }
+   suspendall
+   pushbox
+   paint via3
+   box grow n 0.005um
+   box grow s 0.005um
+   box grow e 0.005um
+   box grow w 0.005um
+   paint m4
+   popbox
+   pushbox
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m3
+   popbox
+   resumeall
+}
+
+proc sky130::via4_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 1.18} {
+      puts stderr "Via3 width must be at least 1.18um"
+      return
+   }
+   if {$h < 1.18} {
+      puts stderr "Via3 height must be at least 1.18um"
+      return
+   }
+   suspendall
+   paint via4
+   pushbox
+   box grow n 0.12um
+   box grow s 0.12um
+   box grow e 0.12um
+   box grow w 0.12um
+   paint m5
+   popbox
+   resumeall
+}
+
+proc sky130::subconn_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.17} {
+      puts stderr "Substrate tap width must be at least 0.17um"
+      return
+   }
+   if {$h < 0.17} {
+      puts stderr "Substrate tap height must be at least 0.17um"
+      return
+   }
+   suspendall
+   paint psc
+   pushbox
+   if {$w > $h} {
+      box grow e 0.08um
+      box grow w 0.08um
+      paint li
+      box grow e 0.04um
+      box grow w 0.04um
+   } else {
+      box grow n 0.08um
+      box grow s 0.08um
+      paint li
+      box grow n 0.04um
+      box grow s 0.04um
+   }
+   paint psd
+   popbox
+   resumeall
+}
+
+#----------------------------------------------------------------
+
+proc sky130::mvsubconn_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.17} {
+      puts stderr "Substrate tap width must be at least 0.17um"
+      return
+   }
+   if {$h < 0.17} {
+      puts stderr "Substrate tap height must be at least 0.17um"
+      return
+   }
+   suspendall
+   paint mvpsc
+   pushbox
+   if {$w > $h} {
+      box grow e 0.08um
+      box grow w 0.08um
+      paint li
+      box grow e 0.04um
+      box grow w 0.04um
+   } else {
+      box grow n 0.08um
+      box grow s 0.08um
+      paint li
+      box grow n 0.04um
+      box grow s 0.04um
+   }
+   paint mvpsd
+   popbox
+   resumeall
+}
+
+#----------------------------------------------------------------
+
+proc sky130::deep_nwell_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 3.0} {
+      puts stderr "Deep-nwell region width must be at least 3.0um"
+      return
+   }
+   if {$h < 3.0} {
+      puts stderr "Deep-nwell region height must be at least 3.0um"
+      return
+   }
+   suspendall
+   tech unlock *
+   paint dnwell
+   pushbox
+   pushbox
+   box grow c 0.4um
+   paint nwell
+   box grow c -1.43um
+   erase nwell
+   popbox
+   box grow c 0.03um
+
+   pushbox
+   box width 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow n -0.3um
+   box grow s -0.3um
+   paint nsc
+   popbox
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   pushbox
+   box height 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow e -0.3um
+   box grow w -0.3um
+   paint nsc
+   popbox
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   pushbox
+   box move n [box height]i
+   box height 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow e -0.3um
+   box grow w -0.3um
+   paint nsc
+   popbox
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   pushbox
+   box move e [box width]i
+   box width 0
+   box grow c 0.085um
+   paint li
+   pushbox
+   box grow n -0.3um
+   box grow s -0.3um
+   paint nsc
+   box grow c 0.1um
+   paint nsd
+   popbox
+
+   popbox
+   tech revert
+   resumeall
+}
+
+#----------------------------------------------------------------
+
+proc sky130::res_recalc {field parameters} {
+    set snake 0
+    set sterm 0.0
+    set caplen 0
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set val [magic::spice2float $val]
+    set l [magic::spice2float $l]
+    set w [magic::spice2float $w]
+
+    if {$snake == 0} {
+	# Straight resistor calculation
+	switch  $field {
+	    val { set l [expr ($val * ($w - $dw) - (2 * $term)) / $rho]
+		  set w [expr ((2 * $term + $l * $rho) / $val) + $dw]
+		}
+	    w   { set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+		  set l [expr ($val * ($w - $dw) - (2 * $term)) / $rho]
+		}
+	    l   { set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+		  set w [expr ((2 * $term + $l * $rho) / $val) + $dw]
+		}
+	}
+    } else {
+        set term [expr $term + $sterm]
+	# Snake resistor calculation
+	switch  $field {
+	    val { set l [expr (($val - $rho * ($nx - 1)) * ($w - $dw) \
+			- (2 * $term) - ($rho * $caplen * ($nx - 1))) \
+			/ ($rho * $nx)]
+
+		  set w [expr ((2 * $term + $l * $rho * $nx \
+			+ $caplen * $rho * ($nx - 1)) \
+			/ ($val - $rho * ($nx - 1))) + $dw]
+		}
+	    w   { set val [expr $rho * ($nx - 1) + ((2 * $term) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+
+		  set l [expr (($val - $rho * ($nx - 1)) * ($w - $dw) \
+			- (2 * $term) - ($rho * $caplen * ($nx - 1))) \
+			/ ($rho * $nx)]
+		}
+	    l   { set val [expr $rho * ($nx - 1) + ((2 * $term) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+
+		  set w [expr ((2 * $term + $l * $rho * $nx \
+			+ $caplen * $rho * ($nx - 1)) \
+			/ ($val - $rho * ($nx - 1))) + $dw]
+		}
+	}
+    }
+
+    set val [magic::3digitpastdecimal $val]
+    set w [magic::3digitpastdecimal $w]
+    set l [magic::3digitpastdecimal $l]
+
+    dict set parameters val $val
+    dict set parameters w $w
+    dict set parameters l $l
+
+    return $parameters
+}
+
+#----------------------------------------------------------------
+# Drawn diode routines
+#----------------------------------------------------------------
+
+proc sky130::diode_recalc {field parameters} {
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    switch  $field {
+	area { puts stdout "area changed" }
+	peri { puts stdout "perimeter changed" }
+	w   { puts stdout "width changed" }
+	l   { puts stdout "length changed" }
+    }
+    dict set parameters area $area
+    dict set parameters peri $peri
+    dict set parameters w $w
+    dict set parameters l $l
+}
+
+#----------------------------------------------------------------
+# diode: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::diode_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w -
+	    peri {
+		# Length, width, and perimeter are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    area {
+		# area also converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e12]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+                # Convert m to ny
+		dict set pdkparams ny $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+# diode: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::diode_dialog {device parameters} {
+    # Editable fields:      w, l, area, perim, nx, ny
+
+    magic::add_entry area "Area (um^2)" $parameters
+    magic::add_entry peri "Perimeter (um)" $parameters
+    sky130::compute_aptot $parameters
+    magic::add_message atot "Total area (um^2)" $parameters
+    magic::add_message ptot "Total perimeter (um)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry ny "Y Repeat" $parameters
+
+    if {[dict exists $parameters compatible]} {
+       set sellist [dict get $parameters compatible]
+       magic::add_selectlist gencell "Device type" $sellist $parameters $device
+    }
+
+    if {[dict exists $parameters doverlap]} {
+	magic::add_checkbox doverlap "Overlap at end contact" $parameters
+    }
+    if {[dict exists $parameters elc]} {
+        magic::add_checkbox elc "Add left end contact" $parameters
+    }
+    if {[dict exists $parameters erc]} {
+        magic::add_checkbox erc "Add right end contact" $parameters
+    }
+    if {[dict exists $parameters etc]} {
+        magic::add_checkbox etc "Add top end contact" $parameters
+    }
+    if {[dict exists $parameters ebc]} {
+        magic::add_checkbox ebc "Add bottom end contact" $parameters
+    }
+
+    if {[dict exists $parameters guard]} {
+        magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    }
+    if {[dict exists $parameters glc]} {
+        magic::add_checkbox glc "Add left guard ring contact" $parameters
+    }
+    if {[dict exists $parameters grc]} {
+        magic::add_checkbox grc "Add right guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+        magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gbc]} {
+        magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+    if {[dict exists $parameters viagb]} {
+	magic::add_entry viagb  "Bottom guard ring via coverage \[+/-\](%)" $parameters
+    }
+    if {[dict exists $parameters viagt]} {
+	magic::add_entry viagt  "Top guard ring via coverage \[+/-\](%)" $parameters
+    }
+    if {[dict exists $parameters viagr]} {
+	magic::add_entry viagr  "Right guard ring via coverage \[+/-\](%)" $parameters
+    }
+    if {[dict exists $parameters viagl]} {
+	magic::add_entry viagl  "Left guard ring via coverage \[+/-\](%)" $parameters
+    }
+
+    if {[dict exists $parameters vias]} {
+	magic::add_checkbox vias "Add vias over contacts" $parameters
+    }
+
+    magic::add_dependency sky130::diode_recalc $device sky130 l w area peri
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+}
+
+#----------------------------------------------------------------
+# Diode total area and perimeter computation
+#----------------------------------------------------------------
+
+proc sky130::compute_aptot {parameters} {
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set area [magic::spice2float $area]
+    set area [magic::3digitpastdecimal $area]
+    set peri [magic::spice2float $peri]
+    set peri [magic::3digitpastdecimal $peri]
+
+    # Compute total area
+    catch {set magic::atot_val [expr ($area * $nx * $ny)]}
+    # Compute total perimeter
+    catch {set magic::ptot_val [expr ($peri * $nx * $ny)]}
+}
+
+#----------------------------------------------------------------
+# diode: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::diode_check {parameters} {
+
+    set guard 0
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l] 
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w] 
+
+    set area [magic::spice2float $area]
+    set area [magic::3digitpastdecimal $area] 
+    set peri [magic::spice2float $peri]
+    set peri [magic::3digitpastdecimal $peri] 
+
+    if {$l == 0} {
+        # Calculate L from W and area
+	set l [expr ($area / $w)]
+	dict set parameters l [magic::float2spice $l]
+    } elseif {$w == 0} {
+        # Calculate W from L and area
+	set w [expr ($area / $l)]
+	dict set parameters w [magic::float2spice $w]
+    }
+    if {$w < $wmin} {
+	puts stderr "Diode width must be >= $wmin"
+	dict set parameters w $wmin
+    } 
+    if {$l < $lmin} {
+	puts stderr "Diode length must be >= $lmin"
+	dict set parameters l $lmin
+    } 
+
+    # Check via coverage for syntax
+    if {$guard == 1} {
+    	if {[catch {expr abs($viagb)}]} {
+	    puts stderr "Guard ring bottom via coverage must be numeric!"
+            dict set parameters viagb 0
+    	} elseif {[expr abs($viagb)] > 100} {
+	    puts stderr "Guard ring bottom via coverage can't be more than 100%"
+            dict set parameters viagb 100
+    	}
+    	if {[catch {expr abs($viagt)}]} {
+	    puts stderr "Guard ring top via coverage must be numeric!"
+            dict set parameters viagt 0
+	} elseif {[expr abs($viagt)] > 100} {
+	    puts stderr "Guard ring top via coverage can't be more than 100%"
+            dict set parameters viagt 100
+	}
+	if {[catch {expr abs($viagr)}]} {
+	    puts stderr "Guard ring right via coverage must be numeric!"
+            dict set parameters viagr 0
+	} elseif {[expr abs($viagr)] > 100} {
+	    puts stderr "Guard ring right via coverage can't be more than 100%"
+            dict set parameters viagr 100
+   	} 
+        if {[catch {expr abs($viagl)}]} {
+	    puts stderr "Guard ring left via coverage must be numeric!"
+            dict set parameters viagl 0
+	} elseif {[expr abs($viagl)] > 100} {
+	   puts stderr "Guard ring left via coverage can't be more than 100%"
+           dict set parameters viagl 100
+	}
+    }
+
+    # Calculate area and perimeter from L and W
+    set area [expr ($l * $w)]
+    dict set parameters area [magic::float2spice $area]
+    set peri [expr (2 * ($l + $w))]
+    dict set parameters peri [magic::float2spice $peri]
+    sky130::compute_aptot $parameters
+
+    return $parameters
+}
+
+#------------------------------------------------------------------
+# NOTE:  sky130_fd_pr__diode_pw2nd_05v5_lvt,
+# sky130_fd_pr__diode_pw2nd_05v5_nvt, sky130_fd_pr__diode_pd2nw_05v5_lvt,
+# and sky130_fd_pr__diode_pd2nw_11v0 are all considered parasitic diodes.
+# They may be generated by invoking the build procedure on the
+# command line.  To enable them in the PDK, add them to the
+# appropriate compatible {} list.
+#------------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt \
+	sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_lvt_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt \
+	sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_nvt_defaults {} {
+    return {w 0.45 l 0.45 area 0.2024 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt \
+	sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_11v0_defaults {} {
+    return {w 0.45 l 0.45 area 0.2024 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt \
+	sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__photodiode_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 xstep 8.0 ystep 8.0}
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pd2nw_05v5 sky130_fd_pr__diode_pd2nw_05v5_lvt \
+	sky130_fd_pr__diode_pd2nw_05v5_hvt sky130_fd_pr__diode_pd2nw_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_lvt_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pd2nw_05v5 sky130_fd_pr__diode_pd2nw_05v5_lvt \
+	sky130_fd_pr__diode_pd2nw_05v5_hvt sky130_fd_pr__diode_pd2nw_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_hvt_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pd2nw_05v5 sky130_fd_pr__diode_pd2nw_05v5_lvt \
+	sky130_fd_pr__diode_pd2nw_05v5_hvt sky130_fd_pr__diode_pd2nw_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+
+proc sky130::sky130_fd_pr__diode_pd2nw_11v0_defaults {} {
+    return {w 0.45 l 0.45 area 0.2024 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 1 gbc 1 doverlap 0 \
+	compatible {sky130_fd_pr__diode_pd2nw_05v5 sky130_fd_pr__diode_pd2nw_05v5_lvt \
+	sky130_fd_pr__diode_pd2nw_05v5_hvt sky130_fd_pr__diode_pd2nw_11v0} \
+	full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_lvt_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_nvt_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_11v0_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__photodiode_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_lvt_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_hvt_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_11v0_convert {parameters} {
+    return [sky130::diode_convert $parameters]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pw2nd_05v5 $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_lvt_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pw2nd_05v5_lvt $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_nvt_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pw2nd_05v5_nvt $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_11v0_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pw2nd_11v0 $parameters
+}
+
+proc sky130::sky130_fd_pr__photodiode_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pd2nw_05v5 $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_lvt_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pd2nw_05v5_lvt $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_hvt_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pd2nw_05v5_hvt $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_11v0_dialog {parameters} {
+    sky130::diode_dialog sky130_fd_pr__diode_pd2nw_11v0 $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_lvt_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_nvt_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pw2nd_11v0_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::sky130_fd_pr__photodiode_check {parameters} {
+    sky130::fixed_check $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_lvt_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_hvt_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+proc sky130::sky130_fd_pr__diode_pd2nw_11v0_check {parameters} {
+    sky130::diode_check $parameters
+}
+
+#----------------------------------------------------------------
+# Diode: Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::diode_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set dev_surround 0
+    set dev_sub_type ""
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # If there is no end_sub_surround, set it to sub_surround
+    if {![dict exists $parameters end_sub_surround]} {
+	set end_sub_surround $sub_surround
+    }
+
+    # Draw the device
+    pushbox
+    box size 0 0
+
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    # Calculate ring size (measured to contact center)
+    set gx [+ $w [* 2.0 [+ $dev_spacing $dev_surround]] $contact_size]
+    set gy [+ $l [* 2.0 [+ $dev_spacing $dev_surround]] $contact_size]
+
+    # Draw the ring first, because diode may occupy well/substrate plane
+    set guardparams $parameters
+    dict set guardparams plus_diff_type $end_type
+    dict set guardparams plus_contact_type $end_contact_type
+    dict set guardparams diff_surround $end_surround
+    dict set guardparams sub_type $end_sub_type
+    dict set guardparams sub_surround $sub_surround
+    dict set guardparams guard_sub_surround $end_sub_surround
+    dict set guardparams glc $elc
+    dict set guardparams grc $erc
+    dict set guardparams gtc $etc
+    dict set guardparams gbc $ebc
+    set cext [sky130::guard_ring $gx $gy $guardparams]
+
+    pushbox
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+    paint ${dev_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+
+    if {$dev_sub_type != ""} {
+	box grow n ${sub_surround}um
+	box grow s ${sub_surround}um
+	box grow e ${sub_surround}um
+	box grow w ${sub_surround}um
+	paint ${dev_sub_type}
+    }
+    popbox
+
+    if {${w} < ${l}} {
+	set orient vert
+    } else {
+	set orient horz
+    }
+
+    # Reduce width by surround amount
+    set w [- $w [* ${dev_surround} 2.0]]
+    set l [- $l [* ${dev_surround} 2.0]]
+
+    # Draw via over contact first
+    if {$vias != 0} {
+        pushbox
+        set ch $l
+    	if {$ch < $via_size} {set ch $via_size}
+    	set cw $w
+    	if {$cw < $via_size} {set cw $via_size}
+	box grow n [/ $ch 2]um
+	box grow s [/ $ch 2]um
+	box grow w [/ $cw 2]um
+	box grow e [/ $cw 2]um
+        sky130::mcon_draw
+        popbox
+    }
+    set cext [sky130::unionbox $cext [sky130::draw_contact ${w} ${l} \
+		${dev_surround} ${metal_surround} ${contact_size} \
+		${dev_type} ${dev_contact_type} li ${orient}]]
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Diode: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::diode_draw {parameters} {
+    tech unlock *
+
+    # Set defaults if they are not in parameters
+    set doverlap 0	;# overlap diodes at contacts
+    set guard 0		;# draw a guard ring
+    set prohibit_overlap false  ;# don't prohibit overlaps
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set bbox [sky130::diode_device $parameters]
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # If prohibit_overlap is true, then end overlapping is prohibited when
+    # nx or ny is > 1 to prevent DRC errors (typically from well spacing rule)
+    if {$prohibit_overlap == true} {
+        if {($nx > 1) || ($ny > 1)} {
+	    set doverlap 0
+	}
+    }
+
+    # Determine tile width and height (depends on overlap)
+
+    if {$doverlap == 0} {
+	set dx [+ $fw $end_spacing]
+        set dy [+ $fh $end_spacing]
+    } else {
+        # overlap contact
+        set dx [- $fw [+ [* 2.0 $sub_surround] [* 2.0 $end_surround] $contact_size]]
+        set dy [- $fh [+ [* 2.0 $sub_surround] [* 2.0 $end_surround] $contact_size]]
+    }
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $ny 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $diff_spacing $diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $diff_spacing $diff_surround]] $contact_size]
+
+	# Draw the guard ring first, because diode may occupy well/substrate plane
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    if {($nx > 1) || ($ny > 1)} {
+	pushbox
+	set hfw [/ $fw 2.0]
+	set hfh [/ $fh 2.0]
+	box move w ${hfw}um
+	box move s ${hfh}um
+	box size ${corex}um ${corey}um
+	paint $end_sub_type
+	popbox
+    }
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $ny} {incr yp} {
+	    sky130::diode_device $parameters
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    tech revert
+}
+
+#----------------------------------------------------------------
+# Photodiode: Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::photodiode_device {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Draw the device
+    pushbox
+    box size 0 0
+
+    # Device has ntap fixed width of 0.41 x 0.41
+    # Surrounded by nwell 0.84 x 0.84
+    # Surrounded by deep nwell 3.0 x 3.0
+
+    pushbox
+    box grow c 0.205um
+    paint nsd
+    popbox
+    pushbox
+    box grow c 0.42um
+    paint nwell
+    popbox
+    pushbox
+    box grow c 1.5um
+    paint photo
+
+    set cext [sky130::getbox]
+
+    popbox
+
+    # Only enough space for one contact
+    set w ${contact_size}
+    set l ${contact_size}
+
+    set cext [sky130::unionbox $cext [sky130::draw_contact ${w} ${l} \
+		0 ${metal_surround} ${contact_size} \
+		nsd nsc li horz]]
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+
+proc sky130::photodiode_draw {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set bbox [sky130::photodiode_device $parameters]
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # Determine tile width and height
+
+    set dx [+ $fw $end_spacing]
+    set dy [+ $fh $end_spacing]
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $ny 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    # Calculate guard ring size (measured to contact center)
+    # Spacing between photodiode (deep nwell) and deep nwell (other) is 5.3um
+    set gx [+ $corex 15.965]
+    set gy [+ $corey 15.965]
+
+    pushbox
+
+    # The deep nwell is offset 0.315 from the nwell ring center to get the
+    # right overlap.  The deep nwell ring has a minimum width of 3um.
+    set hgx [/ $gx 2.0]
+    set hgy [/ $gy 2.0]
+    set dwx [+ $hgx 0.315]
+    set dwy [+ $hgy 0.315]
+    box grow e ${dwx}um
+    box grow w ${dwx}um
+    box grow n ${dwy}um
+    box grow s ${dwy}um
+    paint dnwell
+    box grow e -3.0um
+    box grow w -3.0um
+    box grow n -3.0um
+    box grow s -3.0um
+    erase dnwell
+
+    popbox
+
+    # Draw the guard ring first.  0.63 is the amount nwell surrounds contact;
+    # 0.63 * 2 + 0.17 = total nwell width 1.43um, needed to cover dnwell edge.
+    set newdict [dict create	 \
+	sub_type    space	 \
+	guard_sub_type	 nwell	 \
+	guard_sub_surround  0.63 \
+	plus_diff_type   nsd	 \
+	plus_contact_type nsc	 \
+    ]
+    set guarddict [dict merge $parameters $newdict]
+    sky130::guard_ring $gx $gy $guarddict
+
+    # Draw outside P-ring and generated the 2nd ring
+    set gx [+ $gx [* 2.0 [+ 0.56 $diff_spacing $diff_surround]] $contact_size]
+    set gy [+ $gy [* 2.0 [+ 0.56 $diff_spacing $diff_surround]] $contact_size]
+    sky130::guard_ring $gx $gy $parameters
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $ny} {incr yp} {
+	    sky130::photodiode_device $parameters
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		ndiode \
+	    dev_contact_type	ndic \
+	    end_type		psd \
+	    end_contact_type	psc \
+	    end_sub_type	psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	0 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+} 
+
+#----------------------------------------------------------------
+# NOTE:  Use ppd instead of psd so that there is additional
+# diffusion around the contact, allowing more space for the
+# implant (likewise sky130_fd_pr__diode_pd2nw_05v5_lvt and
+# sky130_fd_pr__diode_pd2nw_11v0).
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_lvt_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		ndiodelvt \
+	    dev_contact_type	ndilvtc \
+	    end_type		ppd \
+	    end_contact_type	psc \
+	    end_sub_type	psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+} 
+
+proc sky130::sky130_fd_pr__diode_pw2nd_05v5_nvt_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		nndiode \
+	    dev_contact_type	nndic \
+	    end_type		mvpsd \
+	    end_contact_type	mvpsc \
+	    end_sub_type	psub \
+	    dev_spacing		0.37 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.30 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+} 
+
+proc sky130::sky130_fd_pr__diode_pw2nd_11v0_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		mvndiode \
+	    dev_contact_type	mvndic \
+	    end_type		mvpsd \
+	    end_contact_type	mvpsc \
+	    end_sub_type	psub \
+	    diff_spacing	0.37 \
+	    dev_spacing		0.39 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.36 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		pdiode \
+	    guard		1 \
+	    dev_contact_type	pdic \
+	    end_type		nsd \
+	    end_contact_type	nsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	0 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_lvt_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		pdiodelvt \
+	    guard		1 \
+	    dev_contact_type	pdilvtc \
+	    end_type		nnd \
+	    end_contact_type	nsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pd2nw_05v5_hvt_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		pdiodehvt \
+	    guard		1 \
+	    dev_contact_type	pdihvtc \
+	    end_type		nnd \
+	    end_contact_type	nsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__diode_pd2nw_11v0_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		1 \
+	    dev_type 		mvpdiode \
+	    dev_contact_type	mvpdic \
+	    end_type		mvnsd \
+	    end_contact_type	mvnsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    sub_type		psub \
+	    diff_spacing	0.58 \
+	    dev_spacing		0.37 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.30 \
+	    end_sub_surround	0.33 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# The photodiode has its own drawing routine, so
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__photodiode_draw {parameters} {
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		1	\
+	    sub_type		space	\
+	    end_spacing		5.0	\
+	    end_surround	1.0	\
+	    sub_spacing		5.3	\
+	    guard_sub_type	pwell	\
+	    guard_sub_surround  0.18	\
+	    plus_diff_type	psd	\
+	    plus_contact_type	psc	\
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::photodiode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# Drawn capacitor routines
+# NOTE:  Work in progress.  These values need to be corrected.
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__cap_mim_m3_1_defaults {} {
+    return {w 2.00 l 2.00 val 8.0 carea 2.00 cperi 0.19 \
+		nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 \
+		lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 \
+		ccov 100}
+}
+proc sky130::sky130_fd_pr__cap_mim_m3_2_defaults {} {
+    return {w 2.00 l 2.00 val 8.0 carea 2.00 cperi 0.19 \
+		nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 \
+		lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 \
+		ccov 100}
+}
+
+
+#----------------------------------------------------------------
+# Recalculate capacitor values from GUI entries.
+# Recomputes W/L and Value as long as 2 of them are present
+# (To be completed)
+#----------------------------------------------------------------
+
+proc sky130::cap_recalc {field parameters} {
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    switch  $field {
+	val { puts stdout "value changed" }
+	w   { puts stdout "width changed" }
+	l   { puts stdout "length changed" }
+    }
+    dict set parameters val $val
+    dict set parameters w $w
+    dict set parameters l $l
+}
+
+#----------------------------------------------------------------
+# Capacitor defaults:
+#----------------------------------------------------------------
+#  w      Width of drawn cap
+#  l      Length of drawn cap
+#  nx     Number of devices in X
+#  ny     Number of devices in Y
+#  val    Default cap value
+#  carea  Area
+#  cperi  Perimeter
+#  dummy  Add dummy cap
+#  square Make square capacitor
+#
+#  (not user-editable)
+#
+#  wmin   Minimum allowed width
+#  lmin   Minimum allowed length
+#  dc     Area to remove to calculated area 
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# capacitor: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::cap_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w {
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+                # Convert m to ny
+		dict set pdkparams ny $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+proc sky130::sky130_fd_pr__cap_mim_m3_1_convert {parameters} {
+    return [cap_convert $parameters]
+}
+proc sky130::sky130_fd_pr__cap_mim_m3_2_convert {parameters} {
+    return [cap_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# capacitor: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::cap_dialog {device parameters} {
+    # Editable fields:      w, l, nx, ny, val
+    # Checked fields:  	    square, dummy
+
+    magic::add_entry val "Value (fF)" $parameters
+    sky130::compute_ctot $parameters
+    magic::add_message ctot "Total capacitance (pF)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry ny "Y Repeat" $parameters
+
+    if {[dict exists $parameters square]} {
+	magic::add_checkbox square "Square capacitor" $parameters
+    }
+    if {[dict exists $parameters bconnect]} {
+	magic::add_checkbox bconnect "Connect bottom plates in array" $parameters
+    }
+    if {[dict exists $parameters tconnect]} {
+	magic::add_checkbox tconnect "Connect top plates in array" $parameters
+    }
+    if {[dict exists $parameters ccov]} {
+    	magic::add_entry ccov "Capacitor contact coverage \[+/-\](%)" $parameters
+    }
+    if {[dict exists $parameters guard]} {
+	magic::add_checkbox guard "Add guard ring" $parameters
+    }
+
+    magic::add_dependency sky130::cap_recalc $device sky130 l w val
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+}
+
+proc sky130::sky130_fd_pr__cap_mim_m3_1_dialog {parameters} {
+    sky130::cap_dialog sky130_fd_pr__cap_mim_m3_1 $parameters
+}
+proc sky130::sky130_fd_pr__cap_mim_m3_2_dialog {parameters} {
+    sky130::cap_dialog sky130_fd_pr__cap_mim_m3_2 $parameters
+}
+
+#----------------------------------------------------------------
+# Capacitor total capacitance computation
+#----------------------------------------------------------------
+
+proc sky130::compute_ctot {parameters} {
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set val [magic::spice2float $val]
+    set val [magic::3digitpastdecimal $val]
+
+    # Compute total capacitance (and convert fF to pF)
+    catch {set magic::ctot_val [expr (0.001 * $val * $nx * $ny)]}
+}
+
+#----------------------------------------------------------------
+# Capacitor: Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::cap_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set cap_surround 0
+    set bot_surround 0
+    set top_surround 0
+    set end_spacing 0
+    set bconnect 0	    ;# bottom plates are connected in array
+    set cap_spacing 0	    ;# cap spacing in array
+    set top_metal_space 0   ;# top metal spacing (if larger than cap spacing)
+    set top_metal_width 0   ;# top metal minimum width
+    set contact_size 0	    ;# cap contact minimum size
+    set ccov 100	    ;# amount of contact coverage
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    if {![dict exists $parameters top_metal_space]} {
+	set top_metal_space $metal_spacing
+    }
+
+    # Draw the device
+    pushbox
+    box size 0 0
+
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    box grow e ${hw}um
+    box grow w ${hw}um
+    box grow n ${hl}um
+    box grow s ${hl}um
+    paint ${cap_type}
+    pushbox
+
+    # Find contact width if ccov is other than 100
+    set cmaxw [- $w [* $cap_surround 2]]
+    set cw [* $cmaxw [/ [expr abs($ccov)] 100.0]]
+    # Contact width must meet minimum
+    if {$cw < $contact_size} {set cw $contact_size}
+    if {$cw < $top_metal_width} {set cw $top_metal_width}
+    # Difference between maximum contact width and actual contact width
+    set cdif [- $cmaxw $cw]
+
+    # Reduce the box to the maximum contact area
+    box grow n -${cap_surround}um
+    box grow s -${cap_surround}um
+    box grow e -${cap_surround}um
+    box grow w -${cap_surround}um
+
+    set anchor [string index $ccov 0]
+    if {$anchor == "+"} {
+	box grow e -${cdif}um
+    } elseif {$anchor == "-"} {
+	box grow w -${cdif}um
+    } else {
+        set cdif [/ ${cdif} 2]
+	box grow w -${cdif}um
+	box grow e -${cdif}um
+    }
+    paint ${cap_contact_type}
+
+    pushbox
+    box grow n ${top_surround}um
+    box grow s ${top_surround}um
+    box grow e ${top_surround}um
+    box grow w ${top_surround}um
+    paint ${top_type}
+    set cext [sky130::getbox]
+    popbox
+    popbox
+    pushbox
+    box grow n ${bot_surround}um
+    box grow s ${bot_surround}um
+    box grow e ${bot_surround}um
+    box grow w ${bot_surround}um
+
+    paint ${bot_type}
+    # Create boundary using properties
+    property FIXED_BBOX [box values]
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+
+    # Calculate the distance from the top metal on the cap contact
+    # to the top metal on the end contact.
+    set top_met_sep [+ $end_spacing [- $cdif $top_surround]]
+
+    # Diagnostic!
+    puts stdout "cdif = $cdif"
+    puts stdout "top_met_sep = $top_met_sep"
+
+    # Increase end spacing if top metal spacing rule is not met
+    set loc_end_spacing $end_spacing
+    if {$top_met_sep < $top_metal_space} {
+	set loc_end_spacing [+ $loc_end_spacing [- $top_metal_space $top_met_sep]]
+    }
+    # Diagnostic!
+    puts stdout "loc_end_spacing = $loc_end_spacing"
+
+    # Extend bottom metal under contact to right
+    box grow e ${loc_end_spacing}um
+    set chw [/ ${contact_size} 2.0]
+    box grow e ${chw}um
+    box grow e ${end_surround}um
+    paint ${bot_type}
+
+    popbox
+    popbox
+
+    # Draw contact to right.  Reduce contact extent if devices are not
+    # wired together and the top metal spacing rule limits the distance
+    set lcont $l
+    if {($bconnect == 0) && ($ny > 1)} {
+	if {$cap_spacing < $top_metal_space} {
+	    set cspace [- $top_metal_space $cap_spacing]
+	    set lcont [- $l $cspace]
+	}
+    }
+
+    pushbox
+    box move e ${hw}um
+    box move e ${bot_surround}um
+    box move e ${loc_end_spacing}um
+    set cl [- [+ ${lcont} [* ${bot_surround} 2.0]] [* ${end_surround} 2.0]]
+    set cl [- ${cl} ${metal_surround}]  ;# see below
+    set cext [sky130::unionbox $cext [sky130::draw_contact 0 ${cl} \
+		${end_surround} ${metal_surround} ${contact_size} \
+		${bot_type} ${top_contact_type} ${top_type} full]]
+    popbox
+    popbox
+
+    return $cext
+
+    # cl shrinks top and bottom to accomodate larger bottom metal
+    # surround rule for contacts near a MiM cap.  This should be its
+    # own variable, but metal_surround is sufficient.
+}
+
+#----------------------------------------------------------------
+# Metal plate sandwich capacitor:  Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::sandwich_cap_device {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    pushbox
+    box size 0 0
+
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    set cw [- [* $hw [/ 2.0 3]] [* $cont_surround 2.0]]
+    set cl [- [* $hl [/ 2.0 3]] [* $cont_surround 2.0]]
+
+    # plate capacitor defines layers p0, p1, etc.
+    for {set i 0} {$i < 20} {incr i} {
+        if {[catch {set layer [subst \$p${i}_type]}]} {break}  ;# no more layers defined
+	pushbox
+	box grow e ${hw}um
+	box grow w ${hw}um
+	box grow n ${hl}um
+	box grow s ${hl}um
+        if {![catch {set shrink [subst \$p${i}_shrink]}]} {
+	    box grow e -${shrink}um
+	    box grow w -${shrink}um
+	    box grow n -${shrink}um
+	    box grow s -${shrink}um
+	    set cutout_spacing [+ [* ${shrink} 2.0] [/ $via_size 2.0] $cont_surround]
+	} else {
+	    set cutout_spacing 0
+	}
+
+	paint ${layer}
+
+	if {$i == 1} {
+	    # Note that cap_type geometry is coincident with p1_type.
+	    # Typically, this will define a layer that outputs as both
+	    # poly and a capacitor definition layer.
+	    if {[dict exists $parameters cap_type]} {
+		paint $cap_type
+	    }
+	}
+	popbox
+
+	# Even layers connect at corners, odd layers connect at sides.
+	# Even layers cut out the sides, odd layers cut out the corners.
+	# Layer zero has no side contacts or cutout.
+
+	if {[% $i 2] == 0} {
+	    set cornercmd  paint
+	    set cornersize $cutout_spacing
+	    set sidecmd    erase
+	    set nssidelong   [+ $cutout_spacing [/ $hw 3.0]]
+	    set ewsidelong   [+ $cutout_spacing [/ $hl 3.0]]
+	    set sideshort    $cutout_spacing
+	} else {
+	    set cornercmd  erase
+	    set cornersize $cutout_spacing
+	    set sidecmd    paint
+	    set nssidelong   [/ $hw 3.0]
+	    set ewsidelong   [/ $hl 3.0]
+	    set sideshort    $cutout_spacing
+	}
+
+	if {$i > 0} {
+	    pushbox
+	    box move e ${hw}um
+	    box grow n ${ewsidelong}um
+	    box grow s ${ewsidelong}um
+	    box grow w ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move n ${hl}um
+	    box grow e ${nssidelong}um
+	    box grow w ${nssidelong}um
+	    box grow s ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box grow n ${ewsidelong}um
+	    box grow s ${ewsidelong}um
+	    box grow e ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box grow e ${nssidelong}um
+	    box grow w ${nssidelong}um
+	    box grow n ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+
+	    pushbox
+	    box move n ${hl}um
+	    box move e ${hw}um
+	    box grow s ${cornersize}um
+	    box grow w ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move n ${hl}um
+	    box move w ${hw}um
+	    box grow s ${cornersize}um
+	    box grow e ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box move e ${hw}um
+	    box grow n ${cornersize}um
+	    box grow w ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box move w ${hw}um
+	    box grow n ${cornersize}um
+	    box grow e ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	}
+    }
+
+    # Draw contacts after all layers have been drawn, so that erasing
+    # layers does not affect the contacts.
+
+    for {set i 0} {$i < 20} {incr i} {
+        if {![catch {set contact [subst \$p${i}_contact_type]}]} {
+	    set layer [subst \$p${i}_type]
+	    set j [+ $i 1]
+	    set toplayer [subst \$p${j}_type]
+
+	    # Draw corner contacts
+	    pushbox
+	    box move e ${hw}um
+	    box move n ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box move n ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move e ${hw}um
+	    box move s ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box move s ${hl}um
+	    sky130::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+
+	    # Draw side contacts (except on poly)
+	    if {$i > 0} {
+		pushbox
+		box move w ${hw}um
+		sky130::draw_contact 0 ${cl} \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move e ${hw}um
+		sky130::draw_contact 0 ${cl} \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move n ${hl}um
+		sky130::draw_contact ${cw} 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move s ${hl}um
+		sky130::draw_contact ${cw} 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+	    }
+	} else {
+	    break
+	}
+    }
+
+    popbox
+    # Bounding box is the same as the device length and width
+    set cext [list -$hw -$hl $hw $hl]
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Capacitor: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::cap_draw {parameters} {
+    tech unlock *
+    set savesnap [snap]
+    snap internal
+
+    # Set defaults if they are not in parameters
+    set coverlap 0	;# overlap capacitors at contacts
+    set guard 0		;# draw a guard ring
+    set sandwich 0	;# this is not a plate sandwich capacitor
+    set cap_spacing 0	;# abutted caps if spacing is zero
+    set cap_diff_spacing 0
+    set wide_cap_spacing 0  ;# additional spacing for wide metal rule
+    set wide_cap_width 0
+    set end_spacing 0
+    set end_surround 0
+    set bot_surround 0
+    set top_metal_width 0
+    set bconnect 0	;# connect bottom plates in array
+    set tconnect 0	;# connect top plates in array
+    set top_type ""
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    if {$sandwich == 1} {
+	set bbox [sky130::sandwich_cap_device $parameters]
+    } else {
+	set bbox [sky130::cap_device $parameters]
+    }
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    set dwide 0
+    if {($fw >= $wide_cap_width) && ($fh >= $wide_cap_width)} {
+	set dwide $wide_cap_spacing
+    }
+
+    # Determine tile width and height (depends on overlap)
+    if {$coverlap == 0} {
+        set dy [+ $fh $cap_spacing $dwide]
+    } else {
+        # overlap at end contact
+        set dy [- $fh [+ $end_surround $end_surround $contact_size]]
+    }
+    # Contact is placed on right so spacing is determined by end_spacing.
+    set dx [+ $fw $end_spacing $dwide]
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $ny 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $cap_diff_spacing $diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $end_spacing $diff_surround]] $contact_size]
+
+	# Draw the guard ring first.
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    set twidth [+ ${contact_size} ${end_surround} ${end_surround}]
+    if {${twidth} < ${top_metal_width}} {
+	set twidth ${top_metal_width}
+    }
+    set hmw [/ $twidth 2.0]
+    set hdy [/ $dy 2.0]
+    set cdx [+ [/ ${w} 2.0] ${bot_surround} ${end_spacing}]
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $ny} {incr yp} {
+	    if {$sandwich == 1} {
+		sky130::sandwich_cap_device $parameters
+	    } else {
+		sky130::cap_device $parameters
+	    }
+	    if {$ny > 1} {
+		pushbox
+		box grow e ${hmw}um
+		box grow w ${hmw}um
+		box grow n ${hdy}um
+		box grow s ${hdy}um
+		if {($top_type != "") && ($tconnect == 1)} {
+		    paint ${top_type}
+		}
+		if {($top_type != "") && ($bconnect == 1)} {
+		    box move e ${cdx}um
+		    paint ${top_type}
+		}
+		popbox
+	    }
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    snap $savesnap
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__cap_mim_m3_1_draw {parameters} {
+    set newdict [dict create \
+	    top_type 		m4 \
+	    top_contact_type	via3 \
+	    cap_type 		mimcap \
+	    cap_contact_type	mimcc \
+	    bot_type 		m3 \
+	    bot_surround	0.5 \
+	    cap_spacing		0.5 \
+	    cap_surround	0.2 \
+	    top_surround	0.005 \
+	    end_surround	0.1 \
+	    end_spacing		0.1 \
+	    contact_size	0.32 \
+	    metal_surround	0.08 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::cap_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__cap_mim_m3_2_draw {parameters} {
+    set newdict [dict create \
+	    top_type 		m5 \
+	    top_contact_type	via4 \
+	    cap_type 		mimcap2 \
+	    cap_contact_type	mim2cc \
+	    bot_type 		m4 \
+	    bot_surround	0.5 \
+	    cap_spacing		0.5 \
+	    cap_surround	0.2 \
+	    top_surround	0.12 \
+	    end_surround	0.1 \
+	    end_spacing		0.1 \
+	    contact_size	1.18 \
+	    metal_surround	0.21 \
+	    top_metal_width	1.6 \
+	    top_metal_space	1.7 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::cap_draw $drawdict]
+}
+
+
+#----------------------------------------------------------------
+# capacitor: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::cap_check {parameters} {
+    # In case wmax and/or lmax are undefined
+    set lmax 0
+    set wmax 0
+    set ccov 100
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l] 
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w] 
+
+    set val   [magic::spice2float $val]
+    set carea [magic::spice2float $carea]
+    set cperi [magic::spice2float $cperi]
+    set dc    [magic::spice2float $dc]
+
+    if {$square == 1} {
+        # Calculate L and W from value
+	set a $carea
+	set b [expr $cperi * 4]
+	set c [expr -4 * $dc - $val]
+	set l [expr ((-$b + sqrt($b * $b - (4 * $a * $c))) / (2 * $a))]
+	dict set parameters l [magic::float2spice $l]
+	set w $l
+	dict set parameters w [magic::float2spice $w]
+    } elseif {$l == 0} {
+        # Calculate L from W and value
+	set l [expr (($val + 4 * $dc - 2 * $w * $cperi) / ($w * $carea + 2 * $cperi))]
+	dict set parameters l [magic::float2spice $l]
+    } elseif {$w == 0} {
+        # Calculate W from L and value
+	set w [expr (($val + 4 * $dc - 2 * $l * $cperi) / ($l * $carea + 2 * $cperi))]
+	dict set parameters w [magic::float2spice $w]
+    }
+    if {$w < $wmin} {
+	puts stderr "Capacitor width must be >= $wmin"
+	dict set parameters w $wmin
+	set w $wmin
+    } 
+    if {$l < $lmin} {
+	puts stderr "Capacitor length must be >= $lmin"
+	dict set parameters l $lmin
+	set l $lmin
+    } 
+    if {($wmax > 0) && ($w > $wmax)} {
+	puts stderr "Capacitor width must be <= $wmax"
+	dict set parameters w $wmax
+	set w $wmax
+    } 
+    if {($lmax > 0) && ($l > $lmax)} {
+	puts stderr "Capacitor length must be <= $lmax"
+	dict set parameters l $lmax
+	set l $lmax
+    } 
+    if {[catch {expr abs($ccov)}]} {
+	puts stderr "Capacitor contact coverage must be numeric!"
+        dict set parameters ccov 100
+    } elseif {[expr abs($ccov)] > 100} {
+	puts stderr "Capaitor contact coverage can't be more than 100%"
+        dict set parameters ccov 100
+    }
+
+    # Calculate value from L and W
+    set cval [expr ($l * $w * $carea + 2 * ($l + $w) * $cperi - 4 * $dc)]
+    dict set parameters val [magic::float2spice $cval]
+    sky130::compute_ctot $parameters
+
+    return $parameters
+}
+
+proc sky130::sky130_fd_pr__cap_mim_m3_1_check {parameters} {
+    return [sky130::cap_check $parameters]
+}
+proc sky130::sky130_fd_pr__cap_mim_m3_2_check {parameters} {
+    return [sky130::cap_check $parameters]
+}
+
+#----------------------------------------------------------------
+# Drawn resistors
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# Resistor defaults:
+#----------------------------------------------------------------
+# User editable values:
+#
+#  val   Resistor value in ohms
+#  w	 Width
+#  l	 Length
+#  t	 Number of turns
+#  m	 Number devices in Y
+#  nx	 Number devices in X
+#  snake Use snake geometry (if not present, snake geometry not allowed)
+#  dummy Flag to mark addition of dummy resistor
+#
+# Non-user editable values:
+#
+#  wmin  Minimum allowed width
+#  lmin  Minimum allowed length
+#  rho	 Resistance in ohms per square
+#  dw    Delta width
+#  term  Resistance per terminal
+#  sterm Additional resistance per terminal for snake geometry
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# sky130_fd_pr__res_iso_pw: Specify all user-editable default values and those
+# needed by sky130_fd_pr__res_iso_pw_check
+# NOTE:  Work in progress.  These values need to be corrected.
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_iso_pw_defaults {} {
+    return {w 2.650 l 26.50 m 1 nx 1 wmin 2.650 lmin 26.50 \
+	 	rho 975 val 4875 dummy 0 dw 0.25 term 1.0 \
+		guard 1 endcov 100 full_metal 1 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+#----------------------------------------------------------------
+# rpp1: Specify all user-editable default values and those
+# needed by rp1_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_po_defaults {} {
+    return {w 0.330 l 1.650 m 1 nx 1 wmin 0.330 lmin 1.650 \
+		rho 48.2 val 241 dummy 0 dw 0.0 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 guard 1 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1 hv_guard 0 n_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+# "term" is rho * 0.06, the distance between xpc edge and CONT.
+proc sky130::sky130_fd_pr__res_high_po_0p35_defaults {} {
+    return {w 0.350 l 0.50 m 1 nx 1 wmin 0.350 lmin 0.50 \
+		rho 319.8 val 456.857 dummy 0 dw 0.0 term 194.82 \
+		sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_high_po_0p35 \
+		sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 \
+		sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} \
+		full_metal 1 wmax 0.350 vias 1 n_guard 0 hv_guard 0 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_high_po_0p69_defaults {} {
+    return {w 0.690 l 1.00 m 1 nx 1 wmin 0.690 lmin 0.50 \
+		rho 319.8 val 463.480 dummy 0 dw 0.0 term 194.82 \
+		sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_high_po_0p35 \
+		sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 \
+		sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} \
+		full_metal 1 wmax 0.690 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_high_po_1p41_defaults {} {
+    return {w 1.410 l 2.00 m 1 nx 1 wmin 1.410 lmin 0.50 \
+		rho 319.8 val 453.620 dummy 0 dw 0.0 term 194.82 \
+		sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_high_po_0p35 \
+		sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 \
+		sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} \
+		full_metal 1 wmax 1.410 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_high_po_2p85_defaults {} {
+    return {w 2.850 l 3.00 m 1 nx 1 wmin 2.850 lmin 0.50 \
+		rho 319.8 val 336.630 dummy 0 dw 0.0 term 194.82 \
+		sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_high_po_0p35 \
+		sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 \
+		sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} \
+		full_metal 1 wmax 2.850 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_high_po_5p73_defaults {} {
+    return {w 5.730 l 6.00 m 1 nx 1 wmin 5.730 lmin 0.50 \
+		rho 319.8 val 334.870 dummy 0 dw 0.0 term 194.82 \
+		sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_high_po_0p35 \
+		sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41 \
+		sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} \
+		full_metal 1 wmax 5.730 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+# "term" is rho * 0.06, the distance between xpc edge and CONT.
+proc sky130::sky130_fd_pr__res_xhigh_po_0p35_defaults {} {
+    return {w 0.350 l 0.50 m 1 nx 1 wmin 0.350 lmin 0.50 \
+		rho 2000 val 2875.143 dummy 0 dw 0.0 term 188.2 \
+		sterm 0.0 caplen 0 wmax 0.350 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_xhigh_po_0p35 \
+		sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 \
+		sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} \
+		full_metal 1 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_0p69_defaults {} {
+    return {w 0.690 l 1.00 m 1 nx 1 wmin 0.690 lmin 0.50 \
+		rho 2000 val 2898.600 dummy 0 dw 0.0 term 188.2 \
+		sterm 0.0 caplen 0 wmax 0.690 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_xhigh_po_0p35 \
+		sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 \
+		sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} \
+		full_metal 1 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_1p41_defaults {} {
+    return {w 1.410 l 2.00 m 1 nx 1 wmin 1.410 lmin 0.50 \
+		rho 2000 val 2836.900 dummy 0 dw 0.0 term 188.2 \
+		sterm 0.0 caplen 0 wmax 1.410 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_xhigh_po_0p35 \
+		sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 \
+		sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} \
+		full_metal 1 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_2p85_defaults {} {
+    return {w 2.850 l 3.00 m 1 nx 1 wmin 2.850 lmin 0.50 \
+		rho 2000 val 2105.300 dummy 0 dw 0.0 term 188.2 \
+		sterm 0.0 caplen 0 wmax 2.850 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_xhigh_po_0p35 \
+		sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 \
+		sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} \
+		full_metal 1 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_5p73_defaults {} {
+    return {w 5.730 l 6.00 m 1 nx 1 wmin 5.730 lmin 0.50 \
+		rho 2000 val 2094.200 dummy 0 dw 0.0 term 188.2 \
+		sterm 0.0 caplen 0 wmax 5.730 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 \
+		compatible {sky130_fd_pr__res_xhigh_po_0p35 \
+		sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 \
+		sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} \
+		full_metal 1 n_guard 0 hv_guard 0 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+#----------------------------------------------------------------
+# sky130_fd_pr__res_generic_nd: Specify all user-editable default values and those
+# needed by rdn_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_nd_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 120 val 600.0 dummy 0 dw 0.05 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 guard 1 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__res_generic_nd__hv_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 120 val 600.0 dummy 0 dw 0.02 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 guard 1 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+#----------------------------------------------------------------
+# sky130_fd_pr__res_generic_pd: Specify all user-editable default values and those
+# needed by rdp_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_pd_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 197 val 985.0 dummy 0 dw 0.02 term 0.0 \
+		sterm 0.0 caplen 0.60 snake 0 guard 1 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+proc sky130::sky130_fd_pr__res_generic_pd__hv_defaults {} {
+    return {w 0.420 l 2.100 m 1 nx 1 wmin 0.42 lmin 2.10 \
+		rho 197 val 985.0 dummy 0 dw 0.02 term 0.0 \
+		sterm 0.0 caplen 0.60 snake 0 guard 1 \
+		glc 1 grc 1 gtc 1 gbc 1 roverlap 0 endcov 100 \
+		full_metal 1 vias 1 \
+		viagb 0 viagt 0 viagl 0 viagr 0}
+}
+
+#----------------------------------------------------------------
+# sky130_fd_pr__res_generic_l1: Specify all user-editable default values and those needed
+# by sky130_fd_pr__res_generic_l1_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_l1_defaults {} {
+    return {w 0.170 l 0.170 m 1 nx 1 wmin 0.17 lmin 0.17 \
+		rho 12.8 val 12.8 dummy 0 dw 0.0 term 0.0 snake 0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# sky130_fd_pr__res_generic_m1: Specify all user-editable default values and those needed
+# by sky130_fd_pr__res_generic_m1_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m1_defaults {} {
+    return {w 0.140 l 0.140 m 1 nx 1 wmin 0.14 lmin 0.14 \
+		rho 0.125 val 0.125 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# sky130_fd_pr__res_generic_m2: Specify all user-editable default values and those needed
+# by sky130_fd_pr__res_generic_m2_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m2_defaults {} {
+    return {w 0.140 l 0.140 m 1 nx 1 wmin 0.14 lmin 0.14 \
+		rho 0.125 val 0.125 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# sky130_fd_pr__res_generic_m3: Specify all user-editable default values and those needed
+# by sky130_fd_pr__res_generic_m3_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m3_defaults {} {
+    return {w 0.300 l 0.300 m 1 nx 1 wmin 0.30 lmin 0.30 \
+		rho 0.047 val 0.047 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# Additional entries for sky130_fd_pr__res_generic_m4 and sky130_fd_pr__res_generic_m5, depending on the
+# back-end metal stack.
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m4_defaults {} {
+    return {w 0.300 l 0.300 m 1 nx 1 wmin 0.30 lmin 0.30 \
+		rho 0.047 val 0.047 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+proc sky130::sky130_fd_pr__res_generic_m5_defaults {} {
+    return {w 1.600 l 1.600 m 1 nx 1 wmin 1.60 lmin 1.60 \
+		rho 0.029 val 0.029 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# resistor: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::res_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w {
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_iso_pw_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_po_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_high_po_0p35_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_0p69_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_1p41_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_2p85_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_5p73_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_xhigh_po_0p35_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_0p69_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_1p41_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_2p85_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_5p73_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_nd_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_pd_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_nd__hv_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_pd__hv_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_l1_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m1_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m2_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m3_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m4_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+proc sky130::sky130_fd_pr__res_generic_m5_convert {parameters} {
+    return [sky130::res_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# resistor: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::res_dialog {device parameters} {
+    # Editable fields:      w, l, t, nx, m, val
+    # Checked fields:  
+
+    magic::add_entry val "Value (ohms)" $parameters
+    if {[dict exists $parameters snake]} {
+	sky130::compute_ltot $parameters
+	magic::add_message ltot "Total length (um)" $parameters
+    }
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry m "Y Repeat" $parameters
+    if {[dict exists $parameters endcov]} {
+	magic::add_entry endcov "End contact coverage (%)" $parameters
+    }
+
+    if {[dict exists $parameters compatible]} {
+	set sellist [dict get $parameters compatible]
+	magic::add_selectlist gencell "Device type" $sellist $parameters $device
+    }
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+
+    if {[dict exists $parameters snake]} {
+	magic::add_checkbox snake "Use snake geometry" $parameters
+    }
+    if {[dict exists $parameters roverlap]} {
+	if {[dict exists $parameters endcov]} {
+            magic::add_checkbox roverlap "Overlap at end contact" $parameters
+	} else {
+            magic::add_checkbox roverlap "Overlap at ends" $parameters
+	}
+    }
+    if {[dict exists $parameters guard]} {
+	magic::add_checkbox guard "Add guard ring" $parameters
+
+    	if {[dict exists $parameters hv_guard]} {
+	    magic::add_checkbox hv_guard "High-voltage guard ring" $parameters
+	}
+	if {[dict exists $parameters n_guard]} {
+	    magic::add_checkbox n_guard "N-well connected guard ring" $parameters
+	}
+	if {[dict exists $parameters full_metal]} {
+	    magic::add_checkbox full_metal "Full metal guard ring" $parameters
+	}
+	if {[dict exists $parameters glc]} {
+	    magic::add_checkbox glc "Add left guard ring contact" $parameters
+	}
+	if {[dict exists $parameters grc]} {
+	    magic::add_checkbox grc "Add right guard ring contact" $parameters
+	}
+	if {[dict exists $parameters gtc]} {
+	    magic::add_checkbox gtc "Add top guard ring contact" $parameters
+	}
+	if {[dict exists $parameters gbc]} {
+	    magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+	}
+
+
+    	magic::add_entry viagb "Bottom guard ring via coverage \[+/-\](%)" $parameters
+    	magic::add_entry viagt "Top guard ring via coverage \[+/-\](%)" $parameters
+    	magic::add_entry viagr "Right guard ring via coverage \[+/-\](%)" $parameters
+    	magic::add_entry viagl "Left guard ring via coverage \[+/-\](%)" $parameters
+    }
+
+    if {[dict exists $parameters vias]} {
+	magic::add_checkbox vias "Add vias over contacts" $parameters
+    }
+
+    if {[dict exists $parameters snake]} {
+       magic::add_dependency sky130::res_recalc $device sky130 l w val nx snake
+    } else {
+       magic::add_dependency sky130::res_recalc $device sky130 l w val nx
+    }
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_iso_pw_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_iso_pw $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_po_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_po $parameters
+}
+
+proc sky130::sky130_fd_pr__res_high_po_0p35_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_high_po_0p35 $parameters
+}
+proc sky130::sky130_fd_pr__res_high_po_0p69_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_high_po_0p69 $parameters
+}
+proc sky130::sky130_fd_pr__res_high_po_1p41_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_high_po_1p41 $parameters
+}
+proc sky130::sky130_fd_pr__res_high_po_2p85_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_high_po_2p85 $parameters
+}
+proc sky130::sky130_fd_pr__res_high_po_5p73_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_high_po_5p73 $parameters
+}
+
+proc sky130::sky130_fd_pr__res_xhigh_po_0p35_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_xhigh_po_0p35 $parameters
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_0p69_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_xhigh_po_0p69 $parameters
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_1p41_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_xhigh_po_1p41 $parameters
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_2p85_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_xhigh_po_2p85 $parameters
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_5p73_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_xhigh_po_5p73 $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_nd_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_nd $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_pd_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_pd $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_nd__hv_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_nd__hv $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_pd__hv_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_pd__hv $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_l1_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_l1 $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_m1_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_m1 $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_m2_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_m2 $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_m3_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_m3 $parameters
+}
+
+proc sky130::sky130_fd_pr__res_generic_m4_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_m4 $parameters
+}
+proc sky130::sky130_fd_pr__res_generic_m5_dialog {parameters} {
+    sky130::res_dialog sky130_fd_pr__res_generic_m5 $parameters
+}
+
+#----------------------------------------------------------------
+# Resistor: Draw a single device in straight geometry
+#----------------------------------------------------------------
+
+proc sky130::res_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set endcov 0	 	;# percent coverage of end contacts
+    set roverlap 0		;# overlap resistors at end contacts
+    set well_res_overlap 0 	;# not a well resistor
+    set end_contact_type ""	;# no contacts for metal resistors
+    set end_overlap_cont 0	;# additional end overlap on sides
+    set vias 0			;# add vias over contacts
+    set res_idtype none
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    if {![dict exists $parameters end_contact_size]} {
+	set end_contact_size $contact_size
+    }
+
+    # Draw the resistor and endcaps
+    pushbox
+    box size 0 0
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+
+    pushbox
+    box grow n ${res_to_endcont}um
+    box grow s ${res_to_endcont}um
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${end_contact_size} 2.0] ${end_surround}]
+	box grow n ${well_extend}um
+	box grow s ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    set cext [sky130::getbox]
+    popbox
+
+    if {$well_res_overlap > 0} {
+	erase ${well_res_type}
+    } else {
+	erase ${end_type}
+    }
+    paint ${res_type}
+    if {"$res_idtype" != "none"} {
+	box grow c 2
+	paint ${res_idtype}
+    }
+    popbox
+
+    # Reduce contact sizes by (end type) surround so that
+    # the contact area edges match the device type width.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set epl [- ${w} [* ${end_surround} 2]]     	    ;# end contact width
+
+    # Reduce end material size for well resistor types
+    if {$well_res_overlap > 0} {
+	set epl [- ${epl} [* ${well_res_overlap} 2]]
+    }
+
+    # Reduce by coverage percentage unless overlapping at contacts
+    if {(${roverlap} == 0) && (${endcov} > 0)} {
+	set cpl [* ${epl} [/ ${endcov} 100.0]]
+    } else {
+	set cpl $epl
+    }
+
+    # Ensure additional overlap of diffusion contact if required
+    set dov [* ${end_overlap_cont} 2]
+    if {[- ${epl} ${cpl}] < $dov} {
+	set cpl [- ${epl} $dov]    ;# additional end contact width
+    }
+
+    set hepl [+ [/ ${epl} 2.0] ${end_surround}]
+    set hesz [/ ${end_contact_size} 2.0]
+
+    # LV substrate diffusion types have a different surround requirement
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $end_type] < 0} {
+	set hesz [+ ${hesz} ${end_surround}]
+    }
+
+    # Top end material & contact
+    pushbox
+    box move n ${hl}um
+    box move n ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	# Draw via over contact first
+	if {$vias != 0} {
+            pushbox
+            set ch $res_to_endcont
+    	    if {$ch < $via_size} {set ch $via_size}
+    	    set cw $epl
+    	    if {$cw < $via_size} {set cw $via_size}
+	    box grow n [/ $via_size 2]um
+	    box grow s [- $ch [/ $via_size 2]]um
+	    box grow w [/ $cw 2]um
+	    box grow e [/ $cw 2]um
+            sky130::mcon_draw
+            popbox
+    	}
+	set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]]
+    }
+    popbox
+
+    # Bottom end material & contact
+    pushbox
+    box move s ${hl}um
+    box move s ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	# Draw via over contact first
+	if {$vias != 0} {
+            pushbox
+            set ch $res_to_endcont
+    	    if {$ch < $via_size} {set ch $via_size}
+    	    set cw $epl
+    	    if {$cw < $via_size} {set cw $via_size}
+	    box grow n [- $ch [/ $via_size 2]]um
+	    box grow s [/ $via_size 2]um
+	    box grow w [/ $cw 2]um
+	    box grow e [/ $cw 2]um
+            sky130::mcon_draw
+            popbox
+    	}
+	set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]]
+    }
+    popbox
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Resistor: Draw a single device in snake geometry
+#----------------------------------------------------------------
+
+proc sky130::res_snake_device {nf parameters} {
+    # nf is the number of fingers of the snake geometry
+
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set endcov 100	 	;# percent coverage of end contacts
+    set well_res_overlap 0 	;# not a well resistor
+    set end_contact_type ""	;# no contacts for metal resistors
+    set mask_clearance 0	;# additional length to clear mask
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    if {![dict exists $parameters end_contact_size]} {
+	set end_contact_size $contact_size
+    }
+
+    # Compute half width and length
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    # Reduce contact sizes by (end type) surround so that
+    # the contact area edges match the device type width.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set epl [- ${w} [* ${end_surround} 2]]     	    ;# end contact width
+
+    # Reduce contact size for well resistor types
+    if {$well_res_overlap > 0} {
+	set epl [- ${epl} [* ${well_res_overlap} 2]]
+    }
+
+    # Reduce contact part of end by coverage percentage
+    if {${endcov} > 0} {
+	set cpl [* ${epl} [/ ${endcov} 100.0]]
+    } else {
+	set cpl $epl
+    }
+
+    set hepl [+ [/ ${epl} 2.0] ${end_surround}]
+    set hesz [+ [/ ${end_contact_size} 2.0] ${end_surround}]
+
+    pushbox
+    box size 0 0	;# Position is taken from caller
+
+    # Front end contact (always bottom)
+    pushbox
+    box move s ${hl}um
+    pushbox
+    box move s ${mask_clearance}um
+    box move s ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::getbox]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]
+    }
+    popbox
+
+    # Draw portion between resistor end and contact.
+    box grow e ${hw}um
+    box grow w ${hw}um
+    pushbox
+    box grow s ${mask_clearance}um
+    paint ${res_type}
+    popbox
+    box move s ${mask_clearance}um
+    box grow s ${res_to_endcont}um
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${end_contact_size} 2.0] ${end_surround}]
+	box grow s ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    # Draw the resistor and endcaps
+    pushbox
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+
+    # Capture these extents in the bounding box in case both contacts
+    # are on one side.
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+
+    set deltax [+ ${res_spacing} ${w}]
+    set deltay [- ${l} ${w}]
+    for {set i 0} {$i < [- $nf 1]} {incr i} {
+	paint ${res_type}
+ 	pushbox
+	if {[% $i 2] == 0} {
+	    box move n ${deltay}um
+	}
+	box height ${w}um
+	box width ${deltax}um
+	paint ${res_type}
+ 	popbox
+	box move e ${deltax}um
+    }
+    paint ${res_type}
+    # Capture these extents in the bounding box
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    # Move box to last finger
+    set lastf [* [- $nf 1] $deltax]
+    box move e ${lastf}um
+
+    # Back-end contact (top or bottom, depending if odd or even turns)
+    pushbox
+
+    if {[% $nf 2] == 1} {
+	set dir n
+    } else {
+	set dir s
+    }
+    box move $dir ${hl}um
+    pushbox
+    box move $dir ${mask_clearance}um
+    box move $dir ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [sky130::unionbox $cext [sky130::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${end_contact_size} \
+		${end_type} ${end_contact_type} li horz]]
+    }
+    popbox
+    # Draw portion between resistor end and contact.
+    box grow e ${hw}um
+    box grow w ${hw}um
+    pushbox
+    box grow $dir ${mask_clearance}um
+    paint ${res_type}
+    popbox
+    box move $dir ${mask_clearance}um
+    box grow $dir ${res_to_endcont}um
+
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${end_contact_size} 2.0] ${end_surround}]
+	box grow $dir ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    popbox
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Resistor: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::res_draw {parameters} {
+    tech unlock *
+    set savesnap [snap]
+    snap internal
+
+    # Set defaults if they are not in parameters
+    set snake 0		;# some resistors don't allow snake geometry
+    set roverlap 0	;# overlap resistors at contacts
+    set guard 0		;# draw a guard ring
+    set plus_diff_type   nsd	;# guard ring diffusion type
+    set overlap_compress 0	;# special Y distance compression
+    set well_res_overlap 0	;# additional well extension behind contact
+    set res_diff_spacing 0	;# spacing from resistor to diffusion
+    set res_idtype  none
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # For devices where inter-device space is smaller than device-to-guard ring
+    if {![dict exists $parameters end_to_end_space]} {
+	set end_to_end_space $end_spacing
+    }
+
+    if {![dict exists $parameters end_contact_size]} {
+	set end_contact_size $contact_size
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set nf $nx
+    if {($snake == 1) && ($nx == 1)} {set snake 0}
+    if {$snake == 1} {
+	set bbox [sky130::res_snake_device $nf $parameters]
+	set nx 1
+    } else {
+	set bbox [sky130::res_device $parameters]
+    }
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # Determine tile width and height (depends on overlap)
+    # Snake resistors cannot overlap.
+    # However, snake resistors with an odd number of fingers can
+    # compress the space if overlap_compress is defined
+
+    if {($roverlap == 1) && ($snake == 1) && ([% $nf 2] == 1) && ($m > 1)} {
+        set dy [- $fh $overlap_compress]
+    } elseif {($roverlap == 0) || ($snake == 1)} {
+        set dy [+ $fh $end_to_end_space]
+    } else {
+        # overlap poly
+        set dy [- $fh [+ [* [+ $end_surround $well_res_overlap] 2.0] $end_contact_size]]
+    }
+    set dx [+ $fw $res_spacing]
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $m 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $plus_diff_type] >= 0} {
+	set guard_diff_surround 0
+    } else {
+	set guard_diff_surround ${diff_surround}
+    }
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $res_diff_spacing $guard_diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $end_spacing $guard_diff_surround]] $contact_size]
+
+	# Draw the guard ring first, because well resistors are on the substrate plane
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    # puts "Device position at = [sky130::getbox]"
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $m} {incr yp} {
+	    if {$snake == 1} {
+		sky130::res_snake_device $nf $parameters
+	    } else {
+		sky130::res_device $parameters
+	    }
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    snap $savesnap
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_po_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+    } else {
+	set gsubtype psub
+    }
+
+    set newdict [dict create \
+	    res_type		npres \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		0.48 \
+	    end_to_end_space	0.52 \
+	    res_to_endcont	$res_to_cont \
+	    res_spacing		$poly_spacing \
+	    res_diff_spacing	0.48 \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_high_po_0p35_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.785
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		ppres \
+	    res_idtype		res0p35 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_high_po_0p69_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.615
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		ppres \
+	    res_idtype		res0p69 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_high_po_1p41_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.525
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		ppres \
+	    res_idtype		res1p41 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_high_po_2p85_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.525
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		ppres \
+	    res_idtype		res2p85 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_high_po_5p73_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.525
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		ppres \
+	    res_idtype		res5p73 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_xhigh_po_0p35_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.785
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		xpres \
+	    res_idtype		res0p35 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_xhigh_po_0p69_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.615
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		xpres \
+	    res_idtype		res0p69 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_xhigh_po_1p41_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.525
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		xpres \
+	    res_idtype		res1p41 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_xhigh_po_2p85_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.525
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		xpres \
+	    res_idtype		res2p85 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_xhigh_po_5p73_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    # Handle options related to guard ring type (high/low voltage, nwell/psub)
+    if {[dict exists $parameters hv_guard]} {
+	set use_hv_guard [dict get $parameters hv_guard]
+    } else {
+	set use_hv_guard 0
+    }
+    if {[dict exists $parameters n_guard]} {
+	set use_n_guard [dict get $parameters n_guard]
+    } else {
+	set use_n_guard 0
+    }
+
+    if {$use_hv_guard == 1} {
+	if {$use_n_guard == 1} {
+	    set gdifftype mvnsd
+	    set gdiffcont mvnsc
+	} else {
+	    set gdifftype mvpsd
+	    set gdiffcont mvpsc
+	}
+	set gsurround 0.33
+    } else {
+	if {$use_n_guard == 1} {
+	    set gdifftype nsd
+	    set gdiffcont nsc
+	} else {
+	    set gdifftype psd
+	    set gdiffcont psc
+	}
+	set gsurround $sub_surround
+    }
+    if {$use_n_guard == 1} {
+	set gsubtype nwell
+	set gresdiff_spacing 0.525
+	set gresdiff_end 0.525
+    } else {
+	set gsubtype psub
+	set gresdiff_spacing 0.48
+	set gresdiff_end 0.48
+    }
+
+    set newdict [dict create \
+	    res_type		xpres \
+	    res_idtype		res5p73 \
+	    end_type 		xpc \
+	    end_contact_type	xpc \
+	    end_contact_size	0 \
+	    plus_diff_type	$gdifftype \
+	    plus_contact_type	$gdiffcont \
+	    sub_type		$gsubtype \
+	    guard_sub_surround	$gsurround \
+	    end_surround	$poly_surround \
+	    end_spacing		$gresdiff_end \
+	    end_to_end_space	0.52 \
+	    end_contact_size	0.19 \
+	    res_to_endcont	1.985 \
+	    res_spacing		1.24 \
+	    res_diff_spacing	$gresdiff_spacing \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_nd_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rdn \
+	    end_type 		ndiff \
+	    end_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		psub \
+	    end_surround	$diff_surround \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		0.30 \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_nd__hv_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		mvrdn \
+	    end_type 		mvndiff \
+	    end_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    sub_type		psub \
+	    end_surround	$diff_surround \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		0.30 \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_pd_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rdp \
+	    end_type 		pdiff \
+	    end_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		nwell \
+	    end_surround	$diff_surround \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		$diff_spacing \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_pd__hv_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		mvrdp \
+	    end_type 		mvpdiff \
+	    end_contact_type	mvpdc \
+	    plus_diff_type	mvnsd \
+	    plus_contact_type	mvnsc \
+	    sub_type		nwell \
+	    end_surround	$diff_surround \
+	    guard_sub_surround	0.33 \
+	    end_spacing		0.44 \
+	    res_to_endcont	0.37 \
+	    res_spacing		0.30 \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_iso_pw_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    well_res_type	pwell \
+	    res_type		rpw \
+	    end_type 		psd \
+	    end_contact_type	psc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		dnwell \
+	    sub_surround	0.23 \
+	    guard_sub_type	nwell \
+	    guard_sub_surround	0.63 \
+	    end_surround	$diff_surround \
+	    end_spacing		0.63 \
+	    end_to_end_space	1.15 \
+	    end_overlap_cont	0.06 \
+	    end_contact_size	0.53 \
+	    overlap_compress	-0.17 \
+	    res_to_endcont	0.265 \
+	    res_spacing		1.4 \
+	    res_diff_spacing	0.63 \
+	    well_res_overlap	0.2 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_l1_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rli \
+	    end_type 		li \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    end_to_end_space	0.23 \
+	    res_spacing		$metal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m1_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm1 \
+	    end_type 		m1 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m2_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm2 \
+	    end_type 		m2 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m3_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm3 \
+	    end_type 		m3 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_generic_m4_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm4 \
+	    end_type 		m4 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	0.28 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m5_draw {parameters} {
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $sky130::ruleset] {
+        set $key [dict get $sky130::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm5 \
+	    end_type 		m5 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    end_to_end_space	1.6 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# Resistor total length computation
+#----------------------------------------------------------------
+
+proc sky130::compute_ltot {parameters} {
+    # In case snake not defined
+    set snake 0
+    set caplen 0
+
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l]
+
+    # Compute total length.  Use catch to prevent error in batch/scripted mode.
+    if {$snake == 1} {
+	catch {set magic::ltot_val [expr ($caplen * ($nx - 1)) + ($l * $nx) + ($nx - 1)]}
+    } else {
+	catch {set magic::ltot_val $l}
+    }
+}
+
+#----------------------------------------------------------------
+# resistor: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::res_check {device parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    set snake 0
+    set guard 0
+    set sterm 0.0
+    set caplen 0
+    set wmax 0
+
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w]
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l]
+
+    set val  [magic::spice2float $val]
+    set rho  [magic::spice2float $rho]
+
+    # nf, m must be integer
+    if {![string is int $nx]} {
+	puts stderr "X repeat must be an integer!"
+        dict set parameters nx 1
+    }
+    if {![string is int $m]} {
+	puts stderr "Y repeat must be an integer!"
+        dict set parameters m 1
+    }
+
+    # Width always needs to be specified
+    if {$w < $wmin} {
+	puts stderr "Resistor width must be >= $wmin um"
+	dict set parameters w $wmin
+    } 
+    if {$wmax > 0 && $w > $wmax} {
+	puts stderr "Resistor width must be <= $wmax um"
+	dict set parameters w $wmax
+    }
+    
+    # Val and W specified - no L
+    if {$l == 0}  {
+   	set l [expr ($w - $dw) * $val / $rho]
+        set l [magic::3digitpastdecimal $l]
+        set stringval [magic::float2spice $val]
+	dict set parameters l [magic::float2spice [expr $l * 1e-6]]
+	# L and W specified - ignore Val if specified
+    } else {
+	if {$snake == 0} {
+	    set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+	} else {
+	    set val [expr $rho * ($nx - 1) + ((2 * ($term + $sterm)) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+	}
+	set val [magic::float2spice $val]
+        dict set parameters val $val
+    }
+    if {$l < $lmin} {
+	puts stderr "Resistor length must be >= $lmin um"
+	dict set parameters l $lmin
+    } 
+    if {$nx < 1} {
+	puts stderr "X repeat must be >= 1"
+	dict set parameters nx 1
+    } 
+    if {$m < 1} {
+	puts stderr "Y repeat must be >= 1"
+	dict set parameters m 1
+    } 
+
+    # Snake resistors cannot have width greater than length
+    if {$snake == 1} {
+	if {$w > $l} {
+	    puts stderr "Snake resistor width must be < length"
+	    dict set parameters w $l
+	}
+    }
+
+    # Check via coverage for syntax
+    if {$guard == 1} {
+    	if {[catch {expr abs($viagb)}]} {
+	    puts stderr "Guard ring bottom via coverage must be numeric!"
+            dict set parameters viagb 0
+    	} elseif {[expr abs($viagb)] > 100} {
+	    puts stderr "Guard ring bottom via coverage can't be more than 100%"
+            dict set parameters viagb 100
+    	}
+    	if {[catch {expr abs($viagt)}]} {
+	    puts stderr "Guard ring top via coverage must be numeric!"
+            dict set parameters viagt 0
+	} elseif {[expr abs($viagt)] > 100} {
+	    puts stderr "Guard ring top via coverage can't be more than 100%"
+            dict set parameters viagt 100
+	}
+	if {[catch {expr abs($viagr)}]} {
+	    puts stderr "Guard ring right via coverage must be numeric!"
+            dict set parameters viagr 0
+	} elseif {[expr abs($viagr)] > 100} {
+	    puts stderr "Guard ring right via coverage can't be more than 100%"
+            dict set parameters viagr 100
+   	} 
+        if {[catch {expr abs($viagl)}]} {
+	    puts stderr "Guard ring left via coverage must be numeric!"
+            dict set parameters viagl 0
+	} elseif {[expr abs($viagl)] > 100} {
+	   puts stderr "Guard ring left via coverage can't be more than 100%"
+           dict set parameters viagl 100
+	}
+    }
+
+    # Diffusion resistors must satisfy diffusion-to-tap spacing of 20um.
+    # Therefore the maximum of guard ring width or height cannot exceed 40um.
+    # If in violation, reduce counts first, as these are easiest to recover
+    # by duplicating the device and overlapping the wells.
+    if {$device == "rdn" || $device == "rdp"} {
+       set origm $m
+       set orignx $nx
+       while true {
+	  set xext [expr ($w + 0.8) * $nx + 1.0]
+	  set yext [expr ($l + 1.7) * $m + 1.7]
+          if {[expr min($xext, $yext)] > 40.0} {
+              if {$yext > 40.0 && $m > 1} {
+		 incr m -1
+	      } elseif {$xext > 40.0 && $nx > 1} {
+		 incr nx -1
+	      } elseif {$yext > 40.0} {
+		 set l 36.6
+		 puts -nonewline stderr "Diffusion resistor length must be < 36.6 um"
+		 puts stderr " to avoid tap spacing violation."
+		 dict set parameters l $l
+	      } elseif {$xext > 40.0} {
+		 set w 38.2
+		 puts -nonewline stderr "Diffusion resistor width must be < 38.2 um"
+		 puts stderr " to avoid tap spacing violation."
+		 dict set parameters w $w
+	      }
+          } else {
+	      break
+	  }
+       }
+       if {$m != $origm} {
+	  puts stderr "Y repeat reduced to prevent tap distance violation"
+	  dict set parameters m $m
+       }
+       if {$nx != $orignx} {
+	  puts stderr "X repeat reduced to prevent tap distance violation"
+	  dict set parameters nx $nx
+       }
+    }
+    sky130::compute_ltot $parameters
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__res_iso_pw_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_iso_pw $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_po_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_po $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_high_po_0p35_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_high_po_0p35 $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_0p69_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_high_po_0p69 $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_1p41_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_high_po_1p41 $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_2p85_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_high_po_2p85 $parameters]
+}
+proc sky130::sky130_fd_pr__res_high_po_5p73_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_high_po_5p73 $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_xhigh_po_0p35_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_xhigh_po_0p35 $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_0p69_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_xhigh_po_0p69 $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_1p41_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_xhigh_po_1p41 $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_2p85_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_xhigh_po_2p85 $parameters]
+}
+proc sky130::sky130_fd_pr__res_xhigh_po_5p73_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_xhigh_po_5p73 $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_nd_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_nd $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_pd_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_pd $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_nd__hv_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_nd__hv $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_pd__hv_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_pd__hv $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_l1_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_l1 $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m1_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_m1 $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m2_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_m2 $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m3_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_m3 $parameters]
+}
+
+proc sky130::sky130_fd_pr__res_generic_m4_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_m4 $parameters]
+}
+proc sky130::sky130_fd_pr__res_generic_m5_check {parameters} {
+    return [sky130::res_check sky130_fd_pr__res_generic_m5 $parameters]
+}
+
+#----------------------------------------------------------------
+# MOS defaults:
+#----------------------------------------------------------------
+#    w       = Gate width
+#    l       = Gate length
+#    m	     = Multiplier
+#    nf	     = Number of fingers
+#    diffcov = Diffusion contact coverage
+#    polycov = Poly contact coverage
+#    topc    = Top gate contact
+#    botc    = Bottom gate contact
+#    guard   = Guard ring
+#
+# (not user-editable)
+#
+#    lmin    = Gate minimum length
+#    wmin    = Gate minimum width
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# pmos: Specify all user-editable default values and those
+# needed by mos_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__pfet_01v8_defaults {} {
+    return {w 0.42 l 0.15 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {sky130_fd_pr__pfet_01v8 \
+		sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt \
+		sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 \
+		viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_lvt_defaults {} {
+    return {w 0.42 l 0.35 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 \
+		compatible {sky130_fd_pr__pfet_01v8 \
+		sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt \
+		sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 \
+		viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_hvt_defaults {} {
+    return {w 0.42 l 0.15 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {sky130_fd_pr__pfet_01v8 \
+		sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt \
+		sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 \
+		viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__pfet_g5v0d10v5_defaults {} {
+    return {w 0.42 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 \
+		compatible {sky130_fd_pr__pfet_01v8 \
+		sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt \
+		sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 \
+		viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+#----------------------------------------------------------------
+# nmos: Specify all user-editable default values and those
+# needed by mos_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__nfet_01v8_defaults {} {
+    return {w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt \
+		sky130_fd_bs_flash__special_sonosfet_star \
+		sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt \
+		sky130_fd_pr__nfet_03v3_nvt} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__nfet_01v8_lvt_defaults {} {
+    return {w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt \
+		sky130_fd_bs_flash__special_sonosfet_star \
+		sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt \
+		sky130_fd_pr__nfet_03v3_nvt} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_bs_flash__special_sonosfet_star_defaults {} {
+    return {w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 \
+		compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt \
+		sky130_fd_bs_flash__special_sonosfet_star \
+		sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt \
+		sky130_fd_pr__nfet_03v3_nvt} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__nfet_g5v0d10v5_defaults {} {
+    return {w 0.42 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 \
+		compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt \
+		sky130_fd_bs_flash__special_sonosfet_star \
+		sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt \
+		sky130_fd_pr__nfet_03v3_nvt} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__nfet_05v0_nvt_defaults {} {
+    return {w 0.42 l 0.90 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.90 wmin 0.42 \
+		compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt \
+		sky130_fd_bs_flash__special_sonosfet_star \
+		sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt \
+		sky130_fd_pr__nfet_03v3_nvt} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__nfet_03v3_nvt_defaults {} {
+    return {w 0.42 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 \
+		compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt \
+		sky130_fd_bs_flash__special_sonosfet_star \
+		sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt \
+		sky130_fd_pr__nfet_03v3_nvt} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+#----------------------------------------------------------------
+# mos varactor: Specify all user-editable default values and those
+# needed by mosvc_check
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__cap_var_lvt_defaults {} {
+    return {w 1.0 l 0.18 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.18 wmin 1.0 \
+		compatible {sky130_fd_pr__cap_var_lvt \
+		sky130_fd_pr__cap_var_hvt sky130_fd_pr__cap_var} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__cap_var_hvt_defaults {} {
+    return {w 1.0 l 0.18 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.18 wmin 1.0 \
+		compatible {sky130_fd_pr__cap_var_lvt \
+		sky130_fd_pr__cap_var_hvt sky130_fd_pr__cap_var} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+proc sky130::sky130_fd_pr__cap_var_defaults {} {
+    return {w 1.0 l 0.50 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 1.0 \
+		compatible {sky130_fd_pr__cap_var_lvt \
+		sky130_fd_pr__cap_var_hvt sky130_fd_pr__cap_var} \
+		full_metal 1 viasrc 100 viadrn 100 viagate 100 \
+		viagb 0 viagr 0 viagl 0 viagt 0}
+}
+
+#----------------------------------------------------------------
+# mos: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::mos_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w {
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		# set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    nf {
+		# Adjustment ot W will be handled below
+		dict set pdkparams [string tolower $key] $value
+	    }
+	}
+    }
+
+    # Magic does not understand "nf" as a parameter, but expands to
+    # "nf" number of devices connected horizontally.  The "w" value
+    # must be divided down accordingly, as the "nf" parameter implies
+    # that the total width "w" is divided into "nf" fingers.
+
+    catch {
+	set w [dict get $pdkparams w]
+	set nf [dict get $pdkparams nf]
+	if {$nf > 1} {
+	    dict set pdkparams w [expr $w / $nf]
+	}
+    }
+
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__nfet_01v8_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_01v8_lvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_bs_flash__special_sonosfet_star_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_g5v0d10v5_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_05v0_nvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_03v3_nvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_lvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_hvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_g5v0d10v5_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_var_lvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_var_hvt_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_var_convert {parameters} {
+    return [sky130::mos_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# mos: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::mos_dialog {device parameters} {
+    # Editable fields:      w, l, nf, m, diffcov, polycov
+    # Checked fields:  topc, botc
+    # For specific devices, gate type is a selection list
+
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry nf "Fingers" $parameters
+    magic::add_entry m "M" $parameters
+
+    if {[dict exists $parameters compatible]} {
+       set sellist [dict get $parameters compatible]
+       magic::add_selectlist gencell "Device type" $sellist $parameters $device
+    }
+
+    magic::add_entry diffcov "Diffusion contact coverage (%)" $parameters
+    magic::add_entry polycov "Poly contact coverage (%)" $parameters
+    magic::add_entry rlcov "Guard ring contact coverage (%)" $parameters
+    if {[dict exists $parameters gbc]} {
+	magic::add_entry tbcov "Guard ring top/bottom contact coverage (%)" $parameters
+    }
+
+    magic::add_checkbox poverlap "Overlap at poly contact" $parameters
+    magic::add_checkbox doverlap "Overlap at diffusion contact" $parameters
+    magic::add_checkbox topc "Add top gate contact" $parameters
+    magic::add_checkbox botc "Add bottom gate contact" $parameters
+
+    magic::add_checkbox guard "Add guard ring" $parameters
+    magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    magic::add_checkbox glc "Add left guard ring contact" $parameters
+    magic::add_checkbox grc "Add right guard ring contact" $parameters
+    if {[dict exists $parameters gbc]} {
+	magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+	magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+
+    magic::add_entry viasrc "Source via coverage \[+/-\](%)" $parameters
+    magic::add_entry viadrn "Drain via coverage \[+/-\](%)" $parameters
+    magic::add_entry viagate "Gate via coverage \[+/-\](%)" $parameters
+    magic::add_entry viagb "Bottom guard ring via coverage \[+/-\](%)" $parameters
+    magic::add_entry viagt "Top guard ring via coverage \[+/-\](%)" $parameters
+    magic::add_entry viagr "Right guard ring via coverage \[+/-\](%)" $parameters
+    magic::add_entry viagl "Left guard ring via coverage \[+/-\](%)" $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__nfet_01v8_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__nfet_01v8 $parameters
+}
+
+proc sky130::sky130_fd_pr__nfet_01v8_lvt_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__nfet_01v8_lvt $parameters
+}
+
+proc sky130::sky130_fd_bs_flash__special_sonosfet_star_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_bs_flash__special_sonosfet_star $parameters
+}
+
+proc sky130::sky130_fd_pr__nfet_g5v0d10v5_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__nfet_g5v0d10v5 $parameters
+}
+
+proc sky130::sky130_fd_pr__nfet_05v0_nvt_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__nfet_05v0_nvt $parameters
+}
+
+proc sky130::sky130_fd_pr__nfet_03v3_nvt_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__nfet_03v3_nvt $parameters
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__pfet_01v8 $parameters
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_lvt_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__pfet_01v8_lvt $parameters
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_hvt_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__pfet_01v8_hvt $parameters
+}
+
+proc sky130::sky130_fd_pr__pfet_g5v0d10v5_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__pfet_g5v0d10v5 $parameters
+}
+
+proc sky130::sky130_fd_pr__cap_var_lvt_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__cap_var_lvt $parameters
+}
+
+proc sky130::sky130_fd_pr__cap_var_hvt_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__cap_var_hvt $parameters
+}
+
+proc sky130::sky130_fd_pr__cap_var_dialog {parameters} {
+    sky130::mos_dialog sky130_fd_pr__cap_var $parameters
+}
+
+#----------------------------------------------------------------
+# getbox:  Get the current cursor box, in microns
+#----------------------------------------------------------------
+
+proc sky130::getbox {} {
+    set curbox [box values]
+    set newbox []
+    set oscale [cif scale out]
+    for {set i 0} {$i < 4} {incr i} {
+        set v [* [lindex $curbox $i] $oscale]
+        lappend newbox $v
+    }
+    return $newbox
+}
+
+#----------------------------------------------------------------
+# unionbox:  Get the union bounding box of box1 and box2
+#----------------------------------------------------------------
+
+proc sky130::unionbox {box1 box2} {
+    set newbox []
+    for {set i 0} {$i < 2} {incr i} {
+        set v [lindex $box1 $i]
+        set o [lindex $box2 $i]
+        if {$v < $o} {
+            lappend newbox $v
+        } else {
+            lappend newbox $o
+        }
+    }
+    for {set i 2} {$i < 4} {incr i} {
+        set v [lindex $box1 $i]
+        set o [lindex $box2 $i]
+        if {$v > $o} {
+            lappend newbox $v
+        } else {
+            lappend newbox $o
+        }
+    }
+    return $newbox
+}
+
+#----------------------------------------------------------------
+# Draw a contact
+#----------------------------------------------------------------
+
+proc sky130::draw_contact {w h s o x atype ctype mtype {orient vert}} {
+
+    # Draw a minimum-size diff contact centered at current position
+    # w is width, h is height.  Minimum size ensured.
+    # x is contact size
+    # s is contact diffusion (or poly) surround
+    # o is contact metal surround
+    # atype is active (e.g., ndiff) or bottom metal if a via
+    # ctype is contact (e.g., ndc)
+    # mtype is metal (e.g., m1) or top metal if a via
+    # orient is the orientation of the contact
+
+    # Set orientations for the bottom material based on material type.
+    # Substrate diffusions (tap) need not overlap the contact in all
+    # directions, but other (diff) types do.  The metal (local
+    # interconnect) layer always overlaps in two directions only.
+
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $atype] >= 0} {
+	set aorient $orient
+    } else {
+	set aorient "full"
+    }
+
+    pushbox
+    box size 0 0
+    if {$w < $x} {set w $x}
+    if {$h < $x} {set h $x}
+    set hw [/ $w 2.0]
+    set hh [/ $h 2.0]
+    box grow n ${hh}um
+    box grow s ${hh}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+    paint ${ctype}
+    pushbox
+    # Bottom layer surrounded on sides as declared by aorient
+    if {($aorient == "vert") || ($aorient == "full")} {
+	box grow n ${s}um
+	box grow s ${s}um
+    }
+    if {($aorient == "horz") || ($aorient == "full")} {
+	box grow e ${s}um
+	box grow w ${s}um
+    }
+    paint ${atype}
+    set extents [sky130::getbox]
+    popbox
+    # Top layer surrounded on sides as declared by orient
+    if {($orient == "vert") || ($orient == "full")} {
+        box grow n ${o}um
+        box grow s ${o}um
+    }
+    if {($orient == "horz") || ($orient == "full")} {
+        box grow e ${o}um
+        box grow w ${o}um
+    }
+    paint ${mtype}
+    popbox
+    return $extents
+}
+
+#----------------------------------------------------------------
+# Draw a guard ring
+#----------------------------------------------------------------
+
+proc sky130::guard_ring {gw gh parameters} {
+
+    # Set local default values if they are not in parameters
+    set rlcov 100	;# Right-left contact coverage percentage
+    set tbcov 100	;# Top-bottom contact coverage percentage
+    set grc 1		;# Draw right side contact
+    set glc 1		;# Draw left side contact
+    set gtc 1		;# Draw right side contact
+    set gbc 1		;# Draw left side contact
+    set viagb 0		;# Draw bottom side via
+    set viagt 0		;# Draw top side via
+    set viagr 0		;# Draw right side via
+    set viagl 0		;# Draw left side via
+    set full_metal 1	;# Draw full (continuous) metal ring
+    set guard_sub_type	 pwell	;# substrate type under guard ring
+    set guard_sub_surround  0	;# substrate type surrounds guard ring
+    set plus_diff_type   nsd	;# guard ring diffusion type
+    set plus_contact_type nsc	;# guard ring diffusion contact type
+    set sub_type	 pwell	;# substrate type
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Set guard_sub_type to sub_type if it is not defined
+    if {![dict exists $parameters guard_sub_type]} {
+	set guard_sub_type $sub_type
+    }
+
+    set hx [/ $contact_size 2.0]
+    set hw [/ $gw 2.0]
+    set hh [/ $gh 2.0]
+
+    # Watch for (LV) substrate diffusion types, which have a different
+    # contact surround amount depending on the direction
+
+    set lv_sub_types {"psd" "nsd"}
+    if {[lsearch $lv_sub_types $plus_diff_type] >= 0} {
+	set diff_surround 0
+    }
+
+    # Compute diffusion width
+    set difft [+ $contact_size $diff_surround $diff_surround]
+    set hdifft [/ $difft 2.0]
+    # Compute guard ring diffusion width and height
+    set hdiffw [/ [+ $gw $difft] 2.0]
+    set hdiffh [/ [+ $gh $difft] 2.0]
+
+    pushbox
+    box size 0 0
+
+    pushbox
+    box move n ${hh}um
+    box grow n ${hdifft}um
+    box grow s ${hdifft}um
+    box grow e ${hdiffw}um
+    box grow w ${hdiffw}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+    pushbox
+    box move s ${hh}um
+    box grow n ${hdifft}um
+    box grow s ${hdifft}um
+    box grow e ${hdiffw}um
+    box grow w ${hdiffw}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+    pushbox
+    box move e ${hw}um
+    box grow e ${hdifft}um
+    box grow w ${hdifft}um
+    box grow n ${hdiffh}um
+    box grow s ${hdiffh}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+    pushbox
+    box move w ${hw}um
+    box grow e ${hdifft}um
+    box grow w ${hdifft}um
+    box grow n ${hdiffh}um
+    box grow s ${hdiffh}um
+    paint $plus_diff_type
+    if {$guard_sub_surround > 0} {
+	box grow c ${guard_sub_surround}um
+	paint $guard_sub_type
+    }
+    popbox
+
+    if {$full_metal} {
+	set hmetw [/ [+ $gw $contact_size] 2.0]
+	set hmeth [/ [+ $gh $contact_size] 2.0]
+	pushbox
+	box move n ${hh}um
+	box grow n ${hx}um
+	box grow s ${hx}um
+	box grow e ${hmetw}um
+	box grow w ${hmetw}um
+	paint li
+	popbox
+	pushbox
+	box move s ${hh}um
+	box grow n ${hx}um
+	box grow s ${hx}um
+	box grow e ${hmetw}um
+	box grow w ${hmetw}um
+	paint li
+	popbox
+	pushbox
+	box move e ${hw}um
+	box grow e ${hx}um
+	box grow w ${hx}um
+	box grow n ${hmeth}um
+	box grow s ${hmeth}um
+	paint li
+	popbox
+	pushbox
+	box move w ${hw}um
+	box grow e ${hx}um
+	box grow w ${hx}um
+	box grow n ${hmeth}um
+	box grow s ${hmeth}um
+	paint li
+	popbox
+    }
+
+    # Set guard ring height so that contact metal reaches to end, scale by $per
+    # set ch [* [+ $gh $contact_size [* $metal_surround -2.0]] [/ $rlcov 100.0]]
+    set ch [* [- $gh $contact_size [* [+ $metal_surround $metal_spacing] \
+		2.0]] [/ $rlcov 100.0]]
+    if {$ch < $contact_size} {set ch $contact_size}
+
+    # Set guard ring width so that contact metal reaches to side contacts
+    set cw [* [- $gw $contact_size [* [+ $metal_surround $metal_spacing] \
+		2.0]] [/ $tbcov 100.0]]
+    if {$cw < $contact_size} {set cw $contact_size}
+
+    if {$tbcov > 0.0} {
+        if {$gtc == 1} {
+            pushbox
+            box move n ${hh}um
+            sky130::draw_contact $cw 0 $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li horz
+            popbox
+	}
+	if {$gbc == 1} {
+	    pushbox
+	    box move s ${hh}um
+	    sky130::draw_contact $cw 0 $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li horz
+	    popbox
+	}
+    }
+    if {$rlcov > 0.0} {
+        if {$grc == 1} {
+            pushbox
+            box move e ${hw}um
+            sky130::draw_contact 0 $ch $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li vert
+            popbox
+        }
+        if {$glc == 1} {
+            pushbox
+            box move w ${hw}um
+            sky130::draw_contact 0 $ch $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type li vert
+            popbox
+        }
+    }
+
+    # Vias
+    if {$viagb != 0} {
+        pushbox
+    	set ch $via_size
+    	set cw [* [- $gw $via_size] [/ [expr abs($viagb)] 100.0]]
+    	if {$cw < $via_size} {set cw $via_size}
+        box move s ${hh}um
+	box grow n [/ $ch 2]um
+	box grow s [/ $ch 2]um
+        set anchor [string index $viagb 0]
+	if {$anchor == "+"} {
+            box move w [/ [- $gw $via_size] 2]um
+	    box grow e ${cw}um
+	} elseif {$anchor == "-"} {
+            box move e [/ [- $gw $via_size] 2]um
+	    box grow w ${cw}um
+	} else {
+	    box grow e [/ $cw 2]um
+	    box grow w [/ $cw 2]um
+	}
+        sky130::mcon_draw horz
+        popbox
+    }
+    if {$viagt != 0} {
+        pushbox
+    	set ch $via_size
+    	set cw [* [- $gw $via_size] [/ [expr abs($viagt)] 100.0]]
+    	if {$cw < $via_size} {set cw $via_size}
+        box move n ${hh}um
+	box grow n [/ $ch 2]um
+	box grow s [/ $ch 2]um
+        set anchor [string index $viagt 0]
+	if {$anchor == "+"} {
+            box move w [/ [- $gw $via_size] 2]um
+	    box grow e ${cw}um
+	} elseif {$anchor == "-"} {
+            box move e [/ [- $gw $via_size] 2]um
+	    box grow w ${cw}um
+	} else {
+	    box grow e [/ $cw 2]um
+	    box grow w [/ $cw 2]um
+	}
+        sky130::mcon_draw horz
+        popbox
+    }
+    if {$viagr != 0} {
+        pushbox
+    	set ch [* [- $gh $via_size] [/ [expr abs($viagr)] 100.0]]
+    	if {$ch < $via_size} {set ch $via_size}
+    	set cw $via_size
+        box move e ${hw}um
+	box grow e [/ $cw 2]um
+	box grow w [/ $cw 2]um
+        set anchor [string index $viagr 0]
+	if {$anchor == "+"} {
+            box move s [/ [- $gh $via_size] 2]um
+	    box grow n ${ch}um
+	} elseif {$anchor == "-"} {
+            box move n [/ [- $gh $via_size] 2]um
+	    box grow s ${ch}um
+	} else {
+	    box grow n [/ $ch 2]um
+	    box grow s [/ $ch 2]um
+	}
+        sky130::mcon_draw vert
+        popbox
+    }
+    if {$viagl != 0} {
+        pushbox
+    	set ch [* [- $gh $via_size] [/ [expr abs($viagl)] 100.0]]
+    	if {$ch < $via_size} {set ch $via_size}
+    	set cw $via_size
+        box move w ${hw}um
+	box grow e [/ $cw 2]um
+	box grow w [/ $cw 2]um
+        set anchor [string index $viagl 0]
+	if {$anchor == "+"} {
+            box move s [/ [- $gh $via_size] 2]um
+	    box grow n ${ch}um
+	} elseif {$anchor == "-"} {
+            box move n [/ [- $gh $via_size] 2]um
+	    box grow s ${ch}um
+	} else {
+	    box grow n [/ $ch 2]um
+	    box grow s [/ $ch 2]um
+	}
+        sky130::mcon_draw vert
+        popbox
+    }
+
+    pushbox
+    box grow e ${hw}um
+    box grow w ${hw}um
+    box grow n ${hh}um
+    box grow s ${hh}um
+    # Create boundary using properties
+    property FIXED_BBOX [box values]
+    box grow c ${hx}um  ;# to edge of contact
+    box grow c ${diff_surround}um  ;# to edge of diffusion
+    box grow c ${sub_surround}um  ;# sub/well overlap of diff (NOT guard_sub)
+    paint $sub_type
+    set cext [sky130::getbox]
+    popbox
+    popbox
+
+    return $cext
+}
+
+#----------------------------------------------------------------
+# MOSFET: Draw a single device
+#----------------------------------------------------------------
+
+proc sky130::mos_device {parameters} {
+
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set diffcov 100	;# percent coverage of diffusion contact
+    set polycov 100	;# percent coverage of poly contact
+    set topc 1		;# draw top poly contact
+    set botc 1		;# draw bottom poly contact
+    set viasrc 100	;# draw source vias
+    set viadrn 100	;# draw drain vias
+    set viagate 100	;# draw gate vias
+    set evens 1		;# even or odd numbered device finger, in X
+    set dev_sub_type ""	;# device substrate type (if different from guard ring)
+    set dev_sub_dist 0	;# device substrate distance (if nondefault dev_sub_type)
+    set min_effl 0	;# gate length below which finger pitch must be stretched
+    set diff_overlap_cont 0	;# extra overlap of end contact by diffusion
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Draw the diffusion and poly
+    pushbox
+    box size 0 0
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    set he [/ $min_effl 2.0]
+    if {$nf == 1 || $he < $hl} {set he $hl}
+    box grow n ${hw}um
+    box grow s ${hw}um
+    box grow e ${hl}um
+    box grow w ${hl}um
+    pushbox
+    if {${diff_extension} > ${gate_to_diffcont}} {
+        box grow e ${diff_extension}um
+        box grow w ${diff_extension}um
+    } else {
+        box grow e ${gate_to_diffcont}um
+        box grow w ${gate_to_diffcont}um
+    }
+    paint ${diff_type}
+    popbox
+    pushbox
+    if {${gate_extension} > ${gate_to_polycont}} {
+	box grow n ${gate_extension}um
+	box grow s ${gate_extension}um
+    } else {
+	if {$topc} {
+	    box grow n ${gate_to_polycont}um
+	} else {
+	    box grow n ${gate_extension}um
+	}
+	if {$botc} {
+	    box grow s ${gate_to_polycont}um
+	} else {
+	    box grow s ${gate_extension}um
+	}
+    }
+    paint ${poly_type}
+    set cext [sky130::getbox]
+    popbox
+    # save gate area now and paint later, so that diffusion surrounding the
+    # contact does not paint over the gate area, in case the gate type is
+    # not part of a "compose" entry in the techfile.
+    set gaterect [box values]
+    popbox
+
+    # Adjust position of contacts for dogbone geometry
+    # Rule 1: Minimize diffusion length.  Contacts only move out
+    # if width <  contact diffusion height.  They move out enough
+    # that the diffusion-to-poly spacing is satisfied.
+
+    set ddover 0
+    set cdwmin [+ ${contact_size} [* ${diff_surround} 2]]
+    set cstem [- ${gate_to_diffcont} [/ ${cdwmin} 2.0]]
+    set cgrow [- ${diff_poly_space} ${cstem}]
+    if {[+ ${w} ${eps}] < ${cdwmin}} {
+        if {${cgrow} > 0} {
+            set gate_to_diffcont [+ ${gate_to_diffcont} ${cgrow}]
+        }
+	set ddover [/ [- ${cdwmin} ${w}] 2.0]
+    }
+
+    # Rule 2: Minimum poly width.  Poly contacts only move out
+    # if length < contact poly width.  They move out enough
+    # that the diffusion-to-poly spacing is satisfied.
+
+    set gporig ${gate_to_polycont}
+    set cplmin [+ ${contact_size} [* ${poly_surround} 2]]
+    set cstem [- ${gate_to_polycont} [/ ${cplmin} 2.0]]
+    set cgrow [- ${diff_poly_space} ${cstem}]
+    if {[+ ${l} ${eps}] < ${cplmin}} {
+        if {${cgrow} > 0} {
+            set gate_to_polycont [+ ${gate_to_polycont} ${cgrow}]
+        }
+    }
+
+    # Rule 3: If both poly and diffusion are dogboned, then move
+    # poly out further to clear spacing to the diffusion contact
+
+    if {[+ ${w} ${eps}] < ${cdwmin}} {
+        if {[+ ${l} ${eps}] < ${cplmin}} {
+            set cgrow [/ [- ${cplmin} ${w}] 2.0]
+            set gate_to_polycont [+ ${gate_to_polycont} ${cgrow}]
+        }
+    }
+
+    # Rule 4: If M > 1 and poly contacts overlap, then increase the
+    # transistor-to-poly-contact distance by the amount of any
+    # diffusion dogbone overhang.
+
+    if {($poverlap == 1) && ($m > 1)} {
+	if {${gate_to_polycont} - $gporig < $ddover} {
+	    set gate_to_polycont [+ ${gporig} ${ddover}]
+	}
+    }
+
+    # Reduce contact sizes by poly or diffusion surround so that
+    # the contact area edges match the device diffusion or poly.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set tsurround [+ ${diff_surround} ${diff_overlap_cont}]
+    set cdw [- ${w} [* ${tsurround} 2]]		;# diff contact height
+    set cpl [- ${l} [* ${poly_surround} 2]]     ;# poly contact width
+
+    # Save the full diffusion (source/drain) and poly (gate) lengths
+    set cdwfull $cdw
+    set cplfull $cpl
+
+    # Reduce by coverage percentage.  NOTE:  If overlapping multiple devices,
+    # keep maximum poly contact coverage.
+
+    set cdw [* ${cdw} [/ ${diffcov} 100.0]]
+    if {($poverlap == 0) || ($m == 1)} {
+	set cpl [* ${cpl} [/ ${polycov} 100.0]]
+    }
+
+    # Right diffusion contact
+    pushbox
+    box move e ${he}um
+    box move e ${gate_to_diffcont}um
+
+    # Source via on top of contact
+    if {$evens == 1} {set viatype $viasrc} else {set viatype $viadrn}
+    if {$viatype != 0} {
+        pushbox
+        set cw $via_size
+    	set ch [* $cdwfull [/ [expr abs($viatype)] 100.0]]
+    	if {$ch < $via_size} {set ch $via_size}
+	box grow e [/ $cw 2]um
+	box grow w [/ $cw 2]um
+        set anchor [string index $viatype 0]
+	if {$anchor == "+"} {
+            box move s [/ [- $cdwfull $via_size] 2]um
+	    box grow n ${ch}um
+	} elseif {$anchor == "-"} {
+            box move n [/ [- $cdwfull $via_size] 2]um
+	    box grow s ${ch}um
+	} else {
+	    box grow n [/ $ch 2]um
+	    box grow s [/ $ch 2]um
+	}
+        sky130::mcon_draw vert
+        popbox
+    }
+    set cext [sky130::unionbox $cext [sky130::draw_contact 0 ${cdw} \
+		${diff_surround} ${metal_surround} ${contact_size}\
+		${diff_type} ${diff_contact_type} li vert]]
+    popbox
+    # Left diffusion contact
+    pushbox
+    box move w ${he}um
+    box move w ${gate_to_diffcont}um
+
+    # Drain via on top of contact
+    if {$evens == 1} {set viatype $viadrn} else {set viatype $viasrc}
+    if {$viatype != 0} {
+        pushbox
+        set cw $via_size
+    	set ch [* $cdwfull [/ [expr abs($viatype)] 100.0]]
+    	if {$ch < $via_size} {set ch $via_size}
+	box grow e [/ $cw 2]um
+	box grow w [/ $cw 2]um
+        set anchor [string index $viatype 0]
+	if {$anchor == "+"} {
+            box move s [/ [- $cdwfull $via_size] 2]um
+	    box grow n ${ch}um
+	} elseif {$anchor == "-"} {
+            box move n [/ [- $cdwfull $via_size] 2]um
+	    box grow s ${ch}um
+	} else {
+	    box grow n [/ $ch 2]um
+	    box grow s [/ $ch 2]um
+	}
+        sky130::mcon_draw vert
+        popbox
+    }
+    set cext [sky130::unionbox $cext [sky130::draw_contact 0 ${cdw} \
+		${diff_surround} ${metal_surround} ${contact_size} \
+		${diff_type} ${diff_contact_type} li vert]]
+    set diffarea $cext
+    popbox
+    # Top poly contact
+    if {$topc} {
+       pushbox
+       box move n ${hw}um
+       box move n ${gate_to_polycont}um
+
+       # Gate via on top of contact
+       if {$viagate != 0} {
+           pushbox
+    	   set ch $via_size
+    	   set cw [* $cplfull [/ [expr abs($viagate)] 100.0]]
+    	   if {$cw < $via_size} {set cw $via_size}
+	   box grow n [/ $ch 2]um
+	   box grow s [/ $ch 2]um
+           set anchor [string index $viagate 0]
+	   if {$anchor == "+"} {
+               box move w [/ [- $cplfull $via_size] 2]um
+	       box grow e ${cw}um
+	   } elseif {$anchor == "-"} {
+               box move e [/ [- $cplfull $via_size] 2]um
+	       box grow w ${cw}um
+	   } else {
+	       box grow e [/ $cw 2]um
+	       box grow w [/ $cw 2]um
+	   }
+           sky130::mcon_draw horz
+           popbox
+       }
+       set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${poly_surround} ${metal_surround} ${contact_size} \
+		${poly_type} ${poly_contact_type} li horz]]
+       popbox
+    }
+    # Bottom poly contact
+    if {$botc} {
+       pushbox
+       box move s ${hw}um
+       box move s ${gate_to_polycont}um
+
+       # Gate via on top of contact
+       if {$viagate != 0} {
+           pushbox
+    	   set ch $via_size
+    	   set cw [* $cplfull [/ [expr abs($viagate)] 100.0]]
+    	   if {$cw < $via_size} {set cw $via_size}
+	   box grow n [/ $ch 2]um
+	   box grow s [/ $ch 2]um
+           set anchor [string index $viagate 0]
+	   if {$anchor == "+"} {
+               box move w [/ [- $cplfull $via_size] 2]um
+	       box grow e ${cw}um
+	   } elseif {$anchor == "-"} {
+               box move e [/ [- $cplfull $via_size] 2]um
+	       box grow w ${cw}um
+	   } else {
+	       box grow e [/ $cw 2]um
+	       box grow w [/ $cw 2]um
+	   }
+           sky130::mcon_draw horz
+           popbox
+       }
+       set cext [sky130::unionbox $cext [sky130::draw_contact ${cpl} 0 \
+		${poly_surround} ${metal_surround} ${contact_size} \
+		${poly_type} ${poly_contact_type} li horz]]
+       popbox
+    }
+
+    # Now draw the gate, after contacts have been drawn
+    pushbox
+    box values {*}${gaterect}
+    # gate_type need not be defined if poly over diff paints the right type.
+    catch {paint ${gate_type}}
+    # sub_surround_dev, if defined, may create a larger area around the gate
+    # than sub_surround creates around the diffusion/poly area.
+    if [dict exists $parameters sub_surround_dev] {
+	box grow n ${sub_surround_dev}um
+	box grow s ${sub_surround_dev}um
+	box grow e ${sub_surround_dev}um
+	box grow w ${sub_surround_dev}um
+	paint ${dev_sub_type}
+	set cext [sky130::unionbox $cext [sky130::getbox]]
+    }
+    popbox
+
+    if {$dev_sub_type != ""} {
+	box values [lindex $diffarea 0]um [lindex $diffarea 1]um \
+	    [lindex $diffarea 2]um [lindex $diffarea 3]um
+	box grow n ${sub_surround}um
+	box grow s ${sub_surround}um
+	box grow e ${sub_surround}um
+	box grow w ${sub_surround}um
+	paint ${dev_sub_type}
+	if {$dev_sub_dist > 0} {
+	    set cext [sky130::unionbox $cext [sky130::getbox]]
+	}
+        # puts stdout "Diagnostic:  bounding box is $cext"
+    }
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# MOSFET: Draw the tiled device
+#----------------------------------------------------------------
+
+proc sky130::mos_draw {parameters} {
+    tech unlock *
+    set savesnap [snap]
+    snap internal
+
+    # Set defaults if they are not in parameters
+    set poverlap 0	;# overlap poly contacts when tiling
+    set doverlap 1	;# overlap diffusion contacts when tiling
+    set dev_sub_dist 0	;# substrate to guard ring, if dev_sub_type defined
+    set dev_sub_space 0	;# distance between substrate areas for arrayed devices
+    set min_allc 0	;# gate length below which poly contacts must be interleaved
+    set id_type ""	;# additional type covering everything
+    set id_surround 0	;# amount of surround on above type
+    set id2_type ""	;# additional type covering everything
+    set id2_surround 0	;# amount of surround on above type
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Diff-to-tap spacing is by default the same as diff spacing
+    if {![dict exist $parameters diff_tap_space]} {
+	set diff_tap_space $diff_spacing
+    }
+
+    # If poverlap is 1 then both poly contacts must be present
+    if {$poverlap == 1} {
+	set topc 1
+	set botc 1
+	dict set parameters topc 1
+	dict set parameters botc 1
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # If dx < (poly contact space + poly contact width), then there is not
+    # enough room for a row of contacts, so force alternating contacts
+
+    set evens 1
+    if {$nf > 1 && $l < $min_allc} {
+	set intc 1
+	set evenodd 1
+	set topc 1
+	set botc 1
+	dict set parameters topc 1
+	dict set parameters botc 1
+	set poverlap 0
+    } else {
+	set intc 0
+    }
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set bbox [sky130::mos_device $parameters]
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # If dev_sub_dist > 0 then each device must be in its own substrate
+    # (well) area, and overlaps are disallowed.  dev_sub_space determines
+    # the distance between individual devices in an array.
+
+    if {$dev_sub_dist > 0} {
+        set poverlap 0
+        set doverlap 0
+
+	if {$dev_sub_space > $poly_spacing} {
+	    set dx [+ $fw $dev_sub_space]
+	    set dy [+ $fh $dev_sub_space]
+	} else {
+	    set dx [+ $fw $poly_spacing]
+	    set dy [+ $fh $poly_spacing]
+	}
+
+    } else {
+
+	# Determine tile width and height (depends on overlap)
+	if {$poverlap == 0} {
+	    set dy [+ $fh $poly_spacing]
+	} else {
+	    # overlap poly
+	    set dy [- $fh [+ $poly_surround $poly_surround $contact_size]]
+	}
+
+	if {$doverlap == 0} {
+	    set dx [+ $fw $diff_spacing]
+	} else {
+	    # overlap diffusions
+	    set dx [- $fw [+ $diff_surround $diff_surround $contact_size]]
+	}
+    }
+
+    # Determine core width and height
+    set corex [+ [* [- $nf 1] $dx] $fw]
+    set corey [+ [* [- $m 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    # If there is a diffusion dogbone, and no top poly contact, then
+    # increase the core height by the amount of the dogbone overhang.
+
+    if {$topc == 0} {
+	set cdwmin [+ ${contact_size} [* ${diff_surround} 2]]
+	if {${w} < ${cdwmin}} {
+	    set corey [+ $corey [/ [- ${cdwmin} ${w}] 2.0]]
+	}
+    }
+
+    # Calculate guard ring size (measured to contact center)
+    if {($guard != 0) || (${id_type} != "")} {
+	if {($dev_sub_dist > 0) && ([+ $dev_sub_dist $sub_surround] > $diff_tap_space)} {
+	    set gx [+ $corex [* 2.0 [+ $dev_sub_dist $diff_surround]] $contact_size]
+	} else {
+	    set gx [+ $corex [* 2.0 [+ $diff_tap_space $diff_surround]] $contact_size]
+	}
+	if {($dev_sub_dist > 0) && ([+ $dev_sub_dist $sub_surround] > $diff_gate_space)} {
+	    set gy [+ $corey [* 2.0 [+ $dev_sub_dist $diff_surround]] $contact_size]
+	} else {
+	    set gy [+ $corey [* 2.0 [+ $diff_gate_space $diff_surround]] $contact_size]
+	}
+
+	# Somewhat tricky. . . if the width is small and the diffusion is 
+	# a dogbone, and the top or bottom poly contact is missing, then
+	# the spacing to the guard ring may be limited by diffusion spacing, not
+	# poly to diffusion.
+
+	set inset [/ [+ $contact_size [* 2.0 $diff_surround] -$w] 2.0]
+	set sdiff [- [+ $inset $diff_tap_space] [+ $gate_extension $diff_gate_space]]
+
+	if {$sdiff > 0} {
+	    if {$topc == 0} {
+		set gy [+ $gy $sdiff]
+		set corelly [+ $corelly [/ $sdiff 2.0]]
+	    }
+	    if {$botc == 0} {
+		set gy [+ $gy $sdiff]
+		set corelly [- $corelly [/ $sdiff 2.0]]
+	    }
+	}
+    }
+    if {$guard != 0} {
+	# Draw the guard ring first, as MOS well may interact with guard ring substrate
+	sky130::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    # If any surrounding identifier type is defined, draw it
+    if {${id_type} != ""} {
+	set hw [/ $gx 2]
+	set hh [/ $gy 2]
+	box grow e ${hw}um
+	box grow w ${hw}um
+	box grow n ${hh}um
+	box grow s ${hh}um
+	box grow c ${id_surround}um
+	paint ${id_type}
+    }
+    popbox
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    for {set xp 0} {$xp < $nf} {incr xp} {
+	dict set parameters evens $evens
+	set evens [- 1 $evens]
+        pushbox
+	if {$intc == 1} {
+	    set evenodd [- 1 $evenodd]
+	    if {$evenodd == 1} {
+		dict set parameters topc 1
+		dict set parameters botc 0
+	    } else {
+		dict set parameters topc 0
+		dict set parameters botc 1
+	    }
+	    set saveeo $evenodd
+	}
+        for {set yp 0} {$yp < $m} {incr yp} {
+            sky130::mos_device $parameters
+            box move n ${dy}um
+	    if {$intc == 1} {
+		set evenodd [- 1 $evenodd]
+		if {$evenodd == 1} {
+		    dict set parameters topc 1
+		    dict set parameters botc 0
+		} else {
+		    dict set parameters topc 0
+		    dict set parameters botc 1
+		}
+	    }
+        }
+	if {$intc == 1} {
+	    set evenodd $saveeo
+	}
+        popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    snap $savesnap
+    tech revert
+}
+
+#-------------------
+# nMOS 1.8V
+#-------------------
+
+proc sky130::sky130_fd_pr__nfet_01v8_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nfet \
+	    diff_type 		ndiff \
+	    diff_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__nfet_01v8_lvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nfetlvt \
+	    diff_type 		ndiff \
+	    diff_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sky130_fd_bs_flash__special_sonosfet_star_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nsonos \
+	    diff_type 		ndiff \
+	    diff_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    id_type		dnwell \
+	    id_surround		1.355 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#-------------------
+# pMOS 1.8V
+#-------------------
+
+proc sky130::sky130_fd_pr__pfet_01v8_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		pfet \
+	    diff_type 		pdiff \
+	    diff_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    dev_sub_type	nwell \
+	    gate_to_polycont	0.32 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_lvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		pfetlvt \
+	    diff_type 		pdiff \
+	    diff_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    dev_sub_type	nwell \
+	    gate_to_polycont	0.32 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_hvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		pfethvt \
+	    diff_type 		pdiff \
+	    diff_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    dev_sub_type	nwell \
+	    gate_to_polycont	0.32 \
+	    min_effl		0.185 \
+	    min_allc		0.26 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#-------------------
+# pMOS 5.0V
+#-------------------
+
+proc sky130::sky130_fd_pr__pfet_g5v0d10v5_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvpfet \
+	    diff_type 		mvpdiff \
+	    diff_contact_type	mvpdc \
+	    plus_diff_type	mvnsd \
+	    plus_contact_type	mvnsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		nwell \
+	    dev_sub_type	nwell \
+	    guard_sub_surround	0.33 \
+	    gate_to_polycont	0.32 \
+	    diff_spacing	0.31 \
+	    diff_tap_space	0.38 \
+	    diff_gate_space	0.38 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#-------------------
+# nMOS 5.0V
+#-------------------
+
+proc sky130::sky130_fd_pr__nfet_g5v0d10v5_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvnfet \
+	    diff_type 		mvndiff \
+	    diff_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    diff_spacing	0.31 \
+	    diff_tap_space	0.38 \
+	    diff_gate_space	0.38 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__nfet_05v0_nvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvnnfet \
+	    diff_type 		mvndiff \
+	    diff_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    diff_spacing	0.30 \
+	    diff_tap_space	0.38 \
+	    diff_gate_space	0.38 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__nfet_03v3_nvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nnfet \
+	    diff_type 		mvndiff \
+	    diff_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    diff_spacing	0.30 \
+	    diff_tap_space	0.38 \
+	    diff_gate_space	0.38 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#------------------------
+# MOS varactor (1.8V)
+#------------------------
+
+proc sky130::sky130_fd_pr__cap_var_lvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		var \
+	    diff_type 		nnd \
+	    diff_contact_type	nsc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    dev_sub_type	nwell \
+	    diff_overlap_cont	0.06 \
+	    dev_sub_dist	0.14 \
+	    dev_sub_space	1.27 \
+	    gate_to_diffcont	0.34 \
+	    diff_extension	0.485 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+proc sky130::sky130_fd_pr__cap_var_hvt_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		varhvt \
+	    diff_type 		nnd \
+	    diff_contact_type	nsc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    dev_sub_type	nwell \
+	    diff_overlap_cont	0.06 \
+	    dev_sub_dist	0.14 \
+	    dev_sub_space	1.27 \
+	    gate_to_diffcont	0.34 \
+	    diff_extension	0.485 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#---------------------------------------------------------
+# MOS varactor (5.0V)
+# NOTE:  dev_sub_space set to 2.0 assuming different nets.
+# Should have option for same-net with merged wells.
+#---------------------------------------------------------
+
+proc sky130::sky130_fd_pr__cap_var_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvvar \
+	    diff_type 		mvnsd \
+	    diff_contact_type	mvnsc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		psub \
+	    dev_sub_type	nwell \
+	    sub_surround	0.38 \
+	    sub_surround_dev	0.56 \
+	    guard_sub_surround	0.18 \
+	    diff_overlap_cont	0.06 \
+	    dev_sub_dist	0.785 \
+	    dev_sub_space	2.0 \
+	    gate_to_diffcont	0.34 \
+	    diff_extension	0.485 \
+    ]
+    set drawdict [dict merge $sky130::ruleset $newdict $parameters]
+    return [sky130::mos_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# MOSFET: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::mos_check {device parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l] 
+    set l [magic::3digitpastdecimal $l]
+    set w [magic::spice2float $w] 
+    set w [magic::3digitpastdecimal $w]
+
+    # nf, m must be integer
+    if {![string is int $nf]} {
+	puts stderr "NF must be an integer!"
+        dict set parameters nf 1
+    }
+    if {![string is int $m]} {
+	puts stderr "M must be an integer!"
+        dict set parameters m 1
+    }
+    # diffcov, polycov must be numeric
+    if {[catch {expr abs($diffcov)}]} {
+	puts stderr "diffcov must be numeric!"
+	set diffcov 100
+	dict set parameters diffcov $diffcov
+    }
+    if {[catch {expr abs($polycov)}]} {
+	puts stderr "polycov must be numeric!"
+	set polycov 100
+	dict set parameters polycov $polycov
+    }
+
+    if {$l < $lmin} {
+	puts stderr "Mos length must be >= $lmin um"
+        dict set parameters l $lmin
+    } 
+    if {$w < $wmin} {
+	puts stderr "Mos width must be >= $wmin um"
+        dict set parameters w $wmin
+    } 
+    if {$nf < 1} {
+	puts stderr "NF must be >= 1"
+        dict set parameters nf 1
+    } 
+    if {$m < 1} {
+	puts stderr "M must be >= 1"
+        dict set parameters m 1
+    } 
+    if {$diffcov < 20 } {
+	puts stderr "Diffusion contact coverage must be at least 20%"
+        dict set parameters diffcov 20
+    } elseif {$diffcov > 100 } {
+	puts stderr "Diffusion contact coverage can't be more than 100%"
+        dict set parameters diffcov 100
+    }
+    if {$polycov < 20 } {
+	puts stderr "Poly contact coverage must be at least 20%"
+        dict set parameters polycov 20
+    } elseif {$polycov > 100 } {
+	puts stderr "Poly contact coverage can't be more than 100%"
+        dict set parameters polycov 100
+    }
+
+    if {[catch {expr abs($viasrc)}]} {
+	puts stderr "Source via coverage must be numeric!"
+        dict set parameters viasrc 100
+    } elseif {[expr abs($viasrc)] > 100} {
+	puts stderr "Source via coverage can't be more than 100%"
+        dict set parameters viasrc 100
+    }
+    if {[catch {expr abs($viadrn)}]} {
+	puts stderr "Drain via coverage must be numeric!"
+        dict set parameters viadrn 100
+    } elseif {[expr abs($viadrn)] > 100} {
+	puts stderr "Drain via coverage can't be more than 100%"
+        dict set parameters viadrn 100
+    }
+    if {[catch {expr abs($viagate)}]} {
+	puts stderr "Gate via coverage must be numeric!"
+        dict set parameters viagate 100
+    } elseif {[expr abs($viagate)] > 100} {
+	puts stderr "Gate via coverage can't be more than 100%"
+        dict set parameters viagate 100
+    }
+    if {[catch {expr abs($viagb)}]} {
+	puts stderr "Guard ring bottom via coverage must be numeric!"
+        dict set parameters viagb 0
+    } elseif {[expr abs($viagb)] > 100} {
+	puts stderr "Guard ring bottom via coverage can't be more than 100%"
+        dict set parameters viagb 100
+    }
+    if {[catch {expr abs($viagt)}]} {
+	puts stderr "Guard ring top via coverage must be numeric!"
+        dict set parameters viagt 0
+    } elseif {[expr abs($viagt)] > 100} {
+	puts stderr "Guard ring top via coverage can't be more than 100%"
+        dict set parameters viagt 100
+    }
+    if {[catch {expr abs($viagr)}]} {
+	puts stderr "Guard ring right via coverage must be numeric!"
+        dict set parameters viagr 0
+    } elseif {[expr abs($viagr)] > 100} {
+	puts stderr "Guard ring right via coverage can't be more than 100%"
+        dict set parameters viagr 100
+    }
+    if {[catch {expr abs($viagl)}]} {
+	puts stderr "Guard ring left via coverage must be numeric!"
+        dict set parameters viagl 0
+    } elseif {[expr abs($viagl)] > 100} {
+	puts stderr "Guard ring left via coverage can't be more than 100%"
+        dict set parameters viagl 100
+    }
+
+    # Values must satisfy diffusion-to-tap spacing of 20um.
+    # Therefore the maximum of guard ring width or height cannot exceed 40um.
+    # If in violation, reduce counts first, as these are easiest to recover
+    # by duplicating the device and overlapping the wells.
+    set origm $m
+    set orignf $nf
+    while true {
+       set yext [expr ($w + 3.0) * $m]
+       set xext [expr ($l + 1.0) * $nf + 1.1]
+       if {[expr min($xext, $yext)] > 40.0} {
+          if {$yext > 40.0 && $m > 1} {
+	     incr m -1
+	  } elseif {$xext > 40.0 && $nf > 1} {
+	     incr nf -1
+	  } elseif {$yext > 40.0} {
+	     set w 37
+	     puts -nonewline stderr "Transistor width must be < 37 um"
+	     puts stderr " to avoid tap spacing violation."
+	     dict set parameters w $w
+	  } elseif {$xext > 40.0} {
+	     set l 37.9
+	     puts -nonewline stderr "Transistor length must be < 37.9 um"
+	     puts stderr " to avoid tap spacing violation."
+	     dict set parameters l $l
+	  }
+       } else {
+	  break
+       }
+    }
+    if {$m != $origm} {
+       puts stderr "Y repeat reduced to prevent tap distance violation"
+       dict set parameters m $m
+    }
+    if {$nf != $orignf} {
+       puts stderr "X repeat reduced to prevent tap distance violation"
+       dict set parameters nf $nf
+    }
+
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__nfet_01v8_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__nfet_01v8 $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_01v8_lvt_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__nfet_01v8_lvt $parameters]
+}
+
+proc sky130::sky130_fd_bs_flash__special_sonosfet_star_check {parameters} {
+   return [sky130::mos_check sky130_fd_bs_flash__special_sonosfet_star $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_g5v0d10v5_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__nfet_g5v0d10v5 $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_05v0_nvt_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__nfet_05v0_nvt $parameters]
+}
+
+proc sky130::sky130_fd_pr__nfet_03v3_nvt_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__nfet_03v3_nvt $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__pfet_01v8 $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_lvt_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__pfet_01v8_lvt $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_01v8_hvt_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__pfet_01v8_hvt $parameters]
+}
+
+proc sky130::sky130_fd_pr__pfet_g5v0d10v5_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__pfet_g5v0d10v5 $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_var_lvt_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__cap_var_lvt $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_var_hvt_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__cap_var_hvt $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_var_check {parameters} {
+   return [sky130::mos_check sky130_fd_pr__cap_var $parameters]
+}
+
+#----------------------------------------------------------------
+# Fixed device: Specify all user-editable default values
+#
+# deltax --- Additional horizontal space between devices
+# deltay --- Additional vertical space between devices
+# nx     --- Number of arrayed devices in X
+# ny     --- Number of arrayed devices in Y
+#
+# Note that these values, specifically nx, ny, deltax,
+# and deltay, are properties of the instance, not the cell.
+# They translate to the instance array x and y counts;  while
+# deltax is the x pitch less the cell width, and deltay is the
+# y pitch less the cell height.
+#
+# non-user-editable
+#
+# nocell --- Indicates that this cell has a predefined layout
+#	     and therefore there is no cell to draw.
+# xstep  --- Width of the cell (nominal array pitch in X)
+# ystep  --- Height of the cell (nominal array pitch in Y)
+#----------------------------------------------------------------
+
+# Fixed-layout devices (from sky130_fd_pr_base, _rf, and _rf2 libraries)
+#
+# Bipolar transistors:
+#
+# sky130_fd_pr__rf_npn_05v5_W1p00L1p00
+# sky130_fd_pr__rf_npn_05v5_W1p00L2p00
+# sky130_fd_pr__rf_pnp_05v5_W3p40L3p40
+# sky130_fd_pr__rf_pnp_05v5_W0p68L0p68
+#
+# Parallel Plate Capacitors:
+#
+# sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldlim5
+# sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield
+# sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1
+# sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1
+#
+# Inductors:
+#
+# sky130_fd_pr__rf_test_coil1
+# sky130_fd_pr__rf_test_coil2
+# sky130_fd_pr__rf_test_coil3
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L1p00_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 7.03 ystep 7.03}
+}
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L2p00_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 7.03 ystep 8.03}
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W0p68L0p68_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 3.72 ystep 3.72}
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 6.44 ystep 6.44}
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil1_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 258 ystep 258}
+}
+proc sky130::sky130_fd_pr__rf_test_coil2_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 290 ystep 404}
+}
+proc sky130::sky130_fd_pr__rf_test_coil3_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 290 ystep 404}
+}
+
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+proc sky130::sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+proc sky130::sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 11.08 ystep 11.36}
+}
+
+#----------------------------------------------------------------
+# Fixed device: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc sky130::fixed_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    m {
+		 dict set pdkparams nx $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L1p00_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L2p00_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W0p68L0p68_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil1_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil2_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil3_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1_convert {parameters} {
+    return [sky130::fixed_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# Fixed device: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc sky130::fixed_dialog {parameters} {
+    # Instance fields:	    nx, ny, pitchx, pitchy
+    # Editable fields:	    nx, ny, deltax, deltay
+    # Non-editable fields:  nocell, xstep, ystep
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # "nocell" field causes nx and ny to be dropped in from
+    # "array count".  Also "pitchx" and "pitchy" are passed
+    # in internal units.  Convert these to microns and generate
+    # If there is no pitchx and pitchy, then the device has not
+    # yet been created, so keep the deltax and deltay defaults.
+
+    if [dict exists $parameters pitchx] {
+	set pitchux [magic::i2u $pitchx]
+	set stepux [magic::spice2float $xstep]
+        set deltax [magic::3digitpastdecimal [expr $pitchux - $stepux]] 
+        # An array size 1 should not cause deltax to go negative
+	if {$deltax < 0.0} {set deltax 0.0}
+	dict set parameters deltax $deltax
+    }
+    if [dict exists $parameters pitchy] {
+	set pitchuy [magic::i2u $pitchy]
+	set stepuy [magic::spice2float $ystep]
+        set deltay [magic::3digitpastdecimal [expr $pitchuy - $stepuy]] 
+        # An array size 1 should not cause deltay to go negative
+	if {$deltay < 0.0} {set deltay 0.0}
+	dict set parameters deltay $deltay
+    }
+
+    magic::add_entry nx "NX" $parameters
+    magic::add_entry ny "NY" $parameters
+    magic::add_entry deltax "X step (um)" $parameters
+    magic::add_entry deltay "Y step (um)" $parameters
+}
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L1p00_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L2p00_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W0p68L0p68_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil1_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil2_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil3_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+proc sky130::sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+proc sky130::sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1_dialog {parameters} {
+    sky130::fixed_dialog $parameters
+}
+
+#----------------------------------------------------------------
+# Fixed device: Draw the device
+#----------------------------------------------------------------
+
+proc sky130::fixed_draw {devname parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # This cell declares "nocell" in parameters, so it needs to
+    # instance the cell and set properties.
+
+    # Instantiate the cell.  The name corresponds to the cell in the sky130_fd_pr_* directory.
+    set instname [getcell ${devname}]
+
+    set deltax [magic::spice2float $deltax] 
+    set deltay [magic::spice2float $deltay] 
+    set xstep [magic::spice2float $xstep] 
+    set ystep [magic::spice2float $ystep] 
+
+    # Array stepping
+    if {$nx > 1 || $ny > 1} {
+        set xstep [expr $xstep + $deltax]
+        set ystep [expr $ystep + $deltay]
+        box size ${xstep}um ${ystep}um
+	array $nx $ny
+    }
+    select cell $instname
+    expand
+    return $instname
+}
+
+#----------------------------------------------------------------
+# No additional parameters declared for drawing
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L1p00_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__rf_npn_05v5_W1p00L1p00 $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L2p00_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__rf_npn_05v5_W1p00L2p00 $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W0p68L0p68_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__rf_pnp_05v5_W0p68L0p68 $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__rf_pnp_05v5_W3p40L3p40 $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil1_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__rf_test_coil1 $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil2_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__rf_test_coil2 $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil3_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__rf_test_coil3 $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5 $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1 $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1_draw {parameters} {
+    return [sky130::fixed_draw sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1 $parameters]
+}
+
+#----------------------------------------------------------------
+# Fixed device: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc sky130::fixed_check {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set deltax [magic::spice2float $deltax -1] 
+    set deltax [magic::3digitpastdecimal $deltax]
+    set deltay [magic::spice2float $deltay -1] 
+    set deltay [magic::3digitpastdecimal $deltay]
+
+    # nx, ny must be integer
+    if {![string is int $nx]} {
+	puts stderr "NX must be an integer!"
+        dict set parameters nx 1
+    }
+    if {![string is int $ny]} {
+	puts stderr "NY must be an integer!"
+        dict set parameters nx 1
+    }
+
+    # Number of devices in X and Y must be at least 1
+    if {$nx < 1} {
+	puts stderr "NX must be >= 1"
+        dict set parameters nx 1
+    }
+    if {$ny < 1} {
+	puts stderr "NY must be >= 1"
+        dict set parameters nx 1
+    }
+    # Step less than zero violates DRC
+    if {$deltax < 0} {
+	puts stderr "X step must be >= 0"
+        dict set parameters deltax 0
+    }
+    if {$deltay < 0} {
+	puts stderr "Y step must be >= 0"
+        dict set parameters deltay 0
+    }
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L1p00_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_npn_05v5_W1p00L2p00_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W0p68L0p68_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_pnp_05v5_W3p40L3p40_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil1_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil2_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr__rf_test_coil3_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_shieldl1_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+proc sky130::sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_shieldl1_check {parameters} {
+    return [sky130::fixed_check $parameters]
+}
+#-------------------------------------------------------------------
+# General-purpose routines for the PDK script in all technologies
+#-------------------------------------------------------------------
+# 
+#----------------------------------------
+# Number Conversion Functions
+#----------------------------------------
+
+#---------------------
+# Microns to Lambda
+#---------------------
+proc magic::u2l {micron} {
+    set techlambda [magic::tech lambda]
+    set tech1 [lindex $techlambda 1]
+    set tech0 [lindex $techlambda 0]
+    set tscale [expr {$tech1 / $tech0}]
+    set lambdaout [expr {((round([magic::cif scale output] * 10000)) / 10000.0)}]
+    return [expr $micron / ($lambdaout*$tscale) ]
+}
+
+#---------------------
+# Lambda to Microns
+#---------------------
+proc magic::l2u {lambda} {
+    set techlambda [magic::tech lambda]
+    set tech1 [lindex $techlambda 1] ; set tech0 [lindex $techlambda 0]
+    set tscale [expr {$tech1 / $tech0}]
+    set lambdaout [expr {((round([magic::cif scale output] * 10000)) / 10000.0)}]
+    return [expr $lambda * $lambdaout * $tscale ]
+}
+
+#---------------------
+# Internal to Microns
+#---------------------
+proc magic::i2u { value } {
+    return [expr {((round([magic::cif scale output] * 10000)) / 10000.0) * $value}]
+}
+
+#---------------------
+# Microns to Internal
+#---------------------
+proc magic::u2i {value} {
+    return [expr {$value / ((round([magic::cif scale output] * 10000)) / 10000.0)}]
+}
+
+#---------------------
+# Float to Spice 
+#---------------------
+proc magic::float2spice {value} { 
+    if {$value >= 1.0e+6} { 
+	set exponent 1e+6
+	set unit "meg"
+    } elseif {$value >= 1.0e+3} { 
+	set exponent 1e+3
+	set unit "k"
+    } elseif { $value >= 1} { 
+	set exponent 1
+	set unit ""
+    } elseif {$value >= 1.0e-3} { 
+	set exponent 1e-3
+	set unit "m"
+    } elseif {$value >= 1.0e-6} { 
+	set exponent 1e-6
+	set unit "u"
+    } elseif {$value >= 1.0e-9} { 
+	set exponent 1e-9
+	set unit "n"
+    } elseif {$value >= 1.0e-12} { 
+	set exponent 1e-12
+	set unit "p"
+    } elseif {$value >= 1.0e-15} { 
+	set exponent 1e-15
+	set unit "f"
+    } else {
+	set exponent 1e-18
+	set unit "a"
+    }
+    set val [expr $value / $exponent]
+    set val [expr int($val * 1000) / 1000.0]
+    if {$val == 0} {set unit ""}
+    return $val$unit
+}
+
+#---------------------
+# Spice to Float
+#---------------------
+proc magic::spice2float {value {faultval 0.0}} { 
+    # Remove trailing units, at least for some common combinations
+    set value [string tolower $value]
+    set value [string map {um u nm n uF n nF n pF p aF a} $value]
+    set value [string map {meg "* 1.0e6" k "* 1.0e3" m "* 1.0e-3" u "* 1.0e-6" \
+		 n "* 1.0 e-9" p "* 1.0e-12" f "* 1.0e-15" a "* 1.0e-15"} $value]
+    if {[catch {set rval [expr $value]}]} {
+	puts stderr "Value is not numeric!"
+	set rval $faultval
+    }
+    return $rval
+}
+
+#---------------------
+# Numeric Precision
+#---------------------
+proc magic::3digitpastdecimal {value} {
+    set new [expr int([expr $value * 1000 + 0.5 ]) / 1000.0]
+    return $new
+}
+
+#-------------------------------------------------------------------
+# File Access Functions
+#-------------------------------------------------------------------
+
+#-------------------------------------------------------------------
+# Ensures that a cell name does not already exist, either in
+# memory or on disk. Modifies the name until it does.
+#-------------------------------------------------------------------
+proc magic:cellnameunique {cellname} {
+    set i 0
+    set newname $cellname
+    while {[cellname list exists $newname] != 0 || [magic::searchcellondisk $newname] != 0} {
+	incr i
+	set newname ${cellname}_$i
+    }
+    return $newname
+}
+
+#-------------------------------------------------------------------
+# Looks to see if a cell exists on disk
+#-------------------------------------------------------------------
+proc magic::searchcellondisk {name} {
+    set rlist {}
+    foreach dir [path search] {
+	set ftry [file join $dir ${name}.mag]
+	if [file exists $ftry] {
+	    return 1
+	}
+    }
+    return 0
+} 
+
+#-------------------------------------------------------------------
+# Checks to see if a cell already exists on disk or in memory
+#-------------------------------------------------------------------
+proc magic::iscellnameunique {cellname} {
+    if {[cellname list exists $cellname] == 0 && [magic::searchcellondisk $cellname] == 0} { 
+	return 1
+    } else {
+	return 0
+    }
+}
+
+#--------------------------------------------------------------
+# Procedure that checks the user's "ip" subdirectory on startup
+# and adds each one's maglef subdirectory to the path.
+#--------------------------------------------------------------
+
+proc magic::query_mylib_ip {} {
+    global TECHPATH
+    global env
+    if [catch {set home $env(SUDO_USER)}] {
+        set home $env(USER)
+    }
+    set homedir /home/${home}
+    set ip_dirs [glob -directory ${homedir}/design/ip *]
+    set proj_dir [pwd]
+    set config_dir .config
+    set info_dir ${proj_dir}/${config_dir}
+    if {![file exists ${info_dir}]} {
+	set config_dir .ef-config
+	set info_dir ${proj_dir}/${config_dir}
+    }
+
+    set info_file ${info_dir}/info
+    set depends [dict create]
+    if {![catch {open $info_file r} ifd]} {
+        set depsec false
+        while {[gets $ifd line] >= 0} {
+	    if {[string first dependencies: $line] >= 0} {
+	        set depsec true
+	    }
+	    if {$depsec} {
+		if {[string first version: $line] >= 0} {
+		    if {$ipname != ""} {
+			set ipvers [string trim [lindex [split $line] 1] ']
+			dict set depends $ipname $ipvers
+			set ipname ""
+		    } else {
+			puts stderr "Badly formatted info file in ${config_dir}!"
+		    }
+		} else {
+		    set ipname [string trim $line :]
+		}
+	    }
+	}
+    }
+
+    foreach dir $ip_dirs {
+	# Version handling:  version dependencies are found in
+	# ${config_dir}/info.  For all other IP, use the most recent
+	# version number.
+	set ipname [lindex [file split $dir] end]
+	if {![catch {set version [dict get $depends $ipname]}]} {
+	    if {[file isdirectory ${dir}/${version}/maglef]} {
+		addpath ${dir}/${version}/maglef
+		continue
+	    } else {
+		puts stderr "ERROR:  Dependency ${ipname} version ${version} does not exist"
+	    }
+	}
+
+	# Secondary directory is the version number.  Use the highest
+	# version available.
+
+	set sub_dirs {}
+        catch {set sub_dirs [glob -directory $dir *]}
+	set maxver 0.0
+	foreach subdir $sub_dirs {
+	    set vidx [string last / $subdir]
+	    incr vidx
+	    set version [string range $subdir $vidx end]
+	    if {$version > $maxver} {
+		set maxver $version
+	    }
+	}
+	if {[file exists ${dir}/${maxver}/maglef]} {
+	    # Compatibility rule:  foundry name must match.
+	    # Get foundry name from ${config_dir}/techdir symbolic link reference
+	    if {[file exists ${dir}/${maxver}/${config_dir}/techdir]} {
+		set technodedir [file link ${dir}/${maxver}/${config_dir}/techdir]
+		set nidx [string last / $technodedir]
+		set techdir [string range $technodedir 0 $nidx-1]
+		if {$techdir == $TECHPATH} {
+		    addpath ${dir}/${maxver}/maglef
+		}
+	    }
+	}
+    }
+}
+
+#--------------------------------------------------------------
+# Procedure that checks the user's design directory on startup
+# and adds each one's mag subdirectory to the path.
+#--------------------------------------------------------------
+
+proc magic::query_my_projects {} {
+    global TECHPATH
+    global env
+    if [catch {set home $env(SUDO_USER)}] {
+        set home $env(USER)
+    }
+    set homedir /home/${home}
+    set proj_dirs [glob -directory ${homedir}/design *]
+    foreach dir $proj_dirs {
+	# Compatibility rule:  foundry name must match.
+	# Get foundry name from ${config_dir}/techdir symbolic link reference
+	if {[file exists ${dir}/mag]} {
+	    set config_dir .config
+	    set tech_dir ${dir}/${config_dir}
+	    if {![file exists ${tech_dir}]} {
+		set config_dir .ef-config
+		set tech_dir ${dir}/${config_dir}
+	    }
+	    if {[file exists ${dir}/${config_dir}/techdir]} {
+		set technodedir [file link ${dir}/${config_dir}/techdir]
+		set nidx [string last / $technodedir]
+		set techdir [string range $technodedir 0 $nidx-1]
+		if {$techdir == $TECHPATH} {
+		    addpath ${dir}/mag
+		}
+	    }
+	}
+    }
+}
+
+#----------------------------------------------------------------

mag/sky130A.tech

diff --git a/mag/sky130A.tech b/mag/sky130A.tech
new file mode 100755
index 0000000..d61e19d
--- /dev/null
+++ b/mag/sky130A.tech
@@ -0,0 +1,6031 @@
+#------------------------------------------------------------------------
+# Copyright (c) 2020 R. Timothy Edwards
+# Revisions:  See below
+#
+# This file is an Open Source foundry process describing
+# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
+# process.  The file may be distributed under the terms
+# of the Apache 2.0 license agreement.
+#
+#------------------------------------------------------------------------
+tech
+  format 35
+  sky130A
+end
+
+version
+ version 1.0.310-0-gd7faec2
+ description "SkyWater SKY130: Open Source rules and DRC"
+ requires magic-8.3.277
+end
+
+#------------------------------------------------------------------------
+# Status 7/10/20: Rev 1 (alpha):
+# First public release
+# Status 8/14/20: Rev 2 (alpha):
+# Started updating with new device/model naming convention
+# Status 1/3/21: Taking out of beta and declaring an official release.
+# Status 3/17/22: Added fringeshieldhalo to improve parasitic capacitance
+#		  calculations.
+#------------------------------------------------------------------------
+
+#------------------------------------------------------------------------
+# Supported device types
+#------------------------------------------------------------------------
+# device name			magic ID layer	description
+#------------------------------------------------------------------------
+# sky130_fd_pr__nfet_01v8	nfet		standard nFET
+# sky130_fd_pr__nfet_01v8	scnfet		standard nFET in standard cell**
+# sky130_fd_pr__special_nfet_latch npd		special nFET in SRAM cell
+# sky130_fd_pr__special_nfet_pass  npass	special nFET in SRAM cell
+# sky130_fd_pr__nfet_01v8_lvt	nfetlvt		low Vt nFET
+# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
+# sky130_fd_pr__pfet_01v8	pfet		standard pFET
+# sky130_fd_pr__pfet_01v8	scpfet		standard pFET in standard cell**
+# sky130_fd_pr__special_pfet_pass ppu		special pFET in SRAM cell
+# sky130_fd_pr__pfet_01v8_lvt	pfetlvt		low Vt pFET
+# sky130_fd_pr__pfet_01v8_mvt	pfetmvt		med Vt pFET
+# sky130_fd_pr__pfet_01v8_hvt	pfethvt		high Vt pFET
+# sky130_fd_pr__nfet_03v3_nvt	nnfet		native nFET
+# sky130_fd_pr__pfet_g5v0d10v5	mvpfet		thickox pFET
+# sky130_fd_pr__nfet_g5v0d10v5	mvnfet		thickox nFET
+# sky130_fd_pr__nfet_01v8_nvt	mvnnfet		thickox native nFET
+# sky130_fd_pr__diode_pw2nd_05v5 ndiode		n+ diff diode
+# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt	low Vt n+ diff diode
+# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode	diode with nndiff
+# sky130_fd_pr__diode_pw2nd_11v0 mvndiode	thickox n+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5 pdiode		p+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt	low Vt p+ diff diode
+# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt	high Vt p+ diff diode
+# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode	thickox p+ diff diode
+# sky130_fd_pr__npn_05v5	pbase		NPN in deep nwell
+# sky130_fd_pr__npn_11v0	pbase		thick oxide gated NPN
+# sky130_fd_pr__pnp_05v5	nbase		PNP
+# sky130_fd_pr__cap_mim_m3_1	mimcap		MiM cap 1st plate
+# sky130_fd_pr__cap_mim_m3_2	mimcap2		MiM cap 2nd plate
+# sky130_fd_pr__res_generic_nd	rdn		n+ diff resistor
+# sky130_fd_pr__res_generic_nd__hv mvrdn	thickox n+ diff resistor
+# sky130_fd_pr__res_generic_pd	rdp		p+ diff resistor
+# sky130_fd_pr__res_generic_pd__nv mvrdp	thickox p+ diff resistor
+# sky130_fd_pr__res_generic_l1	rli		local interconnect resistor
+# sky130_fd_pr__res_generic_po	npres		n+ poly resistor
+# sky130_fd_pr__res_high_po_*	ppres (*)	p+ poly resistor (300 Ohms/sq)
+# sky130_fd_pr__res_xhigh_po_*	xres (*)	p+ poly resistor (2k Ohms/sq)
+# sky130_fd_pr__cap_var_lvt	varactor	low Vt varactor
+# sky130_fd_pr__cap_var_hvt	varactorhvt	high Vt varactor
+# sky130_fd_pr__cap_var		mvvaractor	thickox varactor
+# sky130_fd_pr__res_iso_pw	rpw		pwell resistor (in deep nwell)
+# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd	ESD thickox nFET
+# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd	ESD thickox pFET
+# sky130_fd_pr__photodiode	photo		Photodiode
+#
+# (*) Note that ppres may extract into some generic type called
+# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
+# allowed, and these are created from fixed layouts like the types below.
+#
+# (**) nFET and pFET in standard cells are the same as devices
+# outside of the standard cell except for the DRC rule for
+# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
+#
+#-------------------------------------------------------------
+# The following devices are not extracted but are represented
+# only by script-generated subcells in the PDK.
+#-------------------------------------------------------------
+# sky130_fd_pr__esd_nfet_01v8		ESD nFET
+# sky130_fd_pr__esd_nfet_05v0_nvt	ESD native nFET
+# sky130_fd_pr__special_nfet_pass_flash	flash nFET device
+# sky130_fd_pr__esd_rf_diode_pw2nd_11v0	ESD n+ diode
+# sky130_fd_pr__esd_rf_diode_pd2nw_11v0	ESD p+ diode
+# sky130_fd_pr__cap_vpp_*		Vpp cap
+# sky130_fd_pr__ind_*			inductor
+# sky130_fd_pr__fuse_m4			metal fuse device
+#--------------------------------------------------------------
+
+#-----------------------------------------------------
+# Tile planes
+#-----------------------------------------------------
+
+planes
+  dwell,dw
+  well,w
+  active,a
+  locali,li1,li
+  metal1,m1
+  metal2,m2
+  metal3,m3
+  cap1,c1
+  metal4,m4
+  cap2,c2
+  metal5,m5
+  metali,mi
+  block,b
+  comment,c
+end
+
+#-----------------------------------------------------
+# Tile types
+#-----------------------------------------------------
+
+types
+# Deep nwell
+  dwell dnwell,dnw
+  dwell isosubstrate,isosub
+  dwell photodiode,photo
+
+# Wells
+  well nwell,nw
+  well pwell,pw
+  well rpw,rpwell
+ -well obswell
+  well pbase,npn
+  well nbase,pnp
+
+# Transistors
+  active nmos,ntransistor,nfet
+ -active scnmos,scntransistor,scnfet
+ -active npd,npdfet,sramnfet
+ -active npass,npassfet,srampassfet
+  active pmos,ptransistor,pfet
+ -active scpmos,scptransistor,scpfet
+ -active scpmoshvt,scpfethvt
+ -active ppu,ppufet,srampfet
+  active nnmos,nntransistor,nnfet
+  active mvnmos,mvntransistor,mvnfet
+  active mvpmos,mvptransistor,mvpfet
+  active mvnnmos,mvnntransistor,mvnnfet
+ -active mvnmosesd,mvntransistoresd,mvnfetesd
+ -active mvpmosesd,mvptransistoresd,mvpfetesd
+  active varactor,varact,var
+  active mvvaractor,mvvaract,mvvar
+
+  active pmoslvt,pfetlvt
+  active pmosmvt,pfetmvt
+  active pmoshvt,pfethvt
+  active nmoslvt,nfetlvt
+  active varactorhvt,varacthvt,varhvt
+ -active nsonos,sonos
+ -active sramnvar,corenvar,corenvaractor
+ -active srampvar,corepvar,corepvaractor
+
+# Diffusions
+ -active fomfill
+  active ndiff,ndiffusion,ndif
+  active pdiff,pdiffusion,pdif
+  active mvndiff,mvndiffusion,mvndif
+  active mvpdiff,mvpdiffusion,mvpdif
+  active ndiffc,ndcontact,ndc
+  active pdiffc,pdcontact,pdc
+  active mvndiffc,mvndcontact,mvndc
+  active mvpdiffc,mvpdcontact,mvpdc
+  active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
+  active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
+  active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
+  active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
+  active psubdiffcont,psubstratepcontact,psc,ptapc
+  active nsubdiffcont,nsubstratencontact,nsc,ntapc
+  active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
+  active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
+ -active obsactive
+ -active mvobsactive
+
+# Poly
+  active poly,p,polysilicon
+  active polycont,pc,pcontact,polycut,polyc
+  active xpolycontact,xpolyc,xpc
+ -active polyfill
+
+# Resistors
+  active npolyres,npres,mrp1
+  active ppolyres,ppres,xhrpoly
+  active xpolyres,xpres,xres,uhrpoly
+  active ndiffres,rnd,rdn,rndiff
+  active pdiffres,rpd,rdp,rpdiff
+  active mvndiffres,mvrnd,mvrdn,mvrndiff
+  active mvpdiffres,mvrpd,mvrdp,mvrpdiff
+  active rmp
+
+# Diodes
+  active pdiode,pdi
+  active ndiode,ndi
+  active nndiode,nndi
+  active pdiodec,pdic
+  active ndiodec,ndic
+  active nndiodec,nndic
+  active mvpdiode,mvpdi
+  active mvndiode,mvndi
+  active mvpdiodec,mvpdic
+  active mvndiodec,mvndic
+  active pdiodelvt,pdilvt
+  active pdiodehvt,pdihvt
+  active ndiodelvt,ndilvt
+  active pdiodelvtc,pdilvtc
+  active pdiodehvtc,pdihvtc
+  active ndiodelvtc,ndilvtc
+
+# Local Interconnect 
+  locali locali,li1,li
+ -locali corelocali,coreli1,coreli
+  locali rlocali,rli1,rli
+  locali viali,vial,mcon,m1c,v0
+ -locali obsli1,obsli
+ -locali obsli1c,obsmcon
+ -locali lifill
+
+# Metal 1
+  metal1 metal1,m1,met1
+  metal1 rmetal1,rm1,rmet1
+  metal1 via1,m2contact,m2cut,m2c,via,v,v1
+ -metal1 obsm1
+  metal1 padl
+ -metal1 m1fill
+
+
+# Metal 2
+  metal2 metal2,m2,met2
+  metal2 rmetal2,rm2,rmet2
+  metal2 via2,m3contact,m3cut,m3c,v2
+ -metal2 obsm2
+ -metal2 m2fill
+
+# Metal 3
+  metal3 metal3,m3,met3
+  metal3 rmetal3,rm3,rmet3
+ -metal3 obsm3
+  metal3 via3,v3
+ -metal3 m3fill
+
+  cap1 mimcap,mim,capm
+  cap1 mimcapcontact,mimcapc,mimcc,capmc
+
+# Metal 4
+  metal4 metal4,m4,met4
+  metal4 rmetal4,rm4,rmet4
+ -metal4 obsm4
+  metal4 via4,v4
+ -metal4 m4fill
+
+  cap2 mimcap2,mim2,capm2
+  cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
+
+# Metal 5
+  metal5 metal5,m5,met5
+  metal5 rm5,rmetal5,rmet5
+ -metal5 obsm5
+ -metal5 m5fill
+
+  metal5 mrdlcontact,mrdlc,pi1
+  metali metalrdl,mrdl,metrdl,rdl
+ -metali obsmrdl
+  metali pi2
+  block  ubm
+
+# Miscellaneous
+ -block  glass
+ -block  fillblock,fillblock4
+  comment comment
+ -comment obscomment
+# fixed resistor width identifiers
+ -comment res0p35
+ -comment res0p69
+ -comment res1p41
+ -comment res2p85
+ -comment res5p73
+# fixed bipolar area identifiers
+ -comment pnp0p68
+ -comment pnp3p40
+ -comment npn1p00
+ -comment npn2p00
+ -comment npn11p0
+
+end
+
+#-----------------------------------------------------
+# Magic contact types
+#-----------------------------------------------------
+
+contact
+  pc       poly       locali
+  ndc      ndiff      locali
+  pdc      pdiff      locali
+  nsc      nsd        locali
+  psc      psd        locali
+  ndic     ndiode     locali
+  ndilvtc  ndiodelvt  locali
+  nndic    nndiode    locali
+  pdic     pdiode     locali
+  pdilvtc  pdiodelvt  locali
+  pdihvtc  pdiodehvt  locali
+  xpc      xpc        locali
+
+  mvndc   mvndiff   locali
+  mvpdc   mvpdiff   locali
+  mvnsc   mvnsd     locali
+  mvpsc   mvpsd     locali
+  mvndic  mvndiode  locali
+  mvpdic  mvpdiode  locali
+
+  mcon locali metal1
+  obsmcon obsli metal1
+
+  via1   metal1 metal2
+  via2   metal2 metal3
+  via3   metal3 metal4
+  via4   metal4 metal5
+  stackable
+
+  # MiM cap contacts are not stackable!
+  mimcc  mimcap metal4
+  mim2cc mimcap2 metal5
+
+  padl m1 m2 m3 m4 m5 glass
+
+  mrdlc metal5 mrdl
+  pi2   mrdl ubm
+end
+
+#-----------------------------------------------------
+# Layer aliases
+#-----------------------------------------------------
+
+aliases
+
+  allwellplane     nwell
+  allnwell	   nwell,obswell,pnp
+
+  allnfets	   nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
+  allpfets	   pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
+  allfets	   allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
+  allfetsstd	   nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
+  allfetsspecial   scnfet,scpfet,scpfethvt
+  allfetscore	   npass,npd,nsonos,ppu,corenvar,corepvar
+  allfetsnolvt	   nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
+
+  allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
+  allnactive	   allnactivenonfet,allnfets
+  allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
+  allnactivetap	   *nsd,*mvnsd,var,varhvt,mvvar,corenvar
+
+  allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
+  allpactive	   allpactivenonfet,allpfets
+  allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
+  allpactivetap    *psd,*mvpsd,corepvar
+
+  allactivenonfet  allnactivenonfet,allpactivenonfet
+  allactive	   allactivenonfet,allfets
+
+  allactiveres	   ndiffres,pdiffres,mvndiffres,mvpdiffres
+
+  allndifflv       *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
+  allpdifflv       *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
+  alldifflv        allndifflv,allpdifflv
+  allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
+  allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
+  alldifflvnonfet  allndifflvnonfet,allpdifflvnonfet
+
+  allndiffmv       *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
+  allpdiffmv       *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
+  alldiffmv        allndiffmv,allpdiffmv
+  allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
+  allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
+  alldiffmvnontap  allndiffmvnontap,allpdiffmvnontap
+  allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
+  allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
+  alldiffmvnonfet  allndiffmvnonfet,allpdiffmvnonfet
+
+  alldiffnonfet	   alldifflvnonfet,alldiffmvnonfet
+  alldiff	   alldifflv,alldiffmv,fomfill
+
+  allpolyres	   mrp1,xhrpoly,uhrpoly,rmp
+  allpolynonfet	   *poly,allpolyres,xpc
+  allpolynonres	   *poly,allfets,xpc
+
+  allpoly	   allpolynonfet,allfets
+  allpolynoncap	   *poly,xpc,allfets,allpolyres
+
+  allndiffcontlv   ndc,nsc,ndic,nndic,ndilvtc
+  allpdiffcontlv   pdc,psc,pdic,pdilvtc,pdihvtc
+  allndiffcontmv   mvndc,mvnsc,mvndic
+  allpdiffcontmv   mvpdc,mvpsc,mvpdic
+  allndiffcont	   allndiffcontlv,allndiffcontmv
+  allpdiffcont	   allpdiffcontlv,allpdiffcontmv
+  alldiffcontlv	   allndiffcontlv,allpdiffcontlv
+  alldiffcontmv	   allndiffcontmv,allpdiffcontmv
+  alldiffcont	   alldiffcontlv,alldiffcontmv
+
+  allcont	alldiffcont,pc
+
+  allres	allpolyres,allactiveres
+
+  allli		*locali,coreli,rli
+  allm1		*m1,rm1
+  allm2		*m2,rm2
+  allm3		*m3,rm3
+  allm4	   	*m4,rm4
+  allm5	   	*m5,rm5
+
+  allpad	padl
+
+  psub		pwell
+
+  obstypes	obswell,mvobsactive,obsactive,obsli,obsmcon,obsm1,obsm2,obsm3,obsm4,obsm5,obsmrdl,obscomment
+  idtypes	res0p35,res0p69,res1p41,res2p85,res5p73,pnp0p68,pnp3p40,npn1p00,npn2p00,npn11p0
+  blocktypes	fillblock,fillblock4
+  
+end
+
+#-----------------------------------------------------
+# Layer drawing styles
+#-----------------------------------------------------
+
+styles
+ styletype mos
+  dnwell    cwell
+  isosub    subcircuit
+  nwell     nwell
+  pwell	    pwell
+  rpwell    pwell 	ptransistor_stripes
+  photo	    nwell	nwell_field_implant
+  ndiff     ndiffusion
+  fomfill   ndiffusion
+  pdiff     pdiffusion
+  nsd       ndiff_in_nwell
+  psd       pdiff_in_pwell
+  nfet      ntransistor    ntransistor_stripes
+  scnfet    ntransistor    ntransistor_stripes
+  npass	    ntransistor	   ntransistor_stripes
+  npd	    ntransistor	   ntransistor_stripes
+  pfet      ptransistor    ptransistor_stripes
+  scpfet    ptransistor    ptransistor_stripes
+  scpfethvt ptransistor    ptransistor_stripes implant2
+  ppu	    ptransistor	   ptransistor_stripes
+  var       polysilicon    ndiff_in_nwell
+  ndc       ndiffusion     metal1  contact_X'es
+  pdc       pdiffusion     metal1  contact_X'es
+  nsc       ndiff_in_nwell metal1  contact_X'es
+  psc       pdiff_in_pwell metal1  contact_X'es
+  corenvar  polysilicon    ndiff_in_nwell
+  corepvar  polysilicon    pdiff_in_pwell
+
+  pnp	    nwell ntransistor_stripes
+  npn	    pwell ptransistor_stripes
+
+  pfetlvt   ptransistor	ptransistor_stripes implant1
+  pfetmvt   ptransistor	ptransistor_stripes implant3
+  pfethvt   ptransistor ptransistor_stripes implant2
+  nfetlvt   ntransistor ntransistor_stripes implant1
+  nsonos    ntransistor implant3
+  varhvt    polysilicon ndiff_in_nwell implant2
+  nnfet	    ntransistor ndiff_in_nwell
+
+  mvndiff   ndiffusion     hvndiff_mask
+  mvpdiff   pdiffusion     hvpdiff_mask
+  mvnsd     ndiff_in_nwell hvndiff_mask
+  mvpsd     pdiff_in_pwell hvpdiff_mask
+  mvnfet    ntransistor    ntransistor_stripes hvndiff_mask
+  mvnfetesd ntransistor    ntransistor_stripes hvndiff_mask
+  mvnnfet   ntransistor    ndiff_in_nwell hvndiff_mask
+  mvpfet    ptransistor    ptransistor_stripes
+  mvpfetesd ptransistor    ptransistor_stripes
+  mvvar     polysilicon    ndiff_in_nwell hvndiff_mask
+  mvndc     ndiffusion     metal1  contact_X'es hvndiff_mask
+  mvpdc     pdiffusion     metal1  contact_X'es hvpdiff_mask
+  mvnsc     ndiff_in_nwell metal1  contact_X'es hvndiff_mask
+  mvpsc     pdiff_in_pwell metal1  contact_X'es hvpdiff_mask
+
+  poly      polysilicon 
+  polyfill  polysilicon
+  pc        polysilicon    metal1  contact_X'es
+  npolyres  polysilicon    silicide_block nselect2
+  ppolyres  polysilicon    silicide_block pselect2
+  xpc	    polysilicon	   pselect2  metal1  contact_X'es
+  rmp	    polysilicon	   poly_resist_stripes
+
+  res0p35   implant1
+  res0p69   implant1
+  res1p41   implant1
+  res2p85   implant1
+  res5p73   implant1
+  pnp0p68   implant1
+  pnp3p40   implant1
+  npn1p00   implant1
+  npn2p00   implant1
+  npn11p0   implant1
+
+  pdiode    pdiffusion     pselect2
+  ndiode    ndiffusion     nselect2
+  pdiodec   pdiffusion     pselect2 metal1 contact_X'es
+  ndiodec   ndiffusion     nselect2 metal1 contact_X'es
+
+  nndiode   ndiffusion  nselect2 implant3
+  ndiodelvt ndiffusion	nselect2 implant1
+  pdiodelvt pdiffusion  pselect2 implant1
+  pdiodehvt pdiffusion  pselect2 implant2
+  pdilvtc   pdiffusion  pselect2 implant1 metal1 contact_X'es
+  pdihvtc   pdiffusion  pselect2 implant2 metal1 contact_X'es
+  ndilvtc   ndiffusion  nselect2 implant1 metal1 contact_X'es
+
+  mvpdiode    pdiffusion     pselect2 hvpdiff_mask
+  mvndiode    ndiffusion     nselect2 hvndiff_mask
+  mvpdiodec   pdiffusion     pselect2 metal1 contact_X'es hvpdiff_mask
+  mvndiodec   ndiffusion     nselect2 metal1 contact_X'es hvndiff_mask
+  nndiodec    ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
+
+  locali    metal1
+  lifill    metal1
+  coreli    metal1
+  rli       metal1         poly_resist_stripes
+  mcon	    metal1	   metal2 via1arrow
+  obsli     metal1
+  obsmcon   metal1	   metal2 via1arrow
+
+  metal1    metal2
+  m1fill    metal2
+  rm1       metal2         poly_resist_stripes
+  obsm1     metal2
+  m2c       metal2         metal3  via2arrow
+
+
+  metal2    metal3
+  m2fill    metal3
+  rm2       metal3         poly_resist_stripes
+  obsm2     metal3
+  m3c       metal3         metal4  via3alt
+  metal3    metal4
+  m3fill    metal4
+  rm3       metal4         poly_resist_stripes
+  obsm3     metal4
+  mimcap    metal3         mems
+  mimcc     metal3         contact_X'es mems
+  mimcap2   metal4         mems
+  mim2cc    metal4         contact_X'es mems
+  via3      metal4         metal5  via4
+  metal4    metal5
+  m4fill    metal5
+  rm4       metal5         poly_resist_stripes
+  obsm4     metal5
+  via4      metal5         metal6  via5
+  metal5    metal6
+  m5fill    metal6
+  rm5       metal6         poly_resist_stripes
+  obsm5     metal6
+  mrdlc	    metal6  metal7  via6
+  metalrdl  metal7
+  obsmrdl   metal7
+  ubm	    metal8
+  pi2	    metal7  metal8  via7
+
+  glass	    overglass
+  mrp1      poly_resist    poly_resist_stripes
+  xhrpoly   poly_resist    silicide_block
+  uhrpoly   poly_resist
+  ndiffres  ndiffusion	   ndop_stripes
+  pdiffres  pdiffusion	   pdop_stripes
+  mvndiffres  ndiffusion hvndiff_mask   ndop_stripes
+  mvpdiffres  pdiffusion hvpdiff_mask   pdop_stripes
+  comment   comment
+  error_p   error_waffle
+  error_s   error_waffle
+  error_ps  error_waffle
+  fillblock cwell
+  fillblock4 cwell
+
+  obswell   cwell
+  obsactive implant4
+
+  padl      metal6 via6 overglass
+
+  magnet    substrate_field_implant
+  rotate    via3alt
+  fence     via5
+end
+
+#-----------------------------------------------------
+# Special paint/erase rules
+#-----------------------------------------------------
+
+compose
+  compose  nfet  poly  ndiff
+  compose  pfet  poly  pdiff
+  compose  var   poly  nsd
+
+  decompose npass   poly ndiff
+  decompose npd     poly ndiff
+  decompose scnfet  poly ndiff
+  decompose nfetlvt poly ndiff
+  decompose nsonos  poly ndiff
+
+  decompose ppu       poly pdiff
+  decompose scpfet    poly pdiff
+  decompose scpfethvt poly pdiff
+  decompose pfethvt   poly pdiff
+  decompose pfetlvt   poly pdiff
+  decompose pfetmvt   poly pdiff
+  decompose corenvar  poly nsd
+  decompose corepvar  poly psd
+  decompose varhvt    poly nsd
+
+  compose  mvnfet  poly  mvndiff
+  compose  mvpfet  poly  mvpdiff
+  compose  mvvar   poly  mvnsd
+
+  decompose nnfet     poly mvndiff
+  decompose mvnfetesd poly mvndiff
+  decompose mvnnfet   poly mvndiff
+  decompose mvpfetesd poly mvpdiff
+
+  paint	 obsmcon locali	 via1
+  paint	 obsmcon obsm1	 obsli,obsm1
+  
+  paint  ndc     nwell  pdc
+  paint  nfet    nwell  pfet
+  paint  scnfet  nwell  scpfet
+  paint  ndiff   nwell  pdiff
+  paint  psd     nwell  nsd
+  paint  psc     nwell  nsc
+  paint  npd     nwell  ppu
+
+  paint  pdc     pwell  ndc
+  paint  pfet    pwell  nfet
+  paint  scpfet  pwell  scnfet
+  paint  pdiff   pwell  ndiff
+  paint  nsd     pwell  psd
+  paint  nsc     pwell  psc
+  paint  ppu     pwell  npd
+
+  paint  pdc	 coreli pdc
+  paint  ndc	 coreli ndc
+  paint  pc	 coreli pc
+  paint  nsc 	 coreli nsc
+  paint  psc 	 coreli psc
+  paint  viali 	 coreli viali
+  paint  mvpdc	 coreli mvpdc
+  paint  mvndc	 coreli mvndc
+  paint  mvnsc 	 coreli mvnsc
+  paint  mvpsc 	 coreli mvpsc
+
+  paint  coreli  pdc    pdc
+  paint  coreli  ndc    ndc
+  paint  coreli  pc     pc
+  paint  coreli  nsc    nsc
+  paint  coreli  psc    psc
+  paint  coreli  viali  viali
+  paint  coreli  mvpdc  mvpdc
+  paint  coreli  mvndc  mvndc
+  paint  coreli  mvnsc  mvnsc
+  paint  coreli  mvpsc  mvpsc
+
+
+  paint  m4      obsm4  m4
+  paint  m5      obsm5  m5
+end
+
+#-----------------------------------------------------
+# Electrical connectivity
+#-----------------------------------------------------
+
+connect
+  *nwell,*nsd,*mvnsd,dnwell,pnp,photo *nwell,*nsd,*mvnsd,dnwell,pnp,photo
+  pwell,*psd,*mvpsd,npn,isosub  pwell,*psd,*mvpsd,npn,isosub
+  *li,coreli,lifill	*li,coreli,lifill
+  *m1,m1fill,obsmcon	*m1,m1fill,obsmcon
+  *m2,m2fill	*m2,m2fill
+  *m3,m3fill	*m3,m3fill
+  *m4,m4fill	*m4,m4fill
+  *m5,m5fill	*m5,m5fill
+  *mimcap     *mimcap
+  *mimcap2    *mimcap2
+   allnactivenonfet	allnactivenonfet
+   allpactivenonfet	allpactivenonfet
+  *poly,xpc,allfets,polyfill	*poly,xpc,allfets,polyfill
+  # RDL connects to m5 (i.e., padl) through glass cut
+  *mrdl			*mrdl
+  glass			metrdl
+end
+
+#-----------------------------------------------------
+# CIF/GDS output layer definitions
+#-----------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+
+cifoutput
+
+#----------------------------------------------------------------
+style gdsii
+# NOTE: This section is used for actual GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Create a temp layer from the cell bounding box for use in
+# generating ID layers.  Note that "boundary", unlike "bbox",
+# requires the FIXED_BBOX property (abutment box) in the cell.
+#----------------------------------------------------------------
+ templayer CELLBOUND
+	boundary
+
+#----------------------------------------------------------------
+# BOUND
+#----------------------------------------------------------------
+ layer 	BOUND CELLBOUND
+	calma 235 4
+
+#----------------------------------------------------------------
+# DNWELL
+#----------------------------------------------------------------
+
+ layer DNWELL	dnwell,npn,photo
+	calma	64 18
+
+ layer PWRES    rpw
+	and	dnwell
+	calma	64 13
+
+#----------------------------------------------------------------
+# SUBCUT
+#----------------------------------------------------------------
+
+ layer SUBCUT	isosub
+	calma	81 53
+
+#----------------------------------------------------------------
+# NWELL
+#----------------------------------------------------------------
+
+ layer NWELL 	allnwell
+	bloat-all rpw dnwell
+	and-not rpw,pwell
+ 	calma 	64 20
+
+ layer WELLTXT
+ 	labels allnwell noport
+	calma 64 5
+
+ layer WELLPIN
+ 	labels allnwell port
+	calma 64 16
+
+#----------------------------------------------------------------
+# SUB (text/port only)
+#----------------------------------------------------------------
+
+ layer SUBTXT
+ 	labels pwell noport
+	calma 64 59
+
+ layer SUBPIN
+ 	labels pwell port
+	calma 122 16
+
+#----------------------------------------------------------------
+# DIFF
+#----------------------------------------------------------------
+
+ layer DIFF 	allnactivenontap,allpactivenontap,allactiveres
+ 	calma 	65 20
+
+ layer DIFFTXT
+ 	labels allnactivenontap,allpactivenontap noport
+	calma	65 6
+
+ layer DIFFPIN
+ 	labels allnactivenontap,allpactivenontap port
+	calma	65 16
+
+#----------------------------------------------------------------
+# TAP
+#----------------------------------------------------------------
+
+ layer TAP 	allnactivetap,allpactivetap
+ 	labels 	allnactivetap,allpactivetap port
+ 	calma 	65 44
+
+ layer TAPTXT
+ 	labels 	allnactivetap,allpactivetap noport
+	calma	65 5
+
+#----------------------------------------------------------------
+# FOM
+#----------------------------------------------------------------
+
+ layer FOMFILL	fomfill
+	labels	fomfill
+	calma	23 28
+
+#----------------------------------------------------------------
+# PSDM, NSDM (PPLUS, NPLUS implants)
+#----------------------------------------------------------------
+
+ templayer basePSDM pdiffres,mvpdiffres
+	grow	15
+	or	xhrpoly,uhrpoly,xpc
+	grow	110
+	bloat-or allpactivetap * 125 allnactivenontap 0
+	bloat-or allpactivenontap * 125 allnactivetap 0
+
+ templayer baseNSDM ndiffres,mvndiffres
+ 	grow	125
+	bloat-or allnactivetap * 125 allpactivenontap 0
+	bloat-or allnactivenontap * 125 allpactivetap 0
+
+ templayer extendPSDM  basePSDM
+	bridge	380 380
+	and-not baseNSDM
+
+ layer PSDM basePSDM,extendPSDM 
+	grow	185
+	shrink	185
+	close   265000
+	mask-hints PSDM
+	calma	94 20
+
+ templayer extendNSDM  baseNSDM
+	bridge	380 380
+	and-not basePSDM
+
+ layer NSDM baseNSDM,extendNSDM
+	grow	185
+	shrink	185
+ 	close   265000
+	mask-hints NSDM
+ 	calma	93 44
+
+#----------------------------------------------------------------
+# LVID
+#----------------------------------------------------------------
+
+ layer LVID  nnfet
+        grow 100
+	calma 81 60
+
+#----------------------------------------------------------------
+# LVTN
+#----------------------------------------------------------------
+
+ layer LVTN  pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
+        grow 180
+	bridge	380 380
+	grow	185
+	shrink	185
+	close  265000
+	mask-hints LVTN
+	calma 125 44
+
+#----------------------------------------------------------------
+# HVTR
+#----------------------------------------------------------------
+
+ layer HVTR  pfetmvt
+        grow 180
+	bridge	380 380
+	grow	185
+	shrink	185
+	close  265000
+	calma 18 20
+
+#----------------------------------------------------------------
+# HVTP
+#----------------------------------------------------------------
+
+ layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
+        grow 180
+	bridge	380 380
+	grow	185
+	shrink	185
+	close 265000
+	mask-hints HVTP
+	calma 78 44
+
+#----------------------------------------------------------------
+# SONOS
+#----------------------------------------------------------------
+
+ layer SONOS nsonos
+	grow 100
+	grow-min 410
+	bridge 500 410
+	grow 250
+	shrink 250
+	calma 80 20
+
+#----------------------------------------------------------------
+# The coreli layer indicates a cell needing COREID.  Also,
+# devices npd, npass, and ppu indicate a COREID cell.  NOTE:
+# SONOS does not use COREID, counter to SkyWater rules.
+#----------------------------------------------------------------
+
+ layer COREID
+	bloat-all coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
+	mask-hints COREID
+	calma 81 2
+
+#----------------------------------------------------------------
+# STDCELL applies to all cells containing scnfet or scpfet.
+#----------------------------------------------------------------
+
+ layer STDCELL scnfet
+	bloat-all scpfet,scpfethvt,scnfet CELLBOUND
+	mask-hints STDCELL
+	calma 81 4
+
+#----------------------------------------------------------------
+# ESDID is a marker layer for ESD devices in the padframe I/O.
+#----------------------------------------------------------------
+
+ layer ESDID  
+	bloat-all mvnfetesd *mvndiff,*poly
+	bloat-all mvpfetesd *mvpdiff,*poly
+	grow 100
+	mask-hints ESDID
+	calma 81 19
+
+#----------------------------------------------------------------
+# NPNID and PNPID apply to bipolar transistors
+#----------------------------------------------------------------
+
+ layer NPNID
+	bloat-all npn dnwell
+	mask-hints NPNID
+	calma	82 20
+
+ templayer pnparea pnp
+	grow 400
+
+ layer PNPID
+	bloat-all pnparea *psd
+	or pnparea
+	mask-hints PNPID
+	calma	82 44
+
+ layer PHOTO photo
+	calma	81 81
+
+#----------------------------------------------------------------
+# RPM
+#----------------------------------------------------------------
+
+ layer RPM
+	bloat-all xhrpoly xpc
+	grow 200
+	grow-min 1270
+	grow 420
+	shrink 420
+	calma 86 20
+
+#----------------------------------------------------------------
+# URPM (2kOhms/sq. poly implant)
+#----------------------------------------------------------------
+
+ layer URPM
+	bloat-all uhrpoly xpc
+	grow 200
+	grow-min 1270
+	grow 420
+	shrink 420
+	calma 79 20
+
+#----------------------------------------------------------------
+# LDNTM (Tip implant for SONOS FETs)
+#----------------------------------------------------------------
+
+ layer LDNTM
+	bloat-all nsonos *ndiff
+	grow 185
+ 	grow 	345
+ 	shrink 	345
+	calma 11 44
+
+#----------------------------------------------------------------
+# HVNTM (Tip implant for MV ndiff devices)
+#----------------------------------------------------------------
+
+ templayer hvntm_block *mvpsd
+	grow 185
+
+ layer HVNTM
+	bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+	bloat-all mvvaractor *mvnsd
+	and-not hvntm_block
+        grow 185
+ 	grow 	345
+ 	shrink 	345
+	and-not hvntm_block
+	mask-hints HVNTM
+	calma 125 20
+
+#----------------------------------------------------------------
+# POLY
+#----------------------------------------------------------------
+
+ layer POLY 	allpoly
+ 	calma 	66 20
+
+ layer POLYTXT
+	labels  allpoly noport
+	calma	66 5
+
+ layer POLYPIN
+	labels  allpoly port
+	calma	66 16
+
+ layer POLYFILL	polyfill
+	labels 	polyfill
+	calma	28 28
+
+#----------------------------------------------------------------
+# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
+#----------------------------------------------------------------
+
+ templayer thkox_area 	alldiffmv,mvvar
+	grow	185
+	bloat-all alldiffmv nwell
+	grow 345
+	shrink 345
+
+ templayer large_ptap_mv thkox_area
+	shrink	420
+	grow	420
+
+ templayer small_ptap_mv thkox_area
+	and-not large_ptap_mv
+	# (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
+	grow-min 840
+
+ layer HVI 	thkox_area,small_ptap_mv
+	bridge	700 600
+ 	grow 	345
+ 	shrink 	345
+	mask-hints HVI
+ 	calma 	75 20
+
+#----------------------------------------------------------------
+# CONT (LICON)
+#----------------------------------------------------------------
+
+ layer CONT allcont
+ 	squares-grid 0 170 170
+ 	calma	66 44
+
+ # Contact for pres is different than other LICON contacts
+ # See rules LICON 1b, 1c (width/length) and 2b (spacing)
+ templayer xpc_horiz xpc
+	shrink 1007
+	grow 1007
+
+ layer CONT xpc
+	and-not xpc_horiz
+	# Force long edge vertical for contacts narrower than 2um
+	# Minimum space is 350 but 520 satisfies no. of contacts rule
+ 	slots 80 190 520 80 2000 350
+ 	calma	66 44
+
+ layer CONT xpc
+	and xpc_horiz
+	# Force long edge vertical for contacts wider than 2um
+	# Minimum space is 350 but 520 satisfies no. of contacts rule
+ 	slots 80 2000 350 80 190 520
+ 	calma	66 44
+
+#----------------------------------------------------------------
+# NPC (Nitride poly cut)
+# surrounds CONT (LICON) on poly only (i.e., pc)
+#----------------------------------------------------------------
+
+ # Avoids a common case of NPC bridges too close to other LICON shapes.
+ templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
+	grow 90
+
+ layer NPC pc
+ 	squares-grid 0 170 170
+	grow 100
+	bridge 270 270
+	and-not diffcutarea
+	bridge 270 270
+	grow 130
+	shrink 130
+	mask-hints NPC
+	calma  95 20
+
+ # NPC is also generated on xhrpoly and uhrpoly resistors
+
+ layer NPC xpc,xhrpoly,uhrpoly
+        # xpc surrounds precision_resistor by 0.095um
+	grow 95
+	grow 130
+	shrink 130
+	calma  95 20
+
+#----------------------------------------------------------------
+# Device markers
+#----------------------------------------------------------------
+
+ layer DIFFRES rdn,mvrdn,rdp,mvrdp
+	calma 65 13
+
+ layer POLYRES mrp1
+	calma 66 13
+
+ # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
+ layer POLYSHORT rmp
+	calma 66 15
+
+ # POLYRES extends to edge of contact cut
+ layer POLYRES xhrpoly,uhrpoly
+	grow 60
+	and xpc
+	or xhrpoly,uhrpoly
+	calma 66 13
+
+ layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
+        # To be done:  Expand to include anode, cathode, and guard ring
+	calma 81 23
+
+#----------------------------------------------------------------
+# LI
+#----------------------------------------------------------------
+ layer LI allli
+	calma 67 20
+
+ layer LITXT
+ 	labels *locali,coreli noport
+	calma 67 5
+
+ layer LIPIN
+ 	labels *locali,coreli port
+	calma 67 16
+
+ layer LIRES rli
+	labels rli
+	calma 67 13
+
+ layer LIFILL	lifill
+	labels 	lifill
+	calma	56 28
+
+#----------------------------------------------------------------
+# MCON
+#----------------------------------------------------------------
+ layer MCON mcon
+ 	squares-grid 0 170 190
+ 	calma 	67 44
+
+#----------------------------------------------------------------
+# MET1
+#----------------------------------------------------------------
+ layer MET1 	allm1
+ 	calma 	68 20
+
+ layer MET1TXT
+	labels	allm1 noport
+	calma 	68 5
+
+ layer MET1PIN
+	labels	allm1 port
+	calma 	68 16
+
+ layer MET1RES rm1
+	labels rm1
+	calma 68 13
+
+ layer MET1FILL m1fill
+	labels m1fill
+	calma 36 28
+
+#----------------------------------------------------------------
+# VIA1
+#----------------------------------------------------------------
+ layer VIA1 	via1
+ 	squares-grid 55 150 170
+ 	calma 	68 44
+
+
+#----------------------------------------------------------------
+# MET2
+#----------------------------------------------------------------
+ layer MET2 	allm2
+ 	calma 	69 20
+
+ layer MET2TXT
+	labels	allm2 noport
+	calma	69 5
+
+ layer MET2PIN
+	labels	allm2 port
+	calma	69 16
+
+ layer MET2RES rm2
+	labels rm2
+	calma 69 13
+
+ layer MET2FILL m2fill
+	labels m2fill
+	calma 41 28
+
+#----------------------------------------------------------------
+# VIA2
+#----------------------------------------------------------------
+ layer VIA2 	via2
+ 	squares-grid 40 200 200
+ 	calma 	69 44
+
+#----------------------------------------------------------------
+# MET3
+#----------------------------------------------------------------
+ layer MET3 	allm3
+ 	calma 	70 20
+
+ layer MET3TXT
+ 	labels 	allm3 noport
+	calma	70 5
+
+ layer MET3PIN
+	labels	allm3 port
+	calma	70 16 
+
+ layer MET3RES rm3
+	labels rm3
+	calma 70 13
+
+ layer MET3FILL m3fill
+	labels m3fill
+	calma 34 28
+
+#----------------------------------------------------------------
+# VIA3
+#----------------------------------------------------------------
+ layer VIA3	via3
+	or mimcc
+ 	squares-grid 60 200 200
+ 	calma 	70 44
+
+#----------------------------------------------------------------
+# MET4
+#----------------------------------------------------------------
+ layer MET4 	allm4
+ 	calma 	71 20
+
+ layer MET4TXT
+	labels	allm4 noport
+	calma	71 5
+
+ layer MET4PIN
+	labels	allm4 port
+	calma	71 16
+
+ layer MET4RES rm4
+	labels rm4
+	calma 71 13
+
+ layer MET4FILL m4fill
+	labels m4fill
+	calma 51 28
+
+#----------------------------------------------------------------
+# VIA4
+#----------------------------------------------------------------
+ layer VIA4	via4
+	or mim2cc
+ 	squares-grid 190 800 800
+ 	calma 	71 44
+
+#----------------------------------------------------------------
+# MET5
+#----------------------------------------------------------------
+ layer MET5 	allm5,m5fill
+ 	calma 	72 20
+
+ layer MET5TXT
+	labels	allm5 noport
+	calma	72 5
+
+ layer MET5PIN
+	labels	allm5 port
+	calma	72 16
+
+ layer MET5RES rm5
+	labels rm5
+	calma 72 13
+
+ layer MET5FILL m5fill
+	labels m5fill
+	calma 59 28
+
+
+#----------------------------------------------------------------
+# RDL
+#----------------------------------------------------------------
+  layer RDL	*metrdl
+	calma   74 20
+
+  layer RDLTXT
+	labels	*metrdl noport
+	calma	74 5
+
+  layer RDLPIN
+	labels  *metrdl port
+	calma	74 16
+
+  layer PI1	*metrdl
+	and	padl,glass
+	# Test only---needs GDS layer number
+
+  layer	UBM	*metrdl
+	shrink	50000
+	grow	40000
+	# Test only---needs GDS layer number
+	
+  layer	PI2	*metrdl
+	shrink	50000
+	grow	25000
+	# Test only---needs GDS layer number
+
+
+#----------------------------------------------------------------
+# GLASS
+#----------------------------------------------------------------
+ layer GLASS 	glass
+ 	calma 	76 20
+
+#----------------------------------------------------------------
+# CAPM
+#----------------------------------------------------------------
+ layer CAPM 	*mimcap
+ 	labels 	mimcap
+ 	calma 	89 44
+
+ layer CAPM2 	*mimcap2
+ 	labels 	mimcap2
+ 	calma 	97 44
+
+#----------------------------------------------------------------
+# Chip top level marker for DRC latchup rules to check 15um
+# distance to taps (otherwise 6um is used)
+#----------------------------------------------------------------
+
+ layer LOWTAPDENSITY
+	bbox top
+	# Clear 200um for pads + 50um for required high tap density
+	# in critical area.
+	shrink 250000
+	calma	81 14
+
+#----------------------------------------------------------------
+# FILLBLOCK
+#----------------------------------------------------------------
+ layer FILLOBSFOM  obsactive
+	calma	22 24
+
+ layer FILLOBSM1 fillblock,fillblock4
+ 	calma 	62 24
+
+ layer FILLOBSM2 fillblock,fillblock4
+ 	calma 	105 52
+
+ layer FILLOBSM3 fillblock,fillblock4
+ 	calma 	107 24
+
+ layer FILLOBSM4 fillblock,fillblock4
+ 	calma 	112 4
+
+ render	DNWELL 	cwell       -0.1    0.1
+ render	NWELL	nwell        0.0    0.2062
+ render DIFF	ndiffusion   0.2062 0.12
+ render TAP	pdiffusion   0.2062 0.12
+ render POLY	polysilicon  0.3262 0.18
+ render CONT	via          0.5062 0.43
+ render LI	metal1       0.9361 0.10
+ render MCON	via          1.0361 0.34
+ render MET1	metal2       1.3761 0.36
+ render VIA1	via          1.7361 0.27
+ render MET2	metal3       2.0061 0.36
+ render VIA2	via          2.3661 0.42
+ render MET3	metal4       2.7861 0.845
+ render VIA3	via          3.6311 0.39
+ render MET4	metal5       4.0211 0.845
+ render VIA4	via          4.8661 0.505
+ render MET5	metal6       5.3711 1.26
+ render CAPM	metal8       2.4661 0.2
+ render CAPM2	metal9       3.7311 0.2
+ render RDL	metal7      11.8834 4.0
+
+#----------------------------------------------------------------
+style drc
+#----------------------------------------------------------------
+# NOTE:  This style is used for DRC only, not for GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+
+ # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
+ templayer dnwell_shrink dnwell
+ shrink 1030
+
+ templayer nwell_missing dnwell
+ grow 400
+ and-not dnwell_shrink
+ and-not nwell
+
+ templayer pwell_in_dnwell dnwell
+ and-not nwell
+
+ # SONOS nFET devices must be in deep nwell
+ templayer dnwell_missing nsonos
+ and-not dnwell
+
+ # SONOS nFET devices must be in cell with abutment box
+ templayer abutment_box
+	boundary
+
+ templayer bbox_missing nsonos
+	and-not abutment_box
+
+ # Make sure nwell covers varactor poly
+ templayer var_poly_no_nwell
+	bloat-all varactor,mvvaractor *poly
+	grow 150
+	and-not nwell
+
+ # Define MiM cap bottom plate for spacing rule
+ templayer mim_bottom
+ bloat-all *mimcap *metal3
+
+ # Define MiM2 cap bottom plate for spacing rule
+ templayer mim2_bottom
+ bloat-all *mimcap2 *metal4
+
+ # Define areas where mim2cc is inside the boundary of mimcc
+ # by more than the contact surround
+ templayer mim2_contact_overlap
+ bloat-all *mimcap2 mimcc
+ shrink 60
+ and-not *mimcap2
+
+ # Note that metal fill is performed by the foundry and so is not
+ # an option for a cifoutput style.
+
+ # Check latchup rule (15um minimum from tap LICON center to any
+ # non-tap diffusion.  Note that to count as a tap, the diffusion
+ # must be contacted to LI
+
+ templayer ptap_reach psc,mvpsc
+ and-not dnwell
+ # grow total is 15um.  grow in 0.84um increments to ensure that
+ # no nwell ring is crossed
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 635
+ and-not nwell,dnwell
+
+ templayer ptap_missing *ndiff,*mvndiff
+ and-not dnwell
+ and-not ptap_reach
+
+ templayer ntap_reach nsc,mvnsc
+ # grow total is 15um.  grow in 1.27um increments to ensure that
+ # no nwell ring is crossed.  There is no difference between
+ # ntaps in and out of deep nwell.
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 1270
+ and nwell,pnp
+ grow 945
+ and nwell,pnp
+ 
+ templayer ntap_missing *pdiff,*mvpdiff
+ and-not pwell_in_dnwell
+ and-not ntap_reach
+
+ templayer dptap_reach psc,mvpsc
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 635
+ and-not nwell
+ and dnwell
+
+ templayer dptap_missing *ndiff,*mvndiff
+ and dnwell
+ and-not dptap_reach
+
+ templayer pdiff_crosses_dnwell dnwell
+ grow 20
+ and-not dnwell
+ and allpdifflv,allpdiffmv
+
+ # MV nwell must be 2um from any other nwell
+ templayer mvnwell
+ bloat-all alldiffmv nwell
+ grow-min 840
+ bridge	700 600
+
+ # Simple spacing checks to lvnwell must use CIF-DRC rule
+ # Note that HVI may *abut* lvnwell;  this can only be handled
+ # with mask-hints layers.
+
+ templayer drawn_hvi
+	mask-hints HVI
+
+ templayer allmvdiffnowell *mvndiff,*mvpsd
+ and-not drawn_hvi
+
+ templayer nwell_or_hvi nwell,drawn_hvi
+
+ templayer lvnwell nwell
+ and-not mvnwell
+
+ # Check for low-voltage diffusion in high-voltage well
+ templayer lvdiff_in_mvnwell *pdiff,*pdiode,pdiffres,*nsd
+ or pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
+ and mvnwell
+
+ templayer nwell_with_tap
+ bloat-all nsc,mvnsc nwell,pnp
+
+ templayer nwell_missing_tap nwell,pnp
+ and-not nwell_with_tap
+
+ templayer tap_with_licon
+ bloat-all allpactivetap psd,mvpsd
+ bloat-all allnactivetap nsd,mvnsd
+
+ templayer tap_missing_licon allnactivetap,allpactivetap
+ and-not tap_with_licon
+
+ # Make sure varactor nwell contains no P diffusion
+ templayer pdiff_in_varactor_well
+ bloat-all varactor,mvvaractor nwell
+ and allpactive
+
+ # HVNTM spacing requires recreating HVNTM
+ templayer hvntm_block *mvpsd
+ grow 185
+
+ templayer hvntm_generate
+ bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+ bloat-all mvvaractor *mvnsd
+ and-not hvntm_block
+ grow 185
+ grow    345
+ shrink  345
+ and-not hvntm_block
+
+ # RPM spacing checks require recreating RPM
+ templayer rpm_generate
+ bloat-all xhrpoly,uhrpoly xpc
+ grow 200
+ grow-min 1270
+ grow 420
+ shrink 420
+
+ # Check distance RPM to NSDM
+ templayer rpm_nsd_check rpm_generate
+ grow 325
+ and allndifflv,allndiffmv
+
+ # Check distance RPM to (unrelated) POLY
+ templayer rpm_poly_check rpm_generate
+ grow 200
+ and-not xhrpoly,uhrpoly,xpc
+ and allpoly
+
+ # Check distance RPM to HVNTM
+ templayer rpm_hvntm_check rpm_generate
+ grow 385
+ and allndiffmvnontap
+
+ templayer m1_small_hole allm1,obsm1,obsmcon
+ close   140000
+
+ templayer m1_hole_empty m1_small_hole
+ and-not allm1,obsm1,obsmcon
+
+ templayer m2_small_hole allm2,obsm2
+ close   140000
+
+ templayer m2_hole_empty m2_small_hole
+ and-not allm2,obsm2
+
+ templayer m1_huge allm1
+ shrink 1500
+ grow 1500
+
+ templayer m1_large_halo m1_huge
+ grow 280
+ and-not m1_huge
+ and allm1
+
+ templayer m2_huge allm2
+ shrink 1500
+ grow 1500
+
+ templayer m2_large_halo m2_huge
+ grow 280
+ and-not m2_huge
+ and allm2
+
+ templayer m3_huge allm3
+ shrink 1500
+ grow 1500
+
+ templayer m3_large_halo m3_huge
+ grow 400
+ and-not m3_huge
+ and allm3
+
+ templayer m4_huge allm4
+ shrink 1500
+ grow 1500
+
+ templayer m4_large_halo m4_huge
+ grow 400
+ and-not m4_huge
+ and allm4
+
+
+#----------------------------------------------------------------
+style density
+#----------------------------------------------------------------
+# Style used by scripts to check for fill density
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+ templayer fom_all alldiff,fomfill
+
+ templayer poly_all allpoly,polyfill
+
+ templayer li_all allli,lifill
+
+ templayer m1_all allm1,m1fill
+
+ templayer m2_all allm2,m2fill
+
+ templayer m3_all allm3,m3fill
+
+ templayer m4_all allm4,m4fill
+
+ templayer m5_all allm5,m5fill
+
+#----------------------------------------------------------------
+style wafflefill variants (),(tiled)
+#----------------------------------------------------------------
+# Style used by scripts for automatically generating fill layers
+# NOTE: Be sure to generate output on flattened layout.
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Generate and retain a layer representing the bounding box.
+#
+# For variant ():
+# The bounding box is the full extent of geometry on the top level
+# cell.
+#
+# For variant (tiled):
+# Use with a script that breaks layout into flattened tiles and runs
+# fill individually on each.  The tiles should be larger than the
+# step size, and each should draw a layer "comment" the size of the
+# step box.
+#----------------------------------------------------------------
+
+ variants ()
+     templayer	topbox
+	 bbox	top
+
+ variants (tiled)
+     templayer	topbox comment
+	 # Each tile imposes the full keepout distance rule of
+	 # 3um on all sides.
+	 shrink 1500
+
+ variants *
+
+#----------------------------------------------------------------
+# Generate guard-band around nwells to keep FOM from crossing
+# Spacing from LV nwell = Diff/Tap 9 = 0.34um
+# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
+# Enclosure by nwell = Diff/Tap 8 = 0.18um
+#----------------------------------------------------------------
+
+ templayer mvnwell
+ 	bloat-all alldiffmv nwell
+
+ templayer lvnwell allnwell
+	and-not mvnwell
+
+ templayer	well_shrink mvnwell
+	shrink 	250
+	or lvnwell
+	shrink	180
+ templayer	well_guardband allnwell
+	grow	340
+	and-not	well_shrink
+
+#---------------------------------------------------
+# Diffusion and poly keep-out areas
+#---------------------------------------------------
+ templayer      obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
+	or	rpw,pnp,npn
+        grow    500
+	or	well_guardband
+
+ templayer      obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
+	or	rpw,pnp,npn
+	grow	1000
+
+#---------------------------------------------------
+# FOM and POLY fill
+#---------------------------------------------------
+ templayer	fomfill_pass1 topbox
+        # slots   0 4080 1320 0 4080 1320 1360 0
+        slots   0 4080 1600 0 4080 1600 1360 0
+        and-not obstruct_fom
+	and	topbox
+        shrink  2035
+        grow    2035
+
+#---------------------------------------------------
+
+ templayer      obstruct_poly_pass1 fomfill_pass1
+        grow    300
+	or	obstruct_poly
+ templayer	polyfill_pass1 topbox
+        slots   0 720 360 0 720 360 240 0
+        and-not obstruct_poly_pass1
+	and	topbox
+        shrink  355
+        grow    355
+
+#---------------------------------------------------
+
+ templayer      obstruct_fom_pass2 fomfill_pass1
+        grow    1290
+	or	polyfill_pass1
+        grow    300
+	or	obstruct_fom
+ templayer	fomfill_pass2 topbox
+        slots   0 2500 1320 0 2500 1320 1360 0
+        and-not obstruct_fom_pass2
+	and	topbox
+        shrink  1245
+        grow    1245
+
+#---------------------------------------------------
+
+ templayer      obstruct_poly_coarse polyfill_pass1
+	grow	60
+	or	fomfill_pass1,fomfill_pass2
+	grow	300
+	or	obstruct_poly
+ templayer	polyfill_coarse topbox
+        slots   0 720 360 0 720 360 240 120
+        and-not obstruct_poly_coarse
+	and	topbox
+        shrink  355
+        grow    355
+
+#---------------------------------------------------
+ templayer      obstruct_poly_medium polyfill_pass1,polyfill_coarse
+	grow	60
+	or	fomfill_pass1,fomfill_pass2
+        grow    300
+	or	obstruct_poly
+ templayer	polyfill_medium topbox
+        slots   0 540 360 0 540 360 240 100
+        and-not obstruct_poly_medium
+	and	topbox
+        shrink  265
+        grow    265
+
+#---------------------------------------------------
+ templayer      obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
+	grow	60
+	or	fomfill_pass1,fomfill_pass2
+	grow	300
+	or	obstruct_poly
+ templayer	polyfill_fine topbox
+        slots   0 480 360 0 480 360 240 200
+        and-not obstruct_poly_fine
+	and	topbox
+        shrink  235
+        grow    235
+
+#---------------------------------------------------
+
+ templayer      obstruct_fom_coarse fomfill_pass1,fomfill_pass2
+        grow    1290
+	or	polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
+	grow	300
+	or	obstruct_fom
+ templayer	fomfill_coarse topbox
+        slots   0 1500 1320 0 1500 1320 1360 0
+        and-not obstruct_fom_coarse
+	and	topbox
+        shrink  745
+        grow    745
+
+#---------------------------------------------------
+
+ templayer      obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
+        grow    1290
+	or	polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
+	grow	300
+	or	obstruct_fom
+ templayer	fomfill_fine topbox
+        slots   0 500 400 0 500 400 160 0
+        and-not obstruct_fom_fine
+	and	topbox
+        shrink  245
+        grow    245
+
+#---------------------------------------------------
+ layer  FOMFILL fomfill_pass1 
+	or	fomfill_pass2
+	or	fomfill_coarse
+	or	fomfill_fine
+ 	calma 	23 28
+
+ layer	POLYFILL polyfill_pass1 
+	or	 polyfill_coarse
+	or	 polyfill_medium
+	or	 polyfill_fine
+ 	calma 	28 28
+
+#---------------------------------------------------------
+# LI fill
+# Note requirement that LI fill may not overlap (non-fill)
+# diff or poly.
+#---------------------------------------------------------
+
+ templayer      obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
+        grow    2800
+	or	alldiff,allpoly
+	grow	200
+ templayer	lifill_coarse topbox
+        # slots   0 3000 650 0 3000 650 700 0
+        slots   0 3000 900 0 3000 900 700 0
+        and-not obstruct_li_coarse
+	and	topbox
+        shrink  1495
+        grow    1495
+
+ templayer      obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
+        grow    2500
+	or	lifill_coarse
+	grow	300
+	or	alldiff,allpoly
+        grow    200
+ templayer	lifill_medium topbox
+        slots   0 1500 500 0 1500 500 700 0
+        and-not obstruct_li_medium
+	and	topbox
+        shrink  745
+        grow    745
+
+ templayer      obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
+	or	lifill_coarse,lifill_medium
+	grow	300
+	or	alldiff,allpoly
+        grow    200
+ templayer	lifill_fine topbox
+        slots   0 580 500 0 580 500 700 0
+        and-not obstruct_li_fine
+	and	topbox
+        shrink  285
+        grow    285
+
+ layer	LIFILL  lifill_coarse
+	or	lifill_medium
+	or	lifill_fine
+ 	calma 	56 28
+
+#---------------------------------------------------
+# MET1 fill
+#---------------------------------------------------
+
+ templayer      obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+        grow    3000
+ templayer	met1fill_coarse topbox
+        # slots   0 2000 200 0 2000 200 700 0
+        slots   0 2000 800 0 2000 800 700 350
+        and-not obstruct_m1_coarse
+	and	topbox
+        shrink  995
+        grow    995
+
+ templayer      obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+        grow    2800
+	or	met1fill_coarse
+        grow    200
+ templayer	met1fill_medium topbox
+        slots   0 1000 200 0 1000 200 700 0
+        and-not obstruct_m1_medium
+	and	topbox
+        shrink  495
+        grow    495
+
+ templayer      obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+        grow    300
+	or	met1fill_coarse,met1fill_medium
+        grow    200
+ templayer	met1fill_fine topbox
+        slots   0 580 200 0 580 200 700 0
+        and-not obstruct_m1_fine
+	and	topbox
+        shrink  285
+        grow    285
+
+ templayer      obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
+        grow    100
+	or	met1fill_coarse,met1fill_medium,met1fill_fine
+        grow    200
+ templayer	met1fill_veryfine topbox
+        slots   0 300 200 0 300 200 100 50
+        and-not obstruct_m1_veryfine
+	and	topbox
+        shrink  145
+        grow    145
+
+ layer	MET1FILL met1fill_coarse
+	or	met1fill_medium
+	or	met1fill_fine
+	or	met1fill_veryfine
+ 	calma 	36 28
+
+#---------------------------------------------------
+# MET2 fill
+#---------------------------------------------------
+ templayer      obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+        grow    3000
+ templayer	met2fill_coarse topbox
+        # slots   0 2000 200 0 2000 200 700 350
+        slots   0 2000 800 0 2000 800 700 350
+        and-not obstruct_m2
+	and	topbox
+        shrink  995
+        grow    995
+
+ templayer      obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+        grow    2800
+	or	met2fill_coarse
+        grow    200
+ templayer	met2fill_medium topbox
+        slots   0 1000 200 0 1000 200 700 350
+        and-not obstruct_m2_medium
+	and	topbox
+        shrink  495
+        grow    495
+
+ templayer      obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+        grow    300
+	or	met2fill_coarse,met2fill_medium
+        grow    200
+ templayer	met2fill_fine topbox
+        slots   0 580 200 0 580 200 700 350
+        and-not obstruct_m2_fine
+	and	topbox
+        shrink  285
+        grow    285
+
+ templayer      obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
+        grow    100
+	or	met2fill_coarse,met2fill_medium,met2fill_fine
+        grow    200
+ templayer	met2fill_veryfine topbox
+        slots   0 300 200 0 300 200 100 100
+        and-not obstruct_m2_veryfine
+	and	topbox
+        shrink  145
+        grow    145
+
+ layer	MET2FILL met2fill_coarse
+	or met2fill_medium
+	or met2fill_fine
+	or met2fill_veryfine
+ 	calma 	41 28
+
+#---------------------------------------------------
+# MET3 fill
+#---------------------------------------------------
+ templayer      obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+        grow    3000
+ templayer	met3fill_coarse topbox
+        # slots   0 2000 300 0 2000 300 700 700
+        slots   0 2000 800 0 2000 800 700 350
+        and-not obstruct_m3
+	and	topbox
+        shrink  995
+        grow    995
+
+ templayer      obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+        grow    2700
+	or	met3fill_coarse
+        grow    300
+ templayer	met3fill_medium topbox
+        slots   0 1000 300 0 1000 300 700 700
+        and-not obstruct_m3_medium
+	and	topbox
+        shrink  495
+        grow    495
+
+ templayer      obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+        grow    200
+	or	met3fill_coarse,met3fill_medium
+        grow    300
+ templayer	met3fill_fine topbox
+        slots   0 580 300 0 580 300 700 700
+        and-not obstruct_m3_fine
+	and	topbox
+        shrink  285
+        grow    285
+
+ templayer      obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
+	# Note: Adding 0.1 to waffle rule to clear wide spacing rule
+        grow    100
+	or	met3fill_coarse,met3fill_medium,met3fill_fine
+        grow    300
+ templayer	met3fill_veryfine topbox
+        slots   0 400 300 0 400 300 150 200
+        and-not obstruct_m3_veryfine
+	and	topbox
+        shrink  195
+        grow    195
+
+ layer	MET3FILL met3fill_coarse
+	or	met3fill_medium
+	or	met3fill_fine
+	or	met3fill_veryfine
+ 	calma 	34 28
+
+#---------------------------------------------------
+# MET4 fill
+#---------------------------------------------------
+ templayer      obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+        grow    3000
+ templayer	met4fill_coarse topbox
+        # slots   0 2000 300 0 2000 300 700 1050
+        slots   0 2000 800 0 2000 800 700 350
+        and-not obstruct_m4
+	and	topbox
+        shrink  995
+        grow    995
+
+ templayer      obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+        grow    2700
+	or	met4fill_coarse
+        grow    300
+ templayer	met4fill_medium topbox
+        slots   0 1000 300 0 1000 300 700 1050
+        and-not obstruct_m4_medium
+	and	topbox
+        shrink  495
+        grow    495
+
+ templayer      obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+        grow    200
+	or	met4fill_coarse,met4fill_medium
+        grow    300
+ templayer	met4fill_fine topbox
+        slots   0 580 300 0 580 300 700 1050
+        and-not obstruct_m4_fine
+	and	topbox
+        shrink  285
+        grow    285
+
+ templayer      obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
+	# Note: Adding 0.1 to waffle rule to clear wide spacing rule
+        grow    100
+	or	met4fill_coarse,met4fill_medium,met4fill_fine
+        grow    300
+ templayer	met4fill_veryfine topbox
+        slots   0 400 300 0 400 300 150 300
+        and-not obstruct_m4_veryfine
+	and	topbox
+        shrink  195
+        grow    195
+
+ layer	MET4FILL met4fill_coarse
+	or	met4fill_medium
+	or	met4fill_fine
+	or	met4fill_veryfine
+ 	calma 	51 28
+
+#---------------------------------------------------
+# MET5 fill
+#---------------------------------------------------
+ templayer      obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
+        grow    3000
+ templayer	met5fill_coarse topbox
+        slots   0 5000 1600 0 5000 1600 1000 100
+        and-not obstruct_m5
+	and	topbox
+        shrink  2495
+        grow    2495
+
+ templayer      obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
+        grow    1400
+	or	met5fill_coarse
+        grow    1600
+ templayer	met5fill_medium topbox
+        slots   0 3000 1600 0 3000 1600 1000 100
+        and-not obstruct_m5_medium
+	and	topbox
+        shrink  1495
+        grow    1495
+
+ layer	MET5FILL met5fill_coarse
+	or	met5fill_medium
+ 	calma 	59 28
+
+end
+
+#-----------------------------------------------------------------------
+cifinput
+#-----------------------------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+#-----------------------------------------------------------------------
+
+style  sky130 variants (vendor),()
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ ignore NPC
+ ignore SEALID
+ ignore CAPID
+ ignore LDNTM
+ ignore HVNTM
+ ignore POLYMOD
+ ignore LOWTAPDENSITY
+ ignore FILLOBSPOLY
+ ignore MET5BLOCK
+ ignore OUTLINE
+ ignore POLYCUT
+ ignore POLYGATE
+ ignore DIFFCUT
+ ignore HVNWELLID
+ ignore PADDIFFID
+ ignore PADMETALID
+ ignore PADCENTERID
+
+ layer pnp NWELL,WELLTXT,WELLPIN
+ and PNPID
+ labels NWELL
+ variants (vendor)
+ labels WELLTXT port
+ variants ()
+ labels WELLTXT text
+ variants *
+ labels WELLPIN port
+
+ layer nwell NWELL,WELLTXT,WELLPIN
+ and-not PNPID
+ labels NWELL
+ variants (vendor)
+ labels WELLTXT port
+ variants ()
+ labels WELLTXT text
+ variants *
+ labels WELLPIN port
+
+ templayer nwellarea NWELL
+ copyup nwelcheck
+
+ # Copy nwell areas up for diffusion checks
+ templayer xnwelcheck nwelcheck
+ copyup nwelcheck
+
+ templayer hvarea HVI
+ copyup hvcheck
+
+ # Copy high-voltage (HVI) areas up for diffusion checks
+ templayer xhvcheck hvcheck
+ copyup hvcheck
+
+ # Always draw pwell under p-tap and n-diff.  This is not always
+ # necessary but works better with deep nwell for correct extraction.
+ layer pwell TAP,DIFF
+ and-not NWELL,nwelcheck
+ grow 130
+ or SUBTXT,SUBPIN
+ grow 420
+ shrink 420
+ variants (vendor)
+ labels SUBTXT port
+ variants ()
+ labels SUBTXT text
+ variants *
+ labels SUBPIN port
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ layer isosub SUBCUT
+ labels SUBCUT
+
+ layer npn DNWELL
+ and-not NWELL,nwelcheck
+ and NPNID
+
+ layer photo DNWELL
+ and PHOTO
+
+ layer rpw PWRES
+ and DNWELL
+ labels PWRES
+
+ templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and-not NWELL,nwelcheck
+ and-not PSDM
+ and-not DIODE
+ and-not DIFFRES
+ and-not HVI,hvcheck
+ and NSDM
+ and-not CORELI
+ copyup ndifcheck
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer ndiff ndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and-not NWELL,nwelcheck
+ and-not PSDM
+ and-not DIODE
+ and-not DIFFRES
+ and HVI,hvcheck
+ and NSDM
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer mvndiff mvndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF,barediff
+ and NSDM
+ and DIODE
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ labels DIFF
+
+ layer ndiodelvt DIFF,barediff
+ and NSDM
+ and DIODE
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and LVTN
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NSDM
+ and-not HVI,hvcheck
+ and-not NWELL,nwelcheck
+ copyup DIODE,NSDM
+
+ layer ndiffres DIFFRES
+ and NSDM
+ and-not HVI,hvcheck
+ labels DIFF
+
+ templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and NWELL,nwelcheck
+ and-not NSDM
+ and-not DIODE
+ and-not HVI,hvcheck
+ and PSDM
+ copyup pdifcheck
+ labels DIFF 
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer pdiff pdiffarea
+
+ layer mvndiode DIFF,barediff
+ and NSDM
+ and DIODE
+ and HVI,hvcheck
+ and-not POLY
+ and-not PSDM
+ and-not LVTN
+ labels DIFF
+
+ layer nndiode DIFF,barediff
+ and NSDM
+ and DIODE
+ and HVI,hvcheck
+ and-not POLY
+ and-not PSDM
+ and LVTN
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NSDM
+ and HVI,hvcheck
+ and-not NWELL,nwelcheck
+ copyup DIODE,NSDM
+
+ layer mvndiffres DIFFRES
+ and NSDM
+ and HVI,hvcheck
+ labels DIFF
+
+ templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not POLY
+ and NWELL,nwelcheck
+ and-not NSDM
+ and HVI,hvcheck
+ and-not DIODE
+ and-not DIFFRES
+ and PSDM
+ copyup mvpdifcheck
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer mvpdiff mvpdiffarea
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodelvt DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodehvt DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and HVTP
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PSDM
+ and-not HVI,hvcheck
+ copyup DIODE,PSDM
+
+ # Define pfet areas as known pdiff, regardless of the presence of a well.
+
+ templayer pfetarea DIFF,barediff
+ and POLY
+ or baretrans
+ and-not NSDM
+ and-not HVI,hvcheck
+
+ layer pfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scpfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scpfethvt pfetarea
+ and-not LVTN
+ and HVTP
+ and STDCELL
+ labels DIFF
+
+ layer ppu pfetarea
+ and-not LVTN
+ and HVTP
+ and COREID
+ # Shrink-grow operation eliminates the smaller parasitie device
+ # shrink 70
+ # grow 70
+ labels DIFF
+
+ layer pfetlvt pfetarea
+ and LVTN
+ labels DIFF
+
+ layer pfetmvt pfetarea
+ and HVTR
+ labels DIFF
+
+ layer pfethvt pfetarea
+ and HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ # Always force nwell under pfet (nwell encloses pdiff by 0.18)
+ layer nwell pfetarea
+ and-not COREID
+ grow 180
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF,barediff
+ and PSDM
+ and-not POLY
+ and-not NSDM
+ and HVI,hvcheck
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PSDM
+ and HVI,hvcheck
+ copyup DIODE,PSDM
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF,barediff
+ and POLY
+ or baretrans
+ and-not NSDM
+ and HVI,hvcheck
+
+ layer mvpfet mvpfetarea
+ and-not ESDID
+ labels DIFF
+
+ layer mvpfetesd mvpfetarea
+ and ESDID
+ labels DIFF
+
+ layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ and-not DIODE
+ and-not DIFFRES
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer pdiffres DIFFRES
+ and PSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+ labels DIFF
+
+ layer nfet DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not SONOS
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scnfet DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not SONOS
+ and STDCELL
+ labels DIFF
+
+ layer npass DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and COREID
+ labels DIFF
+
+ layer npd DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and COREID
+ # Shrink-grow operation eliminates the smaller npass device
+ shrink 70
+ grow 70
+ labels DIFF
+
+ # Devices abutting tap under gate are officially npd, not npass
+ layer npd TAP
+ grow 100
+ and DIFF
+ and POLY
+ and-not PSDM
+ and NSDM
+ and-not NWELL,nwelcheck
+ and COREID
+ labels DIFF
+
+ layer nfetlvt DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and-not SONOS
+ labels DIFF
+
+ layer nsonos DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and SONOS
+ labels DIFF
+
+ templayer nsdarea TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and-not CORELI
+ copyup nsubcheck
+
+ layer nsd nsdarea
+ labels TAP
+
+ layer nsd TAP,TAPTXT
+ and NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ layer corenvar TAP
+ and NSDM
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea TAP
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels TAP
+
+ layer psd TAP
+ and PSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ layer corepvar TAP
+ and PSDM
+ and POLY
+ and COREID
+ labels TAP
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
+ and-not NSDM
+ and-not POLY
+ and HVI,hvcheck
+ and mvpfetexpand
+ labels DIFF
+ variants (vendor)
+ labels DIFFTXT port
+ variants ()
+ labels DIFFTXT text
+ variants *
+ labels DIFFPIN port
+
+ layer mvpdiffres DIFFRES
+ and PSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+ and-not mvrdpioedge
+ labels DIFF
+
+ templayer mvnfetarea DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and-not LVTN
+ and HVI,hvcheck
+ grow 350
+
+ templayer mvnnfetarea DIFF,TAP,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and LVTN
+ and HVI,hvcheck
+ and-not mvnfetarea
+
+ layer mvnfetesd DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and HVI,hvcheck
+ and ESDID
+ and-not mvnnfetarea
+ labels DIFF
+
+ layer mvnfet DIFF,barediff
+ and POLY
+ or baretrans
+ and-not PSDM
+ and NSDM
+ and HVI,hvcheck
+ and-not ESDID
+ and-not mvnnfetarea
+ labels DIFF
+
+ layer nnfet mvnnfetarea
+ and LVID
+ labels DIFF
+
+ layer mvnnfet mvnnfetarea
+ and-not LVID
+ labels DIFF
+
+ templayer mvnsdarea TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not POLY
+ and-not PSDM
+ and HVI,hvcheck
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels TAP
+
+ layer mvnsd TAP,TAPTXT
+ and NSDM
+ and HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF,barediff
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not POLY
+ and-not NSDM
+ and HVI,hvcheck
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ layer mvpsd TAP,TAPTXT
+ and PSDM
+ and HVI,hvcheck
+ labels TAP
+ labels TAPTXT text
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and-not HVI,hvcheck
+ and nsdexpand
+
+ layer mvpsd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and HVI,hvcheck
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and HVI,hvcheck
+ and mvnsdexpand
+
+ templayer hresarea POLY
+ and RPM
+ grow 3000
+
+ templayer uresarea POLY
+ and URPM
+ grow 3000
+
+ templayer diffresarea DIFFRES
+ and-not HVI,hvcheck
+ grow 3000
+
+ templayer mvdiffresarea DIFFRES
+ and HVI,hvcheck
+ grow 3000
+
+ templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
+
+ layer pfet POLY
+ and DIFF
+ and diffresarea
+ and-not NSDM
+ and-not STDCELL
+
+ layer scpfet POLY
+ and DIFF
+ and diffresarea
+ and-not HVTP
+ and-not NSDM
+ and STDCELL
+
+ layer scpfethvt POLY
+ and DIFF
+ and diffresarea
+ and HVTP
+ and-not NSDM
+ and STDCELL
+
+ templayer xpolyterm RPM,URPM
+ and POLY
+ and-not POLYRES
+ # add back the 0.06um contact surround in the direction of the resistor
+ grow 60
+ and POLY
+
+ layer xpc xpolyterm
+
+ templayer polyarea POLY,POLYTXT,POLYPIN
+ and-not POLYRES
+ and-not POLYSHORT
+ and-not DIFF
+ and-not TAP
+ and-not RPM
+ and-not URPM
+ copyup polycheck
+
+ layer poly polyarea
+ labels POLY
+ variants (vendor)
+ labels POLYTXT port
+ variants ()
+ labels POLYTXT text
+ variants *
+ labels POLYPIN port
+
+ # Copy (non-resistor) poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer mrp1 POLY
+ and POLYRES
+ and-not RPM
+ and-not URPM
+ labels POLY
+
+ layer rmp POLY
+ and POLYSHORT
+ labels POLY
+
+ layer xhrpoly POLY
+ and POLYRES
+ and RPM
+ and-not URPM
+ and PSDM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ layer uhrpoly POLY
+ and POLYRES
+ and URPM
+ and-not RPM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ templayer ndcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and NSDM
+ and-not NWELL,nwelcheck
+ and-not HVI,hvcheck
+
+ layer ndc ndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndcbase
+ labels CONT
+
+ templayer nscbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF,TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+
+ layer nsc nscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nscbase
+ labels CONT
+
+ templayer pdcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+
+ layer pdc pdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcbase
+ labels CONT
+
+ templayer pdcnowell CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and pfetexpand
+ and-not HVI,hvcheck
+
+ layer pdc pdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcnowell
+ labels CONT
+
+ templayer pscbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF,TAP
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not pfetexpand
+ and-not HVI,hvcheck
+
+ layer psc pscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pscbase
+ labels CONT
+
+ templayer pcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and POLY
+ and-not DIFF
+ and-not RPM,URPM
+
+ layer pc pcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pcbase
+ labels CONT
+
+ templayer ndicbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+
+ layer ndic ndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndicbase
+ labels CONT
+
+ templayer ndilvtcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and-not HVI,hvcheck
+ and LVTN
+
+ layer ndilvtc ndilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndilvtcbase
+ labels CONT
+
+ templayer pdicbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and-not HVTP
+
+ layer pdic pdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdicbase
+ labels CONT
+
+ templayer pdilvtcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and LVTN
+ and-not HVTP
+
+ layer pdilvtc pdilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdilvtcbase
+ labels CONT
+
+ templayer pdihvtcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and-not HVI,hvcheck
+ and-not LVTN
+ and HVTP
+
+ layer pdihvtc pdihvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdihvtcbase
+ labels CONT
+
+ templayer mvndcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and NSDM
+ and-not NWELL,nwelcheck
+ and HVI,hvcheck
+
+ layer mvndc mvndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndcbase
+ labels CONT
+
+ templayer mvnscbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF,TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+
+ layer mvnsc mvnscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnscbase
+ labels CONT
+
+ templayer mvpdcbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+
+ layer mvpdc mvpdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcbase
+ labels CONT
+
+ templayer mvpdcnowell CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and mvpfetexpand
+ and MET1
+ and HVI,hvcheck
+
+ layer mvpdc mvpdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcnowell
+ labels CONT
+
+ templayer mvpscbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF,TAP
+ and PSDM
+ and-not NWELL,nwelcheck
+ and-not mvpfetexpand
+ and HVI,hvcheck
+
+ layer mvpsc mvpscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpscbase
+ labels CONT
+
+ templayer mvndicbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and-not LVTN
+ and HVI,hvcheck
+
+ layer mvndic mvndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndicbase
+ labels CONT
+
+ templayer nndicbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and NSDM
+ and DIODE
+ and-not POLY
+ and-not PSDM
+ and LVTN
+ and HVI,hvcheck
+
+ layer nndic nndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nndicbase
+ labels CONT
+
+ templayer mvpdicbase CONT
+ or barecont
+ and LI
+ or barelicont
+ and DIFF
+ and PSDM
+ and DIODE
+ and-not POLY
+ and-not NSDM
+ and HVI,hvcheck
+
+ layer mvpdic mvpdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdicbase
+ labels CONT
+
+ layer	fomfill  FOMFILL
+ labels FOMFILL
+
+ layer	polyfill POLYFILL
+ labels POLYFILL
+
+ layer coreli LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and COREID
+ labels LI
+ variants (vendor)
+ labels LITXT port
+ variants ()
+ labels LITXT text
+ variants *
+ labels LIPIN port
+
+ layer locali LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and-not COREID
+ labels LI
+ variants (vendor)
+ labels LITXT port
+ variants ()
+ labels LITXT text
+ variants *
+ labels LIPIN port
+
+ layer rli LI
+ and LIRES,LISHORT
+ labels LIRES,LISHORT
+
+ layer	lifill LIFILL
+ labels LIFILL
+
+ layer mcon MCON
+ grow 95
+ shrink 95
+ shrink 85
+ grow 85
+ or MCON
+ labels MCON
+
+ layer m1 MET1,MET1TXT,MET1PIN
+ and-not MET1RES,MET1SHORT
+ labels MET1
+ variants (vendor)
+ labels MET1TXT port
+ variants ()
+ labels MET1TXT text
+ variants *
+ labels MET1PIN port
+
+ layer rm1 MET1
+ and MET1RES,MET1SHORT
+ labels MET1RES,MET1SHORT
+
+ layer m1fill MET1FILL
+ labels MET1FILL
+
+ layer mimcap MET3
+ and CAPM
+ labels CAPM
+
+ layer mimcc VIA3
+ and CAPM
+ grow 60
+ grow 40
+ shrink 40
+ labels CAPM
+
+ layer mimcap2 MET4
+ and CAPM2
+ labels CAPM2
+
+ layer mim2cc VIA4
+ and CAPM2
+ grow 190
+ grow 210
+ shrink 210
+ labels CAPM2
+
+
+
+ templayer m2cbase VIA1
+ and-not COREID
+ grow 5
+ or VIA1
+ grow 50
+
+ layer m2c m2cbase
+ grow 30
+ shrink 30
+ shrink 130
+ grow 130
+ or m2cbase
+
+ layer m2 MET2,MET2TXT,MET2PIN
+ and-not MET2RES,MET2SHORT
+ labels MET2
+ variants (vendor)
+ labels MET2TXT port
+ variants ()
+ labels MET2TXT text
+ variants *
+ labels MET2PIN port
+
+ layer rm2 MET2
+ and MET2RES,MET2SHORT
+ labels MET2RES,MET2SHORT
+
+ layer m2fill MET2FILL
+ labels MET2FILL
+
+ templayer m3cbase VIA2
+ grow 40
+
+ layer m3c m3cbase
+ grow 60
+ shrink 60
+ shrink 140 
+ grow 140
+ or m3cbase
+
+ layer m3 MET3,MET3TXT,MET3PIN
+ and-not MET3RES,MET3SHORT
+ labels MET3
+ variants (vendor)
+ labels MET3TXT port
+ variants ()
+ labels MET3TXT text
+ variants *
+ labels MET3PIN port
+
+ layer rm3 MET3
+ and MET3RES,MET3SHORT
+ labels MET3RES,MET3SHORT
+
+ layer m3fill MET3FILL
+ labels MET3FILL
+
+
+ templayer via3base VIA3
+ and-not CAPM
+ grow 60
+
+ layer via3 via3base
+ grow 40
+ shrink 40
+ shrink 160
+ grow 160
+ or via3base
+
+ layer m4 MET4,MET4TXT,MET4PIN
+ and-not MET4RES,MET4SHORT
+ labels MET4
+ variants (vendor)
+ labels MET4TXT port
+ variants ()
+ labels MET4TXT text
+ variants *
+ labels MET4PIN port
+
+ layer rm4 MET4
+ and MET4RES,MET4SHORT
+ labels MET4RES,MET4SHORT
+
+ layer m4fill MET4FILL
+ labels MET4FILL
+
+ layer m5 MET5,MET5TXT,MET5PIN
+ and-not MET5RES,MET5SHORT
+ labels MET5
+ variants (vendor)
+ labels MET5TXT port
+ variants ()
+ labels MET5TXT text
+ variants *
+ labels MET5PIN port
+
+ layer rm5 MET5
+ and MET5RES,MET5SHORT
+ labels MET5RES,MET5SHORT
+
+ layer m5fill MET5FILL
+ labels MET5FILL
+
+ templayer via4base VIA4
+ and-not CAPM2
+ grow 190
+
+ layer via4 via4base
+ grow 210
+ shrink 210
+ shrink 590
+ grow 590
+ or via4base
+
+ layer metrdl RDL,RDLTXT,RDLPIN
+ labels RDL
+ variants (vendor)
+ labels RDLTXT port
+ variants ()
+ labels RDLTXT text
+ variants *
+ labels RDLPIN port
+
+ # Find diffusion not covered in
+ # NSDM or PSDM and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PSDM
+ and-not NSDM
+ and POLY
+ copyup baretrans
+
+ templayer gendiff DIFF,TAP
+ and-not PSDM
+ and-not NSDM
+ and-not POLY
+ and-not COREID
+ copyup barediff
+
+ # Handle contacts found by copyup
+
+ templayer ndiccopy CONT
+ and LI
+ and DIODE
+ and NSDM
+ and-not HVI,hvcheck
+
+ layer ndic ndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndiccopy
+ labels CONT
+
+ templayer mvndiccopy CONT
+ and LI
+ and DIODE
+ and NSDM
+ and HVI,hvcheck
+
+ layer mvndic mvndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndiccopy
+ labels CONT
+
+ templayer pdiccopy CONT
+ and LI
+ and DIODE
+ and PSDM
+ and-not HVI,hvcheck
+
+ layer pdic pdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdiccopy
+ labels CONT
+
+ templayer mvpdiccopy CONT
+ and LI
+ and DIODE
+ and PSDM
+ and HVI,hvcheck
+
+ layer mvpdic mvpdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdiccopy
+ labels CONT
+
+ templayer ndccopy CONT
+ and ndifcheck
+
+ layer ndc ndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndccopy
+ labels CONT
+
+ templayer mvndccopy CONT
+ and mvndifcheck
+
+ layer mvndc mvndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndccopy
+ labels CONT
+
+ templayer pdccopy CONT
+ and pdifcheck
+
+ layer pdc pdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdccopy
+ labels CONT
+
+ templayer mvpdccopy CONT
+ and mvpdifcheck
+
+ layer mvpdc mvpdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdccopy
+ labels CONT
+
+ templayer pccopy CONT
+ and polycheck
+
+ layer pc pccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pccopy
+ labels CONT
+
+ templayer nsccopy CONT
+ and nsubcheck
+
+ layer nsc nsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nsccopy
+ labels CONT
+
+ templayer mvnsccopy CONT
+ and mvnsubcheck
+
+ layer mvnsc mvnsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnsccopy
+ labels CONT
+
+ templayer psccopy CONT
+ and psubcheck
+
+ layer psc psccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or psccopy
+ labels CONT
+
+ templayer mvpsccopy CONT
+ and mvpsubcheck
+
+ layer mvpsc mvpsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpsccopy
+ labels CONT
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+ 
+ templayer barelicont CONT
+ and LI
+ and-not DIFF,TAP
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ and-not CORELI
+ copyup barelicont
+
+ templayer barecont CONT
+ and-not LI
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ and-not CORELI
+ copyup barecont
+
+ layer glass GLASS,PADTXT,PADPIN
+ labels GLASS
+ variants (vendor)
+ labels PADTXT port
+ variants ()
+ labels PADTXT text
+ variants *
+ labels PADPIN port
+
+ templayer boundary BOUND,STDCELL,PADCELL
+ boundary
+
+ layer comment LVSTEXT
+ labels LVSTEXT text
+
+ layer comment TTEXT
+ labels TTEXT text
+
+ layer fillblock  FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+ labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+
+ layer obsactive  FILLOBSFOM
+
+# MOS Varactor
+
+ layer var POLY
+ and TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+ and-not HVTP
+ # NOTE:  Else forms a varactor that is not in the vendor netlist.
+ and-not COREID
+ labels POLY
+
+ layer varhvt POLY
+ and TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and-not HVI,hvcheck
+ and HVTP
+ labels POLY
+
+ layer mvvar POLY
+ and TAP
+ and NSDM
+ and NWELL,nwelcheck
+ and HVI,hvcheck
+ labels POLY
+
+ calma NWELL 64 20
+ calma DIFF 65 20
+ calma DNWELL 64 18
+ calma SUBCUT 81 53
+ calma PWRES 64 13
+ calma TAP  65 44
+ # LVTN
+ calma LVTN 125 44
+ # HVTR
+ calma HVTR 18 20
+ # HVTP
+ calma HVTP 78 44
+ # SONOS (TUNM)
+ calma SONOS 80 20
+ # NSDM (NPLUS)
+ calma NSDM 93 44
+ # PSDM (PPLUS)
+ calma PSDM 94 20
+ # HVI (THKOX)
+ calma HVI 75 20
+ # NPC
+ calma NPC 95 20
+ # P+ POLY MASK
+ calma RPM 86 20
+ calma URPM 79 20
+ calma LDNTM 11 44
+ calma HVNTM 125 20
+ # Poly resistor ID mark
+ calma POLYRES 66 13
+ # Diffusion resistor ID mark
+ calma DIFFRES 65 13
+ calma POLY 66 20
+ calma POLYMOD 66 83
+ # 3.3V native FET ID mark
+ calma LVID 81 60
+ # Diode ID mark
+ calma DIODE 81 23
+ # Bipolar NPN mark
+ calma NPNID 82 20
+ # Bipolar PNP mark
+ calma PNPID 82 44
+ # Capacitor ID
+ calma CAPID 82 64
+ # Core area ID mark
+ calma COREID 81 2
+ # Photodiode ID mark
+ calma PHOTO 81 81
+ # Standard cell ID mark
+ calma STDCELL 81 4
+ # Padframe cell ID mark
+ calma PADCELL 81 3
+ # Seal ring ID mark
+ calma SEALID 81 1
+ # Low tap density ID mark
+ calma LOWTAPDENSITY 81 14
+ # ESD area ID
+ calma ESDID 81 19
+ # Various unused layers
+ calma OUTLINE 236 0
+ calma POLYCUT 66 14
+ calma POLYGATE 66 9
+ calma DIFFCUT 65 14
+ calma HVNWELLID 81 63
+ calma MET5BLOCK 72 10
+ calma PADDIFFID 81 6
+ calma PADMETALID 81 8
+ calma PADCENTERID 81 20
+ 
+ # LICON
+ calma CONT 66 44
+ calma LI   67 20
+ calma MCON 67 44
+
+ calma MET1 68 20
+ calma VIA1 68 44
+ calma MET2 69 20
+ calma VIA2 69 44
+ calma MET3 70 20
+ calma VIA3 70 44
+ calma MET4 71 20
+ calma VIA4 71 44
+ calma MET5 72 20
+ calma RDL 74 20
+ calma GLASS 76 20
+
+ calma SUBTXT  64 59
+ calma PADTXT  76 5
+ calma DIFFTXT 65 6
+ calma TAPTXT  65 5
+ calma WELLTXT  64 5
+ calma LITXT 67 5
+ calma POLYTXT 66 5
+ calma MET1TXT 68 5
+ calma MET2TXT 69 5
+ calma MET3TXT 70 5
+ calma MET4TXT 71 5
+ calma MET5TXT 72 5
+ calma RDLTXT 74 5
+
+ calma LIRES 67 13
+ calma MET1RES 68 13
+ calma MET2RES 69 13
+ calma MET3RES 70 13
+ calma MET4RES 71 13
+ calma MET5RES 72 13
+
+ calma LIFILL   56 28
+ calma MET1FILL 36 28
+ calma MET2FILL 41 28
+ calma MET3FILL 34 28
+ calma MET4FILL 51 28
+ calma MET5FILL 59 28
+
+ calma POLYSHORT 66 15
+ calma LISHORT 67 15
+ calma MET1SHORT 68 15
+ calma MET2SHORT 69 15
+ calma MET3SHORT 70 15
+ calma MET4SHORT 71 15
+ calma MET5SHORT 72 15
+
+ calma SUBPIN 122 16
+ calma PADPIN 76 16
+ calma DIFFPIN 65 16
+ calma POLYPIN 66 16
+ calma WELLPIN 64 16
+ calma LIPIN 67 16
+ calma MET1PIN 68 16
+ calma MET2PIN 69 16
+ calma MET3PIN 70 16
+ calma MET4PIN 71 16
+ calma MET5PIN 72 16
+ calma RDLPIN 74 16
+
+ calma BOUND 235 4
+
+ calma LVSTEXT 83 44
+
+ calma CAPM 89 44
+ calma CAPM2 97 44
+
+ calma FILLOBSM1  62  24
+ calma FILLOBSM2  105 52
+ calma FILLOBSM3  107 24
+ calma FILLOBSM4  112  4
+ calma FILLOBSFOM  22 24
+ calma FILLOBSPOLY 33 24
+
+ calma FOMFILL	  23  28
+ calma POLYFILL	  28  28
+ calma LIFILL	  56  28
+ calma MET1FILL	  36  28
+ calma MET2FILL	  41  28
+ calma MET3FILL	  34  28
+ calma MET4FILL	  51  28
+ calma MET5FILL	  59  28
+
+#-----------------------------------------------------------------------
+
+style  rdlimport
+ # This style is for reading shapes generated with the RDL layers
+
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ layer mrdl RDL
+ layer mrdlc RDLC
+
+ calma RDL 10 0
+ calma RDLC 20 0
+
+end
+
+#-----------------------------------------------------
+# Digital flow maze router cost parameters
+#-----------------------------------------------------
+
+mzrouter
+end
+
+#-----------------------------------------------------
+# Vendor DRC rules
+#-----------------------------------------------------
+
+drc
+
+ style drc variants (fast),(full),(routing)
+ scalefactor 10 
+ cifstyle drc
+
+ variants (fast),(full)
+
+#-----------------------------
+# DNWELL
+#-----------------------------
+
+ width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
+ spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
+ spacing allnwell dnwell 4500 surround_ok \
+	"Deep N-well spacing to N-well < %d (nwell.7)"
+
+ variants (full)
+ cifmaxwidth nwell_missing 0 bend_illegal \
+	"N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
+ cifmaxwidth dnwell_missing 0 bend_illegal \
+	"SONOS nFET must be in Deep N-well (tunm.6a)"
+
+ cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
+	"P+ diff cannot straddle Deep N-well (dnwell.5)"
+ variants (fast),(full)
+
+ width photo 3000 "Photodiode width < %d (photo.2)"
+ spacing photo photo 5000 touching_ok "Photodiode spacing < %d (photo.3)"
+ spacing photo dnwell 5300 touching_illegal \
+	"Photodiode spacing to deep nwell < %d (photo.4)"
+
+#-----------------------------
+# NWELL
+#-----------------------------
+
+ width allnwell 840 "N-well width < %d (nwell.1)"
+ spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
+
+ variants (full)
+ cifmaxwidth nwell_missing_tap 0 bend_illegal \
+	"All nwells must contain metal-connected N+ taps (nwell.4)"
+
+ cifspacing mvnwell lvnwell 2000 touching_illegal \
+	"Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
+ cifspacing mvnwell mvnwell 2000 touching_ok \
+	"Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
+
+ cifmaxwidth lvdiff_in_mvnwell 0 bend_illegal \
+	"All HV nwell can contain only HV diffusion (diff/tap.21)" 
+
+ variants (fast),(full)
+
+#-----------------------------
+# DIFF
+#-----------------------------
+
+ width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
+	150 "Diffusion width < %d (diff/tap.1)"
+ width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
+	"MV Diffusion width < %d (diff/tap.14)"
+
+ width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
+ extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
+ extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
+ extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
+ extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
+ width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
+ spacing alldifflv,var,varhvt,corenvar,corepvar,fomfill \
+	 alldifflv,var,varhvt,corenvar,corepvar,fomfill 270 touching_ok \
+	"Diffusion spacing < %d (diff/tap.3)"
+ spacing alldifflv,var,varhvt alldiffmv,mvvar 270 touching_illegal \
+	"LV to MV Diffusion spacing < %d (diff/tap.3)"
+ spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
+	"MV Diffusion spacing < %d (diff/tap.15a)"
+ spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
+	"MV Diffusion to MV tap spacing < %d (diff/tap.3)"
+ spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
+	touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
+ spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
+	"MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
+ spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (diff/tap.9)"
+ spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (diff/tap.9)"
+ spacing *psd allnwell 130 touching_illegal \
+	"P-tap spacing to N-well < %d (diff/tap.11)"
+ spacing *mvpsd allnwell 130 touching_illegal \
+	"P-tap spacing to N-well < %d (diff/tap.11)"
+ surround *nsd allnwell 180 absence_illegal \
+	"N-well overlap of N-tap < %d (diff/tap.10)"
+ surround *mvnsd allnwell 330 absence_illegal \
+	"N-well overlap of MV N-tap < %d (diff/tap.19)"
+ surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (diff/tap.8)"
+ surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (diff/tap.17)"
+ surround mvvar allnwell 560 absence_illegal \
+	"N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
+ spacing *mvndiode *mvndiode 1070 touching_ok \
+	"MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
+
+variants (full)
+ cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
+	"MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
+ cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \
+	"HVI to HVI or LV nwell spacing < %d (hvi.5)"
+variants (fast),(full)
+
+ spacing allnfets allpactivenonfet 270 touching_illegal \
+	"nFET cannot abut P-diffusion (diff/tap.3)"
+ spacing allpfets allnactivenonfet 270 touching_illegal \
+	"pFET cannot abut N-diffusion (diff/tap.3)"
+
+ # Butting junction rules
+ edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
+	"N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
+ edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
+	"N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
+ edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
+	"P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
+ edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
+	"P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
+
+ edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
+	"MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
+ edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
+	"MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
+ edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
+	"MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
+ edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
+	"MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
+
+ # Sandwiched butting junction restrictions
+ edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
+ edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
+
+ area  *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
+ area  *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
+
+ angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
+
+ variants (full)
+ cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
+
+ # Latchup rules
+ cifmaxwidth ptap_missing 0 bend_illegal \
+	"N-diff distance to P-tap must be < 15.0um (LU.2)"
+ cifmaxwidth dptap_missing 0 bend_illegal \
+	"N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
+ cifmaxwidth ntap_missing 0 bend_illegal \
+	"P-diff distance to N-tap must be < 15.0um (LU.3)"
+
+ variants (fast),(full)
+
+#-----------------------------
+# POLY
+#-----------------------------
+
+ width allpoly,polyfill 150 "poly width < %d (poly.1a)"
+ spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
+
+ spacing allpolynonfet,polyfill \
+	*ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
+	75 corner_ok allfets \
+	"poly spacing to Diffusion < %d (poly.4)"
+ spacing npres *nsd 480 touching_illegal \
+	"poly resistor spacing to N-tap < %d (poly.9)"
+ overhang *ndiff,rndiff nfet,scnfet,npd,npass,nsonos 250 "N-Diffusion overhang of nFET < %d (poly.7)"
+ overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
+	"N-Diffusion overhang of nFET < %d (poly.7)"
+ overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
+ overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
+ overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
+ overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
+ rect_only allfets "No bends in transistors (poly.11)"
+ rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
+ extend  xpc/a xhrpoly,uhrpoly 2160 \
+ 	"poly contact extends poly resistor by < %d (licon.1c + li.5)"
+ spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
+	"Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
+
+ variants (fast)
+
+ spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
+	"Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
+ spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
+	"Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
+ spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
+	"Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
+
+ # Minimum width requirement means actual spacing from res to ndiff has to be
+ # constructed from mask rules.  These supercede the simpler checks.
+
+ variants (full)
+
+ cifmaxwidth rpm_nsd_check 0 bend_illegal \
+	"Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
+ cifmaxwidth rpm_poly_check 0 bend_illegal \
+	"Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
+ cifmaxwidth rpm_hvntm_check 0 bend_illegal \
+	"Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
+
+ variants (fast),(full)
+
+ angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
+
+#--------------------------------------------------------------------
+# HVTP
+#--------------------------------------------------------------------
+
+ spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
+		360 touching_illegal \
+		"Min. spacing between pFET and HVTP < %d (hvtp.4)"
+
+ spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
+		"Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
+
+#--------------------------------------------------------------------
+# LVTN
+#--------------------------------------------------------------------
+
+ spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
+		allfetsnolvt 360 touching_illegal \
+		"Min. spacing between FET and LVTN < %d (lvtn.3a)"
+
+ spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
+		740 touching_illegal \
+		"Min. spacing between LVTN and HVTP < %d (lvtn.9)"
+
+ # Spacing across S/D direction requires edge rule
+ edge4way allfetsnolvt allactivenonfet 415 \
+	~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
+	"Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
+
+#--------------------------------------------------------------------
+# NPC (Nitride poly Cut)
+#--------------------------------------------------------------------
+
+# Layer NPC is defined automatically around poly contacts (grow 0.1um)
+
+#--------------------------------------------------------------------
+# CONT (LICON, contact between poly/diff and LI)
+#--------------------------------------------------------------------
+
+ width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
+ width nsc/li 170 "N-tap contact width     < %d (licon.1)"
+ width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
+ width psc/li 170 "P-tap contact width     < %d (licon.1)"
+ width ndic/li 170 "N-diode contact width < %d (licon.1)"
+ width pdic/li 170 "P-diode contact width < %d (licon.1)"
+ width pc/li  170 "poly contact width        < %d (licon.1)"
+
+ width xpc/li  350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
+ area  xpc/li  700000 350 "poly resistor contact length < 2.0um (licon.1c)"
+ area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
+
+ width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
+ width mvnsc/li 170 "N-tap contact width     < %d (licon.1)"
+ width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
+ width mvpsc/li 170 "P-tap contact width     < %d (licon.1)"
+ width mvndic/li 170 "N-diode contact width < %d (licon.1)"
+ width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
+
+ spacing allpdiffcont allndiffcont 170 touching_illegal \
+	"Diffusion contact spacing < %d (licon.2)"
+ spacing allndiffcont allndiffcont 170 touching_ok \
+	"Diffusion contact spacing < %d (licon.2)"
+ spacing allpdiffcont allpdiffcont 170 touching_ok \
+	"Diffusion contact spacing < %d (licon.2)"
+ spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
+
+ spacing pc alldiff 190 touching_illegal \
+	"poly contact spacing to diffusion < %d (licon.14)"
+ spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
+	"poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
+
+ spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
+	"Diffusion contact to gate < %d (licon.11)"
+ spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
+	"Diffusion contact to standard cell gate < %d (licon.11)"
+ spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
+	"Diffusion contact to SRAM gate < %d (licon.11)"
+ spacing ndc,pdc nsonos 75 touching_illegal \
+	"Diffusion contact to SONOS gate < %d (licon.11)"
+ spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
+	"Diffusion contact to gate < %d (licon.11)"
+ spacing nsc varactor,varhvt 250 touching_illegal \
+	"Diffusion contact to varactor gate < %d (licon.10)"
+ spacing mvnsc mvvar 250 touching_illegal \
+	"Diffusion contact to varactor gate < %d (licon.10)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
+	"N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
+ surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
+	40 absence_illegal \
+	"P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
+ surround ndic/a *ndi 40 absence_illegal \
+	"N-diode overlap of N-diode contact < %d (licon.5a)"
+ surround pdic/a *pdi 40 absence_illegal \
+	"P-diode overlap of N-diode contact < %d (licon.5a)"
+
+ spacing psc/a allnactivenontap 60 touching_illegal \
+	"Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
+ spacing nsc/a allpactivenontap 60 touching_illegal \
+	"Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
+	"N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
+ surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
+	 60 directional \
+	"P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
+ surround ndic/a *ndi 60 directional \
+	"N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+ surround pdic/a *pdi 60 directional \
+	"P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+
+ surround nsc/a *nsd,corenvar 120 directional \
+	"N-tap overlap of N-tap contact < %d in one direction (licon.7)"
+ surround psc/a *psd,corepvar 120 directional \
+	"P-tap overlap of P-tap contact < %d in one direction (licon.7)"
+
+ surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
+	"N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
+ surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
+	"P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
+ surround mvndic/a *mvndi 40 absence_illegal \
+	"N-diode overlap of N-diode contact < %d (licon.5a)"
+ surround mvpdic/a *mvpdi 40 absence_illegal \
+	"P-diode overlap of N-diode contact < %d (licon.5a)"
+
+ spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
+	"Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
+ spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
+	"Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
+
+ surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
+	"N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
+ surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
+	"P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
+ surround mvndic/a *mvndi 60 directional \
+	"N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+ surround mvpdic/a *mvpdi 60 directional \
+	"P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
+
+ surround mvnsc/a *mvnsd 120 directional \
+	"N-tap overlap of N-tap contact < %d in one direction (licon.7)"
+ surround mvpsc/a *mvpsd 120 directional \
+	"P-tap overlap of P-tap contact < %d in one direction (licon.7)"
+
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
+	"poly overlap of poly contact < %d (licon.8)"
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
+	"poly overlap of poly contact < %d in one direction (licon.8a)"
+
+ exact_overlap (allcont)/a
+
+#-------------------------------------------------------------
+# LI - Local interconnect layer
+#-------------------------------------------------------------
+
+variants *
+
+ width *li 170 "Local interconnect width < %d (li.1)"
+ width rli 290 "Local interconnect width < %d (li.7)"
+
+ spacing *locali,rli *locali,rli,*obsli 170 touching_ok  \
+	"Local interconnect spacing < %d (li.3)"
+
+ # Local interconnect in core (SRAM) cells has more relaxed rules.  There are
+ # no special layers for the contacts in core cells, so they must be included
+ # in the rule.
+ width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
+	"Core local interconnect width < %d (li.c1)"
+
+ spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
+	"Core local interconnect spacing < %d (li.c2)"
+
+ surround pc/li *li,coreli 80 directional \
+	"Local interconnect overlap of poly contact < %d in one direction (li.5)"
+
+ surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
+	*li,rli,coreli 80 directional \
+	"Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
+
+ area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
+
+ angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
+ angles coreli 45 \
+	"Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
+
+#-------------------------------------------------------------
+# MCON - Contact between local interconnect and metal1
+#-------------------------------------------------------------
+
+ width mcon/m1 170 "mcon.width < %d (mcon.1)"
+ spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
+
+ exact_overlap mcon/li
+
+#-------------------------------------------------------------
+# METAL1 -
+#-------------------------------------------------------------
+
+ width *m1,rm1 140 "Metal1 width < %d (met1.1)"
+ spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
+ area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
+
+ surround mcon/m1 *met1 30 absence_illegal \
+	"Metal1 overlap of local interconnect contact < %d (met1.4)"
+ surround mcon/m1 *met1 60 directional \
+	"Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
+
+ angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
+	"Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
+ widespacing *obsm1 3005 allm1 280 touching_ok \
+	"Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
+
+variants (full)
+ cifmaxwidth m1_hole_empty 0 bend_illegal \
+	"Min area of metal1 holes > 0.14um^2 (met1.7)"
+
+ cifspacing m1_large_halo m1_large_halo 280 touching_ok \
+	"Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
+variants *
+
+#--------------------------------------------------
+# VIA1
+#--------------------------------------------------
+
+ width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
+ spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
+ surround v1/m1 *m1,rm1 30 directional \
+	"Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
+ surround v1/m2 *m2,rm2 30 directional \
+	"Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
+
+ exact_overlap v1/m1
+
+
+#--------------------------------------------------
+# METAL2 - 
+#--------------------------------------------------
+
+ width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
+ spacing allm2  allm2,obsm2,m2fill 140 touching_ok       "Metal2 spacing < %d (met2.2)"
+ area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
+
+ angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm2 3005 allm2,obsm2,m2fill  280 touching_ok \
+	"Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
+ widespacing obsm2 3005 allm2  280 touching_ok \
+	"Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
+
+variants (full)
+ cifmaxwidth m2_hole_empty 0 bend_illegal \
+	"Min area of metal2 holes > 0.14um^2 (met2.7)"
+
+ cifspacing m2_large_halo m2_large_halo 280 touching_ok \
+	"Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
+variants *
+
+#--------------------------------------------------
+# VIA2
+#--------------------------------------------------
+
+ width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)"
+
+ spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)"
+
+ surround v2/m2 *m2,rm2 45 directional \
+	"Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)"
+ surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)"
+
+ exact_overlap v2/m2
+
+#--------------------------------------------------
+# METAL3 - 
+#--------------------------------------------------
+
+ width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
+ spacing allm3 allm3,obsm3,m3fill  300 touching_ok "Metal3 spacing < %d (met3.2)"
+ area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
+
+ angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm3,m3fill 3005 allm3,obsm3  400 touching_ok \
+	"Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
+ widespacing obsm3 3005 allm3  400 touching_ok \
+	"Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
+variants (full)
+ cifspacing m3_large_halo m3_large_halo 400 touching_ok \
+	"Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
+variants *
+
+
+#--------------------------------------------------
+# VIA3 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)"
+ spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)"
+ surround v3/m3 *m3,rm3 30 directional \
+	"Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)"
+ surround v3/m4 *m4,rm4 5 absence_illegal \
+	"Metal4 overlap of via3 < %d (met4.3 - via3.4)"
+
+ exact_overlap v3/m3
+
+#-----------------------------
+# METAL4 - METAL4 Module
+#-----------------------------
+
+variants *
+
+ width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
+ spacing allm4  allm4,obsm4,m4fill 300 touching_ok      "Metal4 spacing < %d (met4.2)"
+ area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
+
+ angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
+
+variants (fast),(full)
+ widespacing allm4,m4fill 3005 allm4,obsm4  400 touching_ok \
+	"Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
+ widespacing obsm4 3005 allm4  400 touching_ok \
+	"Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
+variants (full)
+ cifspacing m4_large_halo m4_large_halo 400 touching_ok \
+	"Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
+variants *
+
+#--------------------------------------------------
+# VIA4 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)"
+ spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)"
+ surround v4/m5 *m5,rm5 120 absence_illegal \
+	"Metal5 overlap of via4 < %d (met5.3 - via4.4)"
+
+ exact_overlap v4/m4
+
+#-----------------------------
+# METAL5 - METAL5 Module
+#-----------------------------
+
+ width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
+ spacing allm5  allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
+ area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
+
+ angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
+
+
+
+variants (full)
+
+ width metrdl 10000 "RDL width < %d (rdl.1)"
+ spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
+ surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
+ spacing padl metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
+
+variants (fast),(full)
+
+
+#--------------------------------------------------
+# NMOS, PMOS
+#--------------------------------------------------
+
+ edge4way *poly allfetsstd 420 allfets 0 0 \
+	"Transistor width < %d (diff/tap.2)"
+ edge4way *poly allfetsspecial 360 allfets 0 0 \
+	"Transistor in standard cell width < %d (diff/tap.2)"
+ edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
+	"N-Transistor in SRAM core width < %d (diff/tap.2)"
+ edge4way *poly ppu 140 allfets 0 0 \
+	"P-Transistor in SRAM core width < %d (diff/tap.2)"
+
+ # Except:  Note that standard cells allow transistor width minimum 0.36um
+ width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
+
+ spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
+	"poly spacing to diffusion tap < %d (poly.5)"
+ spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
+	"poly spacing to diffusion tap < %d (poly.5)"
+ spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
+	"poly spacing to diffusion tap < %d (poly.5)"
+ spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
+	"poly spacing to diffusion tap < %d (poly.5)"
+
+ edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
+	"Butting P-tap spacing to NMOS gate < %d (poly.6)"
+ edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
+	"Butting N-tap spacing to PMOS gate < %d (poly.6)"
+ edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
+	"Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
+ edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
+	"Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
+
+ # No LV FETs in HV diff
+ spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
+	"LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
+	"LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ # No HV FETs in LV diff
+ spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
+	"MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
+	"MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
+
+ # Minimum length of MV FETs.  Note that this is larger than the minimum
+ # width (0.29um), so an edge rule is required
+
+ edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
+	"MV NMOS minimum length < %d (poly.13)"
+
+ edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
+	"MV Varactor minimum length < %d (poly.13)"
+
+ edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
+	"MV PMOS minimum length < %d (poly.13)"
+
+#--------------------------------------------------
+# mrp1 (N+ poly resistor)
+#--------------------------------------------------
+
+  width mrp1 330 "mrp1 resistor width < %d (poly.3)"
+
+#--------------------------------------------------
+# xhrpoly (P+ poly resistor)
+# uhrpoly (P+ poly resistor, 2kOhm/sq)
+#--------------------------------------------------
+
+  # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
+  width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
+  width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
+
+  spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+	"xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
+
+  spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
+	"Poly resistor spacing to poly < %d (poly.9)"
+
+  spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
+	"Poly resistor spacing to poly < %d (poly.9)"
+
+  spacing mrp1 *poly 480 touching_ok \
+	"Poly resistor spacing to poly < %d (poly.9)"
+
+  spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+	"Poly resistor spacing to diffusion < %d (poly.9)"
+
+#------------------------------------
+# nsonos
+#------------------------------------
+
+variants (full)
+  cifmaxwidth bbox_missing 0 bend_illegal \
+	"SONOS transistor must be in cell with abutment box (tunm.8)"
+variants (fast),(full)
+
+#------------------------------------
+# MOS Varactor device rules
+#------------------------------------
+
+ overhang *nsd var,varhvt 250 \
+ "N-Tap overhang of Varactor < %d (var.4)"
+
+ overhang *mvnsd mvvar 250 \
+ "N-Tap overhang of Varactor < %d (var.4)"
+
+ width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
+ extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
+
+variants (full)
+ cifmaxwidth var_poly_no_nwell 0 bend_illegal \
+	"N-well overlap of varactor poly < 0.15um (varac.5)"
+
+ cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
+	"Varactor N-well must not contain P+ diffusion (varac.7)"
+variants (fast),(full)
+
+#-----------------------------------------------------------
+# MiM CAP (CAPM) - 
+#-----------------------------------------------------------
+
+ width *mimcap 1000 "MiM cap width < %d (capm.1)"
+ spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
+ spacing *mimcap via3/m3 80 touching_illegal \
+	"MiM cap spacing to via3 < %d (capm.5 - via3.4)"
+ surround *mimcc *mimcap 80 absence_illegal \
+	"MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
+ rect_only *mimcap "MiM cap must be rectangular (capm.7)
+
+ surround *mimcap *metal3/m3 140 absence_illegal \
+	"Metal3 must surround MiM cap by %d (capm.3)"
+ spacing via2 *mimcap 100 touching_illegal \
+	"MiM cap spacing to via2 < %d (capm.8 - via2.4)"
+ spacing *mimcap *metal3/m3 500 surround_ok \
+	"MiM cap spacing to unrelated metal3 < %d (capm.11)"
+
+variants (full)
+ cifspacing mim_bottom mim_bottom 1200 touching_ok \
+	 "MiM cap bottom plate spacing < %d (capm.2b)"
+variants (fast),(full)
+
+ # MiM cap contact rules (VIA3)
+
+ width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
+ spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
+ surround mimcc/m4 *m4 5 directional \
+	"Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
+ exact_overlap mimcc/c1
+
+ width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
+ spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
+ spacing *mimcap2 via4/m4 10 touching_illegal \
+	"MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
+ surround *mim2cc *mimcap2 10 absence_illegal \
+	"MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
+ rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
+
+ surround *mimcap2 *metal4/m4 140 absence_illegal \
+	"Metal4 must surround MiM2 cap by %d (cap2m.3)"
+ spacing via3 *mimcap2 80 touching_illegal \
+	"MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
+ spacing *mimcap2 *metal4/m4 500 surround_ok \
+	"MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
+
+variants (full)
+ cifmaxwidth mim2_contact_overlap 0 bend_illegal \
+	"MiM2 cap contact must not cross MiM cap contact (cap2m.8)"
+ 
+ cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
+ 	"MiM2 cap bottom plate spacing < %d (cap2m.2b)"
+variants (fast),(full)
+
+ # MiM cap contact rules (VIA4)
+
+ width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
+ spacing mim2cc mim2cc 420 touching_ok \
+	"MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
+ surround mim2cc/m5 *m5 120 absence_illegal \
+	"Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
+ exact_overlap mim2cc/c2
+
+
+#----------------------------
+# HVNTM
+#----------------------------
+variants (full)
+ cifspacing hvntm_generate hvntm_generate 700 touching_ok \
+ 	"HVNTM spacing < %d (hvntm.2)"
+variants (fast),(full)
+
+#----------------------------
+# End DRC style
+#----------------------------
+
+end
+
+#----------------------------
+# LEF format definitions
+#----------------------------
+
+lef
+
+ masterslice pwell  pwell PWELL substrate
+ masterslice nwell  nwell NWELL
+
+ routing li	li1 LI1 LI li
+
+ routing m1	met1 MET1 m1
+ routing m2	met2 MET2 m2
+ routing m3	met3 MET3 m3
+ routing m4	met4 MET4 m4
+ routing m5	met5 MET5 m5
+ routing mrdl	met6 MET6 m6 MRDL METRDL
+
+ cut mcon  mcon MCON Mcon
+ cut m2c  via via1 VIA VIA1 cont2 via12
+ cut m3c  via2 VIA2 cont3 via23
+ cut via3 via3 VIA3 cont4 via34
+ cut via4 via4 VIA4 cont5 via45
+
+ obs obsli   li1
+ obs obsm1   met1
+ obs obsm2   met2
+ obs obsm3   met3
+
+ obs obsm4   met4
+ obs obsm5   met5
+ obs obsmrdl met6
+
+ # NOTE: obsmcon only used with li1, not obsli.
+ obs obsmcon mcon
+
+ # Vias on obstruction layers should be ignored, so cast to obstruction metal.
+ obs obsm1   via
+ obs obsm2   via2
+ obs obsm3   via3
+ obs obsm4   via4
+
+end
+
+#-----------------------------------------------------
+# Device and Parasitic extraction
+#-----------------------------------------------------
+
+extract
+ style ngspice variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc)
+ cscale 1
+ # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
+ # dimensions must be in units of microns in the extract file.
+ # Use extract style "ngspice(si)" to override this and produce
+ # a file with SI units for length/area.
+
+ variants (),(orig),(hrhc),(lrhc),(hrlc),(lrlc)
+ lambda  1E6
+ variants (si)
+ lambda 1.0
+ variants *
+
+ units	microns
+ step   7
+ sidehalo 8
+ fringeshieldhalo 8
+
+ # NOTE:  MiM cap layers have been purposely put out of order,
+ # may want to reconsider.
+
+ planeorder dwell 	0
+ planeorder well 	1
+ planeorder active 	2
+ planeorder locali 	3
+ planeorder metal1 	4
+ planeorder metal2 	5
+ planeorder metal3 	6
+ planeorder metal4 	7
+ planeorder metal5 	8
+ planeorder metali	9
+ planeorder block      10
+ planeorder comment    11
+ planeorder cap1       12
+ planeorder cap2       13
+
+ height	dnwell 	    -0.1    0.1
+ height	nwell,pwell  0.0    0.2062
+ height alldiff	     0.2062 0.12
+ height fomfill	     0.2062 0.12
+ height allpoly	     0.3262 0.18
+ height polyfill     0.3262 0.18
+ height alldiffcont  0.3262 0.61
+ height pc	     0.5062 0.43
+ height allli	     0.9361 0.10
+ height mcon	     1.0361 0.34
+ height allm1	     1.3761 0.36
+ height m1fill	     1.3761 0.36
+ height v1	     1.7361 0.27
+ height allm2	     2.0061 0.36
+ height m2fill	     2.0061 0.36
+ height v2	     2.3661 0.42
+ height allm3	     2.7861 0.845
+ height m3fill	     2.7861 0.845
+ height mimcap	     2.4661 0.2
+ height mimcap2	     3.7311 0.2
+ height mimcc	     2.6661 0.12
+ height mim2cc	     3.9311 0.09
+ height v3	     3.6311 0.39
+ height allm4	     4.0211 0.845
+ height m4fill	     4.0211 0.845
+ height v4	     4.8661 0.505
+ height allm5	     5.3711 1.26
+ height m5fill	     5.3711 1.26
+ height mrdlc	     6.6311 0.63
+ height mrdl	     7.2611 3.0
+
+ # Antenna check parameters
+ # Note that checks w/diode diffusion are not modeled
+ model partial
+ antenna poly sidewall 50 none
+ antenna allcont surface 3 none
+ antenna li sidewall 75 0 450
+ antenna mcon surface 3 0 18
+ antenna m1,m2,m3 sidewall 400 2600 400
+ antenna v1 surface 3 0 18
+ antenna v2 surface 6 0 36
+ antenna m4,m5 sidewall 400 2600 400
+ antenna v3,v4 surface 6 0 36
+
+ tiedown alldiffnonfet
+
+ substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
+
+# Resistances are in milliohms per square
+# Optional 3rd argument is the corner adjustment fraction
+# Device values come from trtc.cor (typical corner)
+
+variants (),(orig),(si)
+
+ resist (pwell,isosub)/well     4400000
+ resist (dnwell)/dwell          2200000
+ resist (nwell)/well             950000
+ resist (rpw)/well              3050000 0.5
+ resist (*ndiff,nsd)/active 	 120000
+ resist (*pdiff,*psd)/active	 197000
+ resist (*mvndiff,mvnsd)/active  114000
+ resist (*mvpdiff,*mvpsd)/active 191000
+
+ resist ndiffres/active 	120000 0.5
+ resist pdiffres/active 	197000 0.5
+ resist mvndiffres/active 	114000 0.5
+ resist mvpdiffres/active 	191000 0.5
+ resist mrp1/active		 48200 0.5
+ resist xhrpoly/active	        319800 0.5
+ resist uhrpoly/active	       2000000 0.5
+
+ resist (allpolynonres)/active   48200
+ resist rmp/active   		 48200
+
+ resist (allli)/locali		 12800
+ resist (allm1)/metal1		   125
+ resist (allm2)/metal2		   125
+ resist (allm3)/metal3	            47
+ resist (allm4)/metal4  	    47
+ resist (allm5)/metal5  	    29
+ resist mrdl/metali		     5
+
+ contact ndc,nsc		185000
+ contact pdc,psc		585000
+ contact mvndc,mvnsc		185000
+ contact mvpdc,mvpsc	  	585000
+ contact pc			152000
+ contact mcon			  9300
+ contact m2c			  4500
+ contact m3c			  3410
+ contact mimcc			  4500
+ contact mim2cc			  3410
+ contact via3			  3410
+ contact via4			   380
+ contact mrdlc			     6
+
+variants (hrhc),(hrlc)
+
+ # High-end corner resistances
+ # No corner values available for: substrate, xhrpoly, uhrpoly, RDL
+ resist (pwell,isosub)/well     4400000
+ resist (dnwell)/dwell          2575000
+ resist (nwell)/well            1350000
+ resist (rpw)/well              3535000 0.5
+ resist (*ndiff,nsd)/active 	 132000
+ resist (*pdiff,*psd)/active	 228000
+ resist (*mvndiff,mvnsd)/active  126000
+ resist (*mvpdiff,*mvpsd)/active 228000
+
+ resist ndiffres/active 	132000 0.5
+ resist pdiffres/active 	228000 0.5
+ resist mvndiffres/active 	126000 0.5
+ resist mvpdiffres/active 	228000 0.5
+ resist mrp1/active		 55800 0.5
+ resist xhrpoly/active	        319800 0.5
+ resist uhrpoly/active	       2000000 0.5
+
+ resist (allpolynonres)/active   55800
+ resist rmp/active   		 55800
+
+ resist (allli)/locali		 17000
+ resist (allm1)/metal1		   145
+ resist (allm2)/metal2		   145
+ resist (allm3)/metal3	            56
+ resist (allm4)/metal4  	    56
+ resist (allm5)/metal5  	    36
+ resist mrdl/metali		     5
+
+ contact ndc,nsc		280000
+ contact pdc,psc		840000
+ contact mvndc,mvnsc		280000
+ contact mvpdc,mvpsc	  	840000
+ contact pc			252000
+ contact mcon			 23000
+ contact m2c			 15000
+ contact m3c			  8000
+ contact mimcc			 15000
+ contact mim2cc			  8000
+ contact via3			  8000
+ contact via4			   891
+ contact mrdlc			     6
+
+variants (lrhc),(lrlc)
+
+ # Low-end corner resistances
+ # No corner values available for: substrate, xhrpoly, uhrpoly, RDL
+ resist (pwell,isosub)/well     4400000
+ resist (dnwell)/dwell          1825000
+ resist (nwell)/well             550000
+ resist (rpw)/well              2565000 0.5
+ resist (*ndiff,nsd)/active 	 108000
+ resist (*pdiff,*psd)/active	 166000
+ resist (*mvndiff,mvnsd)/active  102000
+ resist (*mvpdiff,*mvpsd)/active 160000
+
+ resist ndiffres/active 	108000 0.5
+ resist pdiffres/active 	166000 0.5
+ resist mvndiffres/active 	102000 0.5
+ resist mvpdiffres/active 	160000 0.5
+ resist mrp1/active		 42200 0.5
+ resist xhrpoly/active	        319800 0.5
+ resist uhrpoly/active	       2000000 0.5
+
+ resist (allpolynonres)/active   42200
+ resist rmp/active   		 42200
+
+ resist (allli)/locali		 10500
+ resist (allm1)/metal1		   105
+ resist (allm2)/metal2		   105
+ resist (allm3)/metal3	            38
+ resist (allm4)/metal4  	    38
+ resist (allm5)/metal5  	    21
+ resist mrdl/metali		     5
+
+ contact ndc,nsc		 95000
+ contact pdc,psc		345000
+ contact mvndc,mvnsc		 95000
+ contact mvpdc,mvpsc	  	345000
+ contact pc			 52000
+ contact mcon			  1600
+ contact m2c			  2000
+ contact m3c			   500
+ contact mimcc			  2000
+ contact mim2cc			   500
+ contact via3			   500
+ contact via4			    12
+ contact mrdlc			     6
+
+variants *
+
+ # These types should not be considered as electrical nodes
+ resist blocktypes	 	 None
+ resist obstypes	 	 None
+ resist idtypes	 	 	 None
+ resist comment	 	 	 None
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values:  Use document (...)
+#-------------------------------------------------------------------------
+# This uses the new "default" definitions that determine the intervening
+# planes from the planeorder stack, take care of the reflexive sideoverlap
+# definitions, and generally clean up the section and make it more readable.
+#
+# Also uses "units microns" statement.  All values are taken from the
+# document PEX/xRC/cap_models.  Fringe capacitance values are approximated.
+# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
+#-------------------------------------------------------------------------
+# Remember that device capacitances to substrate are taken care of by the
+# models.  Thus, active and poly definitions ignore all "fet" types.
+# fet types are excluded when computing parasitic capacitance to
+# active from layers above them because poly is a shield; fet types are
+# included for parasitics from layers above to poly.  Resistor types
+# should be removed from all parasitic capacitance calculations, or else
+# they just create floating caps.  Technically, the capacitance probably
+# should be split between the two terminals.  Unsure of the correct model.
+#-------------------------------------------------------------------------
+
+variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc)
+# Nominal capacitances
+
+#deep n-well
+defaultareacap     dnwell dwell 120
+
+#p-well
+defaultoverlap     pwell well dnwell dwell 120
+
+#n-well
+# NOTE:  This value not found in PEX files
+defaultareacap     nwell well dnwell dwell 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  17
+# defaultareacap     allpolynonfet active  106
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active 17.0
+ defaultareacap     *poly active 106.13
+ defaultperimeter   *poly active 55.27
+ defaultsideoverlap *poly active nwell,pwell well  55.27
+
+#locali
+ defaultsidewall    allli locali 28.0
+ defaultareacap     allli locali 36.99
+ defaultperimeter   allli locali 40.70
+ defaultoverlap     allli locali nwell,pwell well  36.99
+ defaultsideoverlap allli locali nwell,pwell well  40.70
+
+#locali->diff
+ defaultoverlap     allli locali allactivenonfet active 55.3
+ defaultsideoverlap allli locali allactivenonfet active 44.27
+
+#locali->poly
+ defaultoverlap     allli locali allpolynonres active 94.16
+ defaultsideoverlap allli locali allpolynonres active 51.85
+ defaultsideoverlap *poly active allli locali 25.14
+
+#metal1
+ defaultsidewall    allm1 metal1 36.9
+ defaultareacap     allm1 metal1 25.78
+ defaultperimeter   allm1 metal1 40.57
+ defaultoverlap     allm1 metal1 nwell,pwell well  25.78
+ defaultsideoverlap allm1 metal1 nwell,pwell well  40.57
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 33.6
+ defaultsideoverlap allm1 metal1 allactivenonfet active 43.10
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 44.81
+ defaultsideoverlap allm1 metal1 allpolynonres active 46.72
+ defaultsideoverlap *poly active allm1 metal1 16.69
+
+#metal1->locali
+ defaultoverlap     allm1 metal1 allli locali 114.20
+ defaultsideoverlap allm1 metal1 allli locali 59.50
+ defaultsideoverlap allli locali allm1 metal1 34.70
+
+#metal2
+ defaultsidewall    allm2 metal2      39.1
+
+ defaultareacap     allm2 metal2 16.9
+ defaultperimeter   allm2 metal2 37.76
+ defaultoverlap     allm2 metal2 nwell,pwell well 16.9
+ defaultsideoverlap allm2 metal2 nwell,pwell well 37.76
+
+#metal2->diff
+ defaultoverlap     allm2 metal2 allactivenonfet active 20.8
+ defaultsideoverlap allm2 metal2 allactivenonfet active 39.54
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 24.50
+ defaultsideoverlap allm2 metal2 allpolynonres active 41.22
+ defaultsideoverlap *poly active allm2 metal2 11.17
+
+#metal2->locali
+ defaultoverlap     allm2 metal2 allli locali 37.56
+ defaultsideoverlap allm2 metal2 allli locali 46.28
+ defaultsideoverlap allli locali allm2 metal2 21.74
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 133.86
+ defaultsideoverlap allm2 metal2 allm1 metal1 67.05
+ defaultsideoverlap allm1 metal1 allm2 metal2 48.19
+
+
+#metal3
+ defaultsidewall    allm3 metal3     56.2
+
+ defaultareacap     allm3 metal3 12.37
+ defaultperimeter   allm3 metal3 40.99
+ defaultoverlap     allm3 metal3 nwell,pwell well 12.37
+ defaultsideoverlap allm3 metal3 nwell,pwell well 40.99
+
+#metal3->diff
+ defaultoverlap     allm3 metal3 allactive active 14.2
+ defaultsideoverlap allm3 metal3 allactive active 42.25
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 16.06
+ defaultsideoverlap allm3 metal3 allpolynonres active 43.53
+ defaultsideoverlap *poly active allm3 metal3 9.18
+
+#metal3->locali
+ defaultoverlap     allm3 metal3 allli locali 20.79
+ defaultsideoverlap allm3 metal3 allli locali 46.71
+ defaultsideoverlap allli locali allm3 metal3 15.08
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 34.54
+ defaultsideoverlap allm3 metal3 allm1 metal1 54.81
+ defaultsideoverlap allm1 metal1 allm3 metal3 26.68
+
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 86.19
+ defaultsideoverlap allm3 metal3 allm2 metal2 69.85
+ defaultsideoverlap allm2 metal2 allm3 metal3 44.43
+
+#metal4
+ defaultsidewall    allm4 metal4 59.0
+ defaultareacap     allm4 metal4 8.42
+ defaultperimeter   allm4 metal4 36.68
+ defaultoverlap     allm4 metal4 nwell,pwell well 8.42
+ defaultsideoverlap allm4 metal4 nwell,pwell well 36.68
+
+#metal4->diff
+ defaultoverlap     allm4 metal4 allactivenonfet active 9.41
+ defaultsideoverlap allm4 metal4 allactivenonfet active 37.57
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 10.01
+ defaultsideoverlap allm4 metal4 allpolynonres active 38.11
+ defaultsideoverlap *poly active allm4 metal4 6.35
+
+#metal4->locali
+ defaultoverlap     allm4 metal4 allli locali 11.67
+ defaultsideoverlap allm4 metal4 allli locali 39.71
+ defaultsideoverlap allli locali allm4 metal4 10.14
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 15.03
+ defaultsideoverlap allm4 metal4 allm1 metal1 42.56
+ defaultsideoverlap allm1 metal1 allm4 metal4 16.42
+
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 20.33
+ defaultsideoverlap allm4 metal4 allm2 metal2 46.38
+ defaultsideoverlap allm2 metal2 allm4 metal4 22.33
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 84.03
+ defaultsideoverlap allm4 metal4 allm3 metal3 70.52
+ defaultsideoverlap allm3 metal3 allm4 metal4 42.64
+
+#metal5
+ defaultsidewall    allm5 metal5 95.1
+ defaultareacap     allm5 metal5 6.32
+ defaultperimeter   allm5 metal5 38.85
+ defaultoverlap     allm5 metal5 nwell,pwell well  6.32
+ defaultsideoverlap allm5 metal5 nwell,pwell well  38.85
+
+#metal5->diff
+ defaultoverlap     allm5 metal5 allactivenonfet active 6.88
+ defaultsideoverlap allm5 metal5 allactivenonfet active 39.52
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 7.21
+ defaultsideoverlap allm5 metal5 allpolynonres active 39.91
+ defaultsideoverlap *poly active allm5 metal5 6.49
+
+#metal5->locali
+ defaultoverlap     allm5 metal5 allli locali 8.03
+ defaultsideoverlap allm5 metal5 allli locali 41.15
+ defaultsideoverlap allli locali allm5 metal5 7.64
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 9.48
+ defaultsideoverlap allm5 metal5 allm1 metal1 43.19
+ defaultsideoverlap allm1 metal1 allm5 metal5 12.02
+
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 11.34
+ defaultsideoverlap allm5 metal5 allm2 metal2 45.59
+ defaultsideoverlap allm2 metal2 allm5 metal5 15.69
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 19.63
+ defaultsideoverlap allm5 metal5 allm3 metal3 54.15
+ defaultsideoverlap allm3 metal3 allm5 metal5 27.84
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 68.33
+ defaultsideoverlap allm5 metal5 allm4 metal4 82.82
+ defaultsideoverlap allm4 metal4 allm5 metal5 46.98
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values for minimum corner
+#-------------------------------------------------------------------------
+
+variants (hrlc),(lrlc)
+# Minimum corner capacitances
+
+#deep n-well
+defaultareacap     dnwell dwell 120
+
+#p-well
+defaultoverlap     pwell well dnwell dwell 120
+
+#n-well
+# NOTE:  This value not found in PEX files
+defaultareacap     nwell well dnwell dwell 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  80.4
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active 17.0
+ defaultareacap     *poly active 80.4
+ defaultperimeter   *poly active 48.83
+ defaultsideoverlap *poly active nwell,pwell well  48.83
+
+#locali
+ defaultsidewall    allli locali 26.7
+ defaultareacap     allli locali 29.3
+ defaultperimeter   allli locali 35.69
+ defaultoverlap     allli locali nwell,pwell well  29.3
+ defaultsideoverlap allli locali nwell,pwell well  35.69
+
+#locali->diff
+ defaultoverlap     allli locali allactivenonfet active 45.3
+ defaultsideoverlap allli locali allactivenonfet active 39.59
+
+#locali->poly
+ defaultoverlap     allli locali allpolynonres active 64.5
+ defaultsideoverlap allli locali allpolynonres active 43.75
+ defaultsideoverlap *poly active allli locali 21.21
+
+#metal1
+ defaultsidewall    allm1 metal1 35.6
+ defaultareacap     allm1 metal1 20.2
+ defaultperimeter   allm1 metal1 34.41
+ defaultoverlap     allm1 metal1 nwell,pwell well  20.2
+ defaultsideoverlap allm1 metal1 nwell,pwell well  34.41
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 26.7
+ defaultsideoverlap allm1 metal1 allactivenonfet active 37.22
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 32.3
+ defaultsideoverlap allm1 metal1 allpolynonres active 40.34
+ defaultsideoverlap *poly active allm1 metal1 14.41
+
+#metal1->locali
+ defaultoverlap     allm1 metal1 allli locali 77.2
+ defaultsideoverlap allm1 metal1 allli locali 49.46
+ defaultsideoverlap allli locali allm1 metal1 28.84
+
+#metal2
+ defaultsidewall    allm2 metal2      37.6
+
+ defaultareacap     allm2 metal2 14.0
+ defaultperimeter   allm2 metal2 32.60
+ defaultoverlap     allm2 metal2 nwell,pwell well 14.0
+ defaultsideoverlap allm2 metal2 nwell,pwell well 32.60
+
+#metal2->diff
+ defaultoverlap     allm2 metal2 allactivenonfet active 16.8
+ defaultsideoverlap allm2 metal2 allactivenonfet active 34.16
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 18.9
+ defaultsideoverlap allm2 metal2 allpolynonres active 34.46
+ defaultsideoverlap *poly active allm2 metal2 9.34
+
+#metal2->locali
+ defaultoverlap     allm2 metal2 allli locali 28.6
+ defaultsideoverlap allm2 metal2 allli locali 39.67
+ defaultsideoverlap allli locali allm2 metal2 18.63
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 80.4
+ defaultsideoverlap allm2 metal2 allm1 metal1 53.85
+ defaultsideoverlap allm1 metal1 allm2 metal2 38.70
+
+
+#metal3
+ defaultsidewall    allm3 metal3     52.0
+
+ defaultareacap     allm3 metal3 10.2
+ defaultperimeter   allm3 metal3 36.05
+ defaultoverlap     allm3 metal3 nwell,pwell well 10.2
+ defaultsideoverlap allm3 metal3 nwell,pwell well 36.05
+
+#metal3->diff
+ defaultoverlap     allm3 metal3 allactive active 11.7
+ defaultsideoverlap allm3 metal3 allactive active 37.59
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 12.6
+ defaultsideoverlap allm3 metal3 allpolynonres active 38.28
+ defaultsideoverlap *poly active allm3 metal3 8.07
+
+#metal3->locali
+ defaultoverlap     allm3 metal3 allli locali 16.3
+ defaultsideoverlap allm3 metal3 allli locali 41.75
+ defaultsideoverlap allli locali allm3 metal3 13.48
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 25.8
+ defaultsideoverlap allm3 metal3 allm1 metal1 48.82
+ defaultsideoverlap allm1 metal1 allm3 metal3 23.76
+
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 59.5
+ defaultsideoverlap allm3 metal3 allm2 metal2 61.18
+ defaultsideoverlap allm2 metal2 allm3 metal3 38.92
+
+#metal4
+ defaultsidewall    allm4 metal4 53.7
+ defaultareacap     allm4 metal4 7.28
+ defaultperimeter   allm4 metal4 32.39
+ defaultoverlap     allm4 metal4 nwell,pwell well 7.28
+ defaultsideoverlap allm4 metal4 nwell,pwell well 32.39
+
+#metal4->diff
+ defaultoverlap     allm4 metal4 allactivenonfet active 7.98
+ defaultsideoverlap allm4 metal4 allactivenonfet active 33.54
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 8.42
+ defaultsideoverlap allm4 metal4 allpolynonres active 33.59
+ defaultsideoverlap *poly active allm4 metal4 5.60
+
+#metal4->locali
+ defaultoverlap     allm4 metal4 allli locali 9.92
+ defaultsideoverlap allm4 metal4 allli locali 35.49
+ defaultsideoverlap allli locali allm4 metal4 9.06
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 12.8
+ defaultsideoverlap allm4 metal4 allm1 metal1 38.29
+ defaultsideoverlap allm1 metal1 allm4 metal4 14.77
+
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 17.8
+ defaultsideoverlap allm4 metal4 allm2 metal2 42.08
+ defaultsideoverlap allm2 metal2 allm4 metal4 20.26
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 57.6
+ defaultsideoverlap allm4 metal4 allm3 metal3 59.42
+ defaultsideoverlap allm3 metal3 allm4 metal4 35.93
+
+#metal5
+ defaultsidewall    allm5 metal5 81.5
+ defaultareacap     allm5 metal5 5.56
+ defaultperimeter   allm5 metal5 34.65
+ defaultoverlap     allm5 metal5 nwell,pwell well  5.56
+ defaultsideoverlap allm5 metal5 nwell,pwell well  34.65
+
+#metal5->diff
+ defaultoverlap     allm5 metal5 allactivenonfet active 5.96
+ defaultsideoverlap allm5 metal5 allactivenonfet active 35.55
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 6.2
+ defaultsideoverlap allm5 metal5 allpolynonres active 35.59
+ defaultsideoverlap *poly active allm5 metal5 5.79
+
+#metal5->locali
+ defaultoverlap     allm5 metal5 allli locali 6.97
+ defaultsideoverlap allm5 metal5 allli locali 37.24
+ defaultsideoverlap allli locali allm5 metal5 6.91
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 8.26
+ defaultsideoverlap allm5 metal5 allm1 metal1 39.30
+ defaultsideoverlap allm1 metal1 allm5 metal5 10.94
+
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 10.1
+ defaultsideoverlap allm5 metal5 allm2 metal2 41.75
+ defaultsideoverlap allm2 metal2 allm5 metal5 14.37
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 16.7
+ defaultsideoverlap allm5 metal5 allm3 metal3 48.75
+ defaultsideoverlap allm3 metal3 allm5 metal5 25.06
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 48.7
+ defaultsideoverlap allm5 metal5 allm4 metal4 70.26
+ defaultsideoverlap allm4 metal4 allm5 metal5 39.86
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values for maximum corner
+#-------------------------------------------------------------------------
+
+variants (hrhc),(lrhc)
+# Maximum corner capacitances
+
+#deep n-well
+defaultareacap     dnwell dwell 120
+
+#p-well
+defaultoverlap     pwell well dnwell dwell 120
+
+#n-well
+# NOTE:  This value not found in PEX files
+defaultareacap     nwell well dnwell dwell 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  106
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active 17.0
+ defaultareacap     *poly active 155.0
+ defaultperimeter   *poly active 64.82
+ defaultsideoverlap *poly active nwell,pwell well  64.82
+
+#locali
+ defaultsidewall    allli locali 28.7
+ defaultareacap     allli locali 49.7
+ defaultperimeter   allli locali 47.02
+ defaultoverlap     allli locali nwell,pwell well  49.7
+ defaultsideoverlap allli locali nwell,pwell well  47.02
+
+#locali->diff
+ defaultoverlap     allli locali allactivenonfet active 70.9
+ defaultsideoverlap allli locali allactivenonfet active 49.94
+
+#locali->poly
+ defaultoverlap     allli locali allpolynonres active 174.0
+ defaultsideoverlap allli locali allpolynonres active 66.60
+ defaultsideoverlap *poly active allli locali 32.29
+
+#metal1
+ defaultsidewall    allm1 metal1 37.6
+ defaultareacap     allm1 metal1 35.7
+ defaultperimeter   allm1 metal1 49.59
+ defaultoverlap     allm1 metal1 nwell,pwell well  35.7
+ defaultsideoverlap allm1 metal1 nwell,pwell well  49.59
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 45.4
+ defaultsideoverlap allm1 metal1 allactivenonfet active 51.17
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 73.2
+ defaultsideoverlap allm1 metal1 allpolynonres active 59.78
+ defaultsideoverlap *poly active allm1 metal1 21.36
+
+#metal1->locali
+ defaultoverlap     allm1 metal1 allli locali 215.0
+ defaultsideoverlap allm1 metal1 allli locali 80.12
+ defaultsideoverlap allli locali allm1 metal1 46.73
+
+#metal2
+ defaultsidewall    allm2 metal2      40.2
+
+ defaultareacap     allm2 metal2 23.5
+ defaultperimeter   allm2 metal2 46.03
+ defaultoverlap     allm2 metal2 nwell,pwell well 23.5
+ defaultsideoverlap allm2 metal2 nwell,pwell well 46.03
+
+#metal2->diff
+ defaultoverlap     allm2 metal2 allactivenonfet active 27.4
+ defaultsideoverlap allm2 metal2 allactivenonfet active 47.45
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 35.5
+ defaultsideoverlap allm2 metal2 allpolynonres active 51.29
+ defaultsideoverlap *poly active allm2 metal2 13.90
+
+#metal2->locali
+ defaultoverlap     allm2 metal2 allli locali 52.3
+ defaultsideoverlap allm2 metal2 allli locali 55.56
+ defaultsideoverlap allli locali allm2 metal2 26.10
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 313.0
+ defaultsideoverlap allm2 metal2 allm1 metal1 102.37
+ defaultsideoverlap allm1 metal1 allm2 metal2 73.576
+
+
+#metal3
+ defaultsidewall    allm3 metal3     60.6
+
+ defaultareacap     allm3 metal3 16.3
+ defaultperimeter   allm3 metal3 47.38
+ defaultoverlap     allm3 metal3 nwell,pwell well 16.3
+ defaultsideoverlap allm3 metal3 nwell,pwell well 47.38
+
+#metal3->diff
+ defaultoverlap     allm3 metal3 allactive active 18.1
+ defaultsideoverlap allm3 metal3 allactive active 48.19
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 21.3
+ defaultsideoverlap allm3 metal3 allpolynonres active 50.44
+ defaultsideoverlap *poly active allm3 metal3 10.64
+
+#metal3->locali
+ defaultoverlap     allm3 metal3 allli locali 26.3 
+ defaultsideoverlap allm3 metal3 allli locali 53.29
+ defaultsideoverlap allli locali allm3 metal3 17.20
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 45.2
+ defaultsideoverlap allm3 metal3 allm1 metal1 62.88
+ defaultsideoverlap allm1 metal1 allm3 metal3 30.61
+
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 131.0
+ defaultsideoverlap allm3 metal3 allm2 metal2 82.67
+ defaultsideoverlap allm2 metal2 allm3 metal3 52.59
+
+#metal4
+ defaultsidewall    allm4 metal4 65.4
+ defaultareacap     allm4 metal4 10.7
+ defaultperimeter   allm4 metal4 42.40
+ defaultoverlap     allm4 metal4 nwell,pwell well 10.7
+ defaultsideoverlap allm4 metal4 nwell,pwell well 42.40
+
+#metal4->diff
+ defaultoverlap     allm4 metal4 allactivenonfet active 11.4
+ defaultsideoverlap allm4 metal4 allactivenonfet active 43.0
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 12.6
+ defaultsideoverlap allm4 metal4 allpolynonres active 43.99
+ defaultsideoverlap *poly active allm4 metal4 7.33
+
+#metal4->locali
+ defaultoverlap     allm4 metal4 allli locali 14.3
+ defaultsideoverlap allm4 metal4 allli locali 45.09
+ defaultsideoverlap allli locali allm4 metal4 11.51
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 18.5
+ defaultsideoverlap allm4 metal4 allm1 metal1 48.07
+ defaultsideoverlap allm1 metal1 allm4 metal4 18.55
+
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 25.2
+ defaultsideoverlap allm4 metal4 allm2 metal2 51.98
+ defaultsideoverlap allm2 metal2 allm4 metal4 25.03
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 191.0
+ defaultsideoverlap allm4 metal4 allm3 metal3 92.12
+ defaultsideoverlap allm3 metal3 allm4 metal4 55.70
+
+#metal5
+ defaultsidewall    allm5 metal5 118.7
+ defaultareacap     allm5 metal5 7.76
+ defaultperimeter   allm5 metal5 44.91
+ defaultoverlap     allm5 metal5 nwell,pwell well  7.76
+ defaultsideoverlap allm5 metal5 nwell,pwell well  44.91
+
+#metal5->diff
+ defaultoverlap     allm5 metal5 allactivenonfet active 8.14
+ defaultsideoverlap allm5 metal5 allactivenonfet active 45.47
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 8.74
+ defaultsideoverlap allm5 metal5 allpolynonres active 46.31
+ defaultsideoverlap *poly active allm5 metal5 7.53
+
+#metal5->locali
+ defaultoverlap     allm5 metal5 allli locali 9.48
+ defaultsideoverlap allm5 metal5 allli locali 47.09
+ defaultsideoverlap allli locali allm5 metal5 8.74
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 11.2
+ defaultsideoverlap allm5 metal5 allm1 metal1 49.44
+ defaultsideoverlap allm1 metal1 allm5 metal5 13.76
+
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 13.3
+ defaultsideoverlap allm5 metal5 allm2 metal2 51.69
+ defaultsideoverlap allm2 metal2 allm5 metal5 17.79
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 24.6
+ defaultsideoverlap allm5 metal5 allm3 metal3 63.24
+ defaultsideoverlap allm3 metal3 allm5 metal5 32.51
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 115.0
+ defaultsideoverlap allm5 metal5 allm4 metal4 109.69
+ defaultsideoverlap allm4 metal4 allm5 metal5 62.22
+
+#---------------------------------------------------------
+
+variants *
+
+
+# Devices:  Base models (not subcircuit wrappers)
+
+variants (),(si),(hrhc),(lrhc),(hrlc),(lrlc)
+
+ device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
+	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
+	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
+	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
+	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
+	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+
+ device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
+	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_nfet_latch npd \
+	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_nfet_latch npd \
+	*ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__special_nfet_pass npass \
+	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
+	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
+	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device subcircuit sky130_fd_pr__cap_var_lvt varactor \
+	*nndiff pwell,space/w error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
+	*nndiff pwell,space/w error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var mvvaractor \
+	*mvnndiff pwell,space/w error l=l w=w
+
+ # Bipolars
+ device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \
+	error +npn1p00
+ device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \
+	error +npn2p00
+ device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
+ device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \
+	pwell,space/w +pnp0p68
+ device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \
+	pwell,space/w +pnp3p40
+ device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
+ device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \
+	dnwell space/w error +npn11p0
+ device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
+
+ # Ignore the extended-drain FET geometry that forms part of the high-voltage
+ # bipolar devices.
+ device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
+ device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
+
+ # Extended drain devices (must appear before the regular devices)
+ device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
+	dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
+ device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
+	dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
+ device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
+	pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
+
+ device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
+	*mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
+	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
+	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
+	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
+	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+ device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
+	*mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
+	a1=as p1=ps a2=ad p2=pd
+
+ device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
+ device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
+ device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
+ device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
+ device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
+ device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
+ device ndiode   sky130_fd_pr__model__parasitic__diode_ps2dn \
+	photo pwell,space/w error a=area
+
+ device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
+	xpc pwell,space/w error +res0p35 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_0p69  xhrpoly \
+	xpc pwell,space/w error +res0p69 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_1p41  xhrpoly \
+	xpc pwell,space/w error +res1p41 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_2p85  xhrpoly \
+	xpc pwell,space/w error +res2p85 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po_5p73  xhrpoly \
+	xpc pwell,space/w error +res5p73 l=l
+ device rsubcircuit sky130_fd_pr__res_high_po	    xhrpoly \
+	xpc pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35  uhrpoly \
+	xpc pwell,space/w error +res0p35 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69  uhrpoly \
+	xpc pwell,space/w error +res0p69 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41  uhrpoly \
+	xpc pwell,space/w error +res1p41 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85  uhrpoly \
+	xpc pwell,space/w error +res2p85 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73  uhrpoly \
+	xpc pwell,space/w error +res5p73 l=l
+ device rsubcircuit sky130_fd_pr__res_xhigh_po	     uhrpoly \
+	xpc pwell,space/w error l=l w=w
+
+ device rsubcircuit sky130_fd_pr__res_generic_nd     ndiffres \
+	*ndiff pwell,space/w  error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_pd     pdiffres \
+	*pdiff nwell    error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_iso_pw   rpw \
+        pwell dnwell error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_nd__hv  mvndiffres \
+	*mvndiff pwell,space/w error l=l w=w
+ device rsubcircuit sky130_fd_pr__res_generic_pd__hv  mvpdiffres \
+	*mvpdiff nwell  error l=l w=w
+
+ device resistor sky130_fd_pr__res_generic_po rmp *poly
+ device resistor sky130_fd_pr__res_generic_po mrp1 *poly
+
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area p=pj
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area p=pj
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area p=pj
+ device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area p=pj
+
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area p=pj
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area p=pj
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area p=pj
+ device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area p=pj
+
+
+ device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap  *m3 w=w l=l
+ device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
+
+ variants (orig)
+
+ device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell 
+ device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell 
+ device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell 
+ device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell 
+ device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell 
+ device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_pass  npass ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
+	pwell,space/w
+
+ # Note that corenvar, corepvar are not considered devices, and extract as
+ # parasitic capacitance instead (but cap values need to be added).
+
+ # Extended drain devices (must appear before the regular devices)
+ device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
+	dnwell pwell,space/w error
+ device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
+	dnwell pwell,space/w error
+ device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
+	pwell,space/w nwell error
+
+ device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell 
+ device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell 
+ device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
+ device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
+
+ # These devices always extract as subcircuits
+ device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
+ device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
+
+ device resistor sky130_fd_pr__res_generic_po rmp     *poly
+ device resistor sky130_fd_pr__res_generic_l1 rli1    *li,coreli
+ device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
+ device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
+ device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
+ device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
+ device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
+
+ device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
+ device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
+ device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
+ device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
+ device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
+ device resistor sky130_fd_pr__res_high_po xhrpoly xpc 
+ device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
+ device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
+ device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
+ device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
+ device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
+ device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc 
+ device resistor sky130_fd_pr__res_generic_po  mrp1     *poly 
+ device resistor sky130_fd_pr__res_generic_nd  ndiffres *ndiff 
+ device resistor sky130_fd_pr__res_generic_pd  pdiffres *pdiff 
+ device resistor mrdn_hv   mvndiffres *mvndiff 
+ device resistor mrdp_hv   mvpdiffres *mvpdiff 
+ device resistor sky130_fd_pr__res_iso_pw   rpw    pwell
+
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
+ device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
+
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
+ device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
+
+ device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error +npn1p00
+ device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error +npn2p00
+ device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
+ device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w +pnp0p68
+ device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w +pnp3p40
+ device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
+ device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error +npn11p0
+ device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
+
+ device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap  *m3 1
+ device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
+
+end
+
+#-----------------------------------------------------
+# Wiring tool definitions
+#-----------------------------------------------------
+
+wiring
+ # All wiring values are in nanometers
+ scalefactor 10
+
+ contact mcon 170 li 0  0 m1 30 60
+ contact v1  260 m1 0 30 m2  0 30
+ contact v2  280 m2 0 45 m3 25  0
+ contact v3  320 m3 0 30 m4  5  5
+ contact v4 1180 m4 0    m5 120
+
+ contact pc  170  poly 50 80 li 0 80
+ contact pdc 170 pdiff 40 60 li 0 80
+ contact ndc 170 ndiff 40 60 li 0 80
+ contact psc 170   psd 40 60 li 0 80
+ contact nsc 170   nsd 40 60 li 0 80
+
+end
+
+#-----------------------------------------------------
+# Plain old router. . . 
+#-----------------------------------------------------
+
+router
+end
+
+#------------------------------------------------------------
+# Plowing (restored in magic 8.2, need to fill this section)
+#------------------------------------------------------------
+
+plowing
+end
+
+#-----------------------------------------------------------------
+# No special plot layers defined (use default PNM color choices)
+#-----------------------------------------------------------------
+
+plot
+  style pnm
+     default
+     draw fillblock no_color_at_all
+     draw fillblock4 no_color_at_all
+     draw fomfill no_color_at_all
+     draw polyfill no_color_at_all
+     draw m1fill no_color_at_all
+     draw m2fill no_color_at_all
+     draw m3fill no_color_at_all
+     draw m4fill no_color_at_all
+     draw m5fill no_color_at_all
+     draw nwell cwell
+end
+

mag/sky130A_setup.tcl

diff --git a/mag/sky130A_setup.tcl b/mag/sky130A_setup.tcl
new file mode 100755
index 0000000..34dda34
--- /dev/null
+++ b/mag/sky130A_setup.tcl
@@ -0,0 +1,455 @@
+#---------------------------------------------------------------
+# Setup file for netgen LVS
+# SkyWater sky130A
+#---------------------------------------------------------------
+permute default
+property default
+property parallel none
+
+# Allow override of default #columns in the output format.
+catch {format $env(NETGEN_COLUMNS)}
+
+#---------------------------------------------------------------
+# For the following, get the cell lists from
+# circuit1 and circuit2.
+#---------------------------------------------------------------
+
+set cells1 [cells list -all -circuit1]
+set cells2 [cells list -all -circuit2]
+
+# NOTE:  In accordance with the LVS manager GUI, the schematic is
+# always circuit2, so some items like property "par1" only need to
+# be specified for circuit2.
+
+#-------------------------------------------
+# Resistors (except metal)
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__res_iso_pw
+lappend devices sky130_fd_pr__res_high_po_0p35
+lappend devices sky130_fd_pr__res_high_po_0p69
+lappend devices sky130_fd_pr__res_high_po_1p41
+lappend devices sky130_fd_pr__res_high_po_2p85
+lappend devices sky130_fd_pr__res_high_po_5p73
+lappend devices sky130_fd_pr__res_high_po
+lappend devices sky130_fd_pr__res_xhigh_po_0p35
+lappend devices sky130_fd_pr__res_xhigh_po_0p69
+lappend devices sky130_fd_pr__res_xhigh_po_1p41
+lappend devices sky130_fd_pr__res_xhigh_po_2p85
+lappend devices sky130_fd_pr__res_xhigh_po_5p73
+lappend devices sky130_fd_pr__res_xhigh_po
+lappend devices sky130_fd_pr__res_generic_nd
+lappend devices sky130_fd_pr__res_generic_pd
+lappend devices sky130_fd_pr__res_generic_nd__hv
+lappend devices sky130_fd_pr__res_generic_pd__hv
+lappend devices mrdn_hv mrdp_hv
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	permute "-circuit1 $dev" 1 2
+	property "-circuit1 $dev" series enable
+	property "-circuit1 $dev" series {w critical}
+	property "-circuit1 $dev" series {l add}
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" parallel {value par}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit1 $dev" delete mult
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	permute "-circuit2 $dev" 1 2
+	property "-circuit2 $dev" series enable
+	property "-circuit2 $dev" series {w critical}
+	property "-circuit2 $dev" series {l add}
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" parallel {l critical}
+	property "-circuit2 $dev" parallel {w add}
+	property "-circuit2 $dev" parallel {value par}
+	property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete mult
+    }
+}
+
+#-------------------------------------------
+# MRM (metal) resistors and poly resistor
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__res_generic_po
+lappend devices sky130_fd_pr__res_generic_l1
+lappend devices sky130_fd_pr__res_generic_m1
+lappend devices sky130_fd_pr__res_generic_m2
+lappend devices sky130_fd_pr__res_generic_m3
+lappend devices sky130_fd_pr__res_generic_m4
+lappend devices sky130_fd_pr__res_generic_m5
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	permute "-circuit1 $dev" end_a end_b
+	property "-circuit1 $dev" series enable
+	property "-circuit1 $dev" series {w critical}
+	property "-circuit1 $dev" series {l add}
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" parallel {value par}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit1 $dev" delete mult
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	permute "-circuit2 $dev" end_a end_b
+	property "-circuit2 $dev" series enable
+	property "-circuit2 $dev" series {w critical}
+	property "-circuit2 $dev" series {l add}
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" parallel {l critical}
+	property "-circuit2 $dev" parallel {w add}
+	property "-circuit2 $dev" parallel {value par}
+	property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete mult
+    }
+}
+
+#-------------------------------------------
+# (MOS) transistors
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__nfet_01v8
+lappend devices sky130_fd_pr__nfet_01v8_lvt
+lappend devices sky130_fd_bs_flash__special_sonosfet_star
+lappend devices sky130_fd_pr__nfet_g5v0d10v5
+lappend devices sky130_fd_pr__nfet_05v0_nvt
+lappend devices sky130_fd_pr__pfet_01v8
+lappend devices sky130_fd_pr__pfet_01v8_lvt
+lappend devices sky130_fd_pr__pfet_01v8_mvt
+lappend devices sky130_fd_pr__pfet_01v8_hvt
+lappend devices sky130_fd_pr__pfet_g5v0d10v5
+lappend devices sky130_fd_pr__special_pfet_pass
+lappend devices sky130_fd_pr__special_nfet_pass
+lappend devices sky130_fd_pr__special_nfet_latch
+lappend devices sky130_fd_pr__cap_var_lvt
+lappend devices sky130_fd_pr__cap_var_hvt
+lappend devices sky130_fd_pr__cap_var
+lappend devices sky130_fd_pr__nfet_20v0_nvt
+lappend devices sky130_fd_pr__nfet_20v0
+lappend devices sky130_fd_pr__pfet_20v0
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	permute "-circuit1 $dev" 1 3
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" tolerance {w 0.01} {l 0.01}
+	# Ignore these properties
+	property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	permute "-circuit2 $dev" 1 3
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" parallel {l critical}
+	property "-circuit2 $dev" parallel {w add}
+	property "-circuit2 $dev" tolerance {w 0.01} {l 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+    }
+}
+
+#---------------------------------------------------------------------
+# (MOS) ESD transistors.  Note that the ESD transistors have a flanged
+# gate.  Magic disagrees slightly on how to interpret the width of the
+# devices, so the tolerance is increased to 7% to cover the difference
+#---------------------------------------------------------------------
+
+lappend devices sky130_fd_pr__esd_nfet_g5v0d10v5
+lappend devices sky130_fd_pr__esd_pfet_g5v0d10v5
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	permute "-circuit1 $dev" 1 3
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {l critical}
+	property "-circuit1 $dev" parallel {w add}
+	property "-circuit1 $dev" tolerance {w 0.07} {l 0.01}
+	# Ignore these properties
+	property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	permute "-circuit2 $dev" 1 3
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" parallel {l critical}
+	property "-circuit2 $dev" parallel {w add}
+	property "-circuit2 $dev" tolerance {w 0.07} {l 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography
+    }
+}
+
+#-------------------------------------------
+# diodes
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__diode_pw2nd_05v5
+lappend devices sky130_fd_pr__diode_pw2nd_05v5_lvt
+lappend devices sky130_fd_pr__diode_pw2nd_05v5_nvt
+lappend devices sky130_fd_pr__diode_pd2nw_05v5
+lappend devices sky130_fd_pr__diode_pd2nw_05v5_lvt
+lappend devices sky130_fd_pr__diode_pd2nw_05v5_hvt
+lappend devices sky130_fd_pr__diode_pw2nd_11v0
+lappend devices sky130_fd_pr__diode_pd2nw_11v0
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {area add}
+	property "-circuit1 $dev" parallel {value add}
+	property "-circuit1 $dev" tolerance {area 0.02}
+	# Ignore these properties
+	property "-circuit1 $dev" delete mult perim
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" parallel {area add}
+	property "-circuit2 $dev" parallel {value add}
+	property "-circuit2 $dev" tolerance {area 0.02}
+	# Ignore these properties
+	property "-circuit2 $dev" delete mult perim
+    }
+}
+
+#-------------------------------------------
+# capacitors
+# MiM capacitors
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__cap_mim_m3_1
+lappend devices sky130_fd_pr__cap_mim_m3_2
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" parallel {area add}
+	property "-circuit1 $dev" parallel {value add}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit1 $dev" delete mult perim mf
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" parallel {area add}
+	property "-circuit2 $dev" parallel {value add}
+	property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete mult perim mf
+    }
+}
+
+#-------------------------------------------
+# Fixed-layout devices
+# bipolar transistors,
+# VPP capacitors
+#-------------------------------------------
+
+set devices {}
+lappend devices sky130_fd_pr__npn_05v5_W1p00L1p00
+lappend devices sky130_fd_pr__npn_05v5_W1p00L2p00
+lappend devices sky130_fd_pr__pnp_05v5_W0p68L0p68
+lappend devices sky130_fd_pr__pnp_05v5_W3p40L3p40
+lappend devices sky130_fd_pr__npn_05v5
+lappend devices sky130_fd_pr__pnp_05v5
+lappend devices sky130_fd_pr__npn_11v0
+
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m4_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_pom4_shield
+lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_lim4_shield
+lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_polym4_shield
+lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_lim5_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_li_shield
+lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_shield
+lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_li_shield
+lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_m3_shield
+lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_li_shield
+lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_shield
+lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_li_shield
+lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_shield
+lappend devices sky130_fd_pr__ind_04_01
+lappend devices sky130_fd_pr__ind_04_02
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	# Ignore these properties
+	property "-circuit1 $dev" delete mult
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	# Ignore these properties
+	property "-circuit2 $dev" delete mult
+    }
+}
+
+#---------------------------------------------------------------
+# Schematic cells which are not extractable
+#---------------------------------------------------------------
+
+set devices {sky130_fd_io__condiode sky130_fd_io__tap_1}
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+    	ignore class "-circuit1 $dev"
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	ignore class "-circuit2 $dev"
+    }
+}
+
+#---------------------------------------------------------------
+# Digital cells (ignore decap, fill, and tap cells)
+# Make a separate list for each supported library
+#---------------------------------------------------------------
+# e.g., ignore class "-circuit2 sky130_fc_sc_hd__decap_3"
+#---------------------------------------------------------------
+
+if { [info exist ::env(MAGIC_EXT_USE_GDS)] && $::env(MAGIC_EXT_USE_GDS) } {
+    foreach cell $cells1 {
+#        if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+#            ignore class "-circuit1 $cell"
+#        }
+        if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+            ignore class "-circuit1 $cell"
+        }
+        if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+            ignore class "-circuit1 $cell"
+        }
+        if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+            ignore class "-circuit1 $cell"
+        }
+    }
+    foreach cell $cells2 {
+#        if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+#            ignore class "-circuit2 $cell"
+#        }
+        if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+            ignore class "-circuit2 $cell"
+        }
+        if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+            ignore class "-circuit2 $cell"
+        }
+        if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+            ignore class "-circuit2 $cell"
+        }
+    }
+}
+
+#---------------------------------------------------------------
+# Allow the fill, decap, etc., cells to be parallelized
+#---------------------------------------------------------------
+
+foreach cell $cells1 {
+    if {[regexp {sky130_ef_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+    if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+}
+foreach cell $cells2 {
+    if {[regexp {sky130_ef_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+    if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+}
+
+#---------------------------------------------------------------
+# Handle cells captured from Electric
+#
+# Find cells of the form "<library>__<cellname>" in the netlist
+# from Electric where the extracted layout netlist has only
+# "<cellname>".  Cross-check by ensuring that the full name
+# "<library>__<cellname>" does not exist in both cells, and that
+# the truncated name "<cellname>" does not exist in both cells.
+#---------------------------------------------------------------
+# e.g., hydra_spi_controller__hydra_spi_controller
+#---------------------------------------------------------------
+
+foreach cell $cells1 {
+    if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+        if {([lsearch $cells2 $cell] < 0) && \
+                ([lsearch $cells2 $cellname] >= 0) && \
+                ([lsearch $cells1 $cellname] < 0)} {
+            equate classes "-circuit1 $cell" "-circuit2 $cellname"
+	    puts stdout "Matching pins of $cell in circuit 1 and $cellname in circuit 2"
+	    equate pins "-circuit1 $cell" "-circuit2 $cellname"
+        }
+    }
+}
+
+foreach cell $cells2 {
+    if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+        if {([lsearch $cells1 $cell] < 0) && \
+                ([lsearch $cells1 $cellname] >= 0) && \
+                ([lsearch $cells2 $cellname] < 0)} {
+            equate classes "-circuit1 $cellname" "-circuit2 $cell"
+	    puts stdout "Matching pins of $cellname in circuit 1 and $cell in circuit 2"
+	    equate pins "-circuit1 $cellname" "-circuit2 $cell"
+        }
+    }
+}
+
+# Match pins on black-box cells if LVS is called with "-blackbox"
+if {[model blackbox]} {
+    foreach cell $cells1 {
+	if {[model "-circuit1 $cell"] == "blackbox"} {
+	    if {[lsearch $cells2 $cell] >= 0} {
+		puts stdout "Matching pins of $cell in circuits 1 and 2"
+		equate pins "-circuit1 $cell" "-circuit2 $cell"
+	    }
+	}
+    }
+}
+
+#---------------------------------------------------------------

mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.ext

diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.ext b/mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.ext
new file mode 100644
index 0000000..df29dd8
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.ext
@@ -0,0 +1,12 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l
+node "c1_n2050_n3000#" 0 0 -2050 -3000 mim 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23226084 19688 0 0 0 0
+node "m3_n2150_n3100#" 3 12546.2 -2150 -3100 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26653800 20998 592896 12544 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "c1_n2050_n3000#" "m3_n2150_n3100#" 56621.5
+device csubckt sky130_fd_pr__cap_mim_m3_1 -2050 -3000 -2049 -2999 w=4000 l=6000 "None" "c1_n2050_n3000#" 19680 0 "m3_n2150_n3100#" 200 0

mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.mag b/mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.mag
new file mode 100644
index 0000000..d6c8ffd
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_4RCNTW.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662404926
+<< metal3 >>
+rect -2150 3072 2149 3100
+rect -2150 -3072 2065 3072
+rect 2129 -3072 2149 3072
+rect -2150 -3100 2149 -3072
+<< via3 >>
+rect 2065 -3072 2129 3072
+<< mimcap >>
+rect -2050 2960 1950 3000
+rect -2050 -2960 -2010 2960
+rect 1910 -2960 1950 2960
+rect -2050 -3000 1950 -2960
+<< mimcapcontact >>
+rect -2010 -2960 1910 2960
+<< metal4 >>
+rect 2049 3072 2145 3088
+rect -2011 2960 1911 2961
+rect -2011 -2960 -2010 2960
+rect 1910 -2960 1911 2960
+rect -2011 -2961 1911 -2960
+rect 2049 -3072 2065 3072
+rect 2129 -3072 2145 3072
+rect 2049 -3088 2145 -3072
+<< properties >>
+string FIXED_BBOX -2150 -3100 2050 3100
+string gencell sky130_fd_pr__cap_mim_m3_1
+string library sky130
+string parameters w 20.0 l 30.0 val 1.219k carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+<< end >>

mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag b/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
deleted file mode 100644
index f3164a4..0000000
--- a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
+++ /dev/null
@@ -1,33 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606502073
-<< metal3 >>
-rect -3136 3072 3136 3100
-rect -3136 -3072 3052 3072
-rect 3116 -3072 3136 3072
-rect -3136 -3100 3136 -3072
-<< via3 >>
-rect 3052 -3072 3116 3072
-<< mimcap >>
-rect -3036 2960 2964 3000
-rect -3036 -2960 2332 2960
-rect 2924 -2960 2964 2960
-rect -3036 -3000 2964 -2960
-<< mimcapcontact >>
-rect 2332 -2960 2924 2960
-<< metal4 >>
-rect 3036 3072 3132 3088
-rect 2331 2960 2925 2961
-rect 2331 -2960 2332 2960
-rect 2924 -2960 2925 2960
-rect 2331 -2961 2925 -2960
-rect 3036 -3072 3052 3072
-rect 3116 -3072 3132 3072
-rect 3036 -3088 3132 -3072
-<< properties >>
-string gencell sky130_fd_pr__cap_mim_m3_1
-string FIXED_BBOX -3136 -3100 3064 3100
-string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov -10
-string library sky130
-<< end >>

mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.ext

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.ext b/mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.ext
new file mode 100644
index 0000000..dfa75ae
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.ext
@@ -0,0 +1,12 @@
+timestamp 1660420676
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_2 w=w l=l
+node "c2_n551_n400#" 0 0 -551 -400 mim2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 436224 2672 0 0
+node "m4_n651_n500#" 0 1441.37 -651 -500 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1302000 4604 320640 2644 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m4_n651_n500#" "c2_n551_n400#" 1938.05
+device csubckt sky130_fd_pr__cap_mim_m3_2 -551 -400 -550 -399 w=600 l=800 "None" "c2_n551_n400#" 2480 0 "m4_n651_n500#" 200 0

mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.mag b/mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.mag
new file mode 100644
index 0000000..57bebe2
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_3ZFDVT.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1660420676
+<< metal4 >>
+rect -651 459 651 500
+rect -651 -459 395 459
+rect 631 -459 651 459
+rect -651 -500 651 -459
+<< via4 >>
+rect 395 -459 631 459
+<< mimcap2 >>
+rect -551 360 49 400
+rect -551 -360 -511 360
+rect 9 -360 49 360
+rect -551 -400 49 -360
+<< mimcap2contact >>
+rect -511 -360 9 360
+<< metal5 >>
+rect 353 459 673 501
+rect -535 360 33 384
+rect -535 -360 -511 360
+rect 9 -360 33 360
+rect -535 -384 33 -360
+rect 353 -459 395 459
+rect 631 -459 673 459
+rect 353 -501 673 -459
+<< properties >>
+string FIXED_BBOX -651 -500 149 500
+string gencell sky130_fd_pr__cap_mim_m3_2
+string library sky130
+string parameters w 3.0 l 4.0 val 26.66 carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+<< end >>

mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.ext

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.ext b/mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.ext
new file mode 100644
index 0000000..4af4836
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.ext
@@ -0,0 +1,12 @@
+timestamp 1660420676
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_2 w=w l=l
+node "c2_n451_n200#" 0 0 -451 -200 mim2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 135424 1472 0 0
+node "m4_n551_n300#" 0 1007.31 -551 -300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 661200 3404 192640 1844 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m4_n551_n300#" "c2_n451_n200#" 882.293
+device csubckt sky130_fd_pr__cap_mim_m3_2 -451 -200 -450 -199 w=400 l=400 "None" "c2_n451_n200#" 1280 0 "m4_n551_n300#" 200 0

mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.mag b/mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.mag
new file mode 100644
index 0000000..f3d23c7
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_FJFAMD.mag
@@ -0,0 +1,37 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1660420676
+<< error_p >>
+rect -435 160 -67 184
+rect -435 -160 -411 160
+rect -435 -184 -67 -160
+<< metal4 >>
+rect -551 259 551 300
+rect -551 -259 295 259
+rect 531 -259 551 259
+rect -551 -300 551 -259
+<< via4 >>
+rect 295 -259 531 259
+<< mimcap2 >>
+rect -451 160 -51 200
+rect -451 -160 -411 160
+rect -91 -160 -51 160
+rect -451 -200 -51 -160
+<< mimcap2contact >>
+rect -411 -160 -91 160
+<< metal5 >>
+rect 253 259 573 301
+rect -435 160 -67 184
+rect -435 -160 -411 160
+rect -91 -160 -67 160
+rect -435 -184 -67 -160
+rect 253 -259 295 259
+rect 531 -259 573 259
+rect 253 -301 573 -259
+<< properties >>
+string FIXED_BBOX -551 -300 49 300
+string gencell sky130_fd_pr__cap_mim_m3_2
+string library sky130
+string parameters w 2.00 l 2.00 val 9.52 carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+<< end >>

mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.ext

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.ext b/mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.ext
new file mode 100644
index 0000000..1f86feb
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.ext
@@ -0,0 +1,12 @@
+timestamp 1660420676
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_2 w=w l=l
+node "c2_n851_n400#" 0 0 -851 -400 mim2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 897024 3872 0 0
+node "m4_n951_n500#" 0 1787.75 -951 -500 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1902000 5804 320640 2644 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m4_n951_n500#" "c2_n851_n400#" 3222.14
+device csubckt sky130_fd_pr__cap_mim_m3_2 -851 -400 -850 -399 w=1200 l=800 "None" "c2_n851_n400#" 3680 0 "m4_n951_n500#" 200 0

mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.mag b/mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.mag
new file mode 100644
index 0000000..6834609
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_VCH7EQ.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1660420676
+<< metal4 >>
+rect -951 459 951 500
+rect -951 -459 695 459
+rect 931 -459 951 459
+rect -951 -500 951 -459
+<< via4 >>
+rect 695 -459 931 459
+<< mimcap2 >>
+rect -851 360 349 400
+rect -851 -360 -811 360
+rect 309 -360 349 360
+rect -851 -400 349 -360
+<< mimcap2contact >>
+rect -811 -360 309 360
+<< metal5 >>
+rect 653 459 973 501
+rect -835 360 333 384
+rect -835 -360 -811 360
+rect 309 -360 333 360
+rect -835 -384 333 -360
+rect 653 -459 695 459
+rect 931 -459 973 459
+rect 653 -501 973 -459
+<< properties >>
+string FIXED_BBOX -951 -500 449 500
+string gencell sky130_fd_pr__cap_mim_m3_2
+string library sky130
+string parameters w 6.0 l 4.0 val 51.8 carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+<< end >>

mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag b/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
deleted file mode 100644
index 88818f6..0000000
--- a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
+++ /dev/null
@@ -1,33 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606502073
-<< metal4 >>
-rect -3179 3059 3179 3100
-rect -3179 -3059 2923 3059
-rect 3159 -3059 3179 3059
-rect -3179 -3100 3179 -3059
-<< via4 >>
-rect 2923 -3059 3159 3059
-<< mimcap2 >>
-rect -3079 2960 2921 3000
-rect -3079 -2960 -3039 2960
-rect 2289 -2960 2921 2960
-rect -3079 -3000 2921 -2960
-<< mimcap2contact >>
-rect -3039 -2960 2289 2960
-<< metal5 >>
-rect 2881 3059 3201 3101
-rect -3063 2960 2313 2984
-rect -3063 -2960 -3039 2960
-rect 2289 -2960 2313 2960
-rect -3063 -2984 2313 -2960
-rect 2881 -3059 2923 3059
-rect 3159 -3059 3201 3059
-rect 2881 -3101 3201 -3059
-<< properties >>
-string gencell sky130_fd_pr__cap_mim_m3_2
-string FIXED_BBOX -3179 -3100 3021 3100
-string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov +90
-string library sky130
-<< end >>

mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.ext

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.ext b/mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.ext
new file mode 100644
index 0000000..c1ccd54
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.ext
@@ -0,0 +1,12 @@
+timestamp 1660521579
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_2 w=w l=l
+node "c2_n451_n200#" 0 0 -451 -200 mim2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 135424 1472 0 0
+node "m4_n551_n300#" 0 1007.31 -551 -300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 661200 3404 192640 1844 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "c2_n451_n200#" "m4_n551_n300#" 882.293
+device csubckt sky130_fd_pr__cap_mim_m3_2 -451 -200 -450 -199 w=400 l=400 "None" "c2_n451_n200#" 1280 0 "m4_n551_n300#" 200 0

mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.mag b/mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.mag
new file mode 100644
index 0000000..286af88
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_WCTBV5.mag
@@ -0,0 +1,37 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1660521579
+<< error_p >>
+rect -435 160 -67 184
+rect -435 -160 -411 160
+rect -435 -184 -67 -160
+<< metal4 >>
+rect -551 259 551 300
+rect -551 -259 295 259
+rect 531 -259 551 259
+rect -551 -300 551 -259
+<< via4 >>
+rect 295 -259 531 259
+<< mimcap2 >>
+rect -451 160 -51 200
+rect -451 -160 -411 160
+rect -91 -160 -51 160
+rect -451 -200 -51 -160
+<< mimcap2contact >>
+rect -411 -160 -91 160
+<< metal5 >>
+rect 253 259 573 301
+rect -435 160 -67 184
+rect -435 -160 -411 160
+rect -91 -160 -67 160
+rect -435 -184 -67 -160
+rect 253 -259 295 259
+rect 531 -259 573 259
+rect 253 -301 573 -259
+<< properties >>
+string FIXED_BBOX -551 -300 49 300
+string gencell sky130_fd_pr__cap_mim_m3_2
+string library sky130
+string parameters w 2.00 l 2.0 val 9.52 carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+<< end >>

mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.ext

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.ext b/mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.ext
new file mode 100644
index 0000000..191ed6f
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.ext
@@ -0,0 +1,12 @@
+timestamp 1660420676
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__cap_mim_m3_2 w=w l=l
+node "c2_n551_n200#" 0 0 -551 -200 mim2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 209024 1872 0 0
+node "m4_n651_n300#" 0 1105.93 -651 -300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 781200 3804 192640 1844 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m4_n651_n300#" "c2_n551_n200#" 1173.66
+device csubckt sky130_fd_pr__cap_mim_m3_2 -551 -200 -550 -199 w=600 l=400 "None" "c2_n551_n200#" 1680 0 "m4_n651_n300#" 200 0

mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.mag

diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.mag b/mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.mag
new file mode 100644
index 0000000..7f6f46e
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_WCTZRP.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1660420676
+<< metal4 >>
+rect -651 259 651 300
+rect -651 -259 395 259
+rect 631 -259 651 259
+rect -651 -300 651 -259
+<< via4 >>
+rect 395 -259 631 259
+<< mimcap2 >>
+rect -551 160 49 200
+rect -551 -160 -511 160
+rect 9 -160 49 160
+rect -551 -200 49 -160
+<< mimcap2contact >>
+rect -511 -160 9 160
+<< metal5 >>
+rect 353 259 673 301
+rect -535 160 33 184
+rect -535 -160 -511 160
+rect 9 -160 33 160
+rect -535 -184 33 -160
+rect 353 -259 395 259
+rect 631 -259 673 259
+rect 353 -301 673 -259
+<< properties >>
+string FIXED_BBOX -651 -300 149 300
+string gencell sky130_fd_pr__cap_mim_m3_2
+string library sky130
+string parameters w 3.0 l 2.0 val 13.9 carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+<< end >>

mag/sky130_fd_pr__nfet_01v8_EDB9KC.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_EDB9KC.mag b/mag/sky130_fd_pr__nfet_01v8_EDB9KC.mag
new file mode 100644
index 0000000..d3d30ad
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_EDB9KC.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1659993752
+<< error_p >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect -29 74 29 80
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect -29 -120 29 -114
+<< pwell >>
+rect -211 -252 211 252
+<< nmos >>
+rect -15 -42 15 42
+<< ndiff >>
+rect -73 30 -15 42
+rect -73 -30 -61 30
+rect -27 -30 -15 30
+rect -73 -42 -15 -30
+rect 15 30 73 42
+rect 15 -30 27 30
+rect 61 -30 73 30
+rect 15 -42 73 -30
+<< ndiffc >>
+rect -61 -30 -27 30
+rect 27 -30 61 30
+<< psubdiff >>
+rect -175 182 -79 216
+rect 79 182 175 216
+rect -175 120 -141 182
+rect 141 120 175 182
+rect -175 -182 -141 -120
+rect 141 -182 175 -120
+rect -175 -216 -79 -182
+rect 79 -216 175 -182
+<< psubdiffcont >>
+rect -79 182 79 216
+rect -175 -120 -141 120
+rect 141 -120 175 120
+rect -79 -216 79 -182
+<< poly >>
+rect -33 114 33 130
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -33 64 33 80
+rect -15 42 15 64
+rect -15 -64 15 -42
+rect -33 -80 33 -64
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -33 -130 33 -114
+<< polycont >>
+rect -17 80 17 114
+rect -17 -114 17 -80
+<< locali >>
+rect -175 182 -79 216
+rect 79 182 175 216
+rect -175 120 -141 182
+rect 141 120 175 182
+rect -33 80 -17 114
+rect 17 80 33 114
+rect -61 30 -27 46
+rect -61 -46 -27 -30
+rect 27 30 61 46
+rect 27 -46 61 -30
+rect -33 -114 -17 -80
+rect 17 -114 33 -80
+rect -175 -182 -141 -120
+rect 141 -182 175 -120
+rect -175 -216 -79 -182
+rect 79 -216 175 -182
+<< viali >>
+rect -17 80 17 114
+rect -61 -30 -27 30
+rect 27 -30 61 30
+rect -17 -114 17 -80
+<< metal1 >>
+rect -29 114 29 120
+rect -29 80 -17 114
+rect 17 80 29 114
+rect -29 74 29 80
+rect -67 30 -21 42
+rect -67 -30 -61 30
+rect -27 -30 -21 30
+rect -67 -42 -21 -30
+rect 21 30 67 42
+rect 21 -30 27 30
+rect 61 -30 67 30
+rect 21 -42 67 -30
+rect -29 -80 29 -74
+rect -29 -114 -17 -80
+rect 17 -114 29 -80
+rect -29 -120 29 -114
+<< properties >>
+string FIXED_BBOX -158 -199 158 199
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.ext
new file mode 100644
index 0000000..51350c0
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.ext
@@ -0,0 +1,15 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 493 126.496 15 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 493 126.677 -73 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n188#" 674 284.464 -33 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16032 956 0 0 4488 400 5336 416 0 0 0 0 0 0 0 0 0 0
+substrate "a_n175_n274#" 0 0 -175 -274 ppd 0 0 0 0 0 0 0 0 0 0 56440 3320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56440 3320 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n188#" "a_15_n100#" 28.3324
+cap "a_15_n100#" "a_n73_n100#" 283.566
+cap "a_n33_n188#" "a_n73_n100#" 28.3324
+device msubckt sky130_fd_pr__nfet_01v8_lvt -15 -100 -14 -99 l=30 w=200 "a_n175_n274#" "a_n33_n188#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.mag
new file mode 100644
index 0000000..feb0446
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_648S5X.mag
@@ -0,0 +1,100 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662404926
+<< error_p >>
+rect -29 172 29 178
+rect -29 138 -17 172
+rect -29 132 29 138
+rect -29 -138 29 -132
+rect -29 -172 -17 -138
+rect -29 -178 29 -172
+<< pwell >>
+rect -211 -310 211 310
+<< nmoslvt >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 88 -15 100
+rect -73 -88 -61 88
+rect -27 -88 -15 88
+rect -73 -100 -15 -88
+rect 15 88 73 100
+rect 15 -88 27 88
+rect 61 -88 73 88
+rect 15 -100 73 -88
+<< ndiffc >>
+rect -61 -88 -27 88
+rect 27 -88 61 88
+<< psubdiff >>
+rect -175 240 -79 274
+rect 79 240 175 274
+rect -175 178 -141 240
+rect 141 178 175 240
+rect -175 -240 -141 -178
+rect 141 -240 175 -178
+rect -175 -274 -79 -240
+rect 79 -274 175 -240
+<< psubdiffcont >>
+rect -79 240 79 274
+rect -175 -178 -141 178
+rect 141 -178 175 178
+rect -79 -274 79 -240
+<< poly >>
+rect -33 172 33 188
+rect -33 138 -17 172
+rect 17 138 33 172
+rect -33 122 33 138
+rect -15 100 15 122
+rect -15 -122 15 -100
+rect -33 -138 33 -122
+rect -33 -172 -17 -138
+rect 17 -172 33 -138
+rect -33 -188 33 -172
+<< polycont >>
+rect -17 138 17 172
+rect -17 -172 17 -138
+<< locali >>
+rect -175 240 -79 274
+rect 79 240 175 274
+rect -175 178 -141 240
+rect 141 178 175 240
+rect -33 138 -17 172
+rect 17 138 33 172
+rect -61 88 -27 104
+rect -61 -104 -27 -88
+rect 27 88 61 104
+rect 27 -104 61 -88
+rect -33 -172 -17 -138
+rect 17 -172 33 -138
+rect -175 -240 -141 -178
+rect 141 -240 175 -178
+rect -175 -274 -79 -240
+rect 79 -274 175 -240
+<< viali >>
+rect -17 138 17 172
+rect -61 -88 -27 88
+rect 27 -88 61 88
+rect -17 -172 17 -138
+<< metal1 >>
+rect -29 172 29 178
+rect -29 138 -17 172
+rect 17 138 29 172
+rect -29 132 29 138
+rect -67 88 -21 100
+rect -67 -88 -61 88
+rect -27 -88 -21 88
+rect -67 -100 -21 -88
+rect 21 88 67 100
+rect 21 -88 27 88
+rect 61 -88 67 88
+rect 21 -100 67 -88
+rect -29 -138 29 -132
+rect -29 -172 -17 -138
+rect 17 -172 29 -138
+rect -29 -178 29 -172
+<< properties >>
+string FIXED_BBOX -158 -257 158 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.ext
new file mode 100644
index 0000000..2e7d40f
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.ext
@@ -0,0 +1,213 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_543_n100#" 466 98.1207 543 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_447_n100#" 442 58.4096 447 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 442 47.3534 351 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_255_n100#" 442 42.4831 255 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 442 40.0479 159 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_63_n100#" 442 38.9074 63 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 442 38.6457 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 442 39.1525 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n225_n100#" 442 40.5359 -225 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n321_n100#" 442 43.2096 -321 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n417_n100#" 442 48.312 -417 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n513_n100#" 442 59.5918 -513 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n605_n100#" 466 99.5866 -605 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_399_n188#" 514 129.256 399 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_495_122#" 514 145.941 495 122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_207_n188#" 514 116.607 207 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_303_122#" 514 115.312 303 122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_15_n188#" 514 122.961 15 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_111_122#" 514 121.291 111 122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n177_n188#" 514 129.375 -177 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n81_122#" 514 127.612 -81 122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n369_n188#" 514 135.845 -369 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n273_122#" 514 133.827 -273 122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n561_n188#" 514 173.983 -561 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_n465_122#" 514 156.223 -465 122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "a_n707_n274#" 0 0 -707 -274 ppd 0 0 0 0 0 0 0 0 0 0 128792 7576 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128792 7576 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_447_n100#" "a_n513_n100#" 14.3638
+cap "a_303_122#" "a_n465_122#" 6.45081
+cap "a_207_n188#" "a_495_122#" 3.46589
+cap "a_n465_122#" "a_n81_122#" 14.0338
+cap "a_n465_122#" "a_n177_n188#" 3.46589
+cap "a_n273_122#" "a_15_n188#" 3.46589
+cap "a_n605_n100#" "a_n417_n100#" 87.4087
+cap "a_n321_n100#" "a_n417_n100#" 241.535
+cap "a_159_n100#" "a_111_122#" 6.25956
+cap "a_n605_n100#" "a_n33_n100#" 24.6699
+cap "a_n33_n100#" "a_n81_122#" 6.25956
+cap "a_n321_n100#" "a_n33_n100#" 53.425
+cap "a_63_n100#" "a_255_n100#" 87.4087
+cap "a_399_n188#" "a_n273_122#" 1.38306
+cap "a_159_n100#" "a_63_n100#" 241.535
+cap "a_n605_n100#" "a_n225_n100#" 38.4743
+cap "a_351_n100#" "a_543_n100#" 87.4087
+cap "a_n177_n188#" "a_n225_n100#" 6.25956
+cap "a_n321_n100#" "a_n225_n100#" 241.535
+cap "a_255_n100#" "a_n513_n100#" 18.1562
+cap "a_447_n100#" "a_543_n100#" 241.535
+cap "a_159_n100#" "a_n513_n100#" 20.9177
+cap "a_351_n100#" "a_447_n100#" 241.535
+cap "a_n561_n188#" "a_n465_122#" 14.1667
+cap "a_303_122#" "a_495_122#" 34.1645
+cap "a_n605_n100#" "a_n129_n100#" 30.0629
+cap "a_n81_122#" "a_n129_n100#" 6.25956
+cap "a_399_n188#" "a_15_n188#" 14.0338
+cap "a_n177_n188#" "a_n129_n100#" 6.25956
+cap "a_n465_122#" "a_111_122#" 8.83801
+cap "a_399_n188#" "a_351_n100#" 6.25956
+cap "a_n321_n100#" "a_n129_n100#" 87.4087
+cap "a_495_122#" "a_n177_n188#" 1.38306
+cap "a_495_122#" "a_n81_122#" 8.83801
+cap "a_303_122#" "a_207_n188#" 14.1667
+cap "a_399_n188#" "a_447_n100#" 6.25956
+cap "a_207_n188#" "a_n81_122#" 3.46589
+cap "a_207_n188#" "a_n177_n188#" 14.0338
+cap "a_n465_122#" "a_n369_n188#" 14.1667
+cap "a_n417_n100#" "a_n369_n188#" 6.25956
+cap "a_63_n100#" "a_n417_n100#" 30.0629
+cap "a_n33_n100#" "a_63_n100#" 241.535
+cap "a_n465_122#" "a_n513_n100#" 6.25956
+cap "a_255_n100#" "a_543_n100#" 53.425
+cap "a_351_n100#" "a_255_n100#" 241.535
+cap "a_159_n100#" "a_543_n100#" 38.4743
+cap "a_n417_n100#" "a_n513_n100#" 241.535
+cap "a_159_n100#" "a_351_n100#" 87.4087
+cap "a_n33_n100#" "a_n513_n100#" 30.0629
+cap "a_n561_n188#" "a_495_122#" 0.863965
+cap "a_255_n100#" "a_447_n100#" 87.4087
+cap "a_159_n100#" "a_447_n100#" 53.425
+cap "a_63_n100#" "a_n225_n100#" 53.425
+cap "a_495_122#" "a_111_122#" 14.0338
+cap "a_207_n188#" "a_n561_n188#" 6.45081
+cap "a_n273_122#" "a_n465_122#" 34.1645
+cap "a_303_122#" "a_n177_n188#" 1.97704
+cap "a_303_122#" "a_n81_122#" 14.0338
+cap "a_207_n188#" "a_111_122#" 14.1667
+cap "a_n81_122#" "a_n177_n188#" 14.1667
+cap "a_n605_n100#" "a_n321_n100#" 53.425
+cap "a_495_122#" "a_n369_n188#" 1.06355
+cap "a_63_n100#" "a_n129_n100#" 87.4087
+cap "a_n225_n100#" "a_n513_n100#" 53.425
+cap "a_207_n188#" "a_n369_n188#" 8.83801
+cap "a_n129_n100#" "a_n513_n100#" 38.4743
+cap "a_n465_122#" "a_15_n188#" 1.97704
+cap "a_n417_n100#" "a_543_n100#" 14.3638
+cap "a_n273_122#" "a_n225_n100#" 6.25956
+cap "a_n417_n100#" "a_351_n100#" 18.1562
+cap "a_n33_n100#" "a_543_n100#" 24.6699
+cap "a_n33_n100#" "a_15_n188#" 6.25956
+cap "a_159_n100#" "a_255_n100#" 241.535
+cap "a_n33_n100#" "a_351_n100#" 38.4743
+cap "a_n417_n100#" "a_447_n100#" 16.0389
+cap "a_399_n188#" "a_n465_122#" 1.06355
+cap "a_303_122#" "a_n561_n188#" 1.06355
+cap "a_n33_n100#" "a_447_n100#" 30.0629
+cap "a_n605_n100#" "a_n561_n188#" 6.25956
+cap "a_n561_n188#" "a_n81_122#" 1.97704
+cap "a_n273_122#" "a_495_122#" 6.45081
+cap "a_n561_n188#" "a_n177_n188#" 14.0338
+cap "a_303_122#" "a_111_122#" 34.1645
+cap "a_n177_n188#" "a_111_122#" 3.46589
+cap "a_n81_122#" "a_111_122#" 34.1645
+cap "a_543_n100#" "a_n225_n100#" 18.1562
+cap "a_n273_122#" "a_207_n188#" 1.97704
+cap "a_351_n100#" "a_n225_n100#" 24.6699
+cap "a_303_122#" "a_n369_n188#" 1.38306
+cap "a_n81_122#" "a_n369_n188#" 3.46589
+cap "a_n369_n188#" "a_n177_n188#" 34.1645
+cap "a_447_n100#" "a_n225_n100#" 20.9177
+cap "a_n321_n100#" "a_n369_n188#" 6.25956
+cap "a_n605_n100#" "a_63_n100#" 20.9177
+cap "a_n321_n100#" "a_63_n100#" 38.4743
+cap "a_n129_n100#" "a_543_n100#" 20.9177
+cap "a_495_122#" "a_543_n100#" 6.25956
+cap "a_351_n100#" "a_n129_n100#" 30.0629
+cap "a_495_122#" "a_15_n188#" 1.97704
+cap "a_447_n100#" "a_n129_n100#" 24.6699
+cap "a_207_n188#" "a_15_n188#" 34.1645
+cap "a_n605_n100#" "a_n513_n100#" 241.535
+cap "a_495_122#" "a_447_n100#" 6.25956
+cap "a_n417_n100#" "a_255_n100#" 20.9177
+cap "a_n321_n100#" "a_n513_n100#" 87.4087
+cap "a_159_n100#" "a_n417_n100#" 24.6699
+cap "a_n33_n100#" "a_255_n100#" 53.425
+cap "a_399_n188#" "a_495_122#" 14.1667
+cap "a_n33_n100#" "a_159_n100#" 87.4087
+cap "a_n561_n188#" "a_111_122#" 1.38306
+cap "a_399_n188#" "a_207_n188#" 34.1645
+cap "a_n273_122#" "a_303_122#" 8.83801
+cap "a_n273_122#" "a_n81_122#" 34.1645
+cap "a_n273_122#" "a_n177_n188#" 14.1667
+cap "a_n561_n188#" "a_n369_n188#" 34.1645
+cap "a_n273_122#" "a_n321_n100#" 6.25956
+cap "a_255_n100#" "a_n225_n100#" 30.0629
+cap "a_n369_n188#" "a_111_122#" 1.97704
+cap "a_159_n100#" "a_n225_n100#" 38.4743
+cap "a_63_n100#" "a_111_122#" 6.25956
+cap "a_255_n100#" "a_n129_n100#" 38.4743
+cap "a_n561_n188#" "a_n513_n100#" 6.25956
+cap "a_303_122#" "a_15_n188#" 3.46589
+cap "a_159_n100#" "a_n129_n100#" 53.425
+cap "a_n417_n100#" "a_n465_122#" 6.25956
+cap "a_n605_n100#" "a_543_n100#" 11.882
+cap "a_303_122#" "a_351_n100#" 6.25956
+cap "a_n81_122#" "a_15_n188#" 14.1667
+cap "a_n177_n188#" "a_15_n188#" 34.1645
+cap "a_n321_n100#" "a_543_n100#" 16.0389
+cap "a_n605_n100#" "a_351_n100#" 14.3638
+cap "a_207_n188#" "a_255_n100#" 6.25956
+cap "a_n321_n100#" "a_351_n100#" 20.9177
+cap "a_159_n100#" "a_207_n188#" 6.25956
+cap "a_n605_n100#" "a_447_n100#" 13.0056
+cap "a_n33_n100#" "a_n417_n100#" 38.4743
+cap "a_n321_n100#" "a_447_n100#" 18.1562
+cap "a_399_n188#" "a_303_122#" 14.1667
+cap "a_63_n100#" "a_n513_n100#" 24.6699
+cap "a_399_n188#" "a_n81_122#" 1.97704
+cap "a_399_n188#" "a_n177_n188#" 8.83801
+cap "a_n273_122#" "a_n561_n188#" 3.46589
+cap "a_n273_122#" "a_111_122#" 14.0338
+cap "a_n417_n100#" "a_n225_n100#" 87.4087
+cap "a_n273_122#" "a_n369_n188#" 14.1667
+cap "a_n33_n100#" "a_n225_n100#" 87.4087
+cap "a_495_122#" "a_n465_122#" 5.07915
+cap "a_n561_n188#" "a_15_n188#" 8.83801
+cap "a_n417_n100#" "a_n129_n100#" 53.425
+cap "a_207_n188#" "a_n465_122#" 1.38306
+cap "a_111_122#" "a_15_n188#" 14.1667
+cap "a_n33_n100#" "a_n129_n100#" 241.535
+cap "a_303_122#" "a_255_n100#" 6.25956
+cap "a_n605_n100#" "a_255_n100#" 16.0389
+cap "a_n321_n100#" "a_255_n100#" 24.6699
+cap "a_n605_n100#" "a_159_n100#" 18.1562
+cap "a_n369_n188#" "a_15_n188#" 14.0338
+cap "a_n321_n100#" "a_159_n100#" 30.0629
+cap "a_399_n188#" "a_n561_n188#" 5.07915
+cap "a_63_n100#" "a_543_n100#" 30.0629
+cap "a_63_n100#" "a_15_n188#" 6.25956
+cap "a_399_n188#" "a_111_122#" 3.46589
+cap "a_63_n100#" "a_351_n100#" 53.425
+cap "a_n129_n100#" "a_n225_n100#" 241.535
+cap "a_63_n100#" "a_447_n100#" 38.4743
+cap "a_399_n188#" "a_n369_n188#" 6.45081
+cap "a_543_n100#" "a_n513_n100#" 13.0056
+cap "a_351_n100#" "a_n513_n100#" 16.0389
+device msubckt sky130_fd_pr__nfet_01v8_lvt 513 -100 514 -99 l=30 w=200 "a_n707_n274#" "a_495_122#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 417 -100 418 -99 l=30 w=200 "a_n707_n274#" "a_399_n188#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 321 -100 322 -99 l=30 w=200 "a_n707_n274#" "a_303_122#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 225 -100 226 -99 l=30 w=200 "a_n707_n274#" "a_207_n188#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 129 -100 130 -99 l=30 w=200 "a_n707_n274#" "a_111_122#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 33 -100 34 -99 l=30 w=200 "a_n707_n274#" "a_15_n188#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -63 -100 -62 -99 l=30 w=200 "a_n707_n274#" "a_n81_122#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -159 -100 -158 -99 l=30 w=200 "a_n707_n274#" "a_n177_n188#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -255 -100 -254 -99 l=30 w=200 "a_n707_n274#" "a_n273_122#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -351 -100 -350 -99 l=30 w=200 "a_n707_n274#" "a_n369_n188#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -447 -100 -446 -99 l=30 w=200 "a_n707_n274#" "a_n465_122#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -543 -100 -542 -99 l=30 w=200 "a_n707_n274#" "a_n561_n188#" 60 0 "a_n605_n100#" 200 0 "a_n513_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.mag
new file mode 100644
index 0000000..c065d41
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_6BNFGK.mag
@@ -0,0 +1,415 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662404926
+<< error_p >>
+rect -461 172 -403 178
+rect -269 172 -211 178
+rect -77 172 -19 178
+rect 115 172 173 178
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+rect 499 172 557 178
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+rect -173 -178 -115 -172
+rect 19 -178 77 -172
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+rect 403 -178 461 -172
+<< pwell >>
+rect -743 -310 743 310
+<< nmoslvt >>
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+rect -351 -100 -321 100
+rect -255 -100 -225 100
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+rect -63 -100 -33 100
+rect 33 -100 63 100
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+rect 417 -100 447 100
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+<< ndiff >>
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+<< ndiffc >>
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+rect -497 -88 -463 88
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+<< psubdiff >>
+rect -707 240 -611 274
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+rect -707 -240 -673 -178
+rect 673 -240 707 -178
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+rect 611 -274 707 -240
+<< psubdiffcont >>
+rect -611 240 611 274
+rect -707 -178 -673 178
+rect 673 -178 707 178
+rect -611 -274 611 -240
+<< poly >>
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+rect -273 172 -207 188
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+rect 15 -138 81 -122
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+<< polycont >>
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+rect -65 138 -31 172
+rect 127 138 161 172
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+rect -545 -172 -511 -138
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+<< locali >>
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+<< viali >>
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+<< metal1 >>
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+rect 19 -138 77 -132
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+rect 211 -178 269 -172
+rect 403 -138 461 -132
+rect 403 -172 415 -138
+rect 449 -172 461 -138
+rect 403 -178 461 -172
+<< properties >>
+string FIXED_BBOX -690 -257 690 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 12 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_6Q7D69.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_6Q7D69.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_6Q7D69.mag
new file mode 100644
index 0000000..442085f
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_6Q7D69.mag
@@ -0,0 +1,184 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662690363
+<< error_p >>
+rect -159 372 -97 378
+rect -31 372 31 378
+rect 97 372 159 378
+rect -159 338 -147 372
+rect -31 338 -19 372
+rect 97 338 109 372
+rect -159 332 -97 338
+rect -31 332 31 338
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+rect 97 -378 159 -372
+<< pwell >>
+rect -359 -510 359 510
+<< nmoslvt >>
+rect -163 -300 -93 300
+rect -35 -300 35 300
+rect 93 -300 163 300
+<< ndiff >>
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+<< ndiffc >>
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+<< psubdiff >>
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+<< psubdiffcont >>
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+<< poly >>
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+<< polycont >>
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+<< locali >>
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+<< metal1 >>
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+rect 19 -372 31 -338
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+rect 97 -372 109 -338
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+rect 97 -378 159 -372
+<< properties >>
+string FIXED_BBOX -306 -457 306 457
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 3 l 0.35 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.ext
new file mode 100644
index 0000000..502e564
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.ext
@@ -0,0 +1,159 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_447_n100#" 466 98.9934 447 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 442 59.4523 351 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_255_n100#" 442 48.6213 255 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
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+device msubckt sky130_fd_pr__nfet_01v8_lvt -447 -100 -446 -99 l=30 w=200 "a_n611_n274#" "a_n465_n188#" 60 0 "a_n509_n100#" 200 0 "a_n417_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.mag
new file mode 100644
index 0000000..2f2ef94
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_9DHFGX.mag
@@ -0,0 +1,355 @@
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+<< properties >>
+string FIXED_BBOX -594 -257 594 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_A33GGX.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_A33GGX.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_A33GGX.mag
new file mode 100644
index 0000000..9193731
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_A33GGX.mag
@@ -0,0 +1,1255 @@
+magic
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+timestamp 1660421802
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+<< properties >>
+string FIXED_BBOX -2034 -257 2034 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 40 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.ext
new file mode 100644
index 0000000..04fef08
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.ext
@@ -0,0 +1,75 @@
+timestamp 1660420676
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_255_n100#" 466 102.271 255 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
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+node "a_n33_n100#" 442 52.1397 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 442 54.5918 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n225_n100#" 442 64.2536 -225 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n317_n100#" 466 103.192 -317 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
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+device msubckt sky130_fd_pr__nfet_01v8_lvt 129 -100 130 -99 l=30 w=200 "a_n419_n274#" "a_111_n188#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 33 -100 34 -99 l=30 w=200 "a_n419_n274#" "a_15_122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -63 -100 -62 -99 l=30 w=200 "a_n419_n274#" "a_n81_n188#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -159 -100 -158 -99 l=30 w=200 "a_n419_n274#" "a_n177_122#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -255 -100 -254 -99 l=30 w=200 "a_n419_n274#" "a_n273_n188#" 60 0 "a_n317_n100#" 200 0 "a_n225_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.mag
new file mode 100644
index 0000000..2f68752
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_B6HS5D.mag
@@ -0,0 +1,235 @@
+magic
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+<< properties >>
+string FIXED_BBOX -402 -257 402 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.ext
new file mode 100644
index 0000000..60c96dd
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.ext
@@ -0,0 +1,33 @@
+timestamp 1660420676
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
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+cap "a_111_n100#" "a_n173_n100#" 53.425
+cap "a_n33_122#" "a_15_n100#" 6.25956
+device msubckt sky130_fd_pr__nfet_01v8_lvt 81 -100 82 -99 l=30 w=200 "a_n275_n274#" "a_63_n188#" 60 0 "a_15_n100#" 200 0 "a_111_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -15 -100 -14 -99 l=30 w=200 "a_n275_n274#" "a_n33_122#" 60 0 "a_n81_n100#" 200 0 "a_15_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -111 -100 -110 -99 l=30 w=200 "a_n275_n274#" "a_n129_n188#" 60 0 "a_n173_n100#" 200 0 "a_n81_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.mag
new file mode 100644
index 0000000..de0f4c5
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_BX7S53.mag
@@ -0,0 +1,145 @@
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+timestamp 1660420676
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+<< properties >>
+string FIXED_BBOX -258 -257 258 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.ext
new file mode 100644
index 0000000..aae1860
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.ext
@@ -0,0 +1,23 @@
+timestamp 1660420676
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 466 114.805 63 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 442 86.3737 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n100#" 466 115.178 -125 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n81_n188#" 514 165.272 -81 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_15_122#" 514 165.272 15 122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "a_n227_n274#" 0 0 -227 -274 ppd 0 0 0 0 0 0 0 0 0 0 63512 3736 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63512 3736 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_122#" "a_n33_n100#" 6.25956
+cap "a_n33_n100#" "a_n81_n188#" 6.25956
+cap "a_n125_n100#" "a_n81_n188#" 6.25956
+cap "a_15_122#" "a_n81_n188#" 14.1667
+cap "a_63_n100#" "a_n33_n100#" 241.535
+cap "a_63_n100#" "a_n125_n100#" 87.4087
+cap "a_63_n100#" "a_15_122#" 6.25956
+cap "a_n125_n100#" "a_n33_n100#" 241.535
+device msubckt sky130_fd_pr__nfet_01v8_lvt 33 -100 34 -99 l=30 w=200 "a_n227_n274#" "a_15_122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -63 -100 -62 -99 l=30 w=200 "a_n227_n274#" "a_n81_n188#" 60 0 "a_n125_n100#" 200 0 "a_n33_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.mag
new file mode 100644
index 0000000..e4497b4
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_DJ7QE5.mag
@@ -0,0 +1,115 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1660420676
+<< error_p >>
+rect 19 172 77 178
+rect 19 138 31 172
+rect 19 132 77 138
+rect -77 -138 -19 -132
+rect -77 -172 -65 -138
+rect -77 -178 -19 -172
+<< pwell >>
+rect -263 -310 263 310
+<< nmoslvt >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -125 88 -63 100
+rect -125 -88 -113 88
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+rect -125 -100 -63 -88
+rect -33 88 33 100
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+rect 63 88 125 100
+rect 63 -88 79 88
+rect 113 -88 125 88
+rect 63 -100 125 -88
+<< ndiffc >>
+rect -113 -88 -79 88
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+rect 79 -88 113 88
+<< psubdiff >>
+rect -227 240 -131 274
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+rect -227 178 -193 240
+rect 193 178 227 240
+rect -227 -240 -193 -178
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+rect -227 -274 -131 -240
+rect 131 -274 227 -240
+<< psubdiffcont >>
+rect -131 240 131 274
+rect -227 -178 -193 178
+rect 193 -178 227 178
+rect -131 -274 131 -240
+<< poly >>
+rect 15 172 81 188
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+rect -63 100 -33 126
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+rect 33 100 63 122
+rect -63 -122 -33 -100
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+rect -31 -172 -15 -138
+rect -81 -188 -15 -172
+<< polycont >>
+rect 31 138 65 172
+rect -65 -172 -31 -138
+<< locali >>
+rect -227 240 -131 274
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+rect 193 178 227 240
+rect 15 138 31 172
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+rect -31 -172 -15 -138
+rect -227 -240 -193 -178
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+rect -227 -274 -131 -240
+rect 131 -274 227 -240
+<< viali >>
+rect 31 138 65 172
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+rect -65 -172 -31 -138
+<< metal1 >>
+rect 19 172 77 178
+rect 19 138 31 172
+rect 65 138 77 172
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+rect -119 -88 -113 88
+rect -79 -88 -73 88
+rect -119 -100 -73 -88
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+rect -77 -138 -19 -132
+rect -77 -172 -65 -138
+rect -31 -172 -19 -138
+rect -77 -178 -19 -172
+<< properties >>
+string FIXED_BBOX -210 -257 210 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.ext
new file mode 100644
index 0000000..d5a5940
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.ext
@@ -0,0 +1,38 @@
+timestamp 1662515274
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_159_n100#" 466 105.34 159 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_63_n100#" 442 66.64 63 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 442 59.6716 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 442 66.3679 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n100#" 466 106.005 -221 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n177_n188#" 1169 315.309 -177 -188 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23592 1520 0 0 4488 400 10201 624 0 0 0 0 0 0 0 0 0 0
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+substrate "a_n323_n274#" 0 0 -323 -274 ppd 0 0 0 0 0 0 0 0 0 0 76568 4504 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 76568 4504 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_159_n100#" "a_n81_122#" 8.10456
+cap "a_n33_n100#" "a_n177_n188#" 45.0046
+cap "a_n33_n100#" "a_63_n100#" 241.535
+cap "a_n221_n100#" "a_159_n100#" 38.4743
+cap "a_n177_n188#" "a_n81_122#" 68.8191
+cap "a_63_n100#" "a_n81_122#" 45.0046
+cap "a_n33_n100#" "a_n129_n100#" 241.535
+cap "a_n177_n188#" "a_n221_n100#" 8.10456
+cap "a_63_n100#" "a_n221_n100#" 53.425
+cap "a_n81_122#" "a_n129_n100#" 18.2521
+cap "a_n221_n100#" "a_n129_n100#" 241.535
+cap "a_n33_n100#" "a_n81_122#" 45.0046
+cap "a_63_n100#" "a_159_n100#" 241.535
+cap "a_n33_n100#" "a_n221_n100#" 87.4087
+cap "a_159_n100#" "a_n129_n100#" 53.425
+cap "a_63_n100#" "a_n177_n188#" 9.02706
+cap "a_n177_n188#" "a_n129_n100#" 45.0046
+cap "a_63_n100#" "a_n129_n100#" 87.4087
+cap "a_n33_n100#" "a_159_n100#" 87.4087
+device msubckt sky130_fd_pr__nfet_01v8_lvt 129 -100 130 -99 l=30 w=200 "a_n323_n274#" "a_n81_122#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 33 -100 34 -99 l=30 w=200 "a_n323_n274#" "a_n177_n188#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -63 -100 -62 -99 l=30 w=200 "a_n323_n274#" "a_n81_122#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -159 -100 -158 -99 l=30 w=200 "a_n323_n274#" "a_n177_n188#" 60 0 "a_n221_n100#" 200 0 "a_n129_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.mag
new file mode 100644
index 0000000..0c0e2ae
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_HNLS5R.mag
@@ -0,0 +1,170 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662515274
+<< pwell >>
+rect -359 -310 359 310
+<< nmoslvt >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< ndiff >>
+rect -221 88 -159 100
+rect -221 -88 -209 88
+rect -175 -88 -159 88
+rect -221 -100 -159 -88
+rect -129 88 -63 100
+rect -129 -88 -113 88
+rect -79 -88 -63 88
+rect -129 -100 -63 -88
+rect -33 88 33 100
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+rect 17 -88 33 88
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+rect 113 -88 129 88
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+rect 159 88 221 100
+rect 159 -88 175 88
+rect 209 -88 221 88
+rect 159 -100 221 -88
+<< ndiffc >>
+rect -209 -88 -175 88
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+rect 175 -88 209 88
+<< psubdiff >>
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+rect 227 240 323 274
+rect -323 178 -289 240
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+rect 227 -274 323 -240
+<< psubdiffcont >>
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+<< poly >>
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+rect 15 -138 81 -122
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+rect 15 -188 81 -172
+<< polycont >>
+rect -65 138 -31 172
+rect 127 138 161 172
+rect -161 -172 -127 -138
+rect 31 -172 65 -138
+<< locali >>
+rect -323 240 -227 274
+rect 227 240 323 274
+rect -323 178 -289 240
+rect 289 178 323 240
+rect -81 138 -65 172
+rect -31 138 -15 172
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+rect 15 -172 31 -138
+rect 65 -172 81 -138
+rect -323 -240 -289 -178
+rect 289 -240 323 -178
+rect -323 -274 -227 -240
+rect 227 -274 323 -240
+<< viali >>
+rect -65 138 -31 172
+rect 127 138 161 172
+rect -209 -88 -175 88
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+rect 175 -88 209 88
+rect -161 -172 -127 -138
+rect 31 -172 65 -138
+<< metal1 >>
+rect -77 175 -19 178
+rect 115 175 173 178
+rect -90 172 175 175
+rect -90 140 -65 172
+rect -77 138 -65 140
+rect -31 140 127 172
+rect -31 138 -19 140
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+rect -215 88 -169 100
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+rect 65 -140 77 -138
+rect 65 -172 80 -140
+rect -175 -175 80 -172
+rect -173 -178 -115 -175
+rect 19 -178 77 -175
+<< properties >>
+string FIXED_BBOX -306 -257 306 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.ext
new file mode 100644
index 0000000..264414f
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.ext
@@ -0,0 +1,2060 @@
+timestamp 1662407989
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_2847_n100#" 466 93.3934 2847 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2751_n100#" 442 53.2828 2751 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2655_n100#" 442 41.7534 2655 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2559_n100#" 442 36.3136 2559 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2463_n100#" 442 33.18 2463 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2367_n100#" 442 31.1627 2367 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2271_n100#" 442 29.7676 2271 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2175_n100#" 442 28.7525 2175 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_2079_n100#" 442 27.9842 2079 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
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+cap "a_975_n188#" "a_2127_n188#" 4.18859
+cap "a_n2289_n188#" "a_n1521_n188#" 6.45081
+cap "a_2031_122#" "a_1071_122#" 5.07915
+cap "a_2751_n100#" "a_1503_n100#" 10.9371
+cap "a_2655_n100#" "a_2175_n100#" 30.0629
+cap "a_n1425_122#" "a_n1041_122#" 14.0338
+cap "a_n1857_n100#" "a_n1761_n100#" 241.535
+cap "a_879_122#" "a_1647_122#" 6.45081
+cap "a_2463_n100#" "a_1695_n100#" 18.1562
+cap "a_n2097_n188#" "a_n1233_122#" 1.06355
+cap "a_n561_n188#" "a_n465_122#" 14.1667
+cap "a_n2049_n100#" "a_n801_n100#" 10.9371
+cap "a_n2481_n188#" "a_n2673_n188#" 34.1645
+cap "a_399_n188#" "a_783_n188#" 14.0338
+cap "a_1023_n100#" "a_1071_122#" 6.25956
+cap "a_n1137_n188#" "a_n2769_122#" 0.0858586
+cap "a_543_n100#" "a_1503_n100#" 14.3638
+cap "a_n33_n100#" "a_n801_n100#" 18.1562
+cap "a_n513_n100#" "a_n1089_n100#" 24.6699
+cap "a_n81_122#" "a_15_n188#" 14.1667
+cap "a_n1281_n100#" "a_n609_n100#" 20.9177
+cap "a_927_n100#" "a_639_n100#" 53.425
+cap "a_495_122#" "a_1359_n188#" 1.06355
+cap "a_1023_n100#" "a_n417_n100#" 9.43637
+cap "a_n2337_n100#" "a_n1185_n100#" 11.882
+cap "a_n2337_n100#" "a_n2529_n100#" 87.4087
+cap "a_1263_122#" "a_2031_122#" 6.45081
+cap "a_2655_n100#" "a_2751_n100#" 241.535
+cap "a_351_n100#" "a_1887_n100#" 8.83052
+cap "a_2463_n100#" "a_2415_122#" 6.25956
+cap "a_975_n188#" "a_1359_n188#" 14.0338
+cap "a_2559_n100#" "a_1695_n100#" 16.0389
+cap "a_n417_n100#" "a_n1185_n100#" 18.1562
+cap "a_n2337_n100#" "a_n1569_n100#" 18.1562
+cap "a_159_n100#" "a_1695_n100#" 8.83052
+cap "a_n321_n100#" "a_1215_n100#" 8.83052
+cap "a_159_n100#" "a_n801_n100#" 14.3638
+cap "a_n1617_122#" "a_n1041_122#" 8.83801
+cap "a_1119_n100#" "a_n513_n100#" 8.29777
+cap "a_n2909_n100#" "a_n1377_n100#" 8.83052
+cap "a_n2289_n188#" "a_n1713_n188#" 8.83801
+cap "a_n561_n188#" "a_n369_n188#" 34.1645
+cap "a_n2097_n188#" "a_n2577_122#" 1.97704
+cap "a_399_n188#" "a_n657_122#" 0.863965
+cap "a_n1569_n100#" "a_n417_n100#" 11.882
+cap "a_447_n100#" "a_1407_n100#" 14.3638
+cap "a_n33_n100#" "a_n81_122#" 6.25956
+cap "a_n129_n100#" "a_n225_n100#" 241.535
+cap "a_1983_n100#" "a_639_n100#" 10.1315
+cap "a_n465_122#" "a_n753_n188#" 3.46589
+cap "a_399_n188#" "a_111_122#" 3.46589
+cap "a_2367_n100#" "a_1023_n100#" 10.1315
+cap "a_n2241_n100#" "a_n2433_n100#" 87.4087
+cap "a_n1473_n100#" "a_n1521_n188#" 6.25956
+cap "a_n1329_n188#" "a_n1281_n100#" 6.25956
+cap "a_2607_122#" "a_1647_122#" 5.07915
+cap "a_n321_n100#" "a_n993_n100#" 20.9177
+cap "a_207_n188#" "a_n1329_n188#" 3.10116
+cap "a_2271_n100#" "a_2847_n100#" 24.6699
+cap "a_2319_n188#" "a_2799_122#" 1.97704
+cap "a_1743_n188#" "a_2799_122#" 0.863965
+cap "a_495_122#" "a_n561_n188#" 0.863965
+cap "a_927_n100#" "a_1023_n100#" 241.535
+cap "a_1887_n100#" "a_831_n100#" 13.0056
+cap "a_351_n100#" "a_1215_n100#" 16.0389
+cap "a_1551_n188#" "a_303_122#" 0.727455
+cap "a_399_n188#" "a_1455_122#" 0.863965
+cap "a_975_n188#" "a_n561_n188#" 3.10116
+cap "a_207_n188#" "a_1359_n188#" 4.18859
+cap "a_1311_n100#" "a_255_n100#" 13.0056
+cap "a_n369_n188#" "a_n753_n188#" 14.0338
+cap "a_n609_n100#" "a_n417_n100#" 87.4087
+cap "a_n2385_122#" "a_n753_n188#" 0.0858586
+cap "a_303_122#" "a_1935_n188#" 0.0858586
+cap "a_n2097_n188#" "a_n2193_122#" 14.1667
+cap "a_n1137_n188#" "a_n465_122#" 1.38306
+cap "a_1647_122#" "a_1167_n188#" 1.97704
+cap "a_2271_n100#" "a_1791_n100#" 30.0629
+cap "a_1983_n100#" "a_2031_122#" 6.25956
+cap "a_n1281_n100#" "a_n225_n100#" 13.0056
+cap "a_63_n100#" "a_111_122#" 6.25956
+cap "a_n2097_n188#" "a_n849_122#" 0.727455
+cap "a_2127_n188#" "a_1071_122#" 0.863965
+cap "a_n2289_n188#" "a_n1233_122#" 0.863965
+cap "a_2223_122#" "a_783_n188#" 0.628198
+cap "a_n513_n100#" "a_n801_n100#" 53.425
+cap "a_1839_122#" "a_783_n188#" 0.863965
+cap "a_1983_n100#" "a_1023_n100#" 14.3638
+cap "a_1887_n100#" "a_1599_n100#" 53.425
+cap "a_n33_n100#" "a_15_n188#" 6.25956
+cap "a_351_n100#" "a_n993_n100#" 10.1315
+cap "a_1551_n188#" "a_2319_n188#" 6.45081
+cap "a_2271_n100#" "a_2175_n100#" 241.535
+cap "a_1743_n188#" "a_1551_n188#" 34.1645
+cap "a_639_n100#" "a_735_n100#" 241.535
+cap "a_n2625_n100#" "a_n2817_n100#" 87.4087
+cap "a_n1041_122#" "a_n1089_n100#" 6.25956
+cap "a_2703_n188#" "a_2223_122#" 1.97704
+cap "a_n1857_n100#" "a_n1281_n100#" 24.6699
+cap "a_447_n100#" "a_n321_n100#" 18.1562
+cap "a_2319_n188#" "a_1935_n188#" 14.0338
+cap "a_2703_n188#" "a_1839_122#" 1.06355
+cap "a_495_122#" "a_n753_n188#" 0.727455
+cap "a_2031_122#" "a_2799_122#" 6.45081
+cap "a_1743_n188#" "a_1935_n188#" 34.1645
+cap "a_2127_n188#" "a_1263_122#" 1.06355
+cap "a_n2097_n188#" "a_n2769_122#" 1.38306
+cap "a_n1137_n188#" "a_n369_n188#" 6.45081
+cap "a_n1137_n188#" "a_n2385_122#" 0.727455
+cap "a_687_122#" "a_n81_122#" 6.45081
+cap "a_1359_n188#" "a_1071_122#" 3.46589
+cap "a_831_n100#" "a_1215_n100#" 38.4743
+cap "a_879_122#" "a_831_n100#" 6.25956
+cap "a_n1377_n100#" "a_n1185_n100#" 87.4087
+cap "a_n2529_n100#" "a_n1377_n100#" 11.882
+cap "a_2271_n100#" "a_2751_n100#" 30.0629
+cap "a_n2289_n188#" "a_n2577_122#" 3.46589
+cap "a_207_n188#" "a_n561_n188#" 6.45081
+cap "a_255_n100#" "a_n129_n100#" 38.4743
+cap "a_927_n100#" "a_n609_n100#" 8.83052
+cap "a_n2433_n100#" "a_n1761_n100#" 20.9177
+cap "a_n1569_n100#" "a_n1377_n100#" 87.4087
+cap "a_1887_n100#" "a_1503_n100#" 38.4743
+cap "a_n1569_n100#" "a_n1617_122#" 6.25956
+cap "a_n705_n100#" "a_63_n100#" 18.1562
+cap "a_1311_n100#" "a_1407_n100#" 241.535
+cap "a_1263_122#" "a_1359_n188#" 14.1667
+cap "a_n2865_n188#" "a_n2673_n188#" 34.1645
+cap "a_1551_n188#" "a_2031_122#" 1.97704
+cap "a_2463_n100#" "a_2559_n100#" 241.535
+cap "a_351_n100#" "a_447_n100#" 241.535
+cap "a_n1137_n188#" "a_495_122#" 0.0858586
+cap "a_n2865_n188#" "a_n2481_n188#" 14.0338
+cap "a_1599_n100#" "a_1215_n100#" 38.4743
+cap "a_n705_n100#" "a_n897_n100#" 87.4087
+cap "a_399_n188#" "a_n273_122#" 1.38306
+cap "a_159_n100#" "a_n33_n100#" 87.4087
+cap "a_n417_n100#" "a_n225_n100#" 87.4087
+cap "a_1935_n188#" "a_2031_122#" 14.1667
+cap "a_2223_122#" "a_1455_122#" 6.45081
+cap "a_2655_n100#" "a_1887_n100#" 18.1562
+cap "a_1119_n100#" "a_639_n100#" 30.0629
+cap "a_n2625_n100#" "a_n1953_n100#" 20.9177
+cap "a_n2145_n100#" "a_n2721_n100#" 24.6699
+cap "a_1023_n100#" "a_735_n100#" 53.425
+cap "a_n2433_n100#" "a_n2385_122#" 6.25956
+cap "a_1839_122#" "a_1455_122#" 14.0338
+cap "a_n2337_n100#" "a_n1857_n100#" 30.0629
+cap "a_n1953_n100#" "a_n993_n100#" 14.3638
+cap "a_n2241_n100#" "a_n2817_n100#" 24.6699
+cap "a_207_n188#" "a_n753_n188#" 5.07915
+cap "a_2511_n188#" "a_1647_122#" 1.06355
+cap "a_n2289_n188#" "a_n2193_122#" 14.1667
+cap "a_n945_n188#" "a_n81_122#" 1.06355
+cap "a_n561_n188#" "a_1071_122#" 0.0858586
+cap "a_n1377_n100#" "a_n609_n100#" 18.1562
+cap "a_n1857_n100#" "a_n417_n100#" 9.43637
+cap "a_n2817_n100#" "a_n2769_122#" 6.25956
+cap "a_n2289_n188#" "a_n849_122#" 0.628198
+cap "a_687_122#" "a_15_n188#" 1.38306
+cap "a_n1281_n100#" "a_255_n100#" 8.83052
+cap "a_n1425_122#" "a_n1329_n188#" 14.1667
+cap "a_1503_n100#" "a_1215_n100#" 53.425
+cap "a_n2625_n100#" "a_n1473_n100#" 11.882
+cap "a_207_n188#" "a_255_n100#" 6.25956
+cap "a_1791_n100#" "a_1839_122#" 6.25956
+cap "a_n2097_n188#" "a_n465_122#" 0.0858586
+cap "a_543_n100#" "a_63_n100#" 30.0629
+cap "a_1407_n100#" "a_n129_n100#" 8.83052
+cap "a_n2529_n100#" "a_n1089_n100#" 9.43637
+cap "a_447_n100#" "a_831_n100#" 38.4743
+cap "a_n1089_n100#" "a_n1185_n100#" 241.535
+cap "a_n993_n100#" "a_n1473_n100#" 30.0629
+cap "a_n2145_n100#" "a_n705_n100#" 9.43637
+cap "a_n2241_n100#" "a_n2289_n188#" 6.25956
+cap "a_n1665_n100#" "a_n897_n100#" 18.1562
+cap "a_n321_n100#" "a_n1761_n100#" 9.43637
+cap "a_2223_122#" "a_2175_n100#" 6.25956
+cap "a_n2289_n188#" "a_n2769_122#" 1.97704
+cap "a_n2481_n188#" "a_n945_n188#" 3.10116
+cap "a_n1905_n188#" "a_n2673_n188#" 6.45081
+cap "a_399_n188#" "a_591_n188#" 34.1645
+cap "a_2127_n188#" "a_2799_122#" 1.38306
+cap "a_n1137_n188#" "a_207_n188#" 3.56376
+cap "a_2655_n100#" "a_1215_n100#" 9.43637
+cap "a_927_n100#" "a_n225_n100#" 11.882
+cap "a_1311_n100#" "a_n321_n100#" 8.29777
+cap "a_n1569_n100#" "a_n1089_n100#" 30.0629
+cap "a_543_n100#" "a_n897_n100#" 9.43637
+cap "a_n1905_n188#" "a_n2481_n188#" 8.83801
+cap "a_1023_n100#" "a_1119_n100#" 241.535
+cap "a_n1329_n188#" "a_n1377_n100#" 6.25956
+cap "a_n2049_n100#" "a_n513_n100#" 8.83052
+cap "a_1743_n188#" "a_1695_n100#" 6.25956
+cap "a_n657_122#" "a_n2001_122#" 3.56376
+cap "a_n1617_122#" "a_n1329_n188#" 3.46589
+cap "a_1695_n100#" "a_639_n100#" 13.0056
+cap "a_303_122#" "a_n81_122#" 14.0338
+cap "a_n513_n100#" "a_n33_n100#" 30.0629
+cap "a_n609_n100#" "a_735_n100#" 10.1315
+cap "a_639_n100#" "a_n801_n100#" 9.43637
+cap "a_n2241_n100#" "a_n1953_n100#" 53.425
+cap "a_n1041_122#" "a_n81_122#" 5.07915
+cap "a_n2097_n188#" "a_n2385_122#" 3.46589
+cap "a_n657_122#" "a_783_n188#" 0.628198
+cap "a_447_n100#" "a_1599_n100#" 11.882
+cap "a_n369_n188#" "a_n321_n100#" 6.25956
+cap "a_2319_n188#" "a_2415_122#" 14.1667
+cap "a_1743_n188#" "a_2415_122#" 1.38306
+cap "a_n945_n188#" "a_15_n188#" 5.07915
+cap "a_495_122#" "a_1647_122#" 4.18859
+cap "a_1359_n188#" "a_2799_122#" 0.628198
+cap "a_2079_n100#" "a_2847_n100#" 18.1562
+cap "a_111_122#" "a_783_n188#" 1.38306
+cap "a_975_n188#" "a_1647_122#" 1.38306
+cap "a_n2433_n100#" "a_n1281_n100#" 11.882
+cap "a_1551_n188#" "a_2127_n188#" 8.83801
+cap "a_159_n100#" "a_n513_n100#" 20.9177
+cap "a_255_n100#" "a_n417_n100#" 20.9177
+cap "a_n1425_122#" "a_n561_n188#" 1.06355
+cap "a_351_n100#" "a_1311_n100#" 14.3638
+cap "a_n2145_n100#" "a_n1665_n100#" 30.0629
+cap "a_n1041_122#" "a_n2673_n188#" 0.0858586
+cap "a_n609_n100#" "a_n1089_n100#" 30.0629
+cap "a_n1377_n100#" "a_n225_n100#" 11.882
+cap "a_n2241_n100#" "a_n1473_n100#" 18.1562
+cap "a_2127_n188#" "a_1935_n188#" 34.1645
+cap "a_n1041_122#" "a_n2481_n188#" 0.628198
+cap "a_2079_n100#" "a_1791_n100#" 53.425
+cap "a_n2817_n100#" "a_n1761_n100#" 13.0056
+cap "a_2271_n100#" "a_1887_n100#" 38.4743
+cap "a_447_n100#" "a_1503_n100#" 13.0056
+cap "a_1455_122#" "a_783_n188#" 1.38306
+cap "a_n129_n100#" "a_n321_n100#" 87.4087
+cap "a_2607_122#" "a_2655_n100#" 6.25956
+cap "a_n657_122#" "a_111_122#" 6.45081
+cap "a_1551_n188#" "a_1359_n188#" 34.1645
+cap "a_n1857_n100#" "a_n1377_n100#" 30.0629
+cap "a_2079_n100#" "a_2175_n100#" 241.535
+cap "a_1023_n100#" "a_1695_n100#" 20.9177
+cap "a_2415_122#" "a_2031_122#" 14.0338
+cap "a_2703_n188#" "a_1455_122#" 0.727455
+cap "a_n1617_122#" "a_n561_n188#" 0.863965
+cap "a_303_122#" "a_15_n188#" 3.46589
+cap "a_1359_n188#" "a_1935_n188#" 8.83801
+cap "a_n1185_n100#" "a_n801_n100#" 38.4743
+cap "a_n1041_122#" "a_15_n188#" 0.863965
+cap "a_n1425_122#" "a_n753_n188#" 1.38306
+cap "a_207_n188#" "a_1647_122#" 0.628198
+cap "a_591_n188#" "a_2223_122#" 0.0858586
+cap "a_2079_n100#" "a_2751_n100#" 20.9177
+cap "a_n1569_n100#" "a_n801_n100#" 18.1562
+cap "a_n2337_n100#" "a_n2433_n100#" 241.535
+cap "a_831_n100#" "a_1311_n100#" 30.0629
+cap "a_927_n100#" "a_255_n100#" 20.9177
+cap "a_n225_n100#" "a_735_n100#" 14.3638
+cap "a_591_n188#" "a_1839_122#" 0.727455
+cap "a_351_n100#" "a_n129_n100#" 30.0629
+cap "a_1455_122#" "a_111_122#" 3.56376
+cap "a_2079_n100#" "a_543_n100#" 8.83052
+cap "a_n1953_n100#" "a_n1761_n100#" 87.4087
+cap "a_399_n188#" "a_n1233_122#" 0.0858586
+cap "a_n1281_n100#" "a_n321_n100#" 14.3638
+cap "a_n2049_n100#" "a_n2909_n100#" 16.0389
+cap "a_n2289_n188#" "a_n2385_122#" 14.1667
+cap "a_2271_n100#" "a_1215_n100#" 13.0056
+cap "a_n657_122#" "a_n705_n100#" 6.25956
+cap "a_n1617_122#" "a_n753_n188#" 1.06355
+cap "a_n1425_122#" "a_n1137_n188#" 3.46589
+cap "a_n225_n100#" "a_n1089_n100#" 16.0389
+cap "a_399_n188#" "a_879_122#" 1.97704
+cap "a_1599_n100#" "a_1311_n100#" 53.425
+cap "a_n609_n100#" "a_n801_n100#" 87.4087
+cap "a_1647_122#" "a_1071_122#" 8.83801
+cap "a_2367_n100#" "a_1407_n100#" 14.3638
+cap "a_n1473_n100#" "a_n1761_n100#" 53.425
+cap "a_687_122#" "a_n945_n188#" 0.0858586
+cap "a_255_n100#" "a_n1377_n100#" 8.29777
+cap "a_2751_n100#" "a_2703_n188#" 6.25956
+cap "a_n33_n100#" "a_639_n100#" 20.9177
+cap "a_n1857_n100#" "a_n1089_n100#" 18.1562
+cap "a_n2529_n100#" "a_n2481_n188#" 6.25956
+cap "a_n273_122#" "a_783_n188#" 0.863965
+cap "a_351_n100#" "a_n1281_n100#" 8.29777
+cap "a_1119_n100#" "a_n225_n100#" 10.1315
+cap "a_n1905_n188#" "a_n2865_n188#" 5.07915
+cap "a_831_n100#" "a_n129_n100#" 14.3638
+cap "a_1647_122#" "a_1263_122#" 14.0338
+cap "a_n1137_n188#" "a_n1617_122#" 1.97704
+cap "a_927_n100#" "a_1407_n100#" 30.0629
+cap "a_1311_n100#" "a_1503_n100#" 87.4087
+cap "a_n2817_n100#" "a_n1281_n100#" 8.83052
+cap "a_1791_n100#" "a_2847_n100#" 13.0056
+cap "a_159_n100#" "a_639_n100#" 30.0629
+cap "a_1887_n100#" "a_1839_122#" 6.25956
+cap "a_63_n100#" "a_1215_n100#" 11.882
+cap "a_2127_n188#" "a_2415_122#" 3.46589
+cap "a_n1809_122#" "a_n2001_122#" 34.1645
+cap "a_n321_n100#" "a_n417_n100#" 241.535
+cap "a_n657_122#" "a_n273_122#" 14.0338
+cap "a_n1665_n100#" "a_n2721_n100#" 13.0056
+cap "a_2175_n100#" "a_2847_n100#" 20.9177
+cap "a_2655_n100#" "a_1311_n100#" 10.1315
+cap "a_255_n100#" "a_735_n100#" 30.0629
+cap "a_n273_122#" "a_111_122#" 14.0338
+cap "a_303_122#" "a_687_122#" 14.0338
+cap "a_1983_n100#" "a_1407_n100#" 24.6699
+cap "a_n2001_122#" "a_n1521_n188#" 1.97704
+cap "a_399_n188#" "a_n849_122#" 0.727455
+cap "a_2463_n100#" "a_1023_n100#" 9.43637
+cap "a_n129_n100#" "a_n1473_n100#" 10.1315
+cap "a_n2909_n100#" "a_n2865_n188#" 6.25956
+cap "a_399_n188#" "a_n177_n188#" 8.83801
+cap "a_591_n188#" "a_783_n188#" 34.1645
+cap "a_1023_n100#" "a_n33_n100#" 13.0056
+cap "a_2415_122#" "a_1359_n188#" 0.863965
+cap "a_63_n100#" "a_n993_n100#" 13.0056
+cap "a_n2433_n100#" "a_n1377_n100#" 13.0056
+cap "a_n2049_n100#" "a_n2529_n100#" 30.0629
+cap "a_1791_n100#" "a_2175_n100#" 38.4743
+cap "a_n2049_n100#" "a_n1185_n100#" 16.0389
+cap "a_n1905_n188#" "a_n945_n188#" 5.07915
+cap "a_2751_n100#" "a_2847_n100#" 241.535
+cap "a_399_n188#" "a_447_n100#" 6.25956
+cap "a_n1329_n188#" "a_n81_122#" 0.727455
+cap "a_n33_n100#" "a_n1185_n100#" 11.882
+cap "a_399_n188#" "a_1167_n188#" 6.45081
+cap "a_n225_n100#" "a_n801_n100#" 24.6699
+cap "a_n1569_n100#" "a_n2049_n100#" 30.0629
+cap "a_351_n100#" "a_n417_n100#" 18.1562
+cap "a_879_122#" "a_2223_122#" 3.56376
+cap "a_1023_n100#" "a_2559_n100#" 8.83052
+cap "a_1503_n100#" "a_n129_n100#" 8.29777
+cap "a_255_n100#" "a_n1089_n100#" 10.1315
+cap "a_n1953_n100#" "a_n1281_n100#" 20.9177
+cap "a_n1809_122#" "a_n657_122#" 4.18859
+cap "a_1359_n188#" "a_n81_122#" 0.628198
+cap "a_n897_n100#" "a_n993_n100#" 241.535
+cap "a_n1569_n100#" "a_n33_n100#" 8.83052
+cap "a_n2337_n100#" "a_n2817_n100#" 30.0629
+cap "a_2319_n188#" "a_687_122#" 0.0858586
+cap "a_879_122#" "a_1839_122#" 5.07915
+cap "a_687_122#" "a_639_n100#" 6.25956
+cap "a_1743_n188#" "a_687_122#" 0.863965
+cap "a_1023_n100#" "a_159_n100#" 16.0389
+cap "a_n1665_n100#" "a_n705_n100#" 14.3638
+cap "a_2751_n100#" "a_1791_n100#" 14.3638
+cap "a_927_n100#" "a_n321_n100#" 10.9371
+cap "a_n1713_n188#" "a_n2001_122#" 3.46589
+cap "a_n513_n100#" "a_639_n100#" 11.882
+cap "a_543_n100#" "a_n705_n100#" 10.9371
+cap "a_159_n100#" "a_n1185_n100#" 10.1315
+cap "a_n1857_n100#" "a_n801_n100#" 13.0056
+cap "a_n1329_n188#" "a_n2673_n188#" 3.56376
+cap "a_n657_122#" "a_591_n188#" 0.727455
+cap "a_2079_n100#" "a_1887_n100#" 87.4087
+cap "a_n1137_n188#" "a_n1089_n100#" 6.25956
+cap "a_n2097_n188#" "a_n1425_122#" 1.38306
+cap "a_n657_122#" "a_n1521_n188#" 1.06355
+cap "a_543_n100#" "a_1791_n100#" 10.9371
+cap "a_n1329_n188#" "a_n2481_n188#" 4.18859
+cap "a_591_n188#" "a_111_122#" 1.97704
+cap "a_2751_n100#" "a_2175_n100#" 24.6699
+cap "a_1119_n100#" "a_255_n100#" 16.0389
+cap "a_111_122#" "a_n1521_n188#" 0.0858586
+cap "a_303_122#" "a_n945_n188#" 0.727455
+cap "a_n1281_n100#" "a_n1473_n100#" 87.4087
+cap "a_n1041_122#" "a_n945_n188#" 14.1667
+cap "a_447_n100#" "a_63_n100#" 38.4743
+cap "a_n2337_n100#" "a_n2289_n188#" 6.25956
+cap "a_1407_n100#" "a_735_n100#" 20.9177
+cap "a_1647_122#" "a_2799_122#" 4.18859
+cap "a_543_n100#" "a_2175_n100#" 8.29777
+cap "a_n2049_n100#" "a_n609_n100#" 9.43637
+cap "a_n2145_n100#" "a_n2625_n100#" 30.0629
+cap "a_n849_122#" "a_n897_n100#" 6.25956
+cap "a_n1905_n188#" "a_n1041_122#" 1.06355
+cap "a_n33_n100#" "a_n609_n100#" 24.6699
+cap "a_n2145_n100#" "a_n993_n100#" 11.882
+cap "a_687_122#" "a_2031_122#" 3.56376
+cap "a_591_n188#" "a_1455_122#" 1.06355
+cap "a_927_n100#" "a_351_n100#" 24.6699
+cap "a_831_n100#" "a_n417_n100#" 10.9371
+cap "a_447_n100#" "a_n897_n100#" 10.1315
+cap "a_n2097_n188#" "a_n1617_122#" 1.97704
+cap "a_n1329_n188#" "a_15_n188#" 3.56376
+cap "a_n2337_n100#" "a_n1953_n100#" 38.4743
+cap "a_n561_n188#" "a_n81_122#" 1.97704
+cap "a_n1377_n100#" "a_n321_n100#" 13.0056
+cap "a_n2241_n100#" "a_n897_n100#" 10.1315
+cap "a_2607_122#" "a_2223_122#" 14.0338
+cap "a_n657_122#" "a_n1713_n188#" 0.863965
+cap "a_n2433_n100#" "a_n1089_n100#" 10.1315
+cap "a_2607_122#" "a_1839_122#" 6.45081
+cap "a_1359_n188#" "a_15_n188#" 3.56376
+cap "a_n753_n188#" "a_n801_n100#" 6.25956
+cap "a_159_n100#" "a_n609_n100#" 18.1562
+cap "a_n1953_n100#" "a_n417_n100#" 8.83052
+cap "a_2079_n100#" "a_1215_n100#" 16.0389
+cap "a_1023_n100#" "a_n513_n100#" 8.83052
+cap "a_1551_n188#" "a_1647_122#" 14.1667
+cap "a_n2001_122#" "a_n1233_122#" 6.45081
+cap "a_n2145_n100#" "a_n2193_122#" 6.25956
+cap "a_2271_n100#" "a_1311_n100#" 14.3638
+cap "a_303_122#" "a_n1041_122#" 3.56376
+cap "a_399_n188#" "a_n465_122#" 1.06355
+cap "a_2367_n100#" "a_831_n100#" 8.83052
+cap "a_n513_n100#" "a_n1185_n100#" 20.9177
+cap "a_351_n100#" "a_1983_n100#" 8.29777
+cap "a_1647_122#" "a_1935_n188#" 3.46589
+cap "a_2223_122#" "a_1167_n188#" 0.863965
+cap "a_1695_n100#" "a_255_n100#" 9.43637
+cap "a_1167_n188#" "a_1839_122#" 1.38306
+cap "a_1119_n100#" "a_1407_n100#" 53.425
+cap "a_255_n100#" "a_n801_n100#" 13.0056
+cap "a_n2337_n100#" "a_n1473_n100#" 16.0389
+cap "a_n1569_n100#" "a_n513_n100#" 13.0056
+cap "a_n417_n100#" "a_n1473_n100#" 13.0056
+cap "a_n753_n188#" "a_n81_122#" 1.38306
+cap "a_n2241_n100#" "a_n2145_n100#" 241.535
+cap "a_927_n100#" "a_831_n100#" 241.535
+cap "a_n321_n100#" "a_735_n100#" 13.0056
+cap "a_n2001_122#" "a_n2577_122#" 8.83801
+cap "a_1743_n188#" "a_303_122#" 0.628198
+cap "a_879_122#" "a_783_n188#" 14.1667
+cap "a_n1425_122#" "a_n2289_n188#" 1.06355
+cap "a_2367_n100#" "a_1599_n100#" 18.1562
+cap "a_n2817_n100#" "a_n1377_n100#" 9.43637
+cap "a_399_n188#" "a_n369_n188#" 6.45081
+cap "a_n657_122#" "a_n1233_122#" 8.83801
+cap "a_n561_n188#" "a_15_n188#" 8.83801
+cap "a_n1809_122#" "a_n273_122#" 3.10116
+cap "a_n33_n100#" "a_n225_n100#" 87.4087
+cap "a_n1233_122#" "a_111_122#" 3.56376
+cap "a_1887_n100#" "a_2847_n100#" 14.3638
+cap "a_591_n188#" "a_543_n100#" 6.25956
+cap "a_n513_n100#" "a_n609_n100#" 241.535
+cap "a_1983_n100#" "a_831_n100#" 11.882
+cap "a_1311_n100#" "a_63_n100#" 10.9371
+cap "a_n321_n100#" "a_n1089_n100#" 18.1562
+cap "a_591_n188#" "a_n273_122#" 1.06355
+cap "a_927_n100#" "a_1599_n100#" 20.9177
+cap "a_n2049_n100#" "a_n1857_n100#" 87.4087
+cap "a_n273_122#" "a_n1521_n188#" 0.727455
+cap "a_n1137_n188#" "a_n81_122#" 0.863965
+cap "a_n657_122#" "a_879_122#" 3.10116
+cap "a_1743_n188#" "a_2319_n188#" 8.83801
+cap "a_n2289_n188#" "a_n1617_122#" 1.38306
+cap "a_351_n100#" "a_735_n100#" 38.4743
+cap "a_399_n188#" "a_495_122#" 14.1667
+cap "a_2127_n188#" "a_687_122#" 0.628198
+cap "a_2367_n100#" "a_1503_n100#" 16.0389
+cap "a_159_n100#" "a_n225_n100#" 38.4743
+cap "a_n897_n100#" "a_n1761_n100#" 16.0389
+cap "a_879_122#" "a_111_122#" 6.45081
+cap "a_1407_n100#" "a_1695_n100#" 53.425
+cap "a_2079_n100#" "a_447_n100#" 8.29777
+cap "a_n2433_n100#" "a_n801_n100#" 8.29777
+cap "a_1791_n100#" "a_1887_n100#" 241.535
+cap "a_n2001_122#" "a_n2193_122#" 34.1645
+cap "a_399_n188#" "a_975_n188#" 8.83801
+cap "a_1119_n100#" "a_n321_n100#" 9.43637
+cap "a_n2001_122#" "a_n849_122#" 4.18859
+cap "a_n753_n188#" "a_15_n188#" 6.45081
+cap "a_n1953_n100#" "a_n1377_n100#" 24.6699
+cap "a_n1425_122#" "a_n1473_n100#" 6.25956
+cap "a_n2865_n188#" "a_n1329_n188#" 3.10116
+cap "a_n1137_n188#" "a_n2673_n188#" 3.10116
+cap "a_1983_n100#" "a_1599_n100#" 38.4743
+cap "a_n1665_n100#" "a_n1713_n188#" 6.25956
+cap "a_1887_n100#" "a_2175_n100#" 53.425
+cap "a_2367_n100#" "a_2655_n100#" 53.425
+cap "a_927_n100#" "a_1503_n100#" 24.6699
+cap "a_n1137_n188#" "a_n2481_n188#" 3.56376
+cap "a_351_n100#" "a_n1089_n100#" 9.43637
+cap "a_2511_n188#" "a_2223_122#" 3.46589
+cap "a_n849_122#" "a_783_n188#" 0.0858586
+cap "a_687_122#" "a_1359_n188#" 1.38306
+cap "a_879_122#" "a_1455_122#" 8.83801
+cap "a_2511_n188#" "a_1839_122#" 1.38306
+cap "a_n1809_122#" "a_n1521_n188#" 3.46589
+cap "a_n177_n188#" "a_783_n188#" 5.07915
+cap "a_n2721_n100#" "a_n2625_n100#" 241.535
+cap "a_n1713_n188#" "a_n273_122#" 0.628198
+cap "a_n2529_n100#" "a_n2909_n100#" 38.4743
+cap "a_2607_122#" "a_2703_n188#" 14.1667
+cap "a_2319_n188#" "a_2031_122#" 3.46589
+cap "a_2847_n100#" "a_1215_n100#" 8.29777
+cap "a_1743_n188#" "a_2031_122#" 3.46589
+cap "a_n2001_122#" "a_n2769_122#" 6.45081
+cap "a_1647_122#" "a_1695_n100#" 6.25956
+cap "a_2751_n100#" "a_1887_n100#" 16.0389
+cap "a_63_n100#" "a_n129_n100#" 87.4087
+cap "a_1167_n188#" "a_783_n188#" 14.0338
+cap "a_n2145_n100#" "a_n1761_n100#" 38.4743
+cap "a_n1569_n100#" "a_n2909_n100#" 10.1315
+cap "a_831_n100#" "a_735_n100#" 241.535
+cap "a_n1377_n100#" "a_n1473_n100#" 241.535
+cap "a_1983_n100#" "a_1503_n100#" 30.0629
+cap "a_1023_n100#" "a_639_n100#" 38.4743
+cap "a_351_n100#" "a_1119_n100#" 18.1562
+cap "a_n657_122#" "a_n2193_122#" 3.10116
+cap "a_n1137_n188#" "a_15_n188#" 4.18859
+cap "a_1791_n100#" "a_1215_n100#" 24.6699
+cap "a_543_n100#" "a_1887_n100#" 10.1315
+cap "a_2415_122#" "a_1647_122#" 6.45081
+cap "a_n657_122#" "a_n849_122#" 34.1645
+cap "a_2703_n188#" "a_1167_n188#" 3.10116
+cap "a_n129_n100#" "a_n897_n100#" 18.1562
+cap "a_399_n188#" "a_207_n188#" 34.1645
+cap "a_n657_122#" "a_n177_n188#" 1.97704
+cap "a_n513_n100#" "a_n225_n100#" 53.425
+cap "a_n2433_n100#" "a_n2481_n188#" 6.25956
+cap "a_n849_122#" "a_111_122#" 5.07915
+cap "a_255_n100#" "a_n33_n100#" 53.425
+cap "a_n1809_122#" "a_n1713_n188#" 14.1667
+cap "a_n1329_n188#" "a_n945_n188#" 14.0338
+cap "a_n177_n188#" "a_111_122#" 3.46589
+cap "a_2175_n100#" "a_1215_n100#" 14.3638
+cap "a_n321_n100#" "a_n801_n100#" 30.0629
+cap "a_1983_n100#" "a_2655_n100#" 20.9177
+cap "a_1551_n188#" "a_1599_n100#" 6.25956
+cap "a_n1905_n188#" "a_n1329_n188#" 8.83801
+cap "a_1599_n100#" "a_735_n100#" 16.0389
+cap "a_n705_n100#" "a_n993_n100#" 53.425
+cap "a_n561_n188#" "a_687_122#" 0.727455
+cap "a_n1857_n100#" "a_n513_n100#" 10.1315
+cap "a_1167_n188#" "a_111_122#" 0.863965
+cap "a_2607_122#" "a_1455_122#" 4.18859
+cap "a_n1713_n188#" "a_n1521_n188#" 34.1645
+cap "a_n1233_122#" "a_n273_122#" 5.07915
+cap "a_159_n100#" "a_255_n100#" 241.535
+cap "a_n561_n188#" "a_n513_n100#" 6.25956
+cap "a_n1281_n100#" "a_63_n100#" 10.1315
+cap "a_495_122#" "a_1839_122#" 3.56376
+cap "a_975_n188#" "a_2223_122#" 0.727455
+cap "a_2751_n100#" "a_1215_n100#" 8.83052
+cap "a_n1953_n100#" "a_n1089_n100#" 16.0389
+cap "a_n2241_n100#" "a_n2721_n100#" 30.0629
+cap "a_1455_122#" "a_n177_n188#" 0.0858586
+cap "a_975_n188#" "a_1839_122#" 1.06355
+cap "a_2079_n100#" "a_1311_n100#" 18.1562
+cap "a_831_n100#" "a_1119_n100#" 53.425
+cap "a_n2721_n100#" "a_n2769_122#" 6.25956
+cap "a_399_n188#" "a_1071_122#" 1.38306
+cap "a_543_n100#" "a_1215_n100#" 20.9177
+cap "a_n1281_n100#" "a_n897_n100#" 38.4743
+cap "a_1167_n188#" "a_1455_122#" 3.46589
+cap "a_351_n100#" "a_1695_n100#" 10.1315
+cap "a_n609_n100#" "a_639_n100#" 10.9371
+cap "a_879_122#" "a_n273_122#" 4.18859
+cap "a_1551_n188#" "a_1503_n100#" 6.25956
+cap "a_1503_n100#" "a_735_n100#" 18.1562
+cap "a_351_n100#" "a_n801_n100#" 11.882
+cap "a_n2001_122#" "a_n465_122#" 3.10116
+cap "a_303_122#" "a_n1329_n188#" 0.0858586
+cap "a_n2433_n100#" "a_n2049_n100#" 38.4743
+cap "a_n1665_n100#" "a_n2625_n100#" 14.3638
+cap "a_n1041_122#" "a_n1329_n188#" 3.46589
+cap "a_687_122#" "a_n753_n188#" 0.628198
+cap "a_n1089_n100#" "a_n1473_n100#" 38.4743
+cap "a_n2529_n100#" "a_n1185_n100#" 10.1315
+cap "a_n2097_n188#" "a_n2673_n188#" 8.83801
+cap "a_399_n188#" "a_1263_122#" 1.06355
+cap "a_n465_122#" "a_783_n188#" 0.727455
+cap "a_2271_n100#" "a_2367_n100#" 241.535
+cap "a_2463_n100#" "a_1407_n100#" 13.0056
+cap "a_447_n100#" "a_n705_n100#" 11.882
+cap "a_n1809_122#" "a_n1233_122#" 8.83801
+cap "a_303_122#" "a_1359_n188#" 0.863965
+cap "a_n1665_n100#" "a_n993_n100#" 20.9177
+cap "a_n2097_n188#" "a_n2481_n188#" 14.0338
+cap "a_1407_n100#" "a_n33_n100#" 9.43637
+cap "a_2319_n188#" "a_2127_n188#" 34.1645
+cap "a_1119_n100#" "a_1599_n100#" 30.0629
+cap "a_1791_n100#" "a_447_n100#" 10.1315
+cap "a_n1569_n100#" "a_n1185_n100#" 38.4743
+cap "a_n2241_n100#" "a_n705_n100#" 8.83052
+cap "a_n1569_n100#" "a_n2529_n100#" 14.3638
+cap "a_1743_n188#" "a_2127_n188#" 14.0338
+cap "a_n561_n188#" "a_n945_n188#" 14.0338
+cap "a_n1905_n188#" "a_n1857_n100#" 6.25956
+cap "a_1647_122#" "a_15_n188#" 0.0858586
+cap "a_543_n100#" "a_n993_n100#" 8.83052
+cap "a_n1905_n188#" "a_n561_n188#" 3.56376
+cap "a_n1233_122#" "a_n1521_n188#" 3.46589
+cap "a_2511_n188#" "a_2703_n188#" 34.1645
+cap "a_n2001_122#" "a_n369_n188#" 0.0858586
+cap "a_1407_n100#" "a_2559_n100#" 11.882
+cap "a_n2001_122#" "a_n2385_122#" 14.0338
+cap "a_207_n188#" "a_1839_122#" 0.0858586
+cap "a_2271_n100#" "a_927_n100#" 10.1315
+cap "a_n2145_n100#" "a_n1281_n100#" 16.0389
+cap "a_159_n100#" "a_1407_n100#" 10.9371
+cap "a_n513_n100#" "a_255_n100#" 18.1562
+cap "a_63_n100#" "a_n417_n100#" 30.0629
+cap "a_n657_122#" "a_n465_122#" 34.1645
+cap "a_n369_n188#" "a_783_n188#" 4.18859
+cap "a_2319_n188#" "a_1359_n188#" 5.07915
+cap "a_831_n100#" "a_1695_n100#" 16.0389
+cap "a_n1809_122#" "a_n2577_122#" 6.45081
+cap "a_591_n188#" "a_879_122#" 3.46589
+cap "a_1743_n188#" "a_1359_n188#" 14.0338
+cap "a_831_n100#" "a_n801_n100#" 8.29777
+cap "a_1023_n100#" "a_n609_n100#" 8.29777
+cap "a_n2337_n100#" "a_n897_n100#" 9.43637
+cap "a_1119_n100#" "a_1503_n100#" 38.4743
+cap "a_n465_122#" "a_111_122#" 8.83801
+cap "a_n417_n100#" "a_n897_n100#" 30.0629
+cap "a_n609_n100#" "a_n1185_n100#" 24.6699
+cap "a_2127_n188#" "a_2031_122#" 14.1667
+cap "a_n273_122#" "a_n849_122#" 8.83801
+cap "a_n945_n188#" "a_n753_n188#" 34.1645
+cap "a_n2577_122#" "a_n1521_n188#" 0.863965
+cap "a_2271_n100#" "a_1983_n100#" 53.425
+cap "a_n1953_n100#" "a_n801_n100#" 11.882
+cap "a_n2909_n100#" "a_n1857_n100#" 13.0056
+cap "a_303_122#" "a_n561_n188#" 1.06355
+cap "a_n273_122#" "a_n177_n188#" 14.1667
+cap "a_n2721_n100#" "a_n1761_n100#" 14.3638
+cap "a_543_n100#" "a_447_n100#" 241.535
+cap "a_n1569_n100#" "a_n609_n100#" 14.3638
+cap "a_n2241_n100#" "a_n1665_n100#" 24.6699
+cap "a_n1905_n188#" "a_n753_n188#" 4.18859
+cap "a_n1713_n188#" "a_n1233_122#" 1.97704
+cap "a_n2097_n188#" "a_n2049_n100#" 6.25956
+cap "a_n1041_122#" "a_n561_n188#" 1.97704
+cap "a_n225_n100#" "a_639_n100#" 16.0389
+cap "a_2223_122#" "a_1071_122#" 4.18859
+cap "a_2655_n100#" "a_1119_n100#" 8.83052
+cap "a_n657_122#" "a_n369_n188#" 3.46589
+cap "a_495_122#" "a_783_n188#" 3.46589
+cap "a_1599_n100#" "a_1695_n100#" 241.535
+cap "a_n273_122#" "a_1167_n188#" 0.628198
+cap "a_1839_122#" "a_1071_122#" 6.45081
+cap "a_2511_n188#" "a_1455_122#" 0.863965
+cap "a_975_n188#" "a_783_n188#" 34.1645
+cap "a_n33_n100#" "a_n321_n100#" 53.425
+cap "a_n369_n188#" "a_111_122#" 1.97704
+cap "a_1359_n188#" "a_2031_122#" 1.38306
+cap "a_n2337_n100#" "a_n2145_n100#" 87.4087
+cap "a_n1809_122#" "a_n2193_122#" 14.0338
+cap "a_927_n100#" "a_63_n100#" 16.0389
+cap "a_n1473_n100#" "a_n801_n100#" 20.9177
+cap "a_2223_122#" "a_1263_122#" 5.07915
+cap "a_n2289_n188#" "a_n2673_n188#" 14.0338
+cap "a_1311_n100#" "a_2847_n100#" 8.83052
+cap "a_n1809_122#" "a_n849_122#" 5.07915
+cap "a_n1137_n188#" "a_n945_n188#" 34.1645
+cap "a_1263_122#" "a_1839_122#" 8.83801
+cap "a_n1713_n188#" "a_n2577_122#" 1.06355
+cap "a_n2289_n188#" "a_n2481_n188#" 34.1645
+cap "a_n1809_122#" "a_n177_n188#" 0.0858586
+cap "a_n705_n100#" "a_n1761_n100#" 13.0056
+cap "a_159_n100#" "a_n321_n100#" 30.0629
+cap "a_303_122#" "a_n753_n188#" 0.863965
+cap "a_1695_n100#" "a_1503_n100#" 87.4087
+cap "a_n2193_122#" "a_n1521_n188#" 1.38306
+cap "a_n1137_n188#" "a_n1905_n188#" 6.45081
+cap "a_n657_122#" "a_495_122#" 4.18859
+cap "a_n1041_122#" "a_n753_n188#" 3.46589
+cap "a_591_n188#" "a_n849_122#" 0.628198
+cap "a_n849_122#" "a_n1521_n188#" 1.38306
+cap "a_975_n188#" "a_n657_122#" 0.0858586
+cap "a_1791_n100#" "a_1311_n100#" 30.0629
+cap "a_1887_n100#" "a_1215_n100#" 20.9177
+cap "a_591_n188#" "a_n177_n188#" 6.45081
+cap "a_495_122#" "a_111_122#" 14.0338
+cap "a_n177_n188#" "a_n1521_n188#" 3.56376
+cap "a_351_n100#" "a_n33_n100#" 38.4743
+cap "a_975_n188#" "a_111_122#" 1.06355
+cap "a_n1809_122#" "a_n2769_122#" 5.07915
+cap "a_2271_n100#" "a_735_n100#" 8.83052
+cap "a_1023_n100#" "a_n225_n100#" 10.9371
+cap "a_303_122#" "a_255_n100#" 6.25956
+cap "a_1647_122#" "a_687_122#" 5.07915
+cap "a_591_n188#" "a_1167_n188#" 8.83801
+cap "a_n2049_n100#" "a_n2817_n100#" 18.1562
+cap "a_2655_n100#" "a_1695_n100#" 14.3638
+cap "a_1311_n100#" "a_2175_n100#" 16.0389
+cap "a_n225_n100#" "a_n1185_n100#" 14.3638
+cap "a_207_n188#" "a_783_n188#" 8.83801
+cap "a_63_n100#" "a_n1377_n100#" 9.43637
+cap "a_399_n188#" "a_1551_n188#" 4.18859
+cap "a_n2769_122#" "a_n1521_n188#" 0.727455
+cap "a_495_122#" "a_1455_122#" 5.07915
+cap "a_351_n100#" "a_159_n100#" 87.4087
+cap "a_n1137_n188#" "a_303_122#" 0.628198
+cap "a_n1569_n100#" "a_n225_n100#" 10.1315
+cap "a_n1713_n188#" "a_n2193_122#" 1.97704
+cap "a_399_n188#" "a_1935_n188#" 3.10116
+cap "a_975_n188#" "a_1455_122#" 1.97704
+cap "a_n1137_n188#" "a_n1041_122#" 14.1667
+cap "a_n1665_n100#" "a_n1761_n100#" 241.535
+cap "a_n2529_n100#" "a_n1857_n100#" 20.9177
+cap "a_n2097_n188#" "a_n2865_n188#" 6.45081
+cap "a_2751_n100#" "a_1311_n100#" 9.43637
+cap "a_n1377_n100#" "a_n897_n100#" 30.0629
+cap "a_n1857_n100#" "a_n1185_n100#" 20.9177
+cap "a_n1713_n188#" "a_n849_122#" 1.06355
+cap "a_n1233_122#" "a_n2577_122#" 3.56376
+cap "a_n1713_n188#" "a_n177_n188#" 3.10116
+cap "a_n273_122#" "a_n465_122#" 34.1645
+cap "a_255_n100#" "a_639_n100#" 38.4743
+cap "a_n705_n100#" "a_n129_n100#" 24.6699
+cap "a_n1569_n100#" "a_n1857_n100#" 53.425
+cap "a_543_n100#" "a_1311_n100#" 18.1562
+cap "a_n657_122#" "a_207_n188#" 1.06355
+cap "a_2463_n100#" "a_831_n100#" 8.29777
+cap "a_n513_n100#" "a_n321_n100#" 87.4087
+cap "a_831_n100#" "a_n33_n100#" 16.0389
+cap "a_n2721_n100#" "a_n1281_n100#" 9.43637
+cap "a_207_n188#" "a_111_122#" 14.1667
+cap "a_783_n188#" "a_1071_122#" 3.46589
+cap "a_2271_n100#" "a_1119_n100#" 11.882
+cap "a_n1713_n188#" "a_n2769_122#" 0.863965
+cap "a_2079_n100#" "a_2367_n100#" 53.425
+cap "a_63_n100#" "a_735_n100#" 20.9177
+cap "a_n2049_n100#" "a_n1953_n100#" 241.535
+cap "a_2127_n188#" "a_1359_n188#" 6.45081
+cap "a_n609_n100#" "a_n225_n100#" 38.4743
+cap "a_2223_122#" "a_2799_122#" 8.83801
+cap "a_447_n100#" "a_1887_n100#" 9.43637
+cap "a_n369_n188#" "a_n273_122#" 14.1667
+cap "a_2703_n188#" "a_1071_122#" 0.0858586
+cap "a_831_n100#" "a_159_n100#" 20.9177
+cap "a_1839_122#" "a_2799_122#" 5.07915
+cap "a_n2433_n100#" "a_n2909_n100#" 30.0629
+cap "a_2463_n100#" "a_1599_n100#" 16.0389
+cap "a_n2145_n100#" "a_n1377_n100#" 18.1562
+cap "a_n1809_122#" "a_n465_122#" 3.56376
+cap "a_1263_122#" "a_783_n188#" 1.97704
+cap "a_n897_n100#" "a_735_n100#" 8.29777
+cap "a_n2625_n100#" "a_n2577_122#" 6.25956
+cap "a_207_n188#" "a_1455_122#" 0.727455
+cap "a_1599_n100#" "a_n33_n100#" 8.29777
+cap "a_n1809_122#" "a_n1761_n100#" 6.25956
+cap "a_927_n100#" "a_2079_n100#" 11.882
+cap "a_n1857_n100#" "a_n609_n100#" 10.9371
+cap "a_n1233_122#" "a_n2193_122#" 5.07915
+cap "a_n2097_n188#" "a_n945_n188#" 4.18859
+cap "a_351_n100#" "a_n513_n100#" 16.0389
+cap "a_63_n100#" "a_n1089_n100#" 11.882
+cap "a_n705_n100#" "a_n1281_n100#" 24.6699
+cap "a_n2049_n100#" "a_n1473_n100#" 24.6699
+cap "a_n1233_122#" "a_n849_122#" 14.0338
+cap "a_591_n188#" "a_n465_122#" 0.863965
+cap "a_n561_n188#" "a_n609_n100#" 6.25956
+cap "a_n1665_n100#" "a_n129_n100#" 8.83052
+cap "a_n2865_n188#" "a_n2817_n100#" 6.25956
+cap "a_n2097_n188#" "a_n1905_n188#" 34.1645
+cap "a_2703_n188#" "a_1263_122#" 0.628198
+cap "a_1023_n100#" "a_255_n100#" 18.1562
+cap "a_n465_122#" "a_n1521_n188#" 0.863965
+cap "a_n1233_122#" "a_n177_n188#" 0.863965
+cap "a_n33_n100#" "a_n1473_n100#" 9.43637
+cap "a_111_122#" "a_1071_122#" 5.07915
+cap "a_1599_n100#" "a_2559_n100#" 14.3638
+cap "a_n2625_n100#" "a_n993_n100#" 8.29777
+cap "a_543_n100#" "a_n129_n100#" 20.9177
+cap "a_495_122#" "a_543_n100#" 6.25956
+cap "a_1551_n188#" "a_2223_122#" 1.38306
+cap "a_1407_n100#" "a_639_n100#" 18.1562
+cap "a_1599_n100#" "a_159_n100#" 9.43637
+cap "a_255_n100#" "a_n1185_n100#" 9.43637
+cap "a_495_122#" "a_n273_122#" 6.45081
+cap "a_n897_n100#" "a_n1089_n100#" 87.4087
+cap "a_303_122#" "a_1647_122#" 3.56376
+cap "a_n2337_n100#" "a_n2721_n100#" 38.4743
+cap "a_1551_n188#" "a_1839_122#" 3.46589
+cap "a_n1809_122#" "a_n369_n188#" 0.628198
+cap "a_975_n188#" "a_n273_122#" 0.727455
+cap "a_2463_n100#" "a_1503_n100#" 14.3638
+cap "a_2223_122#" "a_1935_n188#" 3.46589
+cap "a_n1809_122#" "a_n2385_122#" 8.83801
+cap "a_2079_n100#" "a_1983_n100#" 241.535
+cap "a_2271_n100#" "a_1695_n100#" 24.6699
+cap "a_1119_n100#" "a_63_n100#" 13.0056
+cap "a_1503_n100#" "a_n33_n100#" 8.83052
+cap "a_n1233_122#" "a_n2769_122#" 3.10116
+cap "a_879_122#" "a_n177_n188#" 0.863965
+cap "a_1839_122#" "a_1935_n188#" 14.1667
+cap "a_n2577_122#" "a_n2193_122#" 14.0338
+cap "a_1263_122#" "a_111_122#" 4.18859
+cap "a_159_n100#" "a_n1473_n100#" 8.29777
+cap "a_n2289_n188#" "a_n2865_n188#" 8.83801
+cap "a_n1425_122#" "a_n2001_122#" 8.83801
+cap "a_n1137_n188#" "a_n1185_n100#" 6.25956
+cap "a_591_n188#" "a_n369_n188#" 5.07915
+cap "a_1455_122#" "a_1071_122#" 14.0338
+cap "a_447_n100#" "a_1215_n100#" 18.1562
+cap "a_n369_n188#" "a_n1521_n188#" 4.18859
+cap "a_1167_n188#" "a_1215_n100#" 6.25956
+cap "a_n2385_122#" "a_n1521_n188#" 1.06355
+cap "a_879_122#" "a_1167_n188#" 3.46589
+cap "a_n561_n188#" "a_n1329_n188#" 6.45081
+cap "a_2559_n100#" "a_1503_n100#" 13.0056
+cap "a_n1713_n188#" "a_n465_122#" 0.727455
+cap "a_n2097_n188#" "a_n1041_122#" 0.863965
+cap "a_2463_n100#" "a_2655_n100#" 87.4087
+cap "a_831_n100#" "a_n513_n100#" 10.1315
+cap "a_159_n100#" "a_1503_n100#" 10.1315
+cap "a_n1713_n188#" "a_n1761_n100#" 6.25956
+cap "a_2319_n188#" "a_1647_122#" 1.38306
+cap "a_n1665_n100#" "a_n1281_n100#" 38.4743
+cap "a_1743_n188#" "a_1647_122#" 14.1667
+cap "a_1263_122#" "a_1455_122#" 34.1645
+cap "a_n2337_n100#" "a_n705_n100#" 8.29777
+cap "a_n2577_122#" "a_n2769_122#" 34.1645
+cap "a_n2145_n100#" "a_n1089_n100#" 13.0056
+cap "a_447_n100#" "a_n993_n100#" 9.43637
+cap "a_n1953_n100#" "a_n513_n100#" 9.43637
+cap "a_n2241_n100#" "a_n2625_n100#" 38.4743
+cap "a_n1617_122#" "a_n2001_122#" 14.0338
+cap "a_255_n100#" "a_n609_n100#" 16.0389
+cap "a_495_122#" "a_591_n188#" 14.1667
+cap "a_2655_n100#" "a_2559_n100#" 241.535
+cap "a_1023_n100#" "a_1407_n100#" 38.4743
+cap "a_n705_n100#" "a_n417_n100#" 53.425
+cap "a_n1857_n100#" "a_n225_n100#" 8.29777
+cap "a_n2241_n100#" "a_n993_n100#" 10.9371
+cap "a_975_n188#" "a_591_n188#" 14.0338
+cap "a_n2433_n100#" "a_n1185_n100#" 10.9371
+cap "a_n2433_n100#" "a_n2529_n100#" 241.535
+cap "a_n1425_122#" "a_n657_122#" 6.45081
+cap "a_207_n188#" "a_n273_122#" 1.97704
+cap "a_399_n188#" "a_n81_122#" 1.97704
+cap "a_n1713_n188#" "a_n369_n188#" 3.56376
+cap "a_n1713_n188#" "a_n2385_122#" 1.38306
+cap "a_n849_122#" "a_n2193_122#" 3.56376
+cap "a_2367_n100#" "a_2847_n100#" 30.0629
+cap "a_1887_n100#" "a_1311_n100#" 24.6699
+cap "a_1695_n100#" "a_63_n100#" 8.29777
+cap "a_n321_n100#" "a_639_n100#" 14.3638
+cap "a_n2289_n188#" "a_n945_n188#" 3.56376
+cap "a_n1425_122#" "a_111_122#" 3.10116
+cap "a_n1329_n188#" "a_n753_n188#" 8.83801
+cap "a_2079_n100#" "a_735_n100#" 10.1315
+cap "a_n2433_n100#" "a_n1569_n100#" 16.0389
+cap "a_351_n100#" "a_303_122#" 6.25956
+cap "a_63_n100#" "a_n801_n100#" 16.0389
+cap "a_n2289_n188#" "a_n1905_n188#" 14.0338
+cap "a_n849_122#" "a_n177_n188#" 1.38306
+cap "a_n513_n100#" "a_n1473_n100#" 14.3638
+cap "a_1647_122#" "a_2031_122#" 14.0338
+cap "a_2607_122#" "a_1167_n188#" 0.628198
+cap "a_n2241_n100#" "a_n2193_122#" 6.25956
+cap "a_2703_n188#" "a_2799_122#" 14.1667
+cap "a_2367_n100#" "a_1791_n100#" 24.6699
+cap "a_n1233_122#" "a_n465_122#" 6.45081
+cap "a_n897_n100#" "a_n801_n100#" 241.535
+cap "a_n2193_122#" "a_n2769_122#" 8.83801
+cap "a_n2337_n100#" "a_n1665_n100#" 20.9177
+cap "a_n2909_n100#" "a_n2817_n100#" 241.535
+cap "a_n657_122#" "a_n1617_122#" 5.07915
+cap "a_1167_n188#" "a_n177_n188#" 3.56376
+cap "a_n1665_n100#" "a_n417_n100#" 10.9371
+cap "a_n1905_n188#" "a_n1953_n100#" 6.25956
+cap "a_n273_122#" "a_1071_122#" 3.56376
+cap "a_2367_n100#" "a_2175_n100#" 87.4087
+cap "a_927_n100#" "a_n705_n100#" 8.29777
+cap "a_1551_n188#" "a_783_n188#" 6.45081
+cap "a_735_n100#" "a_783_n188#" 6.25956
+cap "a_351_n100#" "a_639_n100#" 53.425
+cap "a_n1137_n188#" "a_n1329_n188#" 34.1645
+cap "a_879_122#" "a_n465_122#" 3.56376
+cap "a_927_n100#" "a_1791_n100#" 16.0389
+cap "a_543_n100#" "a_n417_n100#" 14.3638
+cap "a_n2721_n100#" "a_n1377_n100#" 10.1315
+cap "a_591_n188#" "a_207_n188#" 14.0338
+cap "a_1935_n188#" "a_783_n188#" 4.18859
+cap "a_2511_n188#" "a_879_122#" 0.0858586
+cap "a_1311_n100#" "a_1215_n100#" 241.535
+cap "a_1551_n188#" "a_2703_n188#" 4.18859
+cap "a_n1233_122#" "a_n369_n188#" 1.06355
+cap "a_1983_n100#" "a_2847_n100#" 16.0389
+cap "a_n2385_122#" "a_n1233_122#" 4.18859
+cap "a_n2289_n188#" "a_n1041_122#" 0.727455
+cap "a_399_n188#" "a_15_n188#" 14.0338
+cap "a_2079_n100#" "a_1119_n100#" 14.3638
+cap "a_1023_n100#" "a_n321_n100#" 10.1315
+cap "a_n273_122#" "a_1263_122#" 3.10116
+cap "a_2367_n100#" "a_2751_n100#" 38.4743
+cap "a_2703_n188#" "a_1935_n188#" 6.45081
+cap "a_927_n100#" "a_2175_n100#" 10.9371
+cap "a_255_n100#" "a_n225_n100#" 30.0629
+cap "a_2415_122#" "a_2223_122#" 34.1645
+cap "a_n321_n100#" "a_n1185_n100#" 16.0389
+cap "a_n2145_n100#" "a_n801_n100#" 10.1315
+cap "a_n2625_n100#" "a_n1761_n100#" 16.0389
+cap "a_2415_122#" "a_1839_122#" 8.83801
+cap "a_n561_n188#" "a_n753_n188#" 34.1645
+cap "a_2271_n100#" "a_2463_n100#" 87.4087
+cap "a_1455_122#" "a_2799_122#" 3.56376
+cap "a_1983_n100#" "a_1791_n100#" 87.4087
+cap "a_879_122#" "a_n369_n188#" 0.727455
+cap "a_n1569_n100#" "a_n321_n100#" 10.9371
+cap "a_n993_n100#" "a_n1761_n100#" 18.1562
+cap "a_1551_n188#" "a_111_122#" 0.628198
+cap "a_n2909_n100#" "a_n1953_n100#" 14.3638
+cap "a_2847_n100#" "a_2799_122#" 6.25956
+cap "a_n705_n100#" "a_n1377_n100#" 20.9177
+cap "a_n2385_122#" "a_n2577_122#" 34.1645
+cap "a_591_n188#" "a_1071_122#" 1.97704
+cap "a_2271_n100#" "a_2559_n100#" 53.425
+cap "a_1983_n100#" "a_2175_n100#" 87.4087
+cap "a_831_n100#" "a_639_n100#" 87.4087
+cap "a_351_n100#" "a_1023_n100#" 20.9177
+cap "a_927_n100#" "a_543_n100#" 38.4743
+cap "a_1407_n100#" "a_1359_n188#" 6.25956
+cap "a_63_n100#" "a_15_n188#" 6.25956
+cap "a_351_n100#" "a_n1185_n100#" 8.83052
+cap "a_1551_n188#" "a_1455_122#" 14.1667
+cap "a_2511_n188#" "a_2607_122#" 14.1667
+cap "a_n1137_n188#" "a_n561_n188#" 8.83801
+cap "a_n465_122#" "a_n849_122#" 14.0338
+cap "a_495_122#" "a_879_122#" 14.0338
+cap "a_n129_n100#" "a_1215_n100#" 10.1315
+cap "a_2127_n188#" "a_1647_122#" 1.97704
+cap "a_591_n188#" "a_1263_122#" 1.38306
+cap "a_1983_n100#" "a_2751_n100#" 18.1562
+cap "a_n2909_n100#" "a_n1473_n100#" 9.43637
+cap "a_1455_122#" "a_1935_n188#" 1.97704
+cap "a_n1425_122#" "a_n273_122#" 4.18859
+cap "a_n465_122#" "a_n177_n188#" 3.46589
+cap "a_975_n188#" "a_879_122#" 14.1667
+cap "a_2079_n100#" "a_1695_n100#" 38.4743
+cap "a_n609_n100#" "a_n321_n100#" 53.425
+cap "a_n2529_n100#" "a_n2817_n100#" 53.425
+cap "a_n2721_n100#" "a_n1089_n100#" 8.29777
+cap "a_n2817_n100#" "a_n1185_n100#" 8.29777
+cap "a_1599_n100#" "a_639_n100#" 14.3638
+cap "a_1167_n188#" "a_n465_122#" 0.0858586
+cap "a_1983_n100#" "a_543_n100#" 9.43637
+cap "a_1407_n100#" "a_n225_n100#" 8.29777
+cap "a_n705_n100#" "a_735_n100#" 9.43637
+cap "a_n1569_n100#" "a_n2817_n100#" 10.9371
+cap "a_2511_n188#" "a_1167_n188#" 3.56376
+cap "a_447_n100#" "a_1311_n100#" 16.0389
+cap "a_63_n100#" "a_n33_n100#" 241.535
+cap "a_n1665_n100#" "a_n1377_n100#" 53.425
+cap "a_n2241_n100#" "a_n1761_n100#" 30.0629
+cap "a_n1233_122#" "a_n1281_n100#" 6.25956
+cap "a_n1665_n100#" "a_n1617_122#" 6.25956
+cap "a_n2385_122#" "a_n2193_122#" 34.1645
+cap "a_1791_n100#" "a_735_n100#" 13.0056
+cap "a_1647_122#" "a_1359_n188#" 3.46589
+cap "a_n129_n100#" "a_n993_n100#" 16.0389
+cap "a_2751_n100#" "a_2799_122#" 6.25956
+cap "a_n369_n188#" "a_n849_122#" 1.97704
+cap "a_n2049_n100#" "a_n897_n100#" 11.882
+cap "a_n2433_n100#" "a_n1857_n100#" 24.6699
+cap "a_n2385_122#" "a_n849_122#" 3.10116
+cap "a_n369_n188#" "a_n177_n188#" 34.1645
+cap "a_1023_n100#" "a_831_n100#" 87.4087
+cap "a_n1617_122#" "a_n273_122#" 3.56376
+cap "a_207_n188#" "a_n1233_122#" 0.628198
+cap "a_n33_n100#" "a_n897_n100#" 16.0389
+cap "a_n2097_n188#" "a_n1329_n188#" 6.45081
+cap "a_n1137_n188#" "a_n753_n188#" 14.0338
+cap "a_n1809_122#" "a_n1425_122#" 14.0338
+cap "a_2175_n100#" "a_735_n100#" 9.43637
+cap "a_159_n100#" "a_63_n100#" 241.535
+cap "a_351_n100#" "a_n609_n100#" 14.3638
+cap "a_1503_n100#" "a_639_n100#" 16.0389
+cap "a_n705_n100#" "a_n1089_n100#" 38.4743
+cap "a_n369_n188#" "a_1167_n188#" 3.10116
+cap "a_399_n188#" "a_687_122#" 3.46589
+cap "a_n2385_122#" "a_n2769_122#" 14.0338
+cap "a_n1425_122#" "a_n1521_n188#" 14.1667
+cap "a_879_122#" "a_207_n188#" 1.38306
+cap "a_2415_122#" "a_783_n188#" 0.0858586
+cap "a_n2529_n100#" "a_n1953_n100#" 24.6699
+cap "a_159_n100#" "a_n897_n100#" 13.0056
+cap "a_n1953_n100#" "a_n1185_n100#" 18.1562
+cap "a_495_122#" "a_n849_122#" 3.56376
+cap "a_975_n188#" "a_2607_122#" 0.0858586
+cap "a_1023_n100#" "a_1599_n100#" 24.6699
+cap "a_n177_n188#" "a_n129_n100#" 6.25956
+cap "a_n2625_n100#" "a_n1281_n100#" 10.1315
+cap "a_495_122#" "a_n177_n188#" 1.38306
+cap "a_n1569_n100#" "a_n1953_n100#" 38.4743
+cap "a_975_n188#" "a_n177_n188#" 4.18859
+cap "a_447_n100#" "a_n129_n100#" 24.6699
+cap "a_495_122#" "a_447_n100#" 6.25956
+cap "a_2703_n188#" "a_2415_122#" 3.46589
+cap "a_n1809_122#" "a_n1617_122#" 34.1645
+cap "a_543_n100#" "a_735_n100#" 87.4087
+cap "a_n1281_n100#" "a_n993_n100#" 53.425
+cap "a_n2145_n100#" "a_n2049_n100#" 241.535
+cap "a_n81_122#" "a_783_n188#" 1.06355
+cap "a_1791_n100#" "a_1119_n100#" 20.9177
+cap "a_495_122#" "a_1167_n188#" 1.38306
+cap "a_n321_n100#" "a_n225_n100#" 241.535
+cap "a_975_n188#" "a_1167_n188#" 34.1645
+cap "a_2367_n100#" "a_1887_n100#" 30.0629
+cap "a_n2001_122#" "a_n2673_n188#" 1.38306
+cap "a_n1185_n100#" "a_n1473_n100#" 53.425
+cap "a_n2529_n100#" "a_n1473_n100#" 13.0056
+cap "a_n1617_122#" "a_n1521_n188#" 14.1667
+cap "a_1119_n100#" "a_2175_n100#" 13.0056
+cap "a_831_n100#" "a_n609_n100#" 9.43637
+cap "a_n2001_122#" "a_n2481_n188#" 1.97704
+cap "a_n1425_122#" "a_n1713_n188#" 3.46589
+cap "a_n1665_n100#" "a_n1089_n100#" 24.6699
+cap "a_879_122#" "a_1071_122#" 34.1645
+cap "a_1023_n100#" "a_1503_n100#" 30.0629
+cap "a_n1569_n100#" "a_n1473_n100#" 241.535
+cap "a_n1857_n100#" "a_n321_n100#" 8.83052
+cap "a_n2097_n188#" "a_n561_n188#" 3.10116
+cap "a_1407_n100#" "a_255_n100#" 11.882
+cap "a_543_n100#" "a_n1089_n100#" 8.29777
+cap "a_n513_n100#" "a_63_n100#" 24.6699
+cap "a_399_n188#" "a_n945_n188#" 3.56376
+cap "a_n657_122#" "a_n81_122#" 8.83801
+cap "a_927_n100#" "a_1887_n100#" 14.3638
+cap "a_n417_n100#" "a_1215_n100#" 8.29777
+cap "a_n1953_n100#" "a_n609_n100#" 10.1315
+cap "a_2751_n100#" "a_1119_n100#" 8.29777
+cap "a_n81_122#" "a_111_122#" 34.1645
+cap "a_2847_n100#" "a_1695_n100#" 11.882
+cap "a_879_122#" "a_1263_122#" 14.0338
+cap "a_351_n100#" "a_n225_n100#" 24.6699
+cap "a_n2337_n100#" "a_n2625_n100#" 53.425
+cap "a_1263_122#" "a_1215_n100#" 6.25956
+cap "a_207_n188#" "a_n849_122#" 0.863965
+cap "a_2655_n100#" "a_1023_n100#" 8.29777
+cap "a_n513_n100#" "a_n897_n100#" 38.4743
+cap "a_2415_122#" "a_1455_122#" 5.07915
+cap "a_n2289_n188#" "a_n1329_n188#" 5.07915
+cap "a_207_n188#" "a_n177_n188#" 14.0338
+cap "a_2463_n100#" "a_2079_n100#" 38.4743
+cap "a_543_n100#" "a_1119_n100#" 24.6699
+cap "a_n1617_122#" "a_n1713_n188#" 14.1667
+cap "a_n2241_n100#" "a_n1281_n100#" 14.3638
+cap "a_n2337_n100#" "a_n993_n100#" 10.1315
+cap "a_n369_n188#" "a_n465_122#" 14.1667
+cap "a_1551_n188#" "a_591_n188#" 5.07915
+cap "a_n705_n100#" "a_n801_n100#" 241.535
+cap "a_1791_n100#" "a_1695_n100#" 241.535
+cap "a_15_n188#" "a_783_n188#" 6.45081
+cap "a_1983_n100#" "a_1887_n100#" 241.535
+cap "a_2367_n100#" "a_1215_n100#" 11.882
+cap "a_207_n188#" "a_1167_n188#" 5.07915
+cap "a_2223_122#" "a_687_122#" 3.10116
+cap "a_591_n188#" "a_1935_n188#" 3.56376
+cap "a_n417_n100#" "a_n993_n100#" 24.6699
+cap "a_n609_n100#" "a_n1473_n100#" 16.0389
+cap "a_1455_122#" "a_n81_122#" 3.10116
+cap "a_n2097_n188#" "a_n753_n188#" 3.56376
+cap "a_1839_122#" "a_687_122#" 4.18859
+cap "a_2079_n100#" "a_2559_n100#" 30.0629
+cap "a_n2049_n100#" "a_n2001_122#" 6.25956
+cap "a_n2721_n100#" "a_n2673_n188#" 6.25956
+cap "a_399_n188#" "a_303_122#" 14.1667
+cap "a_2175_n100#" "a_1695_n100#" 30.0629
+cap "a_n1857_n100#" "a_n2817_n100#" 14.3638
+cap "a_n1425_122#" "a_n1233_122#" 34.1645
+cap "a_399_n188#" "a_n1041_122#" 0.628198
+cap "a_2607_122#" "a_1071_122#" 3.10116
+cap "a_927_n100#" "a_879_122#" 6.25956
+cap "a_495_122#" "a_n465_122#" 5.07915
+cap "a_927_n100#" "a_1215_n100#" 53.425
+cap "a_n129_n100#" "a_n1761_n100#" 8.29777
+cap "a_n945_n188#" "a_n897_n100#" 6.25956
+cap "a_n2145_n100#" "a_n513_n100#" 8.29777
+cap "a_n657_122#" "a_15_n188#" 1.38306
+cap "a_975_n188#" "a_n465_122#" 0.628198
+cap "a_n177_n188#" "a_1071_122#" 0.727455
+cap "a_2271_n100#" "a_2319_n188#" 6.25956
+cap "a_1311_n100#" "a_n129_n100#" 9.43637
+cap "a_831_n100#" "a_n225_n100#" 13.0056
+cap "a_2511_n188#" "a_975_n188#" 3.10116
+cap "a_2751_n100#" "a_1695_n100#" 13.0056
+cap "a_2271_n100#" "a_639_n100#" 8.29777
+cap "a_255_n100#" "a_n321_n100#" 24.6699
+cap "a_15_n188#" "a_111_122#" 14.1667
+cap "a_2607_122#" "a_1263_122#" 3.56376
+cap "a_1167_n188#" "a_1071_122#" 14.1667
+cap "a_n1665_n100#" "a_n801_n100#" 16.0389
+cap "a_n2097_n188#" "a_n1137_n188#" 5.07915
+cap "a_n2337_n100#" "a_n2241_n100#" 241.535
+cap "a_543_n100#" "a_1695_n100#" 11.882
+cap "a_447_n100#" "a_n417_n100#" 16.0389
+cap "a_n1425_122#" "a_n2577_122#" 4.18859
+cap "a_n1617_122#" "a_n1233_122#" 14.0338
+cap "a_399_n188#" "a_1743_n188#" 3.56376
+cap "a_543_n100#" "a_n801_n100#" 10.1315
+cap "a_1983_n100#" "a_1215_n100#" 18.1562
+cap "a_1263_122#" "a_n177_n188#" 0.628198
+cap "a_495_122#" "a_n369_n188#" 1.06355
+cap "a_975_n188#" "a_n369_n188#" 3.56376
+cap "a_1887_n100#" "a_735_n100#" 11.882
+cap "a_1455_122#" "a_15_n188#" 0.628198
+cap "a_1263_122#" "a_1167_n188#" 14.1667
+cap "a_n1857_n100#" "a_n1953_n100#" 241.535
+cap "a_1887_n100#" "a_1935_n188#" 6.25956
+cap "a_351_n100#" "a_255_n100#" 241.535
+cap "a_n2049_n100#" "a_n2721_n100#" 20.9177
+cap "a_n1281_n100#" "a_n1761_n100#" 30.0629
+cap "a_n225_n100#" "a_n1473_n100#" 10.9371
+cap "a_n1617_122#" "a_n2577_122#" 5.07915
+cap "a_207_n188#" "a_n465_122#" 1.38306
+cap "a_n273_122#" "a_n81_122#" 34.1645
+cap "a_n2625_n100#" "a_n1377_n100#" 10.9371
+cap "a_2271_n100#" "a_1023_n100#" 10.9371
+cap "a_399_n188#" "a_2031_122#" 0.0858586
+cap "a_63_n100#" "a_639_n100#" 24.6699
+cap "a_159_n100#" "a_111_122#" 6.25956
+cap "a_n1425_122#" "a_n2193_122#" 6.45081
+cap "a_n2289_n188#" "a_n753_n188#" 3.10116
+cap "a_n2001_122#" "a_n2865_n188#" 1.06355
+cap "a_975_n188#" "a_495_122#" 1.97704
+cap "a_n1377_n100#" "a_n993_n100#" 38.4743
+cap "a_n1857_n100#" "a_n1473_n100#" 38.4743
+cap "a_n1425_122#" "a_n849_122#" 8.83801
+cap "a_927_n100#" "a_447_n100#" 30.0629
+cap "a_2463_n100#" "a_2847_n100#" 38.4743
+cap "a_n1425_122#" "a_n177_n188#" 0.727455
+cap "a_303_122#" "a_1839_122#" 3.10116
+cap "a_687_122#" "a_783_n188#" 14.1667
+cap "a_n897_n100#" "a_639_n100#" 8.83052
+cap "a_n2049_n100#" "a_n705_n100#" 10.1315
+cap "a_1551_n188#" "a_879_122#" 1.38306
+cap "a_1215_n100#" "a_735_n100#" 30.0629
+cap "a_1887_n100#" "a_1119_n100#" 18.1562
+cap "a_207_n188#" "a_n369_n188#" 8.83801
+cap "a_n705_n100#" "a_n33_n100#" 20.9177
+cap "a_879_122#" "a_1935_n188#" 0.863965
+cap "a_2463_n100#" "a_1791_n100#" 20.9177
+cap "a_2559_n100#" "a_2847_n100#" 53.425
+cap "a_831_n100#" "a_255_n100#" 24.6699
+cap "a_n1425_122#" "a_n2769_122#" 3.56376
+cap "a_n2145_n100#" "a_n2909_n100#" 18.1562
+cap "a_n1617_122#" "a_n2193_122#" 8.83801
+cap "a_n465_122#" "a_1071_122#" 3.10116
+cap "a_1983_n100#" "a_447_n100#" 8.83052
+cap "a_2511_n188#" "a_1071_122#" 0.628198
+cap "a_n2337_n100#" "a_n1761_n100#" 24.6699
+cap "a_2319_n188#" "a_2223_122#" 14.1667
+cap "a_n1137_n188#" "a_n2289_n188#" 4.18859
+cap "a_351_n100#" "a_1407_n100#" 13.0056
+cap "a_2607_122#" "a_2799_122#" 34.1645
+cap "a_1743_n188#" "a_2223_122#" 1.97704
+cap "a_n1617_122#" "a_n849_122#" 6.45081
+cap "a_n1281_n100#" "a_n129_n100#" 11.882
+cap "a_n465_122#" "a_n417_n100#" 6.25956
+cap "a_2319_n188#" "a_1839_122#" 1.97704
+cap "a_n657_122#" "a_687_122#" 3.56376
+cap "a_2463_n100#" "a_2175_n100#" 53.425
+cap "a_1743_n188#" "a_1839_122#" 14.1667
+cap "a_n1617_122#" "a_n177_n188#" 0.628198
+cap "a_591_n188#" "a_n81_122#" 1.38306
+cap "a_1791_n100#" "a_2559_n100#" 18.1562
+cap "a_n705_n100#" "a_159_n100#" 16.0389
+cap "a_n417_n100#" "a_n1761_n100#" 10.1315
+cap "a_n81_122#" "a_n1521_n188#" 0.628198
+cap "a_687_122#" "a_111_122#" 8.83801
+cap "a_1791_n100#" "a_159_n100#" 8.29777
+cap "a_1023_n100#" "a_63_n100#" 14.3638
+cap "a_n2433_n100#" "a_n2817_n100#" 38.4743
+cap "a_n2001_122#" "a_n945_n188#" 0.863965
+cap "a_n273_122#" "a_15_n188#" 3.46589
+cap "a_495_122#" "a_207_n188#" 3.46589
+cap "a_n1809_122#" "a_n2673_n188#" 1.06355
+cap "a_n2241_n100#" "a_n1377_n100#" 16.0389
+cap "a_2511_n188#" "a_1263_122#" 0.727455
+cap "a_975_n188#" "a_207_n188#" 6.45081
+cap "a_1599_n100#" "a_255_n100#" 10.1315
+cap "a_63_n100#" "a_n1185_n100#" 10.9371
+cap "a_n1809_122#" "a_n2481_n188#" 1.38306
+cap "a_n2001_122#" "a_n1905_n188#" 14.1667
+cap "a_2463_n100#" "a_2751_n100#" 53.425
+cap "a_1311_n100#" "a_1263_122#" 6.25956
+cap "a_n369_n188#" "a_1071_122#" 0.628198
+cap "a_1167_n188#" "a_2799_122#" 0.0858586
+cap "a_2175_n100#" "a_2559_n100#" 38.4743
+cap "a_n1617_122#" "a_n2769_122#" 4.18859
+cap "a_n1665_n100#" "a_n2049_n100#" 38.4743
+cap "a_n2337_n100#" "a_n2385_122#" 6.25956
+cap "a_n2625_n100#" "a_n1089_n100#" 8.83052
+cap "a_1119_n100#" "a_1215_n100#" 241.535
+cap "a_n1569_n100#" "a_63_n100#" 8.29777
+cap "a_n2673_n188#" "a_n1521_n188#" 4.18859
+cap "a_n369_n188#" "a_n417_n100#" 6.25956
+cap "a_n1665_n100#" "a_n33_n100#" 8.29777
+cap "a_1551_n188#" "a_2607_122#" 0.863965
+cap "a_687_122#" "a_1455_122#" 6.45081
+cap "a_1887_n100#" "a_1695_n100#" 87.4087
+cap "a_n993_n100#" "a_n1089_n100#" 241.535
+cap "a_n897_n100#" "a_n1185_n100#" 53.425
+cap "a_n2529_n100#" "a_n897_n100#" 8.29777
+cap "a_n2481_n188#" "a_n1521_n188#" 5.07915
+cap "a_543_n100#" "a_n33_n100#" 24.6699
+cap "a_2367_n100#" "a_1311_n100#" 13.0056
+cap "a_2223_122#" "a_2031_122#" 34.1645
+cap "a_2751_n100#" "a_2559_n100#" 87.4087
+cap "a_2607_122#" "a_1935_n188#" 1.38306
+cap "a_n369_n188#" "a_1263_122#" 0.0858586
+cap "a_n1713_n188#" "a_n81_122#" 0.0858586
+cap "a_n1569_n100#" "a_n897_n100#" 20.9177
+cap "a_1839_122#" "a_2031_122#" 34.1645
+cap "a_831_n100#" "a_1407_n100#" 24.6699
+cap "a_255_n100#" "a_1503_n100#" 10.9371
+cap "a_447_n100#" "a_735_n100#" 53.425
+cap "a_n657_122#" "a_n945_n188#" 3.46589
+cap "a_495_122#" "a_1071_122#" 8.83801
+cap "a_1551_n188#" "a_1167_n188#" 14.0338
+cap "a_543_n100#" "a_159_n100#" 38.4743
+cap "a_n2001_122#" "a_n1041_122#" 5.07915
+cap "a_975_n188#" "a_1071_122#" 14.1667
+cap "a_927_n100#" "a_1311_n100#" 38.4743
+cap "a_n2433_n100#" "a_n1953_n100#" 30.0629
+cap "a_n657_122#" "a_n1905_n188#" 0.727455
+cap "a_n1425_122#" "a_n465_122#" 5.07915
+cap "a_n945_n188#" "a_111_122#" 0.863965
+cap "a_591_n188#" "a_15_n188#" 8.83801
+cap "a_n129_n100#" "a_n417_n100#" 53.425
+cap "a_15_n188#" "a_n1521_n188#" 3.10116
+cap "a_1167_n188#" "a_1935_n188#" 6.45081
+cap "a_2079_n100#" "a_639_n100#" 9.43637
+cap "a_351_n100#" "a_n321_n100#" 20.9177
+cap "a_n705_n100#" "a_n513_n100#" 87.4087
+cap "a_303_122#" "a_783_n188#" 1.97704
+cap "a_63_n100#" "a_n609_n100#" 20.9177
+cap "a_n1713_n188#" "a_n2673_n188#" 5.07915
+cap "a_n1713_n188#" "a_n2481_n188#" 6.45081
+cap "a_495_122#" "a_1263_122#" 6.45081
+cap "a_399_n188#" "a_1359_n188#" 5.07915
+cap "a_n2145_n100#" "a_n2529_n100#" 38.4743
+cap "a_1599_n100#" "a_1407_n100#" 87.4087
+cap "a_n2145_n100#" "a_n1185_n100#" 14.3638
+cap "a_447_n100#" "a_n1089_n100#" 8.83052
+cap "a_975_n188#" "a_1263_122#" 3.46589
+cap "a_n609_n100#" "a_n897_n100#" 53.425
+cap "a_1695_n100#" "a_1215_n100#" 30.0629
+cap "a_1983_n100#" "a_1311_n100#" 20.9177
+cap "a_n2145_n100#" "a_n1569_n100#" 24.6699
+cap "a_n2241_n100#" "a_n1089_n100#" 11.882
+cap "a_n2433_n100#" "a_n1473_n100#" 14.3638
+cap "a_n1425_122#" "a_n2385_122#" 5.07915
+cap "a_n1617_122#" "a_n465_122#" 4.18859
+cap "a_n1425_122#" "a_n369_n188#" 0.863965
+cap "a_n1377_n100#" "a_n1761_n100#" 38.4743
+cap "a_n2097_n188#" "a_n2289_n188#" 34.1645
+cap "a_n1233_122#" "a_n81_122#" 4.18859
+cap "a_n657_122#" "a_303_122#" 5.07915
+cap "a_2319_n188#" "a_783_n188#" 3.10116
+cap "a_n2337_n100#" "a_n1281_n100#" 13.0056
+cap "a_1743_n188#" "a_783_n188#" 5.07915
+cap "a_879_122#" "a_2415_122#" 3.10116
+cap "a_447_n100#" "a_1119_n100#" 20.9177
+cap "a_n657_122#" "a_n1041_122#" 14.0338
+cap "a_2079_n100#" "a_2031_122#" 6.25956
+cap "a_2511_n188#" "a_2799_122#" 3.46589
+cap "a_303_122#" "a_111_122#" 34.1645
+cap "a_1119_n100#" "a_1167_n188#" 6.25956
+cap "a_1407_n100#" "a_1503_n100#" 241.535
+cap "a_n1281_n100#" "a_n417_n100#" 16.0389
+cap "a_n1041_122#" "a_111_122#" 4.18859
+cap "a_207_n188#" "a_1071_122#" 1.06355
+cap "a_n1665_n100#" "a_n513_n100#" 11.882
+cap "a_2319_n188#" "a_2703_n188#" 14.0338
+cap "a_927_n100#" "a_n129_n100#" 13.0056
+cap "a_831_n100#" "a_n321_n100#" 11.882
+cap "a_1647_122#" "a_1599_n100#" 6.25956
+cap "a_1743_n188#" "a_2703_n188#" 5.07915
+cap "a_n273_122#" "a_687_122#" 5.07915
+cap "a_2079_n100#" "a_1023_n100#" 13.0056
+cap "a_n993_n100#" "a_n801_n100#" 87.4087
+cap "a_879_122#" "a_n81_122#" 5.07915
+cap "a_975_n188#" "a_927_n100#" 6.25956
+cap "a_543_n100#" "a_n513_n100#" 13.0056
+cap "a_n1233_122#" "a_n2673_n188#" 0.628198
+cap "a_n2721_n100#" "a_n2909_n100#" 87.4087
+cap "a_399_n188#" "a_n561_n188#" 5.07915
+cap "a_n2145_n100#" "a_n609_n100#" 8.83052
+cap "a_n1617_122#" "a_n369_n188#" 0.727455
+cap "a_n1617_122#" "a_n2385_122#" 6.45081
+cap "a_n1233_122#" "a_n2481_n188#" 0.727455
+cap "a_n1953_n100#" "a_n321_n100#" 8.29777
+cap "a_2127_n188#" "a_2223_122#" 14.1667
+cap "a_303_122#" "a_1455_122#" 4.18859
+cap "a_207_n188#" "a_1263_122#" 0.863965
+cap "a_2655_n100#" "a_1407_n100#" 10.9371
+cap "a_2127_n188#" "a_1839_122#" 3.46589
+cap "a_1743_n188#" "a_111_122#" 0.0858586
+cap "a_2511_n188#" "a_1551_n188#" 5.07915
+cap "a_2031_122#" "a_783_n188#" 0.727455
+cap "a_63_n100#" "a_n225_n100#" 53.425
+cap "a_1311_n100#" "a_735_n100#" 24.6699
+cap "a_2511_n188#" "a_1935_n188#" 8.83801
+cap "a_351_n100#" "a_831_n100#" 30.0629
+cap "a_n849_122#" "a_n801_n100#" 6.25956
+cap "a_n1809_122#" "a_n2865_n188#" 0.863965
+cap "a_2463_n100#" "a_1887_n100#" 24.6699
+cap "a_2703_n188#" "a_2031_122#" 1.38306
+cap "a_n2577_122#" "a_n2673_n188#" 14.1667
+cap "a_n1377_n100#" "a_n129_n100#" 10.9371
+cap "a_n1233_122#" "a_15_n188#" 0.727455
+cap "a_2223_122#" "a_1359_n188#" 1.06355
+cap "a_447_n100#" "a_1695_n100#" 10.9371
+cap "a_n225_n100#" "a_n897_n100#" 20.9177
+cap "a_n321_n100#" "a_n1473_n100#" 11.882
+cap "a_2607_122#" "a_2415_122#" 34.1645
+cap "a_2319_n188#" "a_1455_122#" 1.06355
+cap "a_n2577_122#" "a_n2481_n188#" 14.1667
+cap "a_447_n100#" "a_n801_n100#" 10.9371
+cap "a_n2625_n100#" "a_n2673_n188#" 6.25956
+cap "a_1743_n188#" "a_1455_122#" 3.46589
+cap "a_1839_122#" "a_1359_n188#" 1.97704
+cap "a_399_n188#" "a_n753_n188#" 4.18859
+cap "a_591_n188#" "a_687_122#" 14.1667
+cap "a_n273_122#" "a_n945_n188#" 1.38306
+cap "a_n1089_n100#" "a_n1761_n100#" 20.9177
+cap "a_n2865_n188#" "a_n1521_n188#" 3.56376
+cap "a_n2241_n100#" "a_n801_n100#" 9.43637
+cap "a_1263_122#" "a_1071_122#" 34.1645
+cap "a_1887_n100#" "a_2559_n100#" 20.9177
+cap "a_n1905_n188#" "a_n273_122#" 0.0858586
+cap "a_n1857_n100#" "a_n897_n100#" 14.3638
+cap "a_879_122#" "a_15_n188#" 1.06355
+cap "a_n2817_n100#" "a_n1953_n100#" 16.0389
+cap "a_351_n100#" "a_1599_n100#" 10.9371
+cap "a_n1425_122#" "a_207_n188#" 0.0858586
+cap "a_n849_122#" "a_n81_122#" 6.45081
+cap "a_2415_122#" "a_1167_n188#" 0.727455
+cap "a_n705_n100#" "a_639_n100#" 10.1315
+cap "a_n81_122#" "a_n177_n188#" 14.1667
+cap "a_1743_n188#" "a_1791_n100#" 6.25956
+cap "a_1791_n100#" "a_639_n100#" 11.882
+cap "a_2079_n100#" "a_2127_n188#" 6.25956
+cap "a_1167_n188#" "a_n81_122#" 0.727455
+cap "a_1119_n100#" "a_1311_n100#" 87.4087
+cap "a_n129_n100#" "a_735_n100#" 16.0389
+cap "a_n2193_122#" "a_n2673_n188#" 1.97704
+cap "a_1551_n188#" "a_495_122#" 0.863965
+cap "a_n1281_n100#" "a_n1377_n100#" 241.535
+cap "a_399_n188#" "a_n1137_n188#" 3.10116
+cap "a_n1809_122#" "a_n945_n188#" 1.06355
+cap "a_1455_122#" "a_2031_122#" 8.83801
+cap "a_2463_n100#" "a_1215_n100#" 10.9371
+cap "a_n2481_n188#" "a_n2193_122#" 3.46589
+cap "a_975_n188#" "a_1551_n188#" 8.83801
+cap "a_2175_n100#" "a_639_n100#" 8.83052
+cap "a_n33_n100#" "a_1215_n100#" 10.9371
+cap "a_n1665_n100#" "a_n2909_n100#" 10.9371
+cap "a_n1713_n188#" "a_n2865_n188#" 4.18859
+cap "a_495_122#" "a_1935_n188#" 0.628198
+cap "a_n2721_n100#" "a_n1185_n100#" 8.83052
+cap "a_n2721_n100#" "a_n2529_n100#" 87.4087
+cap "a_n2817_n100#" "a_n1473_n100#" 10.1315
+cap "a_n2481_n188#" "a_n849_122#" 0.0858586
+cap "a_n1809_122#" "a_n1905_n188#" 14.1667
+cap "a_303_122#" "a_n273_122#" 8.83801
+cap "a_351_n100#" "a_1503_n100#" 11.882
+cap "a_975_n188#" "a_1935_n188#" 5.07915
+cap "a_n1041_122#" "a_n273_122#" 6.45081
+cap "a_591_n188#" "a_n945_n188#" 3.10116
+cap "a_n2145_n100#" "a_n1857_n100#" 53.425
+cap "a_n1569_n100#" "a_n2721_n100#" 11.882
+cap "a_n945_n188#" "a_n1521_n188#" 8.83801
+cap "a_2559_n100#" "a_1215_n100#" 10.1315
+cap "a_927_n100#" "a_n417_n100#" 10.1315
+cap "a_n2049_n100#" "a_n2625_n100#" 24.6699
+cap "a_255_n100#" "a_63_n100#" 87.4087
+cap "a_n129_n100#" "a_n1089_n100#" 14.3638
+cap "a_n1905_n188#" "a_n1521_n188#" 14.0338
+cap "a_831_n100#" "a_1599_n100#" 18.1562
+cap "a_159_n100#" "a_1215_n100#" 13.0056
+cap "a_n2673_n188#" "a_n2769_122#" 14.1667
+cap "a_n2049_n100#" "a_n993_n100#" 13.0056
+cap "a_2127_n188#" "a_783_n188#" 3.56376
+cap "a_2271_n100#" "a_1407_n100#" 16.0389
+cap "a_n2481_n188#" "a_n2769_122#" 3.46589
+cap "a_n2001_122#" "a_n1329_n188#" 1.38306
+cap "a_n33_n100#" "a_n993_n100#" 14.3638
+cap "a_543_n100#" "a_639_n100#" 241.535
+cap "a_n657_122#" "a_n609_n100#" 6.25956
+cap "a_n849_122#" "a_15_n188#" 1.06355
+cap "a_1023_n100#" "a_1791_n100#" 18.1562
+cap "a_255_n100#" "a_n897_n100#" 11.882
+cap "a_n177_n188#" "a_15_n188#" 34.1645
+cap "a_n705_n100#" "a_n1185_n100#" 30.0629
+cap "a_2127_n188#" "a_2703_n188#" 8.83801
+cap "a_927_n100#" "a_2367_n100#" 9.43637
+cap "a_1119_n100#" "a_n129_n100#" 10.9371
+cap "a_n801_n100#" "a_n1761_n100#" 14.3638
+cap "a_1311_n100#" "a_1695_n100#" 38.4743
+cap "a_n1809_122#" "a_n1041_122#" 6.45081
+cap "a_n1569_n100#" "a_n705_n100#" 16.0389
+cap "a_n2337_n100#" "a_n1377_n100#" 14.3638
+cap "a_1167_n188#" "a_15_n188#" 4.18859
+cap "a_1551_n188#" "a_207_n188#" 3.56376
+cap "a_n1953_n100#" "a_n1473_n100#" 30.0629
+cap "a_n1713_n188#" "a_n945_n188#" 6.45081
+cap "a_1359_n188#" "a_783_n188#" 8.83801
+cap "a_1023_n100#" "a_2175_n100#" 11.882
+cap "a_159_n100#" "a_n993_n100#" 11.882
+cap "a_303_122#" "a_591_n188#" 3.46589
+cap "a_831_n100#" "a_1503_n100#" 20.9177
+cap "a_n1233_122#" "a_n2865_n188#" 0.0858586
+cap "a_n1377_n100#" "a_n417_n100#" 14.3638
+cap "a_2511_n188#" "a_2415_122#" 14.1667
+cap "a_n1713_n188#" "a_n1905_n188#" 34.1645
+cap "a_591_n188#" "a_n1041_122#" 0.0858586
+cap "a_n1041_122#" "a_n1521_n188#" 1.97704
+cap "a_2703_n188#" "a_1359_n188#" 3.56376
+cap "a_n1281_n100#" "a_n1089_n100#" 87.4087
+cap "a_1983_n100#" "a_2367_n100#" 38.4743
+cap "a_n657_122#" "a_n1329_n188#" 1.38306
+cap "a_n465_122#" "a_n81_122#" 14.0338
+cap "a_2607_122#" "a_2559_n100#" 6.25956
+cap "a_879_122#" "a_687_122#" 34.1645
+cap "a_447_n100#" "a_n33_n100#" 30.0629
+cap "a_399_n188#" "a_1647_122#" 0.727455
+cap "a_n2241_n100#" "a_n2049_n100#" 87.4087
+cap "a_1263_122#" "a_2799_122#" 3.10116
+cap "a_n1329_n188#" "a_111_122#" 0.628198
+cap "a_1407_n100#" "a_63_n100#" 10.1315
+cap "a_1599_n100#" "a_1503_n100#" 241.535
+cap "a_591_n188#" "a_639_n100#" 6.25956
+cap "a_1023_n100#" "a_543_n100#" 30.0629
+cap "a_n1665_n100#" "a_n2529_n100#" 16.0389
+cap "a_1743_n188#" "a_591_n188#" 4.18859
+cap "a_n705_n100#" "a_n609_n100#" 241.535
+cap "a_n1665_n100#" "a_n1185_n100#" 30.0629
+cap "a_2127_n188#" "a_1455_122#" 1.38306
+cap "a_n2865_n188#" "a_n2577_122#" 3.46589
+cap "a_n2001_122#" "a_n561_n188#" 0.628198
+cap "a_1359_n188#" "a_111_122#" 0.727455
+cap "a_1551_n188#" "a_1071_122#" 1.97704
+cap "a_927_n100#" "a_1983_n100#" 13.0056
+cap "a_n2433_n100#" "a_n897_n100#" 8.83052
+cap "a_447_n100#" "a_159_n100#" 53.425
+cap "a_n1569_n100#" "a_n1665_n100#" 241.535
+cap "a_n1713_n188#" "a_n1041_122#" 1.38306
+cap "a_1935_n188#" "a_1071_122#" 1.06355
+cap "a_n417_n100#" "a_735_n100#" 11.882
+cap "a_n561_n188#" "a_783_n188#" 3.56376
+cap "a_n369_n188#" "a_n81_122#" 3.46589
+cap "a_n129_n100#" "a_n801_n100#" 20.9177
+cap "a_n1233_122#" "a_n945_n188#" 3.46589
+cap "a_2655_n100#" "a_1599_n100#" 13.0056
+cap "a_1551_n188#" "a_1263_122#" 3.46589
+cap "a_n513_n100#" "a_n993_n100#" 30.0629
+cap "a_n1905_n188#" "a_n1233_122#" 1.38306
+cap "a_1359_n188#" "a_1455_122#" 14.1667
+cap "a_n2337_n100#" "a_n1089_n100#" 10.9371
+cap "a_n1425_122#" "a_n1377_n100#" 6.25956
+cap "a_n1425_122#" "a_n1617_122#" 34.1645
+cap "a_1263_122#" "a_1935_n188#" 1.38306
+cap "a_975_n188#" "a_2415_122#" 0.628198
+cap "a_n2385_122#" "a_n2673_n188#" 3.46589
+cap "a_591_n188#" "a_2031_122#" 0.628198
+cap "a_2367_n100#" "a_735_n100#" 8.29777
+cap "a_n417_n100#" "a_n1089_n100#" 20.9177
+cap "a_n2001_122#" "a_n753_n188#" 0.727455
+cap "a_n465_122#" "a_15_n188#" 1.97704
+cap "a_2127_n188#" "a_2175_n100#" 6.25956
+cap "a_n2865_n188#" "a_n2193_122#" 1.38306
+cap "a_n81_122#" "a_n129_n100#" 6.25956
+cap "a_n2385_122#" "a_n2481_n188#" 14.1667
+cap "a_n657_122#" "a_n561_n188#" 14.1667
+cap "a_495_122#" "a_n81_122#" 8.83801
+cap "a_n1665_n100#" "a_n609_n100#" 13.0056
+cap "a_687_122#" "a_n849_122#" 3.10116
+cap "a_n2145_n100#" "a_n2433_n100#" 53.425
+cap "a_n2577_122#" "a_n945_n188#" 0.0858586
+cap "a_975_n188#" "a_n81_122#" 0.863965
+cap "a_2655_n100#" "a_1503_n100#" 11.882
+cap "a_n561_n188#" "a_111_122#" 1.38306
+cap "a_687_122#" "a_n177_n188#" 1.06355
+cap "a_399_n188#" "a_351_n100#" 6.25956
+cap "a_543_n100#" "a_n609_n100#" 11.882
+cap "a_1119_n100#" "a_1071_122#" 6.25956
+cap "a_n753_n188#" "a_783_n188#" 3.10116
+cap "a_n2721_n100#" "a_n1857_n100#" 16.0389
+cap "a_n1905_n188#" "a_n2577_122#" 1.38306
+cap "a_63_n100#" "a_n321_n100#" 38.4743
+cap "a_n1281_n100#" "a_n801_n100#" 30.0629
+cap "a_303_122#" "a_n1233_122#" 3.10116
+cap "a_927_n100#" "a_735_n100#" 87.4087
+cap "a_1119_n100#" "a_n417_n100#" 8.83052
+cap "a_1167_n188#" "a_687_122#" 1.97704
+cap "a_1887_n100#" "a_639_n100#" 10.9371
+cap "a_n1041_122#" "a_n1233_122#" 34.1645
+cap "a_n945_n188#" "a_n993_n100#" 6.25956
+cap "a_447_n100#" "a_n513_n100#" 14.3638
+cap "a_n2049_n100#" "a_n1761_n100#" 53.425
+cap "a_1647_122#" "a_2223_122#" 8.83801
+cap "a_2511_n188#" "a_2463_n100#" 6.25956
+cap "a_n1569_n100#" "a_n1521_n188#" 6.25956
+cap "a_n369_n188#" "a_15_n188#" 14.0338
+cap "a_n705_n100#" "a_n225_n100#" 30.0629
+cap "a_n2865_n188#" "a_n2769_122#" 14.1667
+cap "a_n321_n100#" "a_n897_n100#" 24.6699
+cap "a_1647_122#" "a_1839_122#" 34.1645
+cap "a_2463_n100#" "a_1311_n100#" 11.882
+cap "a_n1137_n188#" "a_n2001_122#" 1.06355
+cap "a_303_122#" "a_879_122#" 8.83801
+cap "a_1311_n100#" "a_n33_n100#" 10.1315
+cap "a_n657_122#" "a_n753_n188#" 14.1667
+cap "a_2271_n100#" "a_831_n100#" 9.43637
+cap "a_1983_n100#" "a_735_n100#" 10.9371
+cap "a_2511_n188#" "a_2559_n100#" 6.25956
+cap "a_2367_n100#" "a_1119_n100#" 10.9371
+cap "a_n705_n100#" "a_n1857_n100#" 11.882
+cap "a_n753_n188#" "a_111_122#" 1.06355
+cap "a_n945_n188#" "a_n2193_122#" 0.727455
+cap "a_351_n100#" "a_63_n100#" 53.425
+cap "a_n1329_n188#" "a_n273_122#" 0.863965
+cap "a_1983_n100#" "a_1935_n188#" 6.25956
+cap "a_1311_n100#" "a_2559_n100#" 10.9371
+cap "a_n1041_122#" "a_n2577_122#" 3.10116
+cap "a_n945_n188#" "a_n849_122#" 14.1667
+cap "a_2079_n100#" "a_1407_n100#" 20.9177
+cap "a_n1905_n188#" "a_n2193_122#" 3.46589
+cap "a_207_n188#" "a_n81_122#" 3.46589
+cap "a_159_n100#" "a_1311_n100#" 11.882
+cap "a_n945_n188#" "a_n177_n188#" 6.45081
+cap "a_495_122#" "a_15_n188#" 1.97704
+cap "a_n273_122#" "a_1359_n188#" 0.0858586
+cap "a_n1905_n188#" "a_n849_122#" 0.863965
+cap "a_975_n188#" "a_15_n188#" 5.07915
+cap "a_n2145_n100#" "a_n2097_n188#" 6.25956
+cap "a_n2625_n100#" "a_n2909_n100#" 53.425
+cap "a_351_n100#" "a_n897_n100#" 10.9371
+cap "a_2319_n188#" "a_879_122#" 0.628198
+cap "a_927_n100#" "a_1119_n100#" 87.4087
+cap "a_1215_n100#" "a_639_n100#" 24.6699
+cap "a_n2337_n100#" "a_n801_n100#" 8.83052
+cap "a_1551_n188#" "a_2799_122#" 0.727455
+cap "a_1743_n188#" "a_879_122#" 1.06355
+cap "a_n1041_122#" "a_n993_n100#" 6.25956
+cap "a_1023_n100#" "a_1887_n100#" 16.0389
+cap "a_2271_n100#" "a_1599_n100#" 20.9177
+cap "a_n1665_n100#" "a_n225_n100#" 9.43637
+cap "a_1935_n188#" "a_2799_122#" 1.06355
+cap "a_n1137_n188#" "a_n657_122#" 1.97704
+cap "a_n417_n100#" "a_n801_n100#" 38.4743
+cap "a_2415_122#" "a_1071_122#" 3.56376
+cap "a_543_n100#" "a_n225_n100#" 18.1562
+cap "a_n1137_n188#" "a_111_122#" 0.727455
+cap "a_2127_n188#" "a_591_n188#" 3.10116
+cap "a_n1377_n100#" "a_n1089_n100#" 53.425
+cap "a_n273_122#" "a_n225_n100#" 6.25956
+cap "a_n1905_n188#" "a_n2769_122#" 1.06355
+cap "a_n1809_122#" "a_n1329_n188#" 1.97704
+cap "a_n33_n100#" "a_n129_n100#" 241.535
+cap "a_n705_n100#" "a_n753_n188#" 6.25956
+cap "a_n1665_n100#" "a_n1857_n100#" 87.4087
+cap "a_1983_n100#" "a_1119_n100#" 16.0389
+cap "a_n1041_122#" "a_n2193_122#" 4.18859
+cap "a_303_122#" "a_n849_122#" 4.18859
+cap "a_n81_122#" "a_1071_122#" 4.18859
+cap "a_831_n100#" "a_63_n100#" 18.1562
+cap "a_n993_n100#" "a_639_n100#" 8.29777
+cap "a_n465_122#" "a_687_122#" 4.18859
+cap "a_2367_n100#" "a_1695_n100#" 20.9177
+cap "a_2415_122#" "a_1263_122#" 4.18859
+cap "a_n1329_n188#" "a_n1521_n188#" 34.1645
+cap "a_n1041_122#" "a_n849_122#" 34.1645
+cap "a_303_122#" "a_n177_n188#" 1.97704
+cap "a_2271_n100#" "a_1503_n100#" 18.1562
+cap "a_n1041_122#" "a_n177_n188#" 1.06355
+cap "a_n465_122#" "a_n513_n100#" 6.25956
+cap "a_n1233_122#" "a_n1185_n100#" 6.25956
+cap "a_879_122#" "a_2031_122#" 4.18859
+cap "a_159_n100#" "a_n129_n100#" 53.425
+cap "a_1551_n188#" "a_1935_n188#" 14.0338
+cap "a_591_n188#" "a_1359_n188#" 6.45081
+cap "a_n513_n100#" "a_n1761_n100#" 10.9371
+cap "a_n561_n188#" "a_n273_122#" 3.46589
+cap "a_303_122#" "a_1167_n188#" 1.06355
+cap "a_n705_n100#" "a_255_n100#" 14.3638
+cap "a_207_n188#" "a_15_n188#" 34.1645
+cap "a_2367_n100#" "a_2415_122#" 6.25956
+cap "a_1263_122#" "a_n81_122#" 3.56376
+cap "a_1023_n100#" "a_1215_n100#" 87.4087
+cap "a_1791_n100#" "a_255_n100#" 8.83052
+cap "a_n2145_n100#" "a_n2817_n100#" 20.9177
+cap "a_2319_n188#" "a_2607_122#" 3.46589
+cap "a_927_n100#" "a_1695_n100#" 18.1562
+cap "a_n2241_n100#" "a_n2909_n100#" 20.9177
+cap "a_1743_n188#" "a_2607_122#" 1.06355
+cap "a_1647_122#" "a_783_n188#" 1.06355
+cap "a_2271_n100#" "a_2655_n100#" 38.4743
+cap "a_1599_n100#" "a_63_n100#" 8.83052
+cap "a_n1953_n100#" "a_n897_n100#" 13.0056
+cap "a_n2049_n100#" "a_n1281_n100#" 18.1562
+cap "a_n369_n188#" "a_687_122#" 0.863965
+cap "a_n1281_n100#" "a_n33_n100#" 10.9371
+cap "a_n2385_122#" "a_n2865_n188#" 1.97704
+cap "a_n2433_n100#" "a_n2721_n100#" 53.425
+cap "a_n2097_n188#" "a_n2001_122#" 14.1667
+cap "a_2703_n188#" "a_1647_122#" 0.863965
+cap "a_n1809_122#" "a_n1857_n100#" 6.25956
+cap "a_n2529_n100#" "a_n2577_122#" 6.25956
+cap "a_n1713_n188#" "a_n1329_n188#" 14.0338
+cap "a_447_n100#" "a_639_n100#" 87.4087
+cap "a_63_n100#" "a_n1473_n100#" 8.83052
+cap "a_2319_n188#" "a_1167_n188#" 4.18859
+cap "a_1743_n188#" "a_1167_n188#" 8.83801
+cap "a_n2625_n100#" "a_n2529_n100#" 241.535
+cap "a_n1809_122#" "a_n561_n188#" 0.727455
+cap "a_1983_n100#" "a_1695_n100#" 53.425
+cap "a_n2625_n100#" "a_n1185_n100#" 9.43637
+cap "a_n465_122#" "a_n945_n188#" 1.97704
+cap "a_n273_122#" "a_n753_n188#" 1.97704
+cap "a_1407_n100#" "a_1455_122#" 6.25956
+cap "a_1119_n100#" "a_735_n100#" 38.4743
+cap "a_159_n100#" "a_n1281_n100#" 9.43637
+cap "a_15_n188#" "a_1071_122#" 0.863965
+cap "a_n2529_n100#" "a_n993_n100#" 8.83052
+cap "a_63_n100#" "a_1503_n100#" 9.43637
+cap "a_n993_n100#" "a_n1185_n100#" 87.4087
+cap "a_n897_n100#" "a_n1473_n100#" 24.6699
+cap "a_n1905_n188#" "a_n465_122#" 0.628198
+cap "a_n1569_n100#" "a_n2625_n100#" 13.0056
+cap "a_591_n188#" "a_n561_n188#" 4.18859
+cap "a_495_122#" "a_687_122#" 34.1645
+cap "a_1407_n100#" "a_2847_n100#" 9.43637
+cap "a_1647_122#" "a_111_122#" 3.10116
+cap "a_2607_122#" "a_2031_122#" 8.83801
+cap "a_n561_n188#" "a_n1521_n188#" 5.07915
+cap "a_975_n188#" "a_687_122#" 3.46589
+cap "a_207_n188#" "a_159_n100#" 6.25956
+cap "a_543_n100#" "a_255_n100#" 53.425
+cap "a_n1377_n100#" "a_n801_n100#" 24.6699
+cap "a_n1569_n100#" "a_n993_n100#" 24.6699
+cap "a_n1425_122#" "a_n81_122#" 3.56376
+cap "a_n513_n100#" "a_n129_n100#" 38.4743
+cap "a_n2145_n100#" "a_n1953_n100#" 87.4087
+cap "a_n2097_n188#" "a_n657_122#" 0.628198
+cap "a_1263_122#" "a_15_n188#" 0.727455
+cap "a_1791_n100#" "a_1407_n100#" 38.4743
+cap "a_n2337_n100#" "a_n2049_n100#" 53.425
+cap "a_n369_n188#" "a_n945_n188#" 8.83801
+cap "a_n2385_122#" "a_n945_n188#" 0.628198
+cap "a_n1809_122#" "a_n753_n188#" 0.863965
+cap "a_1167_n188#" "a_2031_122#" 1.06355
+cap "a_1647_122#" "a_1455_122#" 34.1645
+cap "a_n1905_n188#" "a_n369_n188#" 3.10116
+cap "a_n1137_n188#" "a_n273_122#" 1.06355
+cap "a_n2049_n100#" "a_n417_n100#" 8.29777
+cap "a_2415_122#" "a_2799_122#" 14.0338
+cap "a_n2385_122#" "a_n1905_n188#" 1.97704
+cap "a_n1425_122#" "a_n2673_n188#" 0.727455
+cap "a_303_122#" "a_n465_122#" 6.45081
+cap "a_1023_n100#" "a_447_n100#" 24.6699
+cap "a_n1233_122#" "a_n1329_n188#" 14.1667
+cap "a_1407_n100#" "a_2175_n100#" 18.1562
+cap "a_n33_n100#" "a_n417_n100#" 38.4743
+cap "a_n1425_122#" "a_n2481_n188#" 0.863965
+cap "a_n1041_122#" "a_n465_122#" 8.83801
+cap "a_2127_n188#" "a_879_122#" 0.727455
+cap "a_n2145_n100#" "a_n1473_n100#" 20.9177
+cap "a_n1617_122#" "a_n81_122#" 3.10116
+cap "a_n1713_n188#" "a_n561_n188#" 4.18859
+cap "a_591_n188#" "a_n753_n188#" 3.56376
+cap "a_447_n100#" "a_n1185_n100#" 8.29777
+cap "a_n753_n188#" "a_n1521_n188#" 6.45081
+cap "a_2079_n100#" "a_831_n100#" 10.9371
+cap "a_n609_n100#" "a_n993_n100#" 38.4743
+cap "a_n2909_n100#" "a_n1761_n100#" 11.882
+cap "a_1695_n100#" "a_735_n100#" 14.3638
+cap "a_n2241_n100#" "a_n2529_n100#" 53.425
+cap "a_n2241_n100#" "a_n1185_n100#" 13.0056
+cap "a_n801_n100#" "a_735_n100#" 8.83052
+cap "a_495_122#" "a_n945_n188#" 0.628198
+cap "a_2751_n100#" "a_1407_n100#" 10.1315
+cap "a_n1281_n100#" "a_n513_n100#" 18.1562
+cap "a_207_n188#" "a_687_122#" 1.97704
+cap "a_2463_n100#" "a_2367_n100#" 241.535
+cap "a_159_n100#" "a_n417_n100#" 24.6699
+cap "a_n2433_n100#" "a_n1665_n100#" 18.1562
+cap "a_n2289_n188#" "a_n2001_122#" 3.46589
+cap "a_n2241_n100#" "a_n1569_n100#" 20.9177
+cap "a_303_122#" "a_n369_n188#" 1.38306
+cap "a_1551_n188#" "a_2415_122#" 1.06355
+cap "a_n1617_122#" "a_n2673_n188#" 0.863965
+cap "a_n1809_122#" "a_n1137_n188#" 1.38306
+cap "a_879_122#" "a_1359_n188#" 1.97704
+cap "a_n2577_122#" "a_n1329_n188#" 0.727455
+cap "a_n1425_122#" "a_15_n188#" 0.628198
+cap "a_543_n100#" "a_1407_n100#" 16.0389
+cap "a_2511_n188#" "a_2319_n188#" 34.1645
+cap "a_n1041_122#" "a_n369_n188#" 1.38306
+cap "a_2511_n188#" "a_1743_n188#" 6.45081
+cap "a_n2385_122#" "a_n1041_122#" 3.56376
+cap "a_n1617_122#" "a_n2481_n188#" 1.06355
+cap "a_2415_122#" "a_1935_n188#" 1.97704
+cap "a_2079_n100#" "a_1599_n100#" 30.0629
+cap "a_1311_n100#" "a_639_n100#" 20.9177
+cap "a_2367_n100#" "a_2559_n100#" 87.4087
+cap "a_831_n100#" "a_783_n188#" 6.25956
+cap "a_n705_n100#" "a_n321_n100#" 38.4743
+cap "a_n1089_n100#" "a_n801_n100#" 53.425
+cap "a_n2001_122#" "a_n1953_n100#" 6.25956
+cap "a_n1713_n188#" "a_n753_n188#" 5.07915
+cap "a_n1137_n188#" "a_n1521_n188#" 14.0338
+cap "a_1551_n188#" "a_n81_122#" 0.0858586
+cap "a_927_n100#" "a_2463_n100#" 8.83052
+cap "a_927_n100#" "a_n33_n100#" 14.3638
+cap "a_n225_n100#" "a_1215_n100#" 9.43637
+cap "a_447_n100#" "a_n609_n100#" 13.0056
+cap "a_n2721_n100#" "a_n2817_n100#" 241.535
+cap "a_2607_122#" "a_2127_n188#" 1.97704
+cap "a_n1233_122#" "a_n561_n188#" 1.38306
+cap "a_303_122#" "a_495_122#" 34.1645
+cap "a_687_122#" "a_1071_122#" 14.0338
+cap "a_n2241_n100#" "a_n609_n100#" 8.29777
+cap "a_n1617_122#" "a_15_n188#" 0.0858586
+cap "a_1119_n100#" "a_1695_n100#" 24.6699
+cap "a_n657_122#" "a_n2289_n188#" 0.0858586
+cap "a_495_122#" "a_n1041_122#" 3.10116
+cap "a_975_n188#" "a_303_122#" 1.38306
+cap "a_927_n100#" "a_2559_n100#" 8.29777
+cap "a_2079_n100#" "a_1503_n100#" 24.6699
+cap "a_2463_n100#" "a_1983_n100#" 30.0629
+cap "a_927_n100#" "a_159_n100#" 18.1562
+cap "a_n1329_n188#" "a_n2193_122#" 1.06355
+cap "a_207_n188#" "a_n945_n188#" 4.18859
+cap "a_2511_n188#" "a_2031_122#" 1.97704
+cap "a_351_n100#" "a_n705_n100#" 13.0056
+cap "a_879_122#" "a_n561_n188#" 0.628198
+cap "a_n1137_n188#" "a_n1713_n188#" 8.83801
+cap "a_n1329_n188#" "a_n849_122#" 1.97704
+cap "a_2127_n188#" "a_1167_n188#" 5.07915
+cap "a_n513_n100#" "a_n417_n100#" 241.535
+cap "a_1263_122#" "a_687_122#" 8.83801
+cap "a_351_n100#" "a_1791_n100#" 9.43637
+cap "a_n225_n100#" "a_n993_n100#" 18.1562
+cap "a_n2049_n100#" "a_n1377_n100#" 20.9177
+cap "a_n1329_n188#" "a_n177_n188#" 4.18859
+cap "a_2607_122#" "a_1359_n188#" 0.727455
+cap "a_n1665_n100#" "a_n321_n100#" 10.1315
+cap "a_1887_n100#" "a_255_n100#" 8.29777
+cap "a_n1377_n100#" "a_n33_n100#" 10.1315
+cap "a_1743_n188#" "a_495_122#" 0.727455
+cap "a_2079_n100#" "a_2655_n100#" 24.6699
+cap "a_1983_n100#" "a_2559_n100#" 24.6699
+cap "a_1023_n100#" "a_1311_n100#" 53.425
+cap "a_n129_n100#" "a_639_n100#" 18.1562
+cap "a_n2625_n100#" "a_n1857_n100#" 18.1562
+cap "a_n1185_n100#" "a_n1761_n100#" 24.6699
+cap "a_n2529_n100#" "a_n1761_n100#" 18.1562
+cap "a_1359_n188#" "a_n177_n188#" 3.10116
+cap "a_975_n188#" "a_2319_n188#" 3.56376
+cap "a_543_n100#" "a_n321_n100#" 16.0389
+cap "a_1743_n188#" "a_975_n188#" 6.45081
+cap "a_n1233_122#" "a_n753_n188#" 1.97704
+cap "a_n1857_n100#" "a_n993_n100#" 16.0389
+cap "a_n273_122#" "a_n321_n100#" 6.25956
+cap "a_1551_n188#" "a_15_n188#" 3.10116
+cap "a_n1569_n100#" "a_n1761_n100#" 87.4087
+cap "a_n2721_n100#" "a_n1953_n100#" 18.1562
+cap "a_n1329_n188#" "a_n2769_122#" 0.628198
+cap "a_1167_n188#" "a_1359_n188#" 34.1645
+cap "a_159_n100#" "a_n1377_n100#" 8.83052
+cap "a_n2909_n100#" "a_n1281_n100#" 8.29777
+cap "a_303_122#" "a_207_n188#" 14.1667
+cap "a_879_122#" "a_n753_n188#" 0.0858586
+cap "a_n177_n188#" "a_n225_n100#" 6.25956
+cap "a_n1041_122#" "a_207_n188#" 0.727455
+cap "a_591_n188#" "a_1647_122#" 0.863965
+cap "a_831_n100#" "a_n705_n100#" 8.83052
+cap "a_2271_n100#" "a_2223_122#" 6.25956
+cap "a_447_n100#" "a_n225_n100#" 20.9177
+cap "a_n1809_122#" "a_n2097_n188#" 3.46589
+cap "a_927_n100#" "a_n513_n100#" 9.43637
+cap "a_1791_n100#" "a_831_n100#" 14.3638
+cap "a_351_n100#" "a_543_n100#" 87.4087
+cap "a_495_122#" "a_2031_122#" 3.10116
+cap "a_n33_n100#" "a_735_n100#" 18.1562
+cap "a_n2721_n100#" "a_n1473_n100#" 10.9371
+cap "a_n1425_122#" "a_n2865_n188#" 0.628198
+cap "a_n561_n188#" "a_n2193_122#" 0.0858586
+cap "a_n1137_n188#" "a_n1233_122#" 14.1667
+cap "a_975_n188#" "a_2031_122#" 0.863965
+cap "a_n1665_n100#" "a_n2817_n100#" 11.882
+cap "a_2655_n100#" "a_2703_n188#" 6.25956
+cap "a_255_n100#" "a_1215_n100#" 14.3638
+cap "a_n561_n188#" "a_n849_122#" 3.46589
+cap "a_1023_n100#" "a_n129_n100#" 11.882
+cap "a_n609_n100#" "a_n1761_n100#" 11.882
+cap "a_n705_n100#" "a_n1953_n100#" 10.9371
+cap "a_399_n188#" "a_1839_122#" 0.628198
+cap "a_1599_n100#" "a_2847_n100#" 10.9371
+cap "a_n2097_n188#" "a_n1521_n188#" 8.83801
+cap "a_n561_n188#" "a_n177_n188#" 14.0338
+cap "a_975_n188#" "a_1023_n100#" 6.25956
+cap "a_831_n100#" "a_2175_n100#" 10.1315
+cap "a_1743_n188#" "a_207_n188#" 3.10116
+cap "a_1887_n100#" "a_1407_n100#" 30.0629
+cap "a_n129_n100#" "a_n1185_n100#" 13.0056
+cap "a_n2241_n100#" "a_n1857_n100#" 38.4743
+cap "a_63_n100#" "a_n897_n100#" 14.3638
+cap "a_159_n100#" "a_735_n100#" 24.6699
+cap "a_n2049_n100#" "a_n1089_n100#" 14.3638
+cap "a_303_122#" "a_1071_122#" 6.45081
+cap "a_1791_n100#" "a_1599_n100#" 87.4087
+cap "a_n33_n100#" "a_n1089_n100#" 13.0056
+cap "a_n1569_n100#" "a_n129_n100#" 9.43637
+cap "a_2511_n188#" "a_2127_n188#" 14.0338
+cap "a_n2337_n100#" "a_n2909_n100#" 24.6699
+cap "a_1455_122#" "a_1503_n100#" 6.25956
+cap "a_n1617_122#" "a_n2865_n188#" 0.727455
+cap "a_255_n100#" "a_n993_n100#" 10.9371
+cap "a_n1137_n188#" "a_n2577_122#" 0.628198
+cap "a_n705_n100#" "a_n1473_n100#" 18.1562
+cap "a_n513_n100#" "a_n1377_n100#" 16.0389
+cap "a_n753_n188#" "a_n2193_122#" 0.628198
+cap "a_n1329_n188#" "a_n465_122#" 1.06355
+cap "a_2847_n100#" "a_1503_n100#" 10.1315
+cap "a_303_122#" "a_1263_122#" 5.07915
+cap "a_1599_n100#" "a_2175_n100#" 24.6699
+cap "a_2463_n100#" "a_1119_n100#" 10.1315
+cap "a_543_n100#" "a_831_n100#" 53.425
+cap "a_n849_122#" "a_n753_n188#" 14.1667
+cap "a_n2097_n188#" "a_n1713_n188#" 14.0338
+cap "a_1119_n100#" "a_n33_n100#" 11.882
+cap "a_159_n100#" "a_n1089_n100#" 10.9371
+cap "a_n1425_122#" "a_n945_n188#" 1.97704
+cap "a_n753_n188#" "a_n177_n188#" 8.83801
+cap "a_2319_n188#" "a_1071_122#" 0.727455
+cap "a_n1665_n100#" "a_n1953_n100#" 53.425
+cap "a_1743_n188#" "a_1071_122#" 1.38306
+cap "a_2511_n188#" "a_1359_n188#" 4.18859
+cap "a_2271_n100#" "a_2079_n100#" 87.4087
+cap "a_n1425_122#" "a_n1905_n188#" 1.97704
+cap "a_1791_n100#" "a_1503_n100#" 53.425
+cap "a_1311_n100#" "a_1359_n188#" 6.25956
+cap "a_n1281_n100#" "a_n1185_n100#" 241.535
+cap "a_n2529_n100#" "a_n1281_n100#" 10.9371
+cap "a_2751_n100#" "a_1599_n100#" 11.882
+cap "a_2655_n100#" "a_2847_n100#" 87.4087
+cap "a_1407_n100#" "a_1215_n100#" 87.4087
+cap "a_1119_n100#" "a_2559_n100#" 9.43637
+cap "a_n417_n100#" "a_639_n100#" 13.0056
+cap "a_n129_n100#" "a_n609_n100#" 30.0629
+cap "a_1551_n188#" "a_687_122#" 1.06355
+cap "a_1119_n100#" "a_159_n100#" 14.3638
+cap "a_n1569_n100#" "a_n1281_n100#" 53.425
+cap "a_687_122#" "a_735_n100#" 6.25956
+cap "a_n369_n188#" "a_n1329_n188#" 5.07915
+cap "a_2319_n188#" "a_1263_122#" 0.863965
+cap "a_n2385_122#" "a_n1329_n188#" 0.863965
+cap "a_1743_n188#" "a_1263_122#" 1.97704
+cap "a_2175_n100#" "a_1503_n100#" 20.9177
+cap "a_543_n100#" "a_1599_n100#" 13.0056
+cap "a_n1137_n188#" "a_n2193_122#" 0.863965
+cap "a_447_n100#" "a_255_n100#" 87.4087
+cap "a_n2145_n100#" "a_n897_n100#" 10.9371
+cap "a_n1809_122#" "a_n2289_n188#" 1.97704
+cap "a_687_122#" "a_1935_n188#" 0.727455
+cap "a_2655_n100#" "a_1791_n100#" 16.0389
+cap "a_n513_n100#" "a_735_n100#" 10.9371
+cap "a_n1665_n100#" "a_n1473_n100#" 87.4087
+cap "a_n225_n100#" "a_n1761_n100#" 8.83052
+cap "a_n1617_122#" "a_n945_n188#" 1.38306
+cap "a_n1137_n188#" "a_n849_122#" 3.46589
+cap "a_n2433_n100#" "a_n2625_n100#" 87.4087
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2817 -100 2818 -99 l=30 w=200 "a_n3011_n274#" "a_2799_122#" 60 0 "a_2751_n100#" 200 0 "a_2847_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2721 -100 2722 -99 l=30 w=200 "a_n3011_n274#" "a_2703_n188#" 60 0 "a_2655_n100#" 200 0 "a_2751_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2625 -100 2626 -99 l=30 w=200 "a_n3011_n274#" "a_2607_122#" 60 0 "a_2559_n100#" 200 0 "a_2655_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2529 -100 2530 -99 l=30 w=200 "a_n3011_n274#" "a_2511_n188#" 60 0 "a_2463_n100#" 200 0 "a_2559_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2433 -100 2434 -99 l=30 w=200 "a_n3011_n274#" "a_2415_122#" 60 0 "a_2367_n100#" 200 0 "a_2463_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2337 -100 2338 -99 l=30 w=200 "a_n3011_n274#" "a_2319_n188#" 60 0 "a_2271_n100#" 200 0 "a_2367_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2241 -100 2242 -99 l=30 w=200 "a_n3011_n274#" "a_2223_122#" 60 0 "a_2175_n100#" 200 0 "a_2271_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2145 -100 2146 -99 l=30 w=200 "a_n3011_n274#" "a_2127_n188#" 60 0 "a_2079_n100#" 200 0 "a_2175_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 2049 -100 2050 -99 l=30 w=200 "a_n3011_n274#" "a_2031_122#" 60 0 "a_1983_n100#" 200 0 "a_2079_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1953 -100 1954 -99 l=30 w=200 "a_n3011_n274#" "a_1935_n188#" 60 0 "a_1887_n100#" 200 0 "a_1983_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1857 -100 1858 -99 l=30 w=200 "a_n3011_n274#" "a_1839_122#" 60 0 "a_1791_n100#" 200 0 "a_1887_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1761 -100 1762 -99 l=30 w=200 "a_n3011_n274#" "a_1743_n188#" 60 0 "a_1695_n100#" 200 0 "a_1791_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1665 -100 1666 -99 l=30 w=200 "a_n3011_n274#" "a_1647_122#" 60 0 "a_1599_n100#" 200 0 "a_1695_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1569 -100 1570 -99 l=30 w=200 "a_n3011_n274#" "a_1551_n188#" 60 0 "a_1503_n100#" 200 0 "a_1599_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1473 -100 1474 -99 l=30 w=200 "a_n3011_n274#" "a_1455_122#" 60 0 "a_1407_n100#" 200 0 "a_1503_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1377 -100 1378 -99 l=30 w=200 "a_n3011_n274#" "a_1359_n188#" 60 0 "a_1311_n100#" 200 0 "a_1407_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1281 -100 1282 -99 l=30 w=200 "a_n3011_n274#" "a_1263_122#" 60 0 "a_1215_n100#" 200 0 "a_1311_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1185 -100 1186 -99 l=30 w=200 "a_n3011_n274#" "a_1167_n188#" 60 0 "a_1119_n100#" 200 0 "a_1215_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 1089 -100 1090 -99 l=30 w=200 "a_n3011_n274#" "a_1071_122#" 60 0 "a_1023_n100#" 200 0 "a_1119_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 993 -100 994 -99 l=30 w=200 "a_n3011_n274#" "a_975_n188#" 60 0 "a_927_n100#" 200 0 "a_1023_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 897 -100 898 -99 l=30 w=200 "a_n3011_n274#" "a_879_122#" 60 0 "a_831_n100#" 200 0 "a_927_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 801 -100 802 -99 l=30 w=200 "a_n3011_n274#" "a_783_n188#" 60 0 "a_735_n100#" 200 0 "a_831_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 705 -100 706 -99 l=30 w=200 "a_n3011_n274#" "a_687_122#" 60 0 "a_639_n100#" 200 0 "a_735_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 609 -100 610 -99 l=30 w=200 "a_n3011_n274#" "a_591_n188#" 60 0 "a_543_n100#" 200 0 "a_639_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 513 -100 514 -99 l=30 w=200 "a_n3011_n274#" "a_495_122#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 417 -100 418 -99 l=30 w=200 "a_n3011_n274#" "a_399_n188#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 321 -100 322 -99 l=30 w=200 "a_n3011_n274#" "a_303_122#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 225 -100 226 -99 l=30 w=200 "a_n3011_n274#" "a_207_n188#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 129 -100 130 -99 l=30 w=200 "a_n3011_n274#" "a_111_122#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 33 -100 34 -99 l=30 w=200 "a_n3011_n274#" "a_15_n188#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -63 -100 -62 -99 l=30 w=200 "a_n3011_n274#" "a_n81_122#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -159 -100 -158 -99 l=30 w=200 "a_n3011_n274#" "a_n177_n188#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -255 -100 -254 -99 l=30 w=200 "a_n3011_n274#" "a_n273_122#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -351 -100 -350 -99 l=30 w=200 "a_n3011_n274#" "a_n369_n188#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -447 -100 -446 -99 l=30 w=200 "a_n3011_n274#" "a_n465_122#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -543 -100 -542 -99 l=30 w=200 "a_n3011_n274#" "a_n561_n188#" 60 0 "a_n609_n100#" 200 0 "a_n513_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -639 -100 -638 -99 l=30 w=200 "a_n3011_n274#" "a_n657_122#" 60 0 "a_n705_n100#" 200 0 "a_n609_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -735 -100 -734 -99 l=30 w=200 "a_n3011_n274#" "a_n753_n188#" 60 0 "a_n801_n100#" 200 0 "a_n705_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -831 -100 -830 -99 l=30 w=200 "a_n3011_n274#" "a_n849_122#" 60 0 "a_n897_n100#" 200 0 "a_n801_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -927 -100 -926 -99 l=30 w=200 "a_n3011_n274#" "a_n945_n188#" 60 0 "a_n993_n100#" 200 0 "a_n897_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1023 -100 -1022 -99 l=30 w=200 "a_n3011_n274#" "a_n1041_122#" 60 0 "a_n1089_n100#" 200 0 "a_n993_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1119 -100 -1118 -99 l=30 w=200 "a_n3011_n274#" "a_n1137_n188#" 60 0 "a_n1185_n100#" 200 0 "a_n1089_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1215 -100 -1214 -99 l=30 w=200 "a_n3011_n274#" "a_n1233_122#" 60 0 "a_n1281_n100#" 200 0 "a_n1185_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1311 -100 -1310 -99 l=30 w=200 "a_n3011_n274#" "a_n1329_n188#" 60 0 "a_n1377_n100#" 200 0 "a_n1281_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1407 -100 -1406 -99 l=30 w=200 "a_n3011_n274#" "a_n1425_122#" 60 0 "a_n1473_n100#" 200 0 "a_n1377_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1503 -100 -1502 -99 l=30 w=200 "a_n3011_n274#" "a_n1521_n188#" 60 0 "a_n1569_n100#" 200 0 "a_n1473_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1599 -100 -1598 -99 l=30 w=200 "a_n3011_n274#" "a_n1617_122#" 60 0 "a_n1665_n100#" 200 0 "a_n1569_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1695 -100 -1694 -99 l=30 w=200 "a_n3011_n274#" "a_n1713_n188#" 60 0 "a_n1761_n100#" 200 0 "a_n1665_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1791 -100 -1790 -99 l=30 w=200 "a_n3011_n274#" "a_n1809_122#" 60 0 "a_n1857_n100#" 200 0 "a_n1761_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1887 -100 -1886 -99 l=30 w=200 "a_n3011_n274#" "a_n1905_n188#" 60 0 "a_n1953_n100#" 200 0 "a_n1857_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -1983 -100 -1982 -99 l=30 w=200 "a_n3011_n274#" "a_n2001_122#" 60 0 "a_n2049_n100#" 200 0 "a_n1953_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2079 -100 -2078 -99 l=30 w=200 "a_n3011_n274#" "a_n2097_n188#" 60 0 "a_n2145_n100#" 200 0 "a_n2049_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2175 -100 -2174 -99 l=30 w=200 "a_n3011_n274#" "a_n2193_122#" 60 0 "a_n2241_n100#" 200 0 "a_n2145_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2271 -100 -2270 -99 l=30 w=200 "a_n3011_n274#" "a_n2289_n188#" 60 0 "a_n2337_n100#" 200 0 "a_n2241_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2367 -100 -2366 -99 l=30 w=200 "a_n3011_n274#" "a_n2385_122#" 60 0 "a_n2433_n100#" 200 0 "a_n2337_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2463 -100 -2462 -99 l=30 w=200 "a_n3011_n274#" "a_n2481_n188#" 60 0 "a_n2529_n100#" 200 0 "a_n2433_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2559 -100 -2558 -99 l=30 w=200 "a_n3011_n274#" "a_n2577_122#" 60 0 "a_n2625_n100#" 200 0 "a_n2529_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2655 -100 -2654 -99 l=30 w=200 "a_n3011_n274#" "a_n2673_n188#" 60 0 "a_n2721_n100#" 200 0 "a_n2625_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2751 -100 -2750 -99 l=30 w=200 "a_n3011_n274#" "a_n2769_122#" 60 0 "a_n2817_n100#" 200 0 "a_n2721_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -2847 -100 -2846 -99 l=30 w=200 "a_n3011_n274#" "a_n2865_n188#" 60 0 "a_n2909_n100#" 200 0 "a_n2817_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.mag
new file mode 100644
index 0000000..c7cc33b
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_LELFGX.mag
@@ -0,0 +1,1855 @@
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+<< properties >>
+string FIXED_BBOX -2994 -257 2994 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 60 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_T28DQP.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_T28DQP.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_T28DQP.mag
new file mode 100644
index 0000000..e2c34e2
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_T28DQP.mag
@@ -0,0 +1,184 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662690363
+<< error_p >>
+rect -159 172 -97 178
+rect -31 172 31 178
+rect 97 172 159 178
+rect -159 138 -147 172
+rect -31 138 -19 172
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+rect -31 -178 31 -172
+rect 97 -178 159 -172
+<< pwell >>
+rect -359 -310 359 310
+<< nmoslvt >>
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+rect -35 -100 35 100
+rect 93 -100 163 100
+<< ndiff >>
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+rect 163 -88 175 88
+rect 209 -88 221 88
+rect 163 -100 221 -88
+<< ndiffc >>
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+rect 47 -88 81 88
+rect 175 -88 209 88
+<< psubdiff >>
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+rect 289 178 323 240
+rect -323 -240 -289 -178
+rect 289 -240 323 -178
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+rect 227 -274 323 -240
+<< psubdiffcont >>
+rect -227 240 227 274
+rect -323 -178 -289 178
+rect 289 -178 323 178
+rect -227 -274 227 -240
+<< poly >>
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+rect -163 138 -147 172
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+<< polycont >>
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+rect -19 138 19 172
+rect 109 138 147 172
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+rect -19 -172 19 -138
+rect 109 -172 147 -138
+<< locali >>
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+rect -323 -240 -289 -178
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+rect -323 -274 -227 -240
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+<< viali >>
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+rect -81 -88 -47 88
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+<< metal1 >>
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+rect 41 -88 47 88
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+rect 19 -172 31 -138
+rect -31 -178 31 -172
+rect 97 -138 159 -132
+rect 97 -172 109 -138
+rect 147 -172 159 -138
+rect 97 -178 159 -172
+<< properties >>
+string FIXED_BBOX -306 -257 306 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1 l 0.35 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.ext

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.ext b/mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.ext
new file mode 100644
index 0000000..0d079c5
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.ext
@@ -0,0 +1,275 @@
+timestamp 1662510845
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_927_n100#" 466 89.3456 927 -100 ndif 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_831_n100#" 442 49.7893 831 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_735_n100#" 442 38.2599 735 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_639_n100#" 442 32.8201 639 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_543_n100#" 442 29.6865 543 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_447_n100#" 442 31.5008 447 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 442 30.364 351 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
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+cap "a_351_n100#" "a_n897_n100#" 10.9371
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+cap "a_351_n100#" "a_159_n100#" 87.4087
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+cap "a_n801_n100#" "a_735_n100#" 8.83052
+cap "a_639_n100#" "a_831_n100#" 87.4087
+cap "a_n945_n188#" "a_447_n100#" 103.259
+cap "a_255_n100#" "a_n417_n100#" 20.9177
+cap "a_n321_n100#" "a_n897_n100#" 24.6699
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+cap "a_351_n100#" "a_639_n100#" 53.425
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+cap "a_n321_n100#" "a_159_n100#" 30.0629
+cap "a_n129_n100#" "a_n705_n100#" 24.6699
+cap "a_n801_n100#" "a_n513_n100#" 53.425
+cap "a_n989_n100#" "a_159_n100#" 11.882
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+cap "a_n129_n100#" "a_n225_n100#" 241.535
+cap "a_n321_n100#" "a_639_n100#" 14.3638
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+cap "a_639_n100#" "a_n989_n100#" 8.29777
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+cap "a_543_n100#" "a_159_n100#" 38.4743
+cap "a_63_n100#" "a_927_n100#" 16.0389
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+cap "a_n609_n100#" "a_n417_n100#" 87.4087
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+cap "a_351_n100#" "a_n609_n100#" 14.3638
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+cap "a_63_n100#" "a_n801_n100#" 16.0389
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+cap "a_n945_n188#" "a_n801_n100#" 90.0091
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+device msubckt sky130_fd_pr__nfet_01v8_lvt 801 -100 802 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_735_n100#" 200 0 "a_831_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 705 -100 706 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_639_n100#" 200 0 "a_735_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 609 -100 610 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_543_n100#" 200 0 "a_639_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 513 -100 514 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 417 -100 418 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 321 -100 322 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 225 -100 226 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 129 -100 130 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt 33 -100 34 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -63 -100 -62 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -159 -100 -158 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -255 -100 -254 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -351 -100 -350 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -447 -100 -446 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -543 -100 -542 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n609_n100#" 200 0 "a_n513_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -639 -100 -638 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n705_n100#" 200 0 "a_n609_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -735 -100 -734 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n801_n100#" 200 0 "a_n705_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -831 -100 -830 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n897_n100#" 200 0 "a_n801_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8_lvt -927 -100 -926 -99 l=30 w=200 "a_n1091_n274#" "a_n945_n188#" 60 0 "a_n989_n100#" 200 0 "a_n897_n100#" 200 0

mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.mag

diff --git a/mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.mag b/mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.mag
new file mode 100644
index 0000000..ddc567e
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_lvt_YTLFGX.mag
@@ -0,0 +1,619 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662510845
+<< pwell >>
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+<< properties >>
+string FIXED_BBOX -1074 -257 1074 257
+string gencell sky130_fd_pr__nfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.15 m 1 nf 20 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag

diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
deleted file mode 100644
index 508a2da..0000000
--- a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
+++ /dev/null
@@ -1,98 +0,0 @@
-magic
-tech $PDK
-timestamp 1606063140
-<< pwell >>
-rect -154 -229 154 229
-<< mvnmos >>
-rect -40 -100 40 100
-<< mvndiff >>
-rect -69 94 -40 100
-rect -69 -94 -63 94
-rect -46 -94 -40 94
-rect -69 -100 -40 -94
-rect 40 94 69 100
-rect 40 -94 46 94
-rect 63 -94 69 94
-rect 40 -100 69 -94
-<< mvndiffc >>
-rect -63 -94 -46 94
-rect 46 -94 63 94
-<< mvpsubdiff >>
-rect -136 205 136 211
-rect -136 188 -82 205
-rect 82 188 136 205
-rect -136 182 136 188
-rect -136 -182 -107 182
-rect 107 157 136 182
-rect 107 -157 113 157
-rect 130 -157 136 157
-rect 107 -182 136 -157
-rect -136 -188 136 -182
-rect -136 -205 -82 -188
-rect 82 -205 136 -188
-rect -136 -211 136 -205
-<< mvpsubdiffcont >>
-rect -82 188 82 205
-rect 113 -157 130 157
-rect -82 -205 82 -188
-<< poly >>
-rect -40 136 40 144
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -40 100 40 119
-rect -40 -119 40 -100
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect -40 -144 40 -136
-<< polycont >>
-rect -32 119 32 136
-rect -32 -136 32 -119
-<< locali >>
-rect -130 188 -82 205
-rect 82 188 130 205
-rect -130 -19 -113 188
-rect 113 157 130 188
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -63 94 -46 102
-rect -63 -102 -46 -94
-rect 46 94 63 102
-rect 46 -102 63 -94
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect 113 -188 130 -157
-rect -130 -205 -82 -188
-rect 82 -205 130 -188
-<< viali >>
-rect -32 119 32 136
-rect -130 -188 -113 -19
-rect -63 -94 -46 94
-rect 46 -94 63 94
-rect -32 -136 32 -119
-<< metal1 >>
-rect -38 136 38 139
-rect -38 119 -32 136
-rect 32 119 38 136
-rect -38 116 38 119
-rect -66 94 -43 100
-rect -133 -19 -110 -13
-rect -133 -188 -130 -19
-rect -113 -188 -110 -19
-rect -66 -94 -63 94
-rect -46 -94 -43 94
-rect -66 -100 -43 -94
-rect 43 94 66 100
-rect 43 -94 46 94
-rect 63 -94 66 94
-rect 43 -100 66 -94
-rect -38 -119 38 -116
-rect -38 -136 -32 -119
-rect 32 -136 38 -119
-rect -38 -139 38 -136
-rect -133 -194 -110 -188
-<< properties >>
-string gencell sky130_fd_pr__nfet_g5v0d10v5
-string FIXED_BBOX -121 -196 121 196
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl +45 viagt 0
-string library sky130
-<< end >>

mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag

diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
deleted file mode 100644
index dbb8180..0000000
--- a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
+++ /dev/null
@@ -1,326 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< pwell >>
-rect -962 -458 962 458
-<< mvnmos >>
-rect -734 -200 -574 200
-rect -516 -200 -356 200
-rect -298 -200 -138 200
-rect -80 -200 80 200
-rect 138 -200 298 200
-rect 356 -200 516 200
-rect 574 -200 734 200
-<< mvndiff >>
-rect -792 188 -734 200
-rect -792 -188 -780 188
-rect -746 -188 -734 188
-rect -792 -200 -734 -188
-rect -574 188 -516 200
-rect -574 -188 -562 188
-rect -528 -188 -516 188
-rect -574 -200 -516 -188
-rect -356 188 -298 200
-rect -356 -188 -344 188
-rect -310 -188 -298 188
-rect -356 -200 -298 -188
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-rect 298 188 356 200
-rect 298 -188 310 188
-rect 344 -188 356 188
-rect 298 -200 356 -188
-rect 516 188 574 200
-rect 516 -188 528 188
-rect 562 -188 574 188
-rect 516 -200 574 -188
-rect 734 188 792 200
-rect 734 -188 746 188
-rect 780 -188 792 188
-rect 734 -200 792 -188
-<< mvndiffc >>
-rect -780 -188 -746 188
-rect -562 -188 -528 188
-rect -344 -188 -310 188
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect 310 -188 344 188
-rect 528 -188 562 188
-rect 746 -188 780 188
-<< mvpsubdiff >>
-rect -926 410 926 422
-rect -926 376 -818 410
-rect 818 376 926 410
-rect -926 364 926 376
-rect -926 314 -868 364
-rect -926 -314 -914 314
-rect -880 -314 -868 314
-rect 868 314 926 364
-rect -926 -364 -868 -314
-rect 868 -314 880 314
-rect 914 -314 926 314
-rect 868 -364 926 -314
-rect -926 -376 926 -364
-rect -926 -410 -818 -376
-rect 818 -410 926 -376
-rect -926 -422 926 -410
-<< mvpsubdiffcont >>
-rect -818 376 818 410
-rect -914 -314 -880 314
-rect 880 -314 914 314
-rect -818 -410 818 -376
-<< poly >>
-rect -734 272 -574 288
-rect -734 238 -718 272
-rect -590 238 -574 272
-rect -734 200 -574 238
-rect -516 272 -356 288
-rect -516 238 -500 272
-rect -372 238 -356 272
-rect -516 200 -356 238
-rect -298 272 -138 288
-rect -298 238 -282 272
-rect -154 238 -138 272
-rect -298 200 -138 238
-rect -80 272 80 288
-rect -80 238 -64 272
-rect 64 238 80 272
-rect -80 200 80 238
-rect 138 272 298 288
-rect 138 238 154 272
-rect 282 238 298 272
-rect 138 200 298 238
-rect 356 272 516 288
-rect 356 238 372 272
-rect 500 238 516 272
-rect 356 200 516 238
-rect 574 272 734 288
-rect 574 238 590 272
-rect 718 238 734 272
-rect 574 200 734 238
-rect -734 -238 -574 -200
-rect -734 -272 -718 -238
-rect -590 -272 -574 -238
-rect -734 -288 -574 -272
-rect -516 -238 -356 -200
-rect -516 -272 -500 -238
-rect -372 -272 -356 -238
-rect -516 -288 -356 -272
-rect -298 -238 -138 -200
-rect -298 -272 -282 -238
-rect -154 -272 -138 -238
-rect -298 -288 -138 -272
-rect -80 -238 80 -200
-rect -80 -272 -64 -238
-rect 64 -272 80 -238
-rect -80 -288 80 -272
-rect 138 -238 298 -200
-rect 138 -272 154 -238
-rect 282 -272 298 -238
-rect 138 -288 298 -272
-rect 356 -238 516 -200
-rect 356 -272 372 -238
-rect 500 -272 516 -238
-rect 356 -288 516 -272
-rect 574 -238 734 -200
-rect 574 -272 590 -238
-rect 718 -272 734 -238
-rect 574 -288 734 -272
-<< polycont >>
-rect -718 238 -590 272
-rect -500 238 -372 272
-rect -282 238 -154 272
-rect -64 238 64 272
-rect 154 238 282 272
-rect 372 238 500 272
-rect 590 238 718 272
-rect -718 -272 -590 -238
-rect -500 -272 -372 -238
-rect -282 -272 -154 -238
-rect -64 -272 64 -238
-rect 154 -272 282 -238
-rect 372 -272 500 -238
-rect 590 -272 718 -238
-<< locali >>
-rect -914 376 -818 410
-rect 818 376 914 410
-rect -914 314 -880 376
-rect 880 314 914 376
-rect -734 238 -718 272
-rect -590 238 -574 272
-rect -516 238 -500 272
-rect -372 238 -356 272
-rect -298 238 -282 272
-rect -154 238 -138 272
-rect -80 238 -64 272
-rect 64 238 80 272
-rect 138 238 154 272
-rect 282 238 298 272
-rect 356 238 372 272
-rect 500 238 516 272
-rect 574 238 590 272
-rect 718 238 734 272
-rect -780 188 -746 204
-rect -780 -204 -746 -188
-rect -562 188 -528 204
-rect -562 -204 -528 -188
-rect -344 188 -310 204
-rect -344 -204 -310 -188
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect 310 188 344 204
-rect 310 -204 344 -188
-rect 528 188 562 204
-rect 528 -204 562 -188
-rect 746 188 780 204
-rect 746 -204 780 -188
-rect -734 -272 -718 -238
-rect -590 -272 -574 -238
-rect -516 -272 -500 -238
-rect -372 -272 -356 -238
-rect -298 -272 -282 -238
-rect -154 -272 -138 -238
-rect -80 -272 -64 -238
-rect 64 -272 80 -238
-rect 138 -272 154 -238
-rect 282 -272 298 -238
-rect 356 -272 372 -238
-rect 500 -272 516 -238
-rect 574 -272 590 -238
-rect 718 -272 734 -238
-rect -914 -376 -880 -314
-rect 880 -376 914 -314
-rect -914 -410 -818 -376
-rect 818 -410 914 -376
-<< viali >>
-rect -914 -263 -880 263
-rect -718 238 -590 272
-rect -500 238 -372 272
-rect -282 238 -154 272
-rect -64 238 64 272
-rect 154 238 282 272
-rect 372 238 500 272
-rect 590 238 718 272
-rect -780 21 -746 171
-rect -562 -171 -528 -21
-rect -344 21 -310 171
-rect -126 -171 -92 -21
-rect 92 21 126 171
-rect 310 -171 344 -21
-rect 528 21 562 171
-rect 746 -171 780 -21
-rect -718 -272 -590 -238
-rect -500 -272 -372 -238
-rect -282 -272 -154 -238
-rect -64 -272 64 -238
-rect 154 -272 282 -238
-rect 372 -272 500 -238
-rect 590 -272 718 -238
-<< metal1 >>
-rect -920 263 -874 275
-rect -920 -263 -914 263
-rect -880 -263 -874 263
-rect -730 272 -578 278
-rect -730 238 -718 272
-rect -590 238 -578 272
-rect -730 232 -578 238
-rect -512 272 -360 278
-rect -512 238 -500 272
-rect -372 238 -360 272
-rect -512 232 -360 238
-rect -294 272 -142 278
-rect -294 238 -282 272
-rect -154 238 -142 272
-rect -294 232 -142 238
-rect -76 272 76 278
-rect -76 238 -64 272
-rect 64 238 76 272
-rect -76 232 76 238
-rect 142 272 294 278
-rect 142 238 154 272
-rect 282 238 294 272
-rect 142 232 294 238
-rect 360 272 512 278
-rect 360 238 372 272
-rect 500 238 512 272
-rect 360 232 512 238
-rect 578 272 730 278
-rect 578 238 590 272
-rect 718 238 730 272
-rect 578 232 730 238
-rect -786 171 -740 183
-rect -786 21 -780 171
-rect -746 21 -740 171
-rect -786 9 -740 21
-rect -350 171 -304 183
-rect -350 21 -344 171
-rect -310 21 -304 171
-rect -350 9 -304 21
-rect 86 171 132 183
-rect 86 21 92 171
-rect 126 21 132 171
-rect 86 9 132 21
-rect 522 171 568 183
-rect 522 21 528 171
-rect 562 21 568 171
-rect 522 9 568 21
-rect -568 -21 -522 -9
-rect -568 -171 -562 -21
-rect -528 -171 -522 -21
-rect -568 -183 -522 -171
-rect -132 -21 -86 -9
-rect -132 -171 -126 -21
-rect -92 -171 -86 -21
-rect -132 -183 -86 -171
-rect 304 -21 350 -9
-rect 304 -171 310 -21
-rect 344 -171 350 -21
-rect 304 -183 350 -171
-rect 740 -21 786 -9
-rect 740 -171 746 -21
-rect 780 -171 786 -21
-rect 740 -183 786 -171
-rect -920 -275 -874 -263
-rect -730 -238 -578 -232
-rect -730 -272 -718 -238
-rect -590 -272 -578 -238
-rect -730 -278 -578 -272
-rect -512 -238 -360 -232
-rect -512 -272 -500 -238
-rect -372 -272 -360 -238
-rect -512 -278 -360 -272
-rect -294 -238 -142 -232
-rect -294 -272 -282 -238
-rect -154 -272 -142 -238
-rect -294 -278 -142 -272
-rect -76 -238 76 -232
-rect -76 -272 -64 -238
-rect 64 -272 76 -238
-rect -76 -278 76 -272
-rect 142 -238 294 -232
-rect 142 -272 154 -238
-rect 282 -272 294 -238
-rect 142 -278 294 -272
-rect 360 -238 512 -232
-rect 360 -272 372 -238
-rect 500 -272 512 -238
-rect 360 -278 512 -272
-rect 578 -238 730 -232
-rect 578 -272 590 -238
-rect 718 -272 730 -238
-rect 578 -278 730 -272
-<< properties >>
-string gencell sky130_fd_pr__nfet_g5v0d10v5
-string FIXED_BBOX -897 -393 897 393
-string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc +40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 70 viagt 0
-string library sky130
-<< end >>

mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag

diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
deleted file mode 100644
index 64df388..0000000
--- a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
+++ /dev/null
@@ -1,93 +0,0 @@
-magic
-tech $PDK
-timestamp 1605994897
-<< pwell >>
-rect -154 -229 154 229
-<< mvnmos >>
-rect -40 -100 40 100
-<< mvndiff >>
-rect -69 94 -40 100
-rect -69 -94 -63 94
-rect -46 -94 -40 94
-rect -69 -100 -40 -94
-rect 40 94 69 100
-rect 40 -94 46 94
-rect 63 -94 69 94
-rect 40 -100 69 -94
-<< mvndiffc >>
-rect -63 -94 -46 94
-rect 46 -94 63 94
-<< mvpsubdiff >>
-rect -136 205 136 211
-rect -136 188 -82 205
-rect 82 188 136 205
-rect -136 182 136 188
-rect -136 -182 -107 182
-rect 107 157 136 182
-rect 107 -157 113 157
-rect 130 -157 136 157
-rect 107 -182 136 -157
-rect -136 -188 136 -182
-rect -136 -205 -82 -188
-rect 82 -205 136 -188
-rect -136 -211 136 -205
-<< mvpsubdiffcont >>
-rect -82 188 82 205
-rect 113 -157 130 157
-rect -82 -205 82 -188
-<< poly >>
-rect -40 136 40 144
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -40 100 40 119
-rect -40 -119 40 -100
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect -40 -144 40 -136
-<< polycont >>
-rect -32 119 32 136
-rect -32 -136 32 -119
-<< locali >>
-rect -130 188 -82 205
-rect 82 188 130 205
-rect -130 -188 -113 188
-rect 113 157 130 188
-rect -40 119 -32 136
-rect 32 119 40 136
-rect -63 94 -46 102
-rect -63 -102 -46 -94
-rect 46 94 63 102
-rect 46 -102 63 -94
-rect -40 -136 -32 -119
-rect 32 -136 40 -119
-rect 113 -188 130 -157
-rect -130 -205 -82 -188
-rect 82 -205 130 -188
-<< viali >>
-rect -32 119 32 136
-rect -63 -94 -46 94
-rect 46 -94 63 94
-rect -32 -136 32 -119
-<< metal1 >>
-rect -38 136 38 139
-rect -38 119 -32 136
-rect 32 119 38 136
-rect -38 116 38 119
-rect -66 94 -43 100
-rect -66 -94 -63 94
-rect -46 -94 -43 94
-rect -66 -100 -43 -94
-rect 43 94 66 100
-rect 43 -94 46 94
-rect 63 -94 66 94
-rect 43 -100 66 -94
-rect -38 -119 38 -116
-rect -38 -136 -32 -119
-rect 32 -136 38 -119
-rect -38 -139 38 -136
-<< properties >>
-string gencell sky130_fd_pr__nfet_g5v0d10v5
-string FIXED_BBOX -121 -196 121 196
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
-string library sky130
-<< end >>

mag/sky130_fd_pr__pfet_01v8_lvt_42Y485.mag

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_42Y485.mag b/mag/sky130_fd_pr__pfet_01v8_lvt_42Y485.mag
new file mode 100644
index 0000000..712e686
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_42Y485.mag
@@ -0,0 +1,184 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662690363
+<< error_p >>
+rect -159 181 -97 187
+rect -31 181 31 187
+rect 97 181 159 187
+rect -159 147 -147 181
+rect -31 147 -19 181
+rect 97 147 109 181
+rect -159 141 -97 147
+rect -31 141 31 147
+rect 97 141 159 147
+rect -159 -147 -97 -141
+rect -31 -147 31 -141
+rect 97 -147 159 -141
+rect -159 -181 -147 -147
+rect -31 -181 -19 -147
+rect 97 -181 109 -147
+rect -159 -187 -97 -181
+rect -31 -187 31 -181
+rect 97 -187 159 -181
+<< nwell >>
+rect -359 -319 359 319
+<< pmoslvt >>
+rect -163 -100 -93 100
+rect -35 -100 35 100
+rect 93 -100 163 100
+<< pdiff >>
+rect -221 88 -163 100
+rect -221 -88 -209 88
+rect -175 -88 -163 88
+rect -221 -100 -163 -88
+rect -93 88 -35 100
+rect -93 -88 -81 88
+rect -47 -88 -35 88
+rect -93 -100 -35 -88
+rect 35 88 93 100
+rect 35 -88 47 88
+rect 81 -88 93 88
+rect 35 -100 93 -88
+rect 163 88 221 100
+rect 163 -88 175 88
+rect 209 -88 221 88
+rect 163 -100 221 -88
+<< pdiffc >>
+rect -209 -88 -175 88
+rect -81 -88 -47 88
+rect 47 -88 81 88
+rect 175 -88 209 88
+<< nsubdiff >>
+rect -323 249 -227 283
+rect 227 249 323 283
+rect -323 187 -289 249
+rect 289 187 323 249
+rect -323 -249 -289 -187
+rect 289 -249 323 -187
+rect -323 -283 -227 -249
+rect 227 -283 323 -249
+<< nsubdiffcont >>
+rect -227 249 227 283
+rect -323 -187 -289 187
+rect 289 -187 323 187
+rect -227 -283 227 -249
+<< poly >>
+rect -163 181 -93 197
+rect -163 147 -147 181
+rect -109 147 -93 181
+rect -163 100 -93 147
+rect -35 181 35 197
+rect -35 147 -19 181
+rect 19 147 35 181
+rect -35 100 35 147
+rect 93 181 163 197
+rect 93 147 109 181
+rect 147 147 163 181
+rect 93 100 163 147
+rect -163 -147 -93 -100
+rect -163 -181 -147 -147
+rect -109 -181 -93 -147
+rect -163 -197 -93 -181
+rect -35 -147 35 -100
+rect -35 -181 -19 -147
+rect 19 -181 35 -147
+rect -35 -197 35 -181
+rect 93 -147 163 -100
+rect 93 -181 109 -147
+rect 147 -181 163 -147
+rect 93 -197 163 -181
+<< polycont >>
+rect -147 147 -109 181
+rect -19 147 19 181
+rect 109 147 147 181
+rect -147 -181 -109 -147
+rect -19 -181 19 -147
+rect 109 -181 147 -147
+<< locali >>
+rect -323 249 -227 283
+rect 227 249 323 283
+rect -323 187 -289 249
+rect 289 187 323 249
+rect -163 147 -147 181
+rect -109 147 -93 181
+rect -35 147 -19 181
+rect 19 147 35 181
+rect 93 147 109 181
+rect 147 147 163 181
+rect -209 88 -175 104
+rect -209 -104 -175 -88
+rect -81 88 -47 104
+rect -81 -104 -47 -88
+rect 47 88 81 104
+rect 47 -104 81 -88
+rect 175 88 209 104
+rect 175 -104 209 -88
+rect -163 -181 -147 -147
+rect -109 -181 -93 -147
+rect -35 -181 -19 -147
+rect 19 -181 35 -147
+rect 93 -181 109 -147
+rect 147 -181 163 -147
+rect -323 -249 -289 -187
+rect 289 -249 323 -187
+rect -323 -283 -227 -249
+rect 227 -283 323 -249
+<< viali >>
+rect -147 147 -109 181
+rect -19 147 19 181
+rect 109 147 147 181
+rect -209 -88 -175 88
+rect -81 -88 -47 88
+rect 47 -88 81 88
+rect 175 -88 209 88
+rect -147 -181 -109 -147
+rect -19 -181 19 -147
+rect 109 -181 147 -147
+<< metal1 >>
+rect -159 181 -97 187
+rect -159 147 -147 181
+rect -109 147 -97 181
+rect -159 141 -97 147
+rect -31 181 31 187
+rect -31 147 -19 181
+rect 19 147 31 181
+rect -31 141 31 147
+rect 97 181 159 187
+rect 97 147 109 181
+rect 147 147 159 181
+rect 97 141 159 147
+rect -215 88 -169 100
+rect -215 -88 -209 88
+rect -175 -88 -169 88
+rect -215 -100 -169 -88
+rect -87 88 -41 100
+rect -87 -88 -81 88
+rect -47 -88 -41 88
+rect -87 -100 -41 -88
+rect 41 88 87 100
+rect 41 -88 47 88
+rect 81 -88 87 88
+rect 41 -100 87 -88
+rect 169 88 215 100
+rect 169 -88 175 88
+rect 209 -88 215 88
+rect 169 -100 215 -88
+rect -159 -147 -97 -141
+rect -159 -181 -147 -147
+rect -109 -181 -97 -147
+rect -159 -187 -97 -181
+rect -31 -147 31 -141
+rect -31 -181 -19 -147
+rect 19 -181 31 -147
+rect -31 -187 31 -181
+rect 97 -147 159 -141
+rect 97 -181 109 -147
+rect 147 -181 159 -147
+rect 97 -187 159 -181
+<< properties >>
+string FIXED_BBOX -306 -266 306 266
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string library sky130
+string parameters w 1 l 0.35 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__pfet_01v8_lvt_75KH85.ext

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_75KH85.ext b/mag/sky130_fd_pr__pfet_01v8_lvt_75KH85.ext
new file mode 100644
index 0000000..cbea10e
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_75KH85.ext
@@ -0,0 +1,35 @@
+timestamp 1662690363
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_163_n64#" 758 0 163 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_35_n64#" 758 0 35 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n93_n64#" 758 0 -93 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n64#" 758 0 -221 -64 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_93_n161#" 249 0 93 -161 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22610 786 0 0 2380 208 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n35_n161#" 249 0 -35 -161 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22610 786 0 0 2380 208 2852 216 0 0 0 0 0 0 0 0 0 0
+node "a_n163_n161#" 249 0 -163 -161 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22610 786 0 0 2380 208 2852 216 0 0 0 0 0 0 0 0 0 0
+node "w_n359_n284#" 9323 1223.47 -359 -284 nw 0 0 0 0 407824 2572 0 0 73032 4296 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 73032 4296 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_163_n64#" "a_n221_n64#" 38.4743
+cap "w_n359_n284#" "a_n221_n64#" 112.192
+cap "w_n359_n284#" "a_n35_n161#" 125.778
+cap "w_n359_n284#" "a_163_n64#" 111.626
+cap "a_n163_n161#" "a_n35_n161#" 78.1837
+cap "a_n93_n64#" "a_n221_n64#" 151.957
+cap "w_n359_n284#" "a_n163_n161#" 165.902
+cap "a_n93_n64#" "a_163_n64#" 61.3771
+cap "a_n93_n64#" "w_n359_n284#" 72.0069
+cap "a_93_n161#" "a_n35_n161#" 78.1837
+cap "w_n359_n284#" "a_93_n161#" 159.036
+cap "a_n221_n64#" "a_35_n64#" 61.3771
+cap "a_n163_n161#" "a_93_n161#" 25.1097
+cap "a_163_n64#" "a_35_n64#" 151.957
+cap "w_n359_n284#" "a_35_n64#" 71.8097
+cap "a_n93_n64#" "a_35_n64#" 151.957
+device msubckt sky130_fd_pr__pfet_01v8_lvt 93 -64 94 -63 l=70 w=200 "w_n359_n284#" "a_93_n161#" 140 0 "a_35_n64#" 200 0 "a_163_n64#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_lvt -35 -64 -34 -63 l=70 w=200 "w_n359_n284#" "a_n35_n161#" 140 0 "a_n93_n64#" 200 0 "a_35_n64#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8_lvt -163 -64 -162 -63 l=70 w=200 "w_n359_n284#" "a_n163_n161#" 140 0 "a_n221_n64#" 200 0 "a_n93_n64#" 200 0

mag/sky130_fd_pr__pfet_01v8_lvt_75KH85.mag

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index 0000000..4b6abf1
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+<< properties >>
+string FIXED_BBOX -306 -231 306 231
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string library sky130
+string parameters w 1 l 0.35 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__pfet_01v8_lvt_D3M3V4.mag

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_D3M3V4.mag b/mag/sky130_fd_pr__pfet_01v8_lvt_D3M3V4.mag
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index 0000000..dea0237
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_D3M3V4.mag
@@ -0,0 +1,1990 @@
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+<< properties >>
+string FIXED_BBOX -2994 -266 2994 266
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.35 m 1 nf 45 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.ext

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.ext b/mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.ext
new file mode 100644
index 0000000..cfd9979
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.ext
@@ -0,0 +1,304 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
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mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.mag

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.mag b/mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.mag
new file mode 100644
index 0000000..d05dc8d
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_D3M934.mag
@@ -0,0 +1,700 @@
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+string gencell sky130_fd_pr__pfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.35 m 1 nf 15 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
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mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.ext

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.ext b/mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.ext
new file mode 100644
index 0000000..8ba4bbc
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.ext
@@ -0,0 +1,754 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
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+node "a_n739_n197#" 361 0 -739 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "a_n867_n197#" 361 0 -867 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "a_n995_n197#" 361 0 -995 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "a_n1123_n197#" 361 0 -1123 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "a_n1251_n197#" 361 0 -1251 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "a_n1379_n197#" 361 0 -1379 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "a_n1507_n197#" 361 0 -1507 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "a_n1635_n197#" 361 0 -1635 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
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+node "a_n1891_n197#" 361 0 -1891 -197 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27580 928 0 0 4760 416 5704 432 0 0 0 0 0 0 0 0 0 0
+node "w_n2087_n319#" 41883 7989.04 -2087 -319 nw 0 0 0 0 2663012 9624 0 0 312800 18400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 312800 18400 0 0 0 0 0 0 0 0 0 0 0 0
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+cap "a_n1891_n197#" "a_n867_n197#" 8.98173
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+cap "a_n1565_n100#" "a_n285_n100#" 10.6547
+cap "a_n1693_n100#" "a_n285_n100#" 9.65722
+cap "a_n1123_n197#" "a_n99_n197#" 8.98173
+cap "w_n2087_n319#" "a_29_n197#" 216.212
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+cap "a_739_n100#" "a_483_n100#" 61.3771
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+cap "a_n1763_n197#" "a_n1635_n197#" 141.126
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+cap "a_n995_n197#" "a_669_n197#" 3.26349
+cap "a_29_n197#" "a_n1507_n197#" 5.85155
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+cap "a_355_n100#" "a_1379_n100#" 13.4288
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+cap "a_n29_n100#" "a_n1181_n100#" 11.882
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+cap "a_1565_n197#" "a_1437_n197#" 141.126
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+cap "a_n1123_n197#" "a_n1891_n197#" 12.2612
+cap "a_1437_n197#" "a_1821_n197#" 27.1097
+cap "a_157_n197#" "a_29_n197#" 141.126
+cap "a_n669_n100#" "a_n1437_n100#" 18.1562
+cap "a_995_n100#" "a_n541_n100#" 8.83052
+cap "a_n925_n100#" "a_227_n100#" 11.882
+cap "a_n611_n197#" "a_29_n197#" 14.9997
+cap "a_n355_n197#" "w_n2087_n319#" 216.212
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+cap "a_n1949_n100#" "a_n797_n100#" 11.882
+cap "a_n355_n197#" "a_n1507_n197#" 7.92226
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+cap "a_29_n197#" "a_925_n197#" 10.3683
+cap "a_n227_n197#" "a_n995_n197#" 12.2612
+cap "a_n29_n100#" "a_995_n100#" 13.4288
+cap "a_n285_n100#" "a_n1181_n100#" 15.4387
+cap "a_n1565_n100#" "a_n1053_n100#" 28.021
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+cap "a_285_n197#" "a_n867_n197#" 7.92226
+cap "w_n2087_n319#" "a_541_n197#" 213.786
+cap "a_n669_n100#" "a_n1181_n100#" 28.021
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+cap "a_n739_n197#" "a_669_n197#" 6.41003
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+cap "a_1507_n100#" "a_483_n100#" 13.4288
+cap "a_n413_n100#" "a_n1053_n100#" 22.0348
+cap "a_n925_n100#" "a_n669_n100#" 61.3771
+cap "a_1181_n197#" "a_925_n197#" 45.4667
+cap "a_n227_n197#" "a_413_n197#" 14.9997
+cap "w_n2087_n319#" "a_285_n197#" 215.813
+cap "a_483_n100#" "a_227_n100#" 61.3771
+cap "a_n99_n197#" "a_1053_n197#" 7.92226
+cap "a_1763_n100#" "a_1379_n100#" 38.4743
+cap "a_1693_n197#" "a_797_n197#" 10.3683
+cap "a_n227_n197#" "a_n1251_n197#" 8.98173
+cap "a_1181_n197#" "a_n99_n197#" 7.08637
+cap "a_n227_n197#" "a_n1123_n197#" 10.3683
+cap "w_n2087_n319#" "a_1891_n100#" 93.2923
+cap "a_1507_n100#" "a_355_n100#" 11.882
+cap "a_157_n197#" "a_285_n197#" 141.126
+cap "a_n355_n197#" "a_n1763_n197#" 6.41003
+cap "a_1565_n197#" "a_413_n197#" 7.92226
+cap "a_99_n100#" "a_n1309_n100#" 9.65722
+cap "a_n611_n197#" "a_285_n197#" 10.3683
+cap "a_739_n100#" "a_1763_n100#" 13.4288
+cap "a_n1565_n100#" "a_n797_n100#" 18.1562
+cap "a_n1693_n100#" "a_n797_n100#" 15.4387
+cap "a_1437_n197#" "a_413_n197#" 8.98173
+cap "a_611_n100#" "a_1635_n100#" 13.4288
+cap "a_n925_n100#" "a_n1053_n100#" 151.957
+cap "a_99_n100#" "a_n1437_n100#" 8.83052
+cap "a_n1565_n100#" "w_n2087_n319#" 34.5367
+cap "a_n1693_n100#" "w_n2087_n319#" 39.3183
+cap "a_1181_n197#" "a_1053_n197#" 141.126
+cap "a_413_n197#" "a_1821_n197#" 6.41003
+cap "a_227_n100#" "a_355_n100#" 151.957
+cap "a_29_n197#" "a_669_n197#" 14.9997
+cap "a_285_n197#" "a_925_n197#" 14.9997
+cap "a_n29_n100#" "a_1251_n100#" 10.6547
+cap "a_n1309_n100#" "a_n797_n100#" 28.021
+cap "a_483_n100#" "a_n413_n100#" 15.4387
+cap "a_n1437_n100#" "a_n797_n100#" 22.0348
+cap "a_n1309_n100#" "w_n2087_n319#" 30.0739
+cap "a_99_n100#" "a_n1181_n100#" 10.6547
+cap "w_n2087_n319#" "a_n1437_n100#" 31.8228
+cap "a_1891_n100#" "a_1379_n100#" 28.021
+cap "a_99_n100#" "a_1635_n100#" 8.83052
+cap "a_285_n197#" "a_n99_n197#" 27.1097
+cap "a_995_n100#" "a_611_n100#" 38.4743
+cap "a_1123_n100#" "a_1251_n100#" 151.957
+cap "a_n355_n197#" "a_669_n197#" 8.98173
+cap "a_797_n197#" "w_n2087_n319#" 206.688
+cap "a_n29_n100#" "a_n541_n100#" 28.021
+cap "a_n797_n100#" "a_n1181_n100#" 38.4743
+cap "a_n227_n197#" "a_29_n197#" 45.4667
+cap "a_n285_n100#" "a_1251_n100#" 8.83052
+cap "a_n157_n100#" "a_n1565_n100#" 9.65722
+cap "a_n157_n100#" "a_n1693_n100#" 8.83052
+cap "w_n2087_n319#" "a_n1181_n100#" 28.8529
+cap "a_285_n197#" "a_1053_n197#" 12.2612
+cap "a_n995_n197#" "a_n867_n197#" 141.126
+cap "a_739_n100#" "a_1891_n100#" 11.882
+cap "a_355_n100#" "a_n413_n100#" 18.1562
+cap "w_n2087_n319#" "a_1635_n100#" 38.2252
+cap "a_669_n197#" "a_541_n197#" 141.126
+cap "a_285_n197#" "a_1181_n197#" 10.3683
+cap "a_413_n197#" "a_n995_n197#" 6.41003
+cap "a_n483_n197#" "w_n2087_n319#" 217.453
+cap "a_99_n100#" "a_995_n100#" 15.4387
+cap "a_483_n100#" "a_n925_n100#" 9.65722
+cap "a_797_n197#" "a_157_n197#" 14.9997
+cap "a_n157_n100#" "a_n1309_n100#" 11.882
+cap "a_n483_n197#" "a_n1507_n197#" 8.98173
+cap "a_n611_n197#" "a_797_n197#" 6.41003
+cap "a_n1251_n197#" "a_n995_n197#" 45.4667
+cap "a_n157_n100#" "a_n1437_n100#" 10.6547
+cap "a_1565_n197#" "a_29_n197#" 5.85155
+cap "a_n355_n197#" "a_n227_n197#" 141.126
+cap "a_n285_n100#" "a_n541_n100#" 61.3771
+cap "a_n1123_n197#" "a_n995_n197#" 141.126
+cap "a_n29_n100#" "a_1123_n100#" 11.882
+cap "a_797_n197#" "a_925_n197#" 141.126
+cap "a_1437_n197#" "a_29_n197#" 6.41003
+cap "a_n483_n197#" "a_157_n197#" 14.9997
+cap "a_n669_n100#" "a_n541_n100#" 151.957
+cap "w_n2087_n319#" "a_995_n100#" 27.6638
+cap "a_1763_n100#" "a_1891_n100#" 151.957
+cap "a_n611_n197#" "a_n483_n197#" 141.126
+cap "a_n29_n100#" "a_n285_n100#" 61.3771
+cap "a_n227_n197#" "a_541_n197#" 12.2612
+cap "a_n925_n100#" "a_355_n100#" 10.6547
+cap "a_n157_n100#" "a_n1181_n100#" 13.4288
+cap "a_n739_n197#" "a_n867_n197#" 141.126
+cap "a_n867_n197#" "a_n1635_n197#" 12.2612
+cap "a_1635_n100#" "a_1379_n100#" 61.3771
+cap "a_n29_n100#" "a_n669_n100#" 22.0348
+cap "a_797_n197#" "a_n99_n197#" 10.3683
+cap "a_n483_n197#" "a_925_n197#" 6.41003
+cap "a_867_n100#" "a_611_n100#" 61.3771
+cap "a_413_n197#" "a_n739_n197#" 7.92226
+cap "a_1123_n100#" "a_n285_n100#" 9.65722
+cap "a_1309_n197#" "a_413_n197#" 10.3683
+cap "a_1693_n197#" "a_669_n197#" 8.98173
+cap "a_n483_n197#" "a_n99_n197#" 27.1097
+cap "a_n1251_n197#" "a_n739_n197#" 19.3132
+cap "a_n1251_n197#" "a_n1635_n197#" 27.1097
+cap "a_739_n100#" "a_1635_n100#" 15.4387
+cap "a_n541_n100#" "a_n1053_n100#" 28.021
+cap "a_797_n197#" "a_1053_n197#" 45.4667
+cap "a_1565_n197#" "a_541_n197#" 8.98173
+cap "a_n1123_n197#" "a_n1635_n197#" 19.3132
+cap "a_n1949_n100#" "a_n413_n100#" 8.83052
+cap "a_n1123_n197#" "a_n739_n197#" 27.1097
+cap "a_n1763_n197#" "w_n2087_n319#" 223.708
+cap "a_995_n100#" "a_1379_n100#" 38.4743
+cap "a_n157_n100#" "a_995_n100#" 11.882
+cap "a_797_n197#" "a_1181_n197#" 27.1097
+cap "a_1437_n197#" "a_541_n197#" 10.3683
+cap "a_n1763_n197#" "a_n1507_n197#" 45.4667
+cap "a_99_n100#" "a_867_n100#" 18.1562
+cap "a_n669_n100#" "a_n285_n100#" 38.4743
+cap "a_1821_n197#" "a_541_n197#" 7.08637
+cap "a_n29_n100#" "a_n1053_n100#" 13.4288
+cap "a_29_n197#" "a_n995_n197#" 8.98173
+cap "a_n483_n197#" "a_n1891_n197#" 6.41003
+cap "a_1507_n100#" "a_611_n100#" 15.4387
+cap "a_n483_n197#" "a_1053_n197#" 5.85155
+cap "a_n1821_n100#" "a_n413_n100#" 9.65722
+cap "a_n1379_n197#" "a_n867_n197#" 19.3132
+cap "a_n483_n197#" "a_1181_n197#" 3.26349
+cap "a_739_n100#" "a_995_n100#" 61.3771
+cap "a_n611_n197#" "a_n1763_n197#" 7.92226
+cap "a_1763_n100#" "a_1635_n100#" 151.957
+cap "a_483_n100#" "a_1251_n100#" 18.1562
+cap "a_227_n100#" "a_611_n100#" 38.4743
+cap "a_867_n100#" "w_n2087_n319#" 27.0787
+cap "a_99_n100#" "a_1507_n100#" 9.65722
+cap "a_n925_n100#" "a_n1949_n100#" 13.4288
+cap "a_n355_n197#" "a_n995_n197#" 14.9997
+cap "a_n1379_n197#" "a_n1251_n197#" 141.126
+cap "a_n285_n100#" "a_n1053_n100#" 18.1562
+cap "a_797_n197#" "a_285_n197#" 19.3132
+cap "a_n1379_n197#" "a_n1123_n197#" 45.4667
+cap "w_n2087_n319#" "a_669_n197#" 210.699
+cap "a_n669_n100#" "a_n1053_n100#" 38.4743
+cap "a_n1693_n100#" "a_n1565_n100#" 151.957
+cap "a_1565_n197#" "a_1693_n197#" 141.126
+cap "a_99_n100#" "a_227_n100#" 151.957
+cap "a_483_n100#" "a_n541_n100#" 13.4288
+cap "a_1763_n100#" "a_995_n100#" 18.1562
+cap "a_n925_n100#" "a_n1821_n100#" 15.4387
+cap "a_1437_n197#" "a_1693_n197#" 45.4667
+cap "a_29_n197#" "a_n739_n197#" 12.2612
+cap "a_n995_n197#" "a_541_n197#" 5.85155
+cap "a_29_n197#" "a_n1635_n197#" 3.26349
+cap "a_n1763_n197#" "a_n99_n197#" 3.26349
+cap "a_355_n100#" "a_1251_n100#" 15.4387
+cap "a_n1309_n100#" "a_n1565_n100#" 61.3771
+cap "a_1507_n100#" "w_n2087_n319#" 33.6325
+cap "a_1693_n197#" "a_1821_n197#" 141.126
+cap "a_1309_n197#" "a_29_n197#" 7.08637
+cap "a_n1693_n100#" "a_n1309_n100#" 38.4743
+cap "a_n483_n197#" "a_285_n197#" 12.2612
+cap "a_867_n100#" "a_1379_n100#" 28.021
+cap "a_n29_n100#" "a_483_n100#" 28.021
+cap "a_n1565_n100#" "a_n1437_n100#" 151.957
+cap "a_157_n197#" "a_669_n197#" 19.3132
+cap "a_n157_n100#" "a_867_n100#" 13.4288
+cap "a_611_n100#" "a_n413_n100#" 13.4288
+cap "a_227_n100#" "a_n797_n100#" 13.4288
+cap "a_n1693_n100#" "a_n1437_n100#" 61.3771
+cap "a_n611_n197#" "a_669_n197#" 7.08637
+cap "a_n1763_n197#" "a_n1891_n197#" 141.126
+cap "a_227_n100#" "w_n2087_n319#" 21.985
+cap "a_1635_n100#" "a_1891_n100#" 61.3771
+cap "a_n227_n197#" "w_n2087_n319#" 216.212
+cap "a_n1309_n100#" "a_n1437_n100#" 151.957
+cap "a_n355_n197#" "a_n1635_n197#" 7.08637
+cap "a_n541_n100#" "a_355_n100#" 15.4387
+cap "a_925_n197#" "a_669_n197#" 45.4667
+cap "a_n355_n197#" "a_1309_n197#" 3.26349
+cap "a_n355_n197#" "a_n739_n197#" 27.1097
+cap "a_n227_n197#" "a_n1507_n197#" 7.08637
+cap "a_483_n100#" "a_1123_n100#" 22.0348
+cap "a_739_n100#" "a_867_n100#" 151.957
+cap "a_n1565_n100#" "a_n1181_n100#" 38.4743
+cap "a_99_n100#" "a_n413_n100#" 28.021
+cap "a_n1693_n100#" "a_n1181_n100#" 28.021
+cap "a_1507_n100#" "a_1379_n100#" 151.957
+cap "a_n29_n100#" "a_355_n100#" 38.4743
+cap "a_483_n100#" "a_n285_n100#" 18.1562
+cap "a_n227_n197#" "a_157_n197#" 27.1097
+cap "a_n99_n197#" "a_669_n197#" 12.2612
+cap "a_n739_n197#" "a_541_n197#" 7.08637
+cap "a_n1379_n197#" "a_29_n197#" 6.41003
+cap "a_1565_n197#" "w_n2087_n319#" 169.528
+cap "a_995_n100#" "a_1891_n100#" 15.4387
+cap "a_483_n100#" "a_n669_n100#" 11.882
+cap "a_n1309_n100#" "a_n1181_n100#" 151.957
+cap "a_1309_n197#" "a_541_n197#" 12.2612
+cap "a_n611_n197#" "a_n227_n197#" 27.1097
+cap "a_1437_n197#" "w_n2087_n319#" 176.349
+cap "a_n797_n100#" "a_n413_n100#" 38.4743
+cap "a_n925_n100#" "a_611_n100#" 8.83052
+cap "a_n1437_n100#" "a_n1181_n100#" 61.3771
+cap "w_n2087_n319#" "a_1821_n197#" 219.194
+cap "a_227_n100#" "a_1379_n100#" 11.882
+cap "a_n157_n100#" "a_227_n100#" 38.4743
+cap "w_n2087_n319#" "a_n413_n100#" 21.985
+cap "a_n227_n197#" "a_925_n197#" 7.92226
+cap "a_1763_n100#" "a_867_n100#" 15.4387
+cap "a_1123_n100#" "a_355_n100#" 18.1562
+cap "a_1053_n197#" "a_669_n197#" 27.1097
+cap "a_1507_n100#" "a_739_n100#" 18.1562
+cap "a_1565_n197#" "a_157_n197#" 6.41003
+cap "a_1181_n197#" "a_669_n197#" 19.3132
+cap "a_n285_n100#" "a_355_n100#" 22.0348
+cap "a_1437_n197#" "a_157_n197#" 7.08637
+cap "a_n483_n197#" "a_797_n197#" 7.08637
+cap "a_n355_n197#" "a_n1379_n197#" 8.98173
+cap "a_99_n100#" "a_n925_n100#" 13.4288
+cap "a_157_n197#" "a_1821_n197#" 3.26349
+cap "a_n227_n197#" "a_n99_n197#" 141.126
+cap "a_739_n100#" "a_227_n100#" 28.021
+cap "a_n669_n100#" "a_355_n100#" 13.4288
+cap "a_483_n100#" "a_n1053_n100#" 8.83052
+cap "a_1565_n197#" "a_925_n197#" 14.9997
+cap "a_1437_n197#" "a_925_n197#" 19.3132
+cap "a_1507_n100#" "a_1763_n100#" 61.3771
+cap "a_n925_n100#" "a_n797_n100#" 151.957
+cap "a_n1949_n100#" "a_n541_n100#" 9.65722
+cap "a_925_n197#" "a_1821_n197#" 10.3683
+cap "a_n227_n197#" "a_n1891_n197#" 3.26349
+cap "a_n925_n100#" "w_n2087_n319#" 27.2604
+cap "a_n227_n197#" "a_1053_n197#" 7.08637
+cap "a_n157_n100#" "a_n413_n100#" 61.3771
+cap "a_1309_n197#" "a_1693_n197#" 27.1097
+cap "a_1565_n197#" "a_n99_n197#" 3.26349
+cap "a_n227_n197#" "a_1181_n197#" 6.41003
+cap "a_1763_n100#" "a_227_n100#" 8.83052
+cap "a_413_n197#" "a_n867_n197#" 7.08637
+cap "w_n2087_n319#" "a_n995_n197#" 218.075
+cap "a_995_n100#" "a_1635_n100#" 22.0348
+cap "a_867_n100#" "a_1891_n100#" 13.4288
+cap "a_n1821_n100#" "a_n541_n100#" 10.6547
+cap "a_1437_n197#" "a_n99_n197#" 5.85155
+cap "a_n995_n197#" "a_n1507_n197#" 19.3132
+cap "a_355_n100#" "a_n1053_n100#" 9.65722
+cap "a_285_n197#" "a_669_n197#" 27.1097
+cap "a_n1251_n197#" "a_n867_n197#" 27.1097
+cap "a_739_n100#" "a_n413_n100#" 11.882
+cap "a_1565_n197#" "a_1053_n197#" 19.3132
+cap "a_n1123_n197#" "a_n867_n197#" 45.4667
+cap "a_413_n197#" "a_n1251_n197#" 3.26349
+cap "a_1565_n197#" "a_1181_n197#" 27.1097
+cap "a_1437_n197#" "a_1053_n197#" 27.1097
+cap "a_157_n197#" "a_n995_n197#" 7.92226
+cap "a_1821_n197#" "a_1053_n197#" 12.2612
+cap "a_n611_n197#" "a_n995_n197#" 27.1097
+cap "a_413_n197#" "a_n1123_n197#" 5.85155
+cap "a_1437_n197#" "a_1181_n197#" 45.4667
+cap "a_611_n100#" "a_1251_n100#" 22.0348
+cap "a_n157_n100#" "a_n925_n100#" 18.1562
+cap "a_1181_n197#" "a_1821_n197#" 14.9997
+cap "a_1507_n100#" "a_1891_n100#" 38.4743
+cap "a_n1949_n100#" "a_n669_n100#" 10.6547
+cap "a_n227_n197#" "a_285_n197#" 19.3132
+cap "a_n1123_n197#" "a_n1251_n197#" 141.126
+cap "w_n2087_n319#" "a_n739_n197#" 217.702
+cap "w_n2087_n319#" "a_n1635_n197#" 221.196
+cap "a_n483_n197#" "a_n1763_n197#" 7.08637
+cap "a_1309_n197#" "w_n2087_n319#" 183.296
+cap "a_n1821_n100#" "a_n285_n100#" 8.83052
+cap "a_n739_n197#" "a_n1507_n197#" 12.2612
+cap "a_n1507_n197#" "a_n1635_n197#" 141.126
+cap "a_99_n100#" "a_1251_n100#" 11.882
+cap "a_611_n100#" "a_n541_n100#" 11.882
+cap "a_n669_n100#" "a_n1821_n100#" 11.882
+cap "a_n995_n197#" "a_n99_n197#" 10.3683
+cap "a_483_n100#" "a_355_n100#" 151.957
+cap "a_157_n197#" "a_n739_n197#" 10.3683
+cap "a_867_n100#" "a_1635_n100#" 18.1562
+cap "a_1565_n197#" "a_285_n197#" 7.08637
+cap "a_1309_n197#" "a_157_n197#" 7.92226
+cap "a_n29_n100#" "a_611_n100#" 22.0348
+cap "a_797_n197#" "a_669_n197#" 141.126
+cap "a_1437_n197#" "a_285_n197#" 7.92226
+cap "a_n611_n197#" "a_n739_n197#" 141.126
+cap "a_n611_n197#" "a_n1635_n197#" 8.98173
+cap "a_n1949_n100#" "a_n1053_n100#" 15.4387
+cap "a_285_n197#" "a_1821_n197#" 5.85155
+cap "a_29_n197#" "a_n867_n197#" 10.3683
+cap "a_n1891_n197#" "a_n995_n197#" 10.3683
+cap "w_n2087_n319#" "a_1251_n100#" 29.5108
+cap "a_99_n100#" "a_n541_n100#" 22.0348
+cap "a_227_n100#" "a_n1309_n100#" 8.83052
+cap "a_413_n197#" "a_29_n197#" 27.1097
+cap "a_925_n197#" "a_n739_n197#" 3.26349
+cap "a_1309_n197#" "a_925_n197#" 27.1097
+cap "a_n1379_n197#" "w_n2087_n319#" 219.196
+cap "a_1123_n100#" "a_611_n100#" 28.021
+cap "a_n1821_n100#" "a_n1053_n100#" 18.1562
+cap "a_n483_n197#" "a_669_n197#" 7.92226
+cap "a_867_n100#" "a_995_n100#" 151.957
+cap "a_99_n100#" "a_n29_n100#" 151.957
+cap "a_29_n197#" "a_n1251_n197#" 7.08637
+cap "a_n1379_n197#" "a_n1507_n197#" 141.126
+cap "a_1507_n100#" "a_1635_n100#" 151.957
+cap "a_n797_n100#" "a_n541_n100#" 61.3771
+cap "a_n1123_n197#" "a_29_n197#" 7.92226
+cap "a_n99_n197#" "a_n1635_n197#" 5.85155
+cap "a_611_n100#" "a_n285_n100#" 15.4387
+cap "w_n2087_n319#" "a_n541_n100#" 25.899
+cap "a_1309_n197#" "a_n99_n197#" 6.41003
+cap "a_n739_n197#" "a_n99_n197#" 14.9997
+cap "a_n355_n197#" "a_n867_n197#" 19.3132
+cap "a_n227_n197#" "a_797_n197#" 8.98173
+cap "a_n669_n100#" "a_611_n100#" 10.6547
+cap "a_n355_n197#" "a_413_n197#" 12.2612
+cap "a_n1379_n197#" "a_157_n197#" 5.85155
+cap "a_n29_n100#" "a_n797_n100#" 18.1562
+cap "a_227_n100#" "a_n1181_n100#" 9.65722
+cap "a_n1565_n100#" "a_n413_n100#" 11.882
+cap "a_n1693_n100#" "a_n413_n100#" 10.6547
+cap "a_227_n100#" "a_1635_n100#" 9.65722
+cap "a_99_n100#" "a_1123_n100#" 13.4288
+cap "a_n29_n100#" "w_n2087_n319#" 21.985
+cap "a_n611_n197#" "a_n1379_n197#" 12.2612
+cap "a_n1891_n197#" "a_n739_n197#" 7.92226
+cap "a_n1891_n197#" "a_n1635_n197#" 45.4667
+cap "a_1379_n100#" "a_1251_n100#" 151.957
+cap "a_n157_n100#" "a_1251_n100#" 9.65722
+cap "a_541_n197#" "a_n867_n197#" 6.41003
+cap "a_n355_n197#" "a_n1251_n197#" 10.3683
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mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.mag

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.mag b/mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.mag
new file mode 100644
index 0000000..aa7b9f8
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_D3Z634.mag
@@ -0,0 +1,1345 @@
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+string FIXED_BBOX -2034 -266 2034 266
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.35 m 1 nf 30 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4.ext

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4.ext b/mag/sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4.ext
new file mode 100644
index 0000000..b058489
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4.ext
@@ -0,0 +1,161 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
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mag/sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4.mag

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4.mag b/mag/sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4.mag
new file mode 100644
index 0000000..7df2fed
--- /dev/null
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+<< properties >>
+string FIXED_BBOX -754 -266 754 266
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string library sky130
+string parameters w 1.0 l 0.35 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>

mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag

diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
deleted file mode 100644
index cda05e3..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
+++ /dev/null
@@ -1,106 +0,0 @@
-magic
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-rect -272 323 -214 373
-rect -272 -323 -260 323
-rect -226 -323 -214 323
-rect 214 323 272 373
-rect -272 -373 -214 -323
-rect 214 -323 226 323
-rect 260 -323 272 323
-rect 214 -373 272 -323
-rect -272 -385 272 -373
-rect -272 -419 -164 -385
-rect 164 -419 272 -385
-rect -272 -431 272 -419
-<< mvnsubdiffcont >>
-rect -164 385 164 419
-rect -260 -323 -226 323
-rect 226 -323 260 323
-rect -164 -419 164 -385
-<< poly >>
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-<< polycont >>
-rect -64 247 64 281
-rect -64 -281 64 -247
-<< locali >>
-rect -260 385 -181 419
-rect 181 385 260 419
-rect -260 323 -226 385
-rect 226 323 260 385
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -260 -385 -226 -323
-rect 226 -385 260 -323
-rect -260 -419 -164 -385
-rect 164 -419 260 -385
-<< viali >>
-rect -181 385 -164 419
-rect -164 385 164 419
-rect 164 385 181 419
-rect -64 247 64 281
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect -64 -281 64 -247
-<< metal1 >>
-rect -193 419 193 425
-rect -193 385 -181 419
-rect 181 385 193 419
-rect -193 379 193 385
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect -132 188 -86 200
-rect -132 -188 -126 188
-rect -92 -188 -86 188
-rect -132 -200 -86 -188
-rect 86 188 132 200
-rect 86 -188 92 188
-rect 126 -188 132 188
-rect 86 -200 132 -188
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -243 -402 243 402
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
-string library sky130
-<< end >>

mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag

diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
deleted file mode 100644
index 07202c9..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
+++ /dev/null
@@ -1,331 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< nwell >>
-rect -992 -497 992 497
-<< mvpmos >>
-rect -734 -200 -574 200
-rect -516 -200 -356 200
-rect -298 -200 -138 200
-rect -80 -200 80 200
-rect 138 -200 298 200
-rect 356 -200 516 200
-rect 574 -200 734 200
-<< mvpdiff >>
-rect -792 188 -734 200
-rect -792 -188 -780 188
-rect -746 -188 -734 188
-rect -792 -200 -734 -188
-rect -574 188 -516 200
-rect -574 -188 -562 188
-rect -528 -188 -516 188
-rect -574 -200 -516 -188
-rect -356 188 -298 200
-rect -356 -188 -344 188
-rect -310 -188 -298 188
-rect -356 -200 -298 -188
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-rect 298 188 356 200
-rect 298 -188 310 188
-rect 344 -188 356 188
-rect 298 -200 356 -188
-rect 516 188 574 200
-rect 516 -188 528 188
-rect 562 -188 574 188
-rect 516 -200 574 -188
-rect 734 188 792 200
-rect 734 -188 746 188
-rect 780 -188 792 188
-rect 734 -200 792 -188
-<< mvpdiffc >>
-rect -780 -188 -746 188
-rect -562 -188 -528 188
-rect -344 -188 -310 188
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect 310 -188 344 188
-rect 528 -188 562 188
-rect 746 -188 780 188
-<< mvnsubdiff >>
-rect -926 419 926 431
-rect -926 385 -818 419
-rect 818 385 926 419
-rect -926 373 926 385
-rect -926 323 -868 373
-rect -926 -323 -914 323
-rect -880 -323 -868 323
-rect 868 323 926 373
-rect -926 -373 -868 -323
-rect 868 -323 880 323
-rect 914 -323 926 323
-rect 868 -373 926 -323
-rect -926 -385 926 -373
-rect -926 -419 -818 -385
-rect 818 -419 926 -385
-rect -926 -431 926 -419
-<< mvnsubdiffcont >>
-rect -818 385 818 419
-rect -914 -323 -880 323
-rect 880 -323 914 323
-rect -818 -419 818 -385
-<< poly >>
-rect -734 281 -574 297
-rect -734 247 -718 281
-rect -590 247 -574 281
-rect -734 200 -574 247
-rect -516 281 -356 297
-rect -516 247 -500 281
-rect -372 247 -356 281
-rect -516 200 -356 247
-rect -298 281 -138 297
-rect -298 247 -282 281
-rect -154 247 -138 281
-rect -298 200 -138 247
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect 138 281 298 297
-rect 138 247 154 281
-rect 282 247 298 281
-rect 138 200 298 247
-rect 356 281 516 297
-rect 356 247 372 281
-rect 500 247 516 281
-rect 356 200 516 247
-rect 574 281 734 297
-rect 574 247 590 281
-rect 718 247 734 281
-rect 574 200 734 247
-rect -734 -247 -574 -200
-rect -734 -281 -718 -247
-rect -590 -281 -574 -247
-rect -734 -297 -574 -281
-rect -516 -247 -356 -200
-rect -516 -281 -500 -247
-rect -372 -281 -356 -247
-rect -516 -297 -356 -281
-rect -298 -247 -138 -200
-rect -298 -281 -282 -247
-rect -154 -281 -138 -247
-rect -298 -297 -138 -281
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-rect 138 -247 298 -200
-rect 138 -281 154 -247
-rect 282 -281 298 -247
-rect 138 -297 298 -281
-rect 356 -247 516 -200
-rect 356 -281 372 -247
-rect 500 -281 516 -247
-rect 356 -297 516 -281
-rect 574 -247 734 -200
-rect 574 -281 590 -247
-rect 718 -281 734 -247
-rect 574 -297 734 -281
-<< polycont >>
-rect -718 247 -590 281
-rect -500 247 -372 281
-rect -282 247 -154 281
-rect -64 247 64 281
-rect 154 247 282 281
-rect 372 247 500 281
-rect 590 247 718 281
-rect -718 -281 -590 -247
-rect -500 -281 -372 -247
-rect -282 -281 -154 -247
-rect -64 -281 64 -247
-rect 154 -281 282 -247
-rect 372 -281 500 -247
-rect 590 -281 718 -247
-<< locali >>
-rect -914 385 -818 419
-rect 818 385 914 419
-rect 880 323 914 385
-rect -734 247 -718 281
-rect -590 247 -574 281
-rect -516 247 -500 281
-rect -372 247 -356 281
-rect -298 247 -282 281
-rect -154 247 -138 281
-rect -80 247 -64 281
-rect 64 247 80 281
-rect 138 247 154 281
-rect 282 247 298 281
-rect 356 247 372 281
-rect 500 247 516 281
-rect 574 247 590 281
-rect 718 247 734 281
-rect -780 188 -746 204
-rect -780 -204 -746 -188
-rect -562 188 -528 204
-rect -562 -204 -528 -188
-rect -344 188 -310 204
-rect -344 -204 -310 -188
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect 310 188 344 204
-rect 310 -204 344 -188
-rect 528 188 562 204
-rect 528 -204 562 -188
-rect 746 188 780 204
-rect 746 -204 780 -188
-rect -734 -281 -718 -247
-rect -590 -281 -574 -247
-rect -516 -281 -500 -247
-rect -372 -281 -356 -247
-rect -298 -281 -282 -247
-rect -154 -281 -138 -247
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect 138 -281 154 -247
-rect 282 -281 298 -247
-rect 356 -281 372 -247
-rect 500 -281 516 -247
-rect 574 -281 590 -247
-rect 718 -281 734 -247
-rect -914 -385 -880 -323
-rect 880 -385 914 -323
-rect -914 -419 -818 -385
-rect 818 -419 914 -385
-<< viali >>
-rect -792 385 792 419
-rect -914 323 -880 385
-rect -914 38 -880 323
-rect -718 247 -590 281
-rect -500 247 -372 281
-rect -282 247 -154 281
-rect -64 247 64 281
-rect 154 247 282 281
-rect 372 247 500 281
-rect 590 247 718 281
-rect -780 21 -746 171
-rect -562 -171 -528 -21
-rect -344 21 -310 171
-rect -126 -171 -92 -21
-rect 92 21 126 171
-rect 310 -171 344 -21
-rect 528 21 562 171
-rect 746 -171 780 -21
-rect -718 -281 -590 -247
-rect -500 -281 -372 -247
-rect -282 -281 -154 -247
-rect -64 -281 64 -247
-rect 154 -281 282 -247
-rect 372 -281 500 -247
-rect 590 -281 718 -247
-<< metal1 >>
-rect -804 419 804 425
-rect -920 385 -874 397
-rect -920 38 -914 385
-rect -880 38 -874 385
-rect -804 385 -792 419
-rect 792 385 804 419
-rect -804 379 804 385
-rect -730 281 -578 287
-rect -730 247 -718 281
-rect -590 247 -578 281
-rect -730 241 -578 247
-rect -512 281 -360 287
-rect -512 247 -500 281
-rect -372 247 -360 281
-rect -512 241 -360 247
-rect -294 281 -142 287
-rect -294 247 -282 281
-rect -154 247 -142 281
-rect -294 241 -142 247
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect 142 281 294 287
-rect 142 247 154 281
-rect 282 247 294 281
-rect 142 241 294 247
-rect 360 281 512 287
-rect 360 247 372 281
-rect 500 247 512 281
-rect 360 241 512 247
-rect 578 281 730 287
-rect 578 247 590 281
-rect 718 247 730 281
-rect 578 241 730 247
-rect -920 26 -874 38
-rect -786 171 -740 183
-rect -786 21 -780 171
-rect -746 21 -740 171
-rect -786 9 -740 21
-rect -350 171 -304 183
-rect -350 21 -344 171
-rect -310 21 -304 171
-rect -350 9 -304 21
-rect 86 171 132 183
-rect 86 21 92 171
-rect 126 21 132 171
-rect 86 9 132 21
-rect 522 171 568 183
-rect 522 21 528 171
-rect 562 21 568 171
-rect 522 9 568 21
-rect -568 -21 -522 -9
-rect -568 -171 -562 -21
-rect -528 -171 -522 -21
-rect -568 -183 -522 -171
-rect -132 -21 -86 -9
-rect -132 -171 -126 -21
-rect -92 -171 -86 -21
-rect -132 -183 -86 -171
-rect 304 -21 350 -9
-rect 304 -171 310 -21
-rect 344 -171 350 -21
-rect 304 -183 350 -171
-rect 740 -21 786 -9
-rect 740 -171 746 -21
-rect 780 -171 786 -21
-rect 740 -183 786 -171
-rect -730 -247 -578 -241
-rect -730 -281 -718 -247
-rect -590 -281 -578 -247
-rect -730 -287 -578 -281
-rect -512 -247 -360 -241
-rect -512 -281 -500 -247
-rect -372 -281 -360 -247
-rect -512 -287 -360 -281
-rect -294 -247 -142 -241
-rect -294 -281 -282 -247
-rect -154 -281 -142 -247
-rect -294 -287 -142 -281
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-rect 142 -247 294 -241
-rect 142 -281 154 -247
-rect 282 -281 294 -247
-rect 142 -287 294 -281
-rect 360 -247 512 -241
-rect 360 -281 372 -247
-rect 500 -281 512 -247
-rect 360 -287 512 -281
-rect 578 -247 730 -241
-rect 578 -281 590 -247
-rect 718 -281 730 -247
-rect 578 -287 730 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -897 -402 897 402
-string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40
-string library sky130
-<< end >>

mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag

diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
deleted file mode 100644
index ceaf969..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
+++ /dev/null
@@ -1,114 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< error_p >>
-rect -221 351 -220 397
-rect -193 379 -192 419
-<< nwell >>
-rect -338 -497 338 497
-<< mvpmos >>
-rect -80 -200 80 200
-<< mvpdiff >>
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-<< mvpdiffc >>
-rect -126 -188 -92 188
-rect 92 -188 126 188
-<< mvnsubdiff >>
-rect -272 419 272 431
-rect -272 385 -164 419
-rect 164 385 272 419
-rect -272 373 272 385
-rect -272 323 -214 373
-rect -272 -323 -260 323
-rect -226 -323 -214 323
-rect 214 323 272 373
-rect -272 -373 -214 -323
-rect 214 -323 226 323
-rect 260 -323 272 323
-rect 214 -373 272 -323
-rect -272 -385 272 -373
-rect -272 -419 -164 -385
-rect 164 -419 272 -385
-rect -272 -431 272 -419
-<< mvnsubdiffcont >>
-rect -164 385 164 419
-rect -260 -323 -226 323
-rect 226 -323 260 323
-rect -164 -419 164 -385
-<< poly >>
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-<< polycont >>
-rect -64 247 64 281
-rect -64 -281 64 -247
-<< locali >>
-rect -260 385 -181 419
-rect 181 385 260 419
-rect 226 323 260 385
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -260 -385 -226 -323
-rect 226 -385 260 -323
-rect -260 -419 -164 -385
-rect 164 -419 260 -385
-<< viali >>
-rect -181 385 -164 419
-rect -164 385 164 419
-rect 164 385 181 419
-rect -260 323 -226 385
-rect -260 0 -226 323
-rect -64 247 64 281
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect -64 -281 64 -247
-<< metal1 >>
-rect -193 419 193 425
-rect -266 385 -220 397
-rect -266 0 -260 385
-rect -226 0 -220 385
-rect -193 385 -181 419
-rect 181 385 193 419
-rect -193 379 193 385
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect -266 -12 -220 0
-rect -132 188 -86 200
-rect -132 -188 -126 188
-rect -92 -188 -86 188
-rect -132 -200 -86 -188
-rect 86 188 132 200
-rect 86 -188 92 188
-rect 126 -188 132 188
-rect 86 -200 132 -188
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -243 -402 243 402
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
-string library sky130
-<< end >>

mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag

diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
deleted file mode 100644
index 23ef875..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
+++ /dev/null
@@ -1,114 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< error_p >>
-rect -221 351 -220 397
-rect -193 379 -192 419
-<< nwell >>
-rect -338 -497 338 497
-<< mvpmos >>
-rect -80 -200 80 200
-<< mvpdiff >>
-rect -138 188 -80 200
-rect -138 -188 -126 188
-rect -92 -188 -80 188
-rect -138 -200 -80 -188
-rect 80 188 138 200
-rect 80 -188 92 188
-rect 126 -188 138 188
-rect 80 -200 138 -188
-<< mvpdiffc >>
-rect -126 -188 -92 188
-rect 92 -188 126 188
-<< mvnsubdiff >>
-rect -272 419 272 431
-rect -272 385 -164 419
-rect 164 385 272 419
-rect -272 373 272 385
-rect -272 323 -214 373
-rect -272 -323 -260 323
-rect -226 -323 -214 323
-rect 214 323 272 373
-rect -272 -373 -214 -323
-rect 214 -323 226 323
-rect 260 -323 272 323
-rect 214 -373 272 -323
-rect -272 -385 272 -373
-rect -272 -419 -164 -385
-rect 164 -419 272 -385
-rect -272 -431 272 -419
-<< mvnsubdiffcont >>
-rect -164 385 164 419
-rect -260 -323 -226 323
-rect 226 -323 260 323
-rect -164 -419 164 -385
-<< poly >>
-rect -80 281 80 297
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -80 200 80 247
-rect -80 -247 80 -200
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -80 -297 80 -281
-<< polycont >>
-rect -64 247 64 281
-rect -64 -281 64 -247
-<< locali >>
-rect -260 385 -181 419
-rect 181 385 260 419
-rect 226 323 260 385
-rect -80 247 -64 281
-rect 64 247 80 281
-rect -126 188 -92 204
-rect -126 -204 -92 -188
-rect 92 188 126 204
-rect 92 -204 126 -188
-rect -80 -281 -64 -247
-rect 64 -281 80 -247
-rect -260 -385 -226 -323
-rect 226 -385 260 -323
-rect -260 -419 -164 -385
-rect 164 -419 260 -385
-<< viali >>
-rect -181 385 -164 419
-rect -164 385 164 419
-rect 164 385 181 419
-rect -260 323 -226 385
-rect -260 38 -226 323
-rect -64 247 64 281
-rect -126 -188 -92 188
-rect 92 -188 126 188
-rect -64 -281 64 -247
-<< metal1 >>
-rect -193 419 193 425
-rect -266 385 -220 397
-rect -266 38 -260 385
-rect -226 38 -220 385
-rect -193 385 -181 419
-rect 181 385 193 419
-rect -193 379 193 385
-rect -76 281 76 287
-rect -76 247 -64 281
-rect 64 247 76 281
-rect -76 241 76 247
-rect -266 26 -220 38
-rect -132 188 -86 200
-rect -132 -188 -126 188
-rect -92 -188 -86 188
-rect -132 -200 -86 -188
-rect 86 188 132 200
-rect 86 -188 92 188
-rect 126 -188 132 188
-rect 86 -200 132 -188
-rect -76 -247 76 -241
-rect -76 -281 -64 -247
-rect 64 -281 76 -247
-rect -76 -287 76 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -243 -402 243 402
-string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100
-string library sky130
-<< end >>

mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag

diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
deleted file mode 100644
index f094850..0000000
--- a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
+++ /dev/null
@@ -1,368 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606063140
-<< nwell >>
-rect -1101 -497 1101 497
-<< mvpmos >>
-rect -843 -200 -683 200
-rect -625 -200 -465 200
-rect -407 -200 -247 200
-rect -189 -200 -29 200
-rect 29 -200 189 200
-rect 247 -200 407 200
-rect 465 -200 625 200
-rect 683 -200 843 200
-<< mvpdiff >>
-rect -901 188 -843 200
-rect -901 -188 -889 188
-rect -855 -188 -843 188
-rect -901 -200 -843 -188
-rect -683 188 -625 200
-rect -683 -188 -671 188
-rect -637 -188 -625 188
-rect -683 -200 -625 -188
-rect -465 188 -407 200
-rect -465 -188 -453 188
-rect -419 -188 -407 188
-rect -465 -200 -407 -188
-rect -247 188 -189 200
-rect -247 -188 -235 188
-rect -201 -188 -189 188
-rect -247 -200 -189 -188
-rect -29 188 29 200
-rect -29 -188 -17 188
-rect 17 -188 29 188
-rect -29 -200 29 -188
-rect 189 188 247 200
-rect 189 -188 201 188
-rect 235 -188 247 188
-rect 189 -200 247 -188
-rect 407 188 465 200
-rect 407 -188 419 188
-rect 453 -188 465 188
-rect 407 -200 465 -188
-rect 625 188 683 200
-rect 625 -188 637 188
-rect 671 -188 683 188
-rect 625 -200 683 -188
-rect 843 188 901 200
-rect 843 -188 855 188
-rect 889 -188 901 188
-rect 843 -200 901 -188
-<< mvpdiffc >>
-rect -889 -188 -855 188
-rect -671 -188 -637 188
-rect -453 -188 -419 188
-rect -235 -188 -201 188
-rect -17 -188 17 188
-rect 201 -188 235 188
-rect 419 -188 453 188
-rect 637 -188 671 188
-rect 855 -188 889 188
-<< mvnsubdiff >>
-rect -1035 419 1035 431
-rect -1035 385 -927 419
-rect 927 385 1035 419
-rect -1035 373 1035 385
-rect -1035 323 -977 373
-rect -1035 -323 -1023 323
-rect -989 -323 -977 323
-rect 977 323 1035 373
-rect -1035 -373 -977 -323
-rect 977 -323 989 323
-rect 1023 -323 1035 323
-rect 977 -373 1035 -323
-rect -1035 -385 1035 -373
-rect -1035 -419 -927 -385
-rect 927 -419 1035 -385
-rect -1035 -431 1035 -419
-<< mvnsubdiffcont >>
-rect -927 385 927 419
-rect -1023 -323 -989 323
-rect 989 -323 1023 323
-rect -927 -419 927 -385
-<< poly >>
-rect -843 281 -683 297
-rect -843 247 -827 281
-rect -699 247 -683 281
-rect -843 200 -683 247
-rect -625 281 -465 297
-rect -625 247 -609 281
-rect -481 247 -465 281
-rect -625 200 -465 247
-rect -407 281 -247 297
-rect -407 247 -391 281
-rect -263 247 -247 281
-rect -407 200 -247 247
-rect -189 281 -29 297
-rect -189 247 -173 281
-rect -45 247 -29 281
-rect -189 200 -29 247
-rect 29 281 189 297
-rect 29 247 45 281
-rect 173 247 189 281
-rect 29 200 189 247
-rect 247 281 407 297
-rect 247 247 263 281
-rect 391 247 407 281
-rect 247 200 407 247
-rect 465 281 625 297
-rect 465 247 481 281
-rect 609 247 625 281
-rect 465 200 625 247
-rect 683 281 843 297
-rect 683 247 699 281
-rect 827 247 843 281
-rect 683 200 843 247
-rect -843 -247 -683 -200
-rect -843 -281 -827 -247
-rect -699 -281 -683 -247
-rect -843 -297 -683 -281
-rect -625 -247 -465 -200
-rect -625 -281 -609 -247
-rect -481 -281 -465 -247
-rect -625 -297 -465 -281
-rect -407 -247 -247 -200
-rect -407 -281 -391 -247
-rect -263 -281 -247 -247
-rect -407 -297 -247 -281
-rect -189 -247 -29 -200
-rect -189 -281 -173 -247
-rect -45 -281 -29 -247
-rect -189 -297 -29 -281
-rect 29 -247 189 -200
-rect 29 -281 45 -247
-rect 173 -281 189 -247
-rect 29 -297 189 -281
-rect 247 -247 407 -200
-rect 247 -281 263 -247
-rect 391 -281 407 -247
-rect 247 -297 407 -281
-rect 465 -247 625 -200
-rect 465 -281 481 -247
-rect 609 -281 625 -247
-rect 465 -297 625 -281
-rect 683 -247 843 -200
-rect 683 -281 699 -247
-rect 827 -281 843 -247
-rect 683 -297 843 -281
-<< polycont >>
-rect -827 247 -699 281
-rect -609 247 -481 281
-rect -391 247 -263 281
-rect -173 247 -45 281
-rect 45 247 173 281
-rect 263 247 391 281
-rect 481 247 609 281
-rect 699 247 827 281
-rect -827 -281 -699 -247
-rect -609 -281 -481 -247
-rect -391 -281 -263 -247
-rect -173 -281 -45 -247
-rect 45 -281 173 -247
-rect 263 -281 391 -247
-rect 481 -281 609 -247
-rect 699 -281 827 -247
-<< locali >>
-rect -1023 385 -927 419
-rect 927 385 1023 419
-rect 989 323 1023 385
-rect -843 247 -827 281
-rect -699 247 -683 281
-rect -625 247 -609 281
-rect -481 247 -465 281
-rect -407 247 -391 281
-rect -263 247 -247 281
-rect -189 247 -173 281
-rect -45 247 -29 281
-rect 29 247 45 281
-rect 173 247 189 281
-rect 247 247 263 281
-rect 391 247 407 281
-rect 465 247 481 281
-rect 609 247 625 281
-rect 683 247 699 281
-rect 827 247 843 281
-rect -889 188 -855 204
-rect -889 -204 -855 -188
-rect -671 188 -637 204
-rect -671 -204 -637 -188
-rect -453 188 -419 204
-rect -453 -204 -419 -188
-rect -235 188 -201 204
-rect -235 -204 -201 -188
-rect -17 188 17 204
-rect -17 -204 17 -188
-rect 201 188 235 204
-rect 201 -204 235 -188
-rect 419 188 453 204
-rect 419 -204 453 -188
-rect 637 188 671 204
-rect 637 -204 671 -188
-rect 855 188 889 204
-rect 855 -204 889 -188
-rect -843 -281 -827 -247
-rect -699 -281 -683 -247
-rect -625 -281 -609 -247
-rect -481 -281 -465 -247
-rect -407 -281 -391 -247
-rect -263 -281 -247 -247
-rect -189 -281 -173 -247
-rect -45 -281 -29 -247
-rect 29 -281 45 -247
-rect 173 -281 189 -247
-rect 247 -281 263 -247
-rect 391 -281 407 -247
-rect 465 -281 481 -247
-rect 609 -281 625 -247
-rect 683 -281 699 -247
-rect 827 -281 843 -247
-rect -1023 -385 -989 -323
-rect 989 -385 1023 -323
-rect -1023 -419 -927 -385
-rect 927 -419 1023 -385
-<< viali >>
-rect -890 385 890 419
-rect -1023 323 -989 385
-rect -1023 0 -989 323
-rect -827 247 -699 281
-rect -609 247 -481 281
-rect -391 247 -263 281
-rect -173 247 -45 281
-rect 45 247 173 281
-rect 263 247 391 281
-rect 481 247 609 281
-rect 699 247 827 281
-rect -889 21 -855 171
-rect -671 -171 -637 -21
-rect -453 21 -419 171
-rect -235 -171 -201 -21
-rect -17 21 17 171
-rect 201 -171 235 -21
-rect 419 21 453 171
-rect 637 -171 671 -21
-rect 855 21 889 171
-rect -827 -281 -699 -247
-rect -609 -281 -481 -247
-rect -391 -281 -263 -247
-rect -173 -281 -45 -247
-rect 45 -281 173 -247
-rect 263 -281 391 -247
-rect 481 -281 609 -247
-rect 699 -281 827 -247
-<< metal1 >>
-rect -902 419 902 425
-rect -1029 385 -983 397
-rect -1029 0 -1023 385
-rect -989 0 -983 385
-rect -902 385 -890 419
-rect 890 385 902 419
-rect -902 379 902 385
-rect -839 281 -687 287
-rect -839 247 -827 281
-rect -699 247 -687 281
-rect -839 241 -687 247
-rect -621 281 -469 287
-rect -621 247 -609 281
-rect -481 247 -469 281
-rect -621 241 -469 247
-rect -403 281 -251 287
-rect -403 247 -391 281
-rect -263 247 -251 281
-rect -403 241 -251 247
-rect -185 281 -33 287
-rect -185 247 -173 281
-rect -45 247 -33 281
-rect -185 241 -33 247
-rect 33 281 185 287
-rect 33 247 45 281
-rect 173 247 185 281
-rect 33 241 185 247
-rect 251 281 403 287
-rect 251 247 263 281
-rect 391 247 403 281
-rect 251 241 403 247
-rect 469 281 621 287
-rect 469 247 481 281
-rect 609 247 621 281
-rect 469 241 621 247
-rect 687 281 839 287
-rect 687 247 699 281
-rect 827 247 839 281
-rect 687 241 839 247
-rect -895 171 -849 183
-rect -895 21 -889 171
-rect -855 21 -849 171
-rect -895 9 -849 21
-rect -459 171 -413 183
-rect -459 21 -453 171
-rect -419 21 -413 171
-rect -459 9 -413 21
-rect -23 171 23 183
-rect -23 21 -17 171
-rect 17 21 23 171
-rect -23 9 23 21
-rect 413 171 459 183
-rect 413 21 419 171
-rect 453 21 459 171
-rect 413 9 459 21
-rect 849 171 895 183
-rect 849 21 855 171
-rect 889 21 895 171
-rect 849 9 895 21
-rect -1029 -12 -983 0
-rect -677 -21 -631 -9
-rect -677 -171 -671 -21
-rect -637 -171 -631 -21
-rect -677 -183 -631 -171
-rect -241 -21 -195 -9
-rect -241 -171 -235 -21
-rect -201 -171 -195 -21
-rect -241 -183 -195 -171
-rect 195 -21 241 -9
-rect 195 -171 201 -21
-rect 235 -171 241 -21
-rect 195 -183 241 -171
-rect 631 -21 677 -9
-rect 631 -171 637 -21
-rect 671 -171 677 -21
-rect 631 -183 677 -171
-rect -839 -247 -687 -241
-rect -839 -281 -827 -247
-rect -699 -281 -687 -247
-rect -839 -287 -687 -281
-rect -621 -247 -469 -241
-rect -621 -281 -609 -247
-rect -481 -281 -469 -247
-rect -621 -287 -469 -281
-rect -403 -247 -251 -241
-rect -403 -281 -391 -247
-rect -263 -281 -251 -247
-rect -403 -287 -251 -281
-rect -185 -247 -33 -241
-rect -185 -281 -173 -247
-rect -45 -281 -33 -247
-rect -185 -287 -33 -281
-rect 33 -247 185 -241
-rect 33 -281 45 -247
-rect 173 -281 185 -247
-rect 33 -287 185 -281
-rect 251 -247 403 -241
-rect 251 -281 263 -247
-rect 391 -281 403 -247
-rect 251 -287 403 -281
-rect 469 -247 621 -241
-rect 469 -281 481 -247
-rect 609 -281 621 -247
-rect 469 -287 621 -281
-rect 687 -247 839 -241
-rect 687 -281 699 -247
-rect 827 -281 839 -247
-rect 687 -287 839 -281
-<< properties >>
-string gencell sky130_fd_pr__pfet_g5v0d10v5
-string FIXED_BBOX -1006 -402 1006 402
-string parameters w 2.00 l 0.80 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40
-string library sky130
-<< end >>

mag/sky130_fd_pr__res_high_po_2p85_MM89SS.ext

diff --git a/mag/sky130_fd_pr__res_high_po_2p85_MM89SS.ext b/mag/sky130_fd_pr__res_high_po_2p85_MM89SS.ext
new file mode 100644
index 0000000..6e76e0c
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_2p85_MM89SS.ext
@@ -0,0 +1,17 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__res_high_po l=l w=w
+parameters sky130_fd_pr__res_high_po_5p73 l=l
+parameters sky130_fd_pr__res_high_po_2p85 l=l
+parameters sky130_fd_pr__res_high_po_1p41 l=l
+parameters sky130_fd_pr__res_high_po_0p69 l=l
+parameters sky130_fd_pr__res_high_po_0p35 l=l
+node "a_n285_n1572#" 77 1142.22 -285 -1572 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 492480 4008 229858 1942 0 0 0 0 0 0 0 0 0 0
+node "a_n285_n1140#" 1279 0 -285 -1140 ppres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1299600 5700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n285_1140#" 77 1142.22 -285 1140 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 492480 4008 229858 1942 0 0 0 0 0 0 0 0 0 0
+substrate "a_n415_n1702#" 0 0 -415 -1702 ppd 0 0 0 0 0 0 0 0 0 0 283288 16664 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 283288 16664 0 0 0 0 0 0 0 0 0 0 0 0
+device rsubckt sky130_fd_pr__res_high_po_2p85 -285 -1140 -284 -1139 l=2280 "a_n415_n1702#" "a_n285_n1140#" 0 0 "a_n285_n1572#" 570 0 "a_n285_1140#" 570 0

mag/sky130_fd_pr__res_high_po_2p85_MM89SS.mag

diff --git a/mag/sky130_fd_pr__res_high_po_2p85_MM89SS.mag b/mag/sky130_fd_pr__res_high_po_2p85_MM89SS.mag
new file mode 100644
index 0000000..9be11a9
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_2p85_MM89SS.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662404926
+<< pwell >>
+rect -451 -1738 451 1738
+<< psubdiff >>
+rect -415 1668 -319 1702
+rect 319 1668 415 1702
+rect -415 1606 -381 1668
+rect 381 1606 415 1668
+rect -415 -1668 -381 -1606
+rect 381 -1668 415 -1606
+rect -415 -1702 -319 -1668
+rect 319 -1702 415 -1668
+<< psubdiffcont >>
+rect -319 1668 319 1702
+rect -415 -1606 -381 1606
+rect 381 -1606 415 1606
+rect -319 -1702 319 -1668
+<< xpolycontact >>
+rect -285 1140 285 1572
+rect -285 -1572 285 -1140
+<< ppolyres >>
+rect -285 -1140 285 1140
+<< locali >>
+rect -415 1668 -319 1702
+rect 319 1668 415 1702
+rect -415 1606 -381 1668
+rect 381 1606 415 1668
+rect -415 -1668 -381 -1606
+rect 381 -1668 415 -1606
+rect -415 -1702 -319 -1668
+rect 319 -1702 415 -1668
+<< viali >>
+rect -269 1157 269 1554
+rect -269 -1554 269 -1157
+<< metal1 >>
+rect -281 1554 281 1560
+rect -281 1157 -269 1554
+rect 269 1157 281 1554
+rect -281 1151 281 1157
+rect -281 -1157 281 -1151
+rect -281 -1554 -269 -1157
+rect 269 -1554 281 -1157
+rect -281 -1560 281 -1554
+<< res2p85 >>
+rect -287 -1142 287 1142
+<< properties >>
+string FIXED_BBOX -398 -1685 398 1685
+string gencell sky130_fd_pr__res_high_po_2p85
+string library sky130
+string parameters w 2.850 l 11.4 m 1 nx 1 wmin 2.850 lmin 0.50 rho 319.8 val 1.415k dummy 0 dw 0.0 term 194.82 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35  sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41  sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 2.850 n_guard 0 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>

mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.ext

diff --git a/mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.ext b/mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.ext
new file mode 100644
index 0000000..27d5409
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.ext
@@ -0,0 +1,17 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__res_high_po l=l w=w
+parameters sky130_fd_pr__res_high_po_5p73 l=l
+parameters sky130_fd_pr__res_high_po_2p85 l=l
+parameters sky130_fd_pr__res_high_po_1p41 l=l
+parameters sky130_fd_pr__res_high_po_0p69 l=l
+parameters sky130_fd_pr__res_high_po_0p35 l=l
+node "a_n285_n4632#" 77 1142.22 -285 -4632 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 492480 4008 229858 1942 0 0 0 0 0 0 0 0 0 0
+node "a_n285_n4200#" 4713 0 -285 -4200 ppres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4788000 17940 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n285_4200#" 77 1142.22 -285 4200 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 492480 4008 229858 1942 0 0 0 0 0 0 0 0 0 0
+substrate "a_n415_n4762#" 0 0 -415 -4762 ppd 0 0 0 0 0 0 0 0 0 0 699448 41144 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 699448 41144 0 0 0 0 0 0 0 0 0 0 0 0
+device rsubckt sky130_fd_pr__res_high_po_2p85 -285 -4200 -284 -4199 l=8400 "a_n415_n4762#" "a_n285_n4200#" 0 0 "a_n285_n4632#" 570 0 "a_n285_4200#" 570 0

mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.mag

diff --git a/mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.mag b/mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.mag
new file mode 100644
index 0000000..3086d6d
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_2p85_MXEQGY.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662404926
+<< pwell >>
+rect -451 -4798 451 4798
+<< psubdiff >>
+rect -415 4728 -319 4762
+rect 319 4728 415 4762
+rect -415 4666 -381 4728
+rect 381 4666 415 4728
+rect -415 -4728 -381 -4666
+rect 381 -4728 415 -4666
+rect -415 -4762 -319 -4728
+rect 319 -4762 415 -4728
+<< psubdiffcont >>
+rect -319 4728 319 4762
+rect -415 -4666 -381 4666
+rect 381 -4666 415 4666
+rect -319 -4762 319 -4728
+<< xpolycontact >>
+rect -285 4200 285 4632
+rect -285 -4632 285 -4200
+<< ppolyres >>
+rect -285 -4200 285 4200
+<< locali >>
+rect -415 4728 -319 4762
+rect 319 4728 415 4762
+rect -415 4666 -381 4728
+rect 381 4666 415 4728
+rect -415 -4728 -381 -4666
+rect 381 -4728 415 -4666
+rect -415 -4762 -319 -4728
+rect 319 -4762 415 -4728
+<< viali >>
+rect -269 4217 269 4614
+rect -269 -4614 269 -4217
+<< metal1 >>
+rect -281 4614 281 4620
+rect -281 4217 -269 4614
+rect 269 4217 281 4614
+rect -281 4211 281 4217
+rect -281 -4217 281 -4211
+rect -281 -4614 -269 -4217
+rect 269 -4614 281 -4217
+rect -281 -4620 281 -4614
+<< res2p85 >>
+rect -287 -4202 287 4202
+<< properties >>
+string FIXED_BBOX -398 -4745 398 4745
+string gencell sky130_fd_pr__res_high_po_2p85
+string library sky130
+string parameters w 2.850 l 42.0 m 1 nx 1 wmin 2.850 lmin 0.50 rho 319.8 val 4.849k dummy 0 dw 0.0 term 194.82 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35  sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41  sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 2.850 n_guard 0 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>

mag/sky130_fd_pr__res_high_po_2p85_P79JE3.ext

diff --git a/mag/sky130_fd_pr__res_high_po_2p85_P79JE3.ext b/mag/sky130_fd_pr__res_high_po_2p85_P79JE3.ext
new file mode 100644
index 0000000..61919f9
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_2p85_P79JE3.ext
@@ -0,0 +1,18 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__res_high_po l=l w=w
+parameters sky130_fd_pr__res_high_po_5p73 l=l
+parameters sky130_fd_pr__res_high_po_2p85 l=l
+parameters sky130_fd_pr__res_high_po_1p41 l=l
+parameters sky130_fd_pr__res_high_po_0p69 l=l
+parameters sky130_fd_pr__res_high_po_0p35 l=l
+node "a_n285_n1192#" 77 1141.87 -285 -1192 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 492480 4008 229858 1942 0 0 0 0 0 0 0 0 0 0
+node "a_n285_n760#" 853 0 -285 -760 ppres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 866400 4180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n285_760#" 77 1141.99 -285 760 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 492480 4008 229858 1942 0 0 0 0 0 0 0 0 0 0
+substrate "a_n415_n1322#" 0 0 -415 -1322 ppd 0 0 0 0 0 0 0 0 0 0 231608 13624 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 231608 13624 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n285_n1192#" "a_n285_760#" 23.9486
+device rsubckt sky130_fd_pr__res_high_po_2p85 -285 -760 -284 -759 l=1520 "a_n415_n1322#" "a_n285_n760#" 0 0 "a_n285_n1192#" 570 0 "a_n285_760#" 570 0

mag/sky130_fd_pr__res_high_po_2p85_P79JE3.mag

diff --git a/mag/sky130_fd_pr__res_high_po_2p85_P79JE3.mag b/mag/sky130_fd_pr__res_high_po_2p85_P79JE3.mag
new file mode 100644
index 0000000..17cfc93
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_2p85_P79JE3.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662404926
+<< pwell >>
+rect -451 -1358 451 1358
+<< psubdiff >>
+rect -415 1288 -319 1322
+rect 319 1288 415 1322
+rect -415 1226 -381 1288
+rect 381 1226 415 1288
+rect -415 -1288 -381 -1226
+rect 381 -1288 415 -1226
+rect -415 -1322 -319 -1288
+rect 319 -1322 415 -1288
+<< psubdiffcont >>
+rect -319 1288 319 1322
+rect -415 -1226 -381 1226
+rect 381 -1226 415 1226
+rect -319 -1322 319 -1288
+<< xpolycontact >>
+rect -285 760 285 1192
+rect -285 -1192 285 -760
+<< ppolyres >>
+rect -285 -760 285 760
+<< locali >>
+rect -415 1288 -319 1322
+rect 319 1288 415 1322
+rect -415 1226 -381 1288
+rect 381 1226 415 1288
+rect -415 -1288 -381 -1226
+rect 381 -1288 415 -1226
+rect -415 -1322 -319 -1288
+rect 319 -1322 415 -1288
+<< viali >>
+rect -269 777 269 1174
+rect -269 -1174 269 -777
+<< metal1 >>
+rect -281 1174 281 1180
+rect -281 777 -269 1174
+rect 269 777 281 1174
+rect -281 771 281 777
+rect -281 -777 281 -771
+rect -281 -1174 -269 -777
+rect 269 -1174 281 -777
+rect -281 -1180 281 -1174
+<< res2p85 >>
+rect -287 -762 287 762
+<< properties >>
+string FIXED_BBOX -398 -1305 398 1305
+string gencell sky130_fd_pr__res_high_po_2p85
+string library sky130
+string parameters w 2.850 l 7.6 m 1 nx 1 wmin 2.850 lmin 0.50 rho 319.8 val 989.515 dummy 0 dw 0.0 term 194.82 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35  sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41  sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 2.850 n_guard 0 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>

mag/sky130_fd_pr__res_high_po_5p73_W59YBA.ext

diff --git a/mag/sky130_fd_pr__res_high_po_5p73_W59YBA.ext b/mag/sky130_fd_pr__res_high_po_5p73_W59YBA.ext
new file mode 100644
index 0000000..243000f
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_5p73_W59YBA.ext
@@ -0,0 +1,17 @@
+timestamp 1662407989
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__res_high_po l=l w=w
+parameters sky130_fd_pr__res_high_po_5p73 l=l
+parameters sky130_fd_pr__res_high_po_2p85 l=l
+parameters sky130_fd_pr__res_high_po_1p41 l=l
+parameters sky130_fd_pr__res_high_po_0p69 l=l
+parameters sky130_fd_pr__res_high_po_0p35 l=l
+node "a_n573_n2072#" 102 1717.96 -573 -2072 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 990144 6312 465442 3094 0 0 0 0 0 0 0 0 0 0
+node "a_n573_n1640#" 915 0 -573 -1640 ppres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3758880 8852 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n573_1640#" 102 1717.96 -573 1640 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 990144 6312 465442 3094 0 0 0 0 0 0 0 0 0 0
+substrate "a_n703_n2202#" 0 0 -703 -2202 ppd 0 0 0 0 0 0 0 0 0 0 390456 22968 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 390456 22968 0 0 0 0 0 0 0 0 0 0 0 0
+device rsubckt sky130_fd_pr__res_high_po_5p73 -573 -1640 -572 -1639 l=3280 "a_n703_n2202#" "a_n573_n1640#" 0 0 "a_n573_n2072#" 1146 0 "a_n573_1640#" 1146 0

mag/sky130_fd_pr__res_high_po_5p73_W59YBA.mag

diff --git a/mag/sky130_fd_pr__res_high_po_5p73_W59YBA.mag b/mag/sky130_fd_pr__res_high_po_5p73_W59YBA.mag
new file mode 100644
index 0000000..877909b
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_5p73_W59YBA.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662407989
+<< pwell >>
+rect -739 -2238 739 2238
+<< psubdiff >>
+rect -703 2168 -607 2202
+rect 607 2168 703 2202
+rect -703 2106 -669 2168
+rect 669 2106 703 2168
+rect -703 -2168 -669 -2106
+rect 669 -2168 703 -2106
+rect -703 -2202 -607 -2168
+rect 607 -2202 703 -2168
+<< psubdiffcont >>
+rect -607 2168 607 2202
+rect -703 -2106 -669 2106
+rect 669 -2106 703 2106
+rect -607 -2202 607 -2168
+<< xpolycontact >>
+rect -573 1640 573 2072
+rect -573 -2072 573 -1640
+<< ppolyres >>
+rect -573 -1640 573 1640
+<< locali >>
+rect -703 2168 -607 2202
+rect 607 2168 703 2202
+rect -703 2106 -669 2168
+rect 669 2106 703 2168
+rect -703 -2168 -669 -2106
+rect 669 -2168 703 -2106
+rect -703 -2202 -607 -2168
+rect 607 -2202 703 -2168
+<< viali >>
+rect -557 1657 557 2054
+rect -557 -2054 557 -1657
+<< metal1 >>
+rect -569 2054 569 2060
+rect -569 1657 -557 2054
+rect 557 1657 569 2054
+rect -569 1651 569 1657
+rect -569 -1657 569 -1651
+rect -569 -2054 -557 -1657
+rect 557 -2054 569 -1657
+rect -569 -2060 569 -2054
+<< res5p73 >>
+rect -575 -1642 575 1642
+<< properties >>
+string FIXED_BBOX -686 -2185 686 2185
+string gencell sky130_fd_pr__res_high_po_5p73
+string library sky130
+string parameters w 5.730 l 16.4 m 1 nx 1 wmin 5.730 lmin 0.50 rho 319.8 val 983.308 dummy 0 dw 0.0 term 194.82 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35  sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41  sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 5.730 n_guard 0 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>

mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.ext

diff --git a/mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.ext b/mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.ext
new file mode 100644
index 0000000..1f3081e
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.ext
@@ -0,0 +1,17 @@
+timestamp 1662404926
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__res_high_po l=l w=w
+parameters sky130_fd_pr__res_high_po_5p73 l=l
+parameters sky130_fd_pr__res_high_po_2p85 l=l
+parameters sky130_fd_pr__res_high_po_1p41 l=l
+parameters sky130_fd_pr__res_high_po_0p69 l=l
+parameters sky130_fd_pr__res_high_po_0p35 l=l
+node "a_n573_n3472#" 102 1717.96 -573 -3472 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 990144 6312 465442 3094 0 0 0 0 0 0 0 0 0 0
+node "a_n573_n3040#" 1697 0 -573 -3040 ppres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6967680 14452 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n573_3040#" 102 1717.96 -573 3040 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 990144 6312 465442 3094 0 0 0 0 0 0 0 0 0 0
+substrate "a_n703_n3602#" 0 0 -703 -3602 ppd 0 0 0 0 0 0 0 0 0 0 580856 34168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 580856 34168 0 0 0 0 0 0 0 0 0 0 0 0
+device rsubckt sky130_fd_pr__res_high_po_5p73 -573 -3040 -572 -3039 l=6080 "a_n703_n3602#" "a_n573_n3040#" 0 0 "a_n573_n3472#" 1146 0 "a_n573_3040#" 1146 0

mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.mag

diff --git a/mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.mag b/mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.mag
new file mode 100644
index 0000000..fd5e1f2
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_5p73_YZEQ6M.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662404926
+<< pwell >>
+rect -739 -3638 739 3638
+<< psubdiff >>
+rect -703 3568 -607 3602
+rect 607 3568 703 3602
+rect -703 3506 -669 3568
+rect 669 3506 703 3568
+rect -703 -3568 -669 -3506
+rect 669 -3568 703 -3506
+rect -703 -3602 -607 -3568
+rect 607 -3602 703 -3568
+<< psubdiffcont >>
+rect -607 3568 607 3602
+rect -703 -3506 -669 3506
+rect 669 -3506 703 3506
+rect -607 -3602 607 -3568
+<< xpolycontact >>
+rect -573 3040 573 3472
+rect -573 -3472 573 -3040
+<< ppolyres >>
+rect -573 -3040 573 3040
+<< locali >>
+rect -703 3568 -607 3602
+rect 607 3568 703 3602
+rect -703 3506 -669 3568
+rect 669 3506 703 3568
+rect -703 -3568 -669 -3506
+rect 669 -3568 703 -3506
+rect -703 -3602 -607 -3568
+rect 607 -3602 703 -3568
+<< viali >>
+rect -557 3057 557 3454
+rect -557 -3454 557 -3057
+<< metal1 >>
+rect -569 3454 569 3460
+rect -569 3057 -557 3454
+rect 557 3057 569 3454
+rect -569 3051 569 3057
+rect -569 -3057 569 -3051
+rect -569 -3454 -557 -3057
+rect 557 -3454 569 -3057
+rect -569 -3460 569 -3454
+<< res5p73 >>
+rect -575 -3042 575 3042
+<< properties >>
+string FIXED_BBOX -686 -3585 686 3585
+string gencell sky130_fd_pr__res_high_po_5p73
+string library sky130
+string parameters w 5.730 l 30.4 m 1 nx 1 wmin 5.730 lmin 0.50 rho 319.8 val 1.764k dummy 0 dw 0.0 term 194.82 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35  sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41  sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 5.730 n_guard 0 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>

mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag

diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag b/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
deleted file mode 100644
index dbaae87..0000000
--- a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
+++ /dev/null
@@ -1,167 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1606074388
-<< pwell >>
-rect -5446 -3098 5446 3098
-<< psubdiff >>
-rect -5410 3028 -5314 3062
-rect 5314 3028 5410 3062
-rect -5410 2966 -5376 3028
-rect 5376 2966 5410 3028
-rect -5410 -3028 -5376 -2966
-rect 5376 -3028 5410 -2966
-rect -5410 -3062 -5314 -3028
-rect 5314 -3062 5410 -3028
-<< psubdiffcont >>
-rect -5314 3028 5314 3062
-rect -5410 -2966 -5376 2966
-rect 5376 -2966 5410 2966
-rect -5314 -3062 5314 -3028
-<< xpolycontact >>
-rect -5280 2500 -5142 2932
-rect -5280 -2932 -5142 -2500
-rect -4894 2500 -4756 2932
-rect -4894 -2932 -4756 -2500
-rect -4508 2500 -4370 2932
-rect -4508 -2932 -4370 -2500
-rect -4122 2500 -3984 2932
-rect -4122 -2932 -3984 -2500
-rect -3736 2500 -3598 2932
-rect -3736 -2932 -3598 -2500
-rect -3350 2500 -3212 2932
-rect -3350 -2932 -3212 -2500
-rect -2964 2500 -2826 2932
-rect -2964 -2932 -2826 -2500
-rect -2578 2500 -2440 2932
-rect -2578 -2932 -2440 -2500
-rect -2192 2500 -2054 2932
-rect -2192 -2932 -2054 -2500
-rect -1806 2500 -1668 2932
-rect -1806 -2932 -1668 -2500
-rect -1420 2500 -1282 2932
-rect -1420 -2932 -1282 -2500
-rect -1034 2500 -896 2932
-rect -1034 -2932 -896 -2500
-rect -648 2500 -510 2932
-rect -648 -2932 -510 -2500
-rect -262 2500 -124 2932
-rect -262 -2932 -124 -2500
-rect 124 2500 262 2932
-rect 124 -2932 262 -2500
-rect 510 2500 648 2932
-rect 510 -2932 648 -2500
-rect 896 2500 1034 2932
-rect 896 -2932 1034 -2500
-rect 1282 2500 1420 2932
-rect 1282 -2932 1420 -2500
-rect 1668 2500 1806 2932
-rect 1668 -2932 1806 -2500
-rect 2054 2500 2192 2932
-rect 2054 -2932 2192 -2500
-rect 2440 2500 2578 2932
-rect 2440 -2932 2578 -2500
-rect 2826 2500 2964 2932
-rect 2826 -2932 2964 -2500
-rect 3212 2500 3350 2932
-rect 3212 -2932 3350 -2500
-rect 3598 2500 3736 2932
-rect 3598 -2932 3736 -2500
-rect 3984 2500 4122 2932
-rect 3984 -2932 4122 -2500
-rect 4370 2500 4508 2932
-rect 4370 -2932 4508 -2500
-rect 4756 2500 4894 2932
-rect 4756 -2932 4894 -2500
-rect 5142 2500 5280 2932
-rect 5142 -2932 5280 -2500
-<< xpolyres >>
-rect -5280 -2500 -5142 2500
-rect -4894 -2500 -4756 2500
-rect -4508 -2500 -4370 2500
-rect -4122 -2500 -3984 2500
-rect -3736 -2500 -3598 2500
-rect -3350 -2500 -3212 2500
-rect -2964 -2500 -2826 2500
-rect -2578 -2500 -2440 2500
-rect -2192 -2500 -2054 2500
-rect -1806 -2500 -1668 2500
-rect -1420 -2500 -1282 2500
-rect -1034 -2500 -896 2500
-rect -648 -2500 -510 2500
-rect -262 -2500 -124 2500
-rect 124 -2500 262 2500
-rect 510 -2500 648 2500
-rect 896 -2500 1034 2500
-rect 1282 -2500 1420 2500
-rect 1668 -2500 1806 2500
-rect 2054 -2500 2192 2500
-rect 2440 -2500 2578 2500
-rect 2826 -2500 2964 2500
-rect 3212 -2500 3350 2500
-rect 3598 -2500 3736 2500
-rect 3984 -2500 4122 2500
-rect 4370 -2500 4508 2500
-rect 4756 -2500 4894 2500
-rect 5142 -2500 5280 2500
-<< locali >>
-rect -5410 3028 -5314 3062
-rect 5314 3028 5410 3062
-rect -5410 2966 -5376 3028
-rect 5376 2966 5410 3028
-rect -5410 -3028 -5376 -2966
-rect 5376 -3028 5410 -2966
-rect -5410 -3062 -5314 -3028
-rect 5314 -3062 5410 -3028
-<< viali >>
-rect -5410 -2725 -5376 2725
-rect 5376 -2725 5410 2725
-rect -4838 -3062 4838 -3028
-<< metal1 >>
-rect -5416 2725 -5370 2737
-rect -5416 -2725 -5410 2725
-rect -5376 -2725 -5370 2725
-rect -5416 -2737 -5370 -2725
-rect 5370 2725 5416 2737
-rect 5370 -2725 5376 2725
-rect 5410 -2725 5416 2725
-rect 5370 -2737 5416 -2725
-rect -4850 -3028 4850 -3022
-rect -4850 -3062 -4838 -3028
-rect 4838 -3062 4850 -3028
-rect -4850 -3068 4850 -3062
-<< res0p69 >>
-rect -5282 -2502 -5140 2502
-rect -4896 -2502 -4754 2502
-rect -4510 -2502 -4368 2502
-rect -4124 -2502 -3982 2502
-rect -3738 -2502 -3596 2502
-rect -3352 -2502 -3210 2502
-rect -2966 -2502 -2824 2502
-rect -2580 -2502 -2438 2502
-rect -2194 -2502 -2052 2502
-rect -1808 -2502 -1666 2502
-rect -1422 -2502 -1280 2502
-rect -1036 -2502 -894 2502
-rect -650 -2502 -508 2502
-rect -264 -2502 -122 2502
-rect 122 -2502 264 2502
-rect 508 -2502 650 2502
-rect 894 -2502 1036 2502
-rect 1280 -2502 1422 2502
-rect 1666 -2502 1808 2502
-rect 2052 -2502 2194 2502
-rect 2438 -2502 2580 2502
-rect 2824 -2502 2966 2502
-rect 3210 -2502 3352 2502
-rect 3596 -2502 3738 2502
-rect 3982 -2502 4124 2502
-rect 4368 -2502 4510 2502
-rect 4754 -2502 4896 2502
-rect 5140 -2502 5282 2502
-<< properties >>
-string gencell sky130_fd_pr__res_xhigh_po_0p69
-string FIXED_BBOX -5393 -3045 5393 3045
-string parameters w 0.69 l 25.0 m 1 nx 28 wmin 0.690 lmin 0.50 rho 2000 val 72.811k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.690 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35  sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41  sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 0 viagb 90 viagt 0 viagl 90 viagr 90
-string library sky130
-<< end >>

mag/user_analog_proj_example.mag

diff --git a/mag/user_analog_proj_example.mag b/mag/user_analog_proj_example.mag
deleted file mode 100644
index fcac6f8..0000000
--- a/mag/user_analog_proj_example.mag
+++ /dev/null
@@ -1,18 +0,0 @@
-magic
-tech $PDK
-magscale 1 2
-timestamp 1639841760
-<< error_p >>
-rect 5036 7870 5051 7898
-rect 5008 7676 5023 7870
-rect 20366 7862 20381 7890
-rect 20394 7668 20409 7862
-use example_por  example_por_1
-timestamp 1639841760
-transform 1 0 14132 0 1 -22
-box 0 0 11344 8338
-use example_por  example_por_0
-timestamp 1639841760
-transform -1 0 11285 0 1 -14
-box 0 0 11344 8338
-<< end >>

mag/user_analog_project_wrapper.ext

diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
new file mode 100644
index 0000000..01d1a5b
--- /dev/null
+++ b/mag/user_analog_project_wrapper.ext
@@ -0,0 +1,2490 @@
+timestamp 1662923024
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use VCO VCO_0 1 0 -7837 0 1 638742
+port "io_analog[4]" 41 329294 702300 334294 704800 m5
+port "io_analog[4]" 47 318994 702300 323994 704800 m5
+port "io_analog[5]" 42 227594 702300 232594 704800 m5
+port "io_analog[5]" 48 217294 702300 222294 704800 m5
+port "io_analog[6]" 43 175894 702300 180894 704800 m5
+port "io_analog[6]" 49 165594 702300 170594 704800 m5
+port "io_analog[4]" 41 329294 702300 334294 704800 m4
+port "io_analog[4]" 47 318994 702300 323994 704800 m4
+port "io_analog[5]" 42 227594 702300 232594 704800 m4
+port "io_analog[5]" 48 217294 702300 222294 704800 m4
+port "io_analog[6]" 43 175894 702300 180894 704800 m4
+port "io_analog[6]" 49 165594 702300 170594 704800 m4
+port "io_in_3v3[0]" 83 583520 1544 584800 1656 m3
+port "io_oeb[26]" 128 -800 1544 480 1656 m3
+port "io_in[0]" 56 583520 2726 584800 2838 m3
+port "io_out[26]" 155 -800 2726 480 2838 m3
+port "io_out[0]" 137 583520 3908 584800 4020 m3
+port "io_in[26]" 74 -800 3908 480 4020 m3
+port "io_oeb[0]" 110 583520 5090 584800 5202 m3
+port "io_in_3v3[26]" 101 -800 5090 480 5202 m3
+port "io_in_3v3[1]" 94 583520 6272 584800 6384 m3
+port "io_oeb[25]" 127 -800 6272 480 6384 m3
+port "io_in[1]" 67 583520 7454 584800 7566 m3
+port "io_out[25]" 154 -800 7454 480 7566 m3
+port "io_out[1]" 148 583520 8636 584800 8748 m3
+port "io_in[25]" 73 -800 8636 480 8748 m3
+port "io_oeb[1]" 121 583520 9818 584800 9930 m3
+port "io_in_3v3[25]" 100 -800 9818 480 9930 m3
+port "io_in_3v3[2]" 102 583520 11000 584800 11112 m3
+port "io_oeb[24]" 126 -800 11000 480 11112 m3
+port "io_in[2]" 75 583520 12182 584800 12294 m3
+port "io_out[24]" 153 -800 12182 480 12294 m3
+port "io_out[2]" 156 583520 13364 584800 13476 m3
+port "io_in[24]" 72 -800 13364 480 13476 m3
+port "io_oeb[2]" 129 583520 14546 584800 14658 m3
+port "io_in_3v3[24]" 99 -800 14546 480 14658 m3
+port "io_in_3v3[3]" 103 583520 15728 584800 15840 m3
+port "gpio_noesd[17]" 26 -800 15728 480 15840 m3
+port "io_in[3]" 76 583520 16910 584800 17022 m3
+port "gpio_analog[17]" 8 -800 16910 480 17022 m3
+port "io_out[3]" 157 583520 18092 584800 18204 m3
+port "io_oeb[3]" 130 583520 19274 584800 19386 m3
+port "io_in_3v3[4]" 104 583520 20456 584800 20568 m3
+port "io_in[4]" 77 583520 21638 584800 21750 m3
+port "io_out[4]" 158 583520 22820 584800 22932 m3
+port "io_oeb[4]" 131 583520 24002 584800 24114 m3
+port "io_oeb[23]" 125 -800 32422 480 32534 m3
+port "io_out[23]" 152 -800 33604 480 33716 m3
+port "io_in[23]" 71 -800 34786 480 34898 m3
+port "io_in_3v3[23]" 98 -800 35968 480 36080 m3
+port "gpio_noesd[16]" 25 -800 37150 480 37262 m3
+port "gpio_analog[16]" 7 -800 38332 480 38444 m3
+port "io_in_3v3[5]" 105 583520 46914 584800 47026 m3
+port "io_in[5]" 78 583520 48096 584800 48208 m3
+port "io_out[5]" 159 583520 49278 584800 49390 m3
+port "io_oeb[5]" 132 583520 50460 584800 50572 m3
+port "io_oeb[22]" 124 -800 75644 480 75756 m3
+port "io_out[22]" 151 -800 76826 480 76938 m3
+port "io_in[22]" 70 -800 78008 480 78120 m3
+port "io_in_3v3[22]" 97 -800 79190 480 79302 m3
+port "gpio_noesd[15]" 24 -800 80372 480 80484 m3
+port "gpio_analog[15]" 6 -800 81554 480 81666 m3
+port "io_in_3v3[6]" 106 583520 91572 584800 91684 m3
+port "io_in[6]" 79 583520 92754 584800 92866 m3
+port "io_out[6]" 160 583520 93936 584800 94048 m3
+port "io_oeb[6]" 133 583520 95118 584800 95230 m3
+port "io_oeb[21]" 123 -800 118866 480 118978 m3
+port "io_out[21]" 150 -800 120048 480 120160 m3
+port "io_in[21]" 69 -800 121230 480 121342 m3
+port "io_in_3v3[21]" 96 -800 122412 480 122524 m3
+port "gpio_noesd[14]" 23 -800 123594 480 123706 m3
+port "gpio_analog[14]" 5 -800 124776 480 124888 m3
+port "vssa1" 565 582340 136830 584800 141630 m3
+port "vssa1" 564 582340 146830 584800 151630 m3
+port "vssd2" 571 0 162888 1660 167688 m3
+port "vssd2" 570 0 172888 1660 177688 m3
+port "vssd1" 569 582340 181430 584800 186230 m3
+port "vssd1" 568 582340 191430 584800 196230 m3
+port "vdda2" 560 0 204888 1660 209688 m3
+port "vdda2" 561 0 214888 1660 219688 m3
+port "vdda1" 559 582340 225230 584800 230030 m3
+port "vdda1" 558 582340 235230 584800 240030 m3
+port "io_oeb[20]" 122 -800 246488 480 246600 m3
+port "io_out[20]" 149 -800 247670 480 247782 m3
+port "io_in[20]" 68 -800 248852 480 248964 m3
+port "io_in_3v3[20]" 95 -800 250034 480 250146 m3
+port "gpio_noesd[13]" 22 -800 251216 480 251328 m3
+port "gpio_analog[13]" 4 -800 252398 480 252510 m3
+port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
+port "gpio_noesd[0]" 18 583520 270412 584800 270524 m3
+port "io_in_3v3[7]" 107 583520 271594 584800 271706 m3
+port "io_in[7]" 80 583520 272776 584800 272888 m3
+port "io_out[7]" 161 583520 273958 584800 274070 m3
+port "io_oeb[7]" 134 583520 275140 584800 275252 m3
+port "io_oeb[19]" 120 -800 289510 480 289622 m3
+port "io_out[19]" 147 -800 290692 480 290804 m3
+port "io_in[19]" 66 -800 291874 480 291986 m3
+port "io_in_3v3[19]" 93 -800 293056 480 293168 m3
+port "gpio_noesd[12]" 21 -800 294238 480 294350 m3
+port "gpio_analog[12]" 3 -800 295420 480 295532 m3
+port "gpio_analog[1]" 9 583520 313652 584800 313764 m3
+port "gpio_noesd[1]" 27 583520 314834 584800 314946 m3
+port "io_in_3v3[8]" 108 583520 316016 584800 316128 m3
+port "io_in[8]" 81 583520 317198 584800 317310 m3
+port "io_out[8]" 162 583520 318380 584800 318492 m3
+port "io_oeb[8]" 135 583520 319562 584800 319674 m3
+port "io_oeb[18]" 119 -800 332732 480 332844 m3
+port "io_out[18]" 146 -800 333914 480 334026 m3
+port "io_in_3v3[18]" 92 -800 336278 480 336390 m3
+port "gpio_noesd[11]" 20 -800 337460 480 337572 m3
+port "gpio_analog[11]" 2 -800 338642 480 338754 m3
+port "gpio_analog[2]" 10 583520 358874 584800 358986 m3
+port "gpio_noesd[2]" 28 583520 360056 584800 360168 m3
+port "io_in_3v3[9]" 109 583520 361238 584800 361350 m3
+port "io_in[9]" 82 583520 362420 584800 362532 m3
+port "io_out[9]" 163 583520 363602 584800 363714 m3
+port "io_oeb[9]" 136 583520 364784 584800 364896 m3
+port "io_oeb[17]" 118 -800 375954 480 376066 m3
+port "io_out[17]" 145 -800 377136 480 377248 m3
+port "io_in_3v3[17]" 91 -800 379500 480 379612 m3
+port "gpio_noesd[10]" 19 -800 380682 480 380794 m3
+port "gpio_analog[10]" 1 -800 381864 480 381976 m3
+port "gpio_analog[3]" 11 583520 405296 584800 405408 m3
+port "gpio_noesd[3]" 29 583520 406478 584800 406590 m3
+port "io_in_3v3[10]" 84 583520 407660 584800 407772 m3
+port "io_in[10]" 57 583520 408842 584800 408954 m3
+port "io_out[10]" 138 583520 410024 584800 410136 m3
+port "io_oeb[10]" 111 583520 411206 584800 411318 m3
+port "io_oeb[16]" 117 -800 419176 480 419288 m3
+port "io_out[16]" 144 -800 420358 480 420470 m3
+port "io_in_3v3[16]" 90 -800 422722 480 422834 m3
+port "gpio_noesd[9]" 35 -800 423904 480 424016 m3
+port "gpio_analog[9]" 17 -800 425086 480 425198 m3
+port "gpio_analog[4]" 12 583520 449718 584800 449830 m3
+port "gpio_noesd[4]" 30 583520 450900 584800 451012 m3
+port "io_in_3v3[11]" 85 583520 452082 584800 452194 m3
+port "io_in[11]" 58 583520 453264 584800 453376 m3
+port "io_out[11]" 139 583520 454446 584800 454558 m3
+port "io_oeb[11]" 112 583520 455628 584800 455740 m3
+port "io_oeb[15]" 116 -800 462398 480 462510 m3
+port "io_out[15]" 143 -800 463580 480 463692 m3
+port "io_in[15]" 62 -800 464762 480 464874 m3
+port "gpio_noesd[8]" 34 -800 467126 480 467238 m3
+port "gpio_analog[8]" 16 -800 468308 480 468420 m3
+port "gpio_analog[5]" 13 583520 494140 584800 494252 m3
+port "gpio_noesd[5]" 31 583520 495322 584800 495434 m3
+port "io_in_3v3[12]" 86 583520 496504 584800 496616 m3
+port "io_in[12]" 59 583520 497686 584800 497798 m3
+port "io_out[12]" 140 583520 498868 584800 498980 m3
+port "io_oeb[12]" 113 583520 500050 584800 500162 m3
+port "io_oeb[14]" 115 -800 505620 480 505732 m3
+port "io_out[14]" 142 -800 506802 480 506914 m3
+port "io_in_3v3[14]" 88 -800 509166 480 509278 m3
+port "gpio_noesd[7]" 33 -800 510348 480 510460 m3
+port "gpio_analog[7]" 15 -800 511530 480 511642 m3
+port "vdda1" 556 582340 540562 584800 545362 m3
+port "vdda1" 557 582340 550562 584800 555362 m3
+port "vssa2" 567 0 549442 1660 554242 m3
+port "vssa2" 566 0 559442 1660 564242 m3
+port "gpio_analog[6]" 14 583520 583562 584800 583674 m3
+port "gpio_noesd[6]" 32 583520 584744 584800 584856 m3
+port "io_in_3v3[13]" 87 583520 585926 584800 586038 m3
+port "io_in[13]" 60 583520 587108 584800 587220 m3
+port "io_out[13]" 141 583520 588290 584800 588402 m3
+port "io_oeb[13]" 114 583520 589472 584800 589584 m3
+port "vccd1" 553 582340 629784 584800 634584 m3
+port "vccd1" 552 582340 639784 584800 644584 m3
+port "vccd2" 555 0 633842 1660 638642 m3
+port "vccd2" 554 0 643842 1660 648642 m3
+port "io_analog[0]" 36 582300 677984 584800 682984 m3
+port "io_analog[1]" 38 566594 702300 571594 704800 m3
+port "vssa1" 562 520594 702340 525394 704800 m3
+port "vssa1" 563 510594 702340 515394 704800 m3
+port "io_analog[2]" 39 465394 702300 470394 704800 m3
+port "io_analog[3]" 40 413394 702300 418394 704800 m3
+port "io_analog[4]" 41 329294 702300 334294 704800 m3
+port "io_clamp_high[0]" 50 326794 702300 328994 704800 m3
+port "io_clamp_low[0]" 53 324294 702300 326494 704800 m3
+port "io_analog[4]" 47 318994 702300 323994 704800 m3
+port "io_analog[5]" 42 227594 702300 232594 704800 m3
+port "io_clamp_high[1]" 51 225094 702300 227294 704800 m3
+port "io_clamp_low[1]" 54 222594 702300 224794 704800 m3
+port "io_analog[5]" 48 217294 702300 222294 704800 m3
+port "io_analog[6]" 43 175894 702300 180894 704800 m3
+port "io_clamp_high[2]" 52 173394 702300 175594 704800 m3
+port "io_clamp_low[2]" 55 170894 702300 173094 704800 m3
+port "io_analog[6]" 49 165594 702300 170594 704800 m3
+port "io_analog[7]" 44 120194 702300 125194 704800 m3
+port "io_analog[8]" 45 68194 702300 73194 704800 m3
+port "io_analog[9]" 46 16194 702300 21194 704800 m3
+port "user_irq[2]" 551 583250 -800 583362 480 m2
+port "user_irq[1]" 550 582068 -800 582180 480 m2
+port "user_irq[0]" 549 580886 -800 580998 480 m2
+port "user_clock2" 548 579704 -800 579816 480 m2
+port "la_oenb[127]" 450 578522 -800 578634 480 m2
+port "la_data_out[127]" 322 577340 -800 577452 480 m2
+port "la_data_in[127]" 194 576158 -800 576270 480 m2
+port "la_oenb[126]" 449 574976 -800 575088 480 m2
+port "la_data_out[126]" 321 573794 -800 573906 480 m2
+port "la_data_in[126]" 193 572612 -800 572724 480 m2
+port "la_oenb[125]" 448 571430 -800 571542 480 m2
+port "la_data_out[125]" 320 570248 -800 570360 480 m2
+port "la_data_in[125]" 192 569066 -800 569178 480 m2
+port "la_oenb[124]" 447 567884 -800 567996 480 m2
+port "la_data_out[124]" 319 566702 -800 566814 480 m2
+port "la_data_in[124]" 191 565520 -800 565632 480 m2
+port "la_oenb[123]" 446 564338 -800 564450 480 m2
+port "la_data_out[123]" 318 563156 -800 563268 480 m2
+port "la_data_in[123]" 190 561974 -800 562086 480 m2
+port "la_oenb[122]" 445 560792 -800 560904 480 m2
+port "la_data_out[122]" 317 559610 -800 559722 480 m2
+port "la_data_in[122]" 189 558428 -800 558540 480 m2
+port "la_oenb[121]" 444 557246 -800 557358 480 m2
+port "la_data_out[121]" 316 556064 -800 556176 480 m2
+port "la_data_in[121]" 188 554882 -800 554994 480 m2
+port "la_oenb[120]" 443 553700 -800 553812 480 m2
+port "la_data_out[120]" 315 552518 -800 552630 480 m2
+port "la_data_in[120]" 187 551336 -800 551448 480 m2
+port "la_oenb[119]" 441 550154 -800 550266 480 m2
+port "la_data_out[119]" 313 548972 -800 549084 480 m2
+port "la_data_in[119]" 185 547790 -800 547902 480 m2
+port "la_oenb[118]" 440 546608 -800 546720 480 m2
+port "la_data_out[118]" 312 545426 -800 545538 480 m2
+port "la_data_in[118]" 184 544244 -800 544356 480 m2
+port "la_oenb[117]" 439 543062 -800 543174 480 m2
+port "la_data_out[117]" 311 541880 -800 541992 480 m2
+port "la_data_in[117]" 183 540698 -800 540810 480 m2
+port "la_oenb[116]" 438 539516 -800 539628 480 m2
+port "la_data_out[116]" 310 538334 -800 538446 480 m2
+port "la_data_in[116]" 182 537152 -800 537264 480 m2
+port "la_oenb[115]" 437 535970 -800 536082 480 m2
+port "la_data_out[115]" 309 534788 -800 534900 480 m2
+port "la_data_in[115]" 181 533606 -800 533718 480 m2
+port "la_oenb[114]" 436 532424 -800 532536 480 m2
+port "la_data_out[114]" 308 531242 -800 531354 480 m2
+port "la_data_in[114]" 180 530060 -800 530172 480 m2
+port "la_oenb[113]" 435 528878 -800 528990 480 m2
+port "la_data_out[113]" 307 527696 -800 527808 480 m2
+port "la_data_in[113]" 179 526514 -800 526626 480 m2
+port "la_oenb[112]" 434 525332 -800 525444 480 m2
+port "la_data_out[112]" 306 524150 -800 524262 480 m2
+port "la_data_in[112]" 178 522968 -800 523080 480 m2
+port "la_oenb[111]" 433 521786 -800 521898 480 m2
+port "la_data_out[111]" 305 520604 -800 520716 480 m2
+port "la_data_in[111]" 177 519422 -800 519534 480 m2
+port "la_oenb[110]" 432 518240 -800 518352 480 m2
+port "la_data_out[110]" 304 517058 -800 517170 480 m2
+port "la_data_in[110]" 176 515876 -800 515988 480 m2
+port "la_oenb[109]" 430 514694 -800 514806 480 m2
+port "la_data_out[109]" 302 513512 -800 513624 480 m2
+port "la_data_in[109]" 174 512330 -800 512442 480 m2
+port "la_oenb[108]" 429 511148 -800 511260 480 m2
+port "la_data_out[108]" 301 509966 -800 510078 480 m2
+port "la_data_in[108]" 173 508784 -800 508896 480 m2
+port "la_oenb[107]" 428 507602 -800 507714 480 m2
+port "la_data_out[107]" 300 506420 -800 506532 480 m2
+port "la_data_in[107]" 172 505238 -800 505350 480 m2
+port "la_oenb[106]" 427 504056 -800 504168 480 m2
+port "la_data_out[106]" 299 502874 -800 502986 480 m2
+port "la_data_in[106]" 171 501692 -800 501804 480 m2
+port "la_oenb[105]" 426 500510 -800 500622 480 m2
+port "la_data_out[105]" 298 499328 -800 499440 480 m2
+port "la_data_in[105]" 170 498146 -800 498258 480 m2
+port "la_oenb[104]" 425 496964 -800 497076 480 m2
+port "la_data_out[104]" 297 495782 -800 495894 480 m2
+port "la_data_in[104]" 169 494600 -800 494712 480 m2
+port "la_oenb[103]" 424 493418 -800 493530 480 m2
+port "la_data_out[103]" 296 492236 -800 492348 480 m2
+port "la_data_in[103]" 168 491054 -800 491166 480 m2
+port "la_oenb[102]" 423 489872 -800 489984 480 m2
+port "la_data_out[102]" 295 488690 -800 488802 480 m2
+port "la_data_in[102]" 167 487508 -800 487620 480 m2
+port "la_oenb[101]" 422 486326 -800 486438 480 m2
+port "la_data_out[101]" 294 485144 -800 485256 480 m2
+port "la_data_in[101]" 166 483962 -800 484074 480 m2
+port "la_oenb[100]" 421 482780 -800 482892 480 m2
+port "la_data_out[100]" 293 481598 -800 481710 480 m2
+port "la_data_in[100]" 165 480416 -800 480528 480 m2
+port "la_oenb[99]" 546 479234 -800 479346 480 m2
+port "la_data_out[99]" 418 478052 -800 478164 480 m2
+port "la_data_in[99]" 290 476870 -800 476982 480 m2
+port "la_oenb[98]" 545 475688 -800 475800 480 m2
+port "la_data_out[98]" 417 474506 -800 474618 480 m2
+port "la_data_in[98]" 289 473324 -800 473436 480 m2
+port "la_oenb[97]" 544 472142 -800 472254 480 m2
+port "la_data_out[97]" 416 470960 -800 471072 480 m2
+port "la_data_in[97]" 288 469778 -800 469890 480 m2
+port "la_oenb[96]" 543 468596 -800 468708 480 m2
+port "la_data_out[96]" 415 467414 -800 467526 480 m2
+port "la_data_in[96]" 287 466232 -800 466344 480 m2
+port "la_oenb[95]" 542 465050 -800 465162 480 m2
+port "la_data_out[95]" 414 463868 -800 463980 480 m2
+port "la_data_in[95]" 286 462686 -800 462798 480 m2
+port "la_oenb[94]" 541 461504 -800 461616 480 m2
+port "la_data_out[94]" 413 460322 -800 460434 480 m2
+port "la_data_in[94]" 285 459140 -800 459252 480 m2
+port "la_oenb[93]" 540 457958 -800 458070 480 m2
+port "la_data_out[93]" 412 456776 -800 456888 480 m2
+port "la_data_in[93]" 284 455594 -800 455706 480 m2
+port "la_oenb[92]" 539 454412 -800 454524 480 m2
+port "la_data_out[92]" 411 453230 -800 453342 480 m2
+port "la_data_in[92]" 283 452048 -800 452160 480 m2
+port "la_oenb[91]" 538 450866 -800 450978 480 m2
+port "la_data_out[91]" 410 449684 -800 449796 480 m2
+port "la_data_in[91]" 282 448502 -800 448614 480 m2
+port "la_oenb[90]" 537 447320 -800 447432 480 m2
+port "la_data_out[90]" 409 446138 -800 446250 480 m2
+port "la_data_in[90]" 281 444956 -800 445068 480 m2
+port "la_oenb[89]" 535 443774 -800 443886 480 m2
+port "la_data_out[89]" 407 442592 -800 442704 480 m2
+port "la_data_in[89]" 279 441410 -800 441522 480 m2
+port "la_oenb[88]" 534 440228 -800 440340 480 m2
+port "la_data_out[88]" 406 439046 -800 439158 480 m2
+port "la_data_in[88]" 278 437864 -800 437976 480 m2
+port "la_oenb[87]" 533 436682 -800 436794 480 m2
+port "la_data_out[87]" 405 435500 -800 435612 480 m2
+port "la_data_in[87]" 277 434318 -800 434430 480 m2
+port "la_oenb[86]" 532 433136 -800 433248 480 m2
+port "la_data_out[86]" 404 431954 -800 432066 480 m2
+port "la_data_in[86]" 276 430772 -800 430884 480 m2
+port "la_oenb[85]" 531 429590 -800 429702 480 m2
+port "la_data_out[85]" 403 428408 -800 428520 480 m2
+port "la_data_in[85]" 275 427226 -800 427338 480 m2
+port "la_oenb[84]" 530 426044 -800 426156 480 m2
+port "la_data_out[84]" 402 424862 -800 424974 480 m2
+port "la_data_in[84]" 274 423680 -800 423792 480 m2
+port "la_oenb[83]" 529 422498 -800 422610 480 m2
+port "la_data_out[83]" 401 421316 -800 421428 480 m2
+port "la_data_in[83]" 273 420134 -800 420246 480 m2
+port "la_oenb[82]" 528 418952 -800 419064 480 m2
+port "la_data_out[82]" 400 417770 -800 417882 480 m2
+port "la_data_in[82]" 272 416588 -800 416700 480 m2
+port "la_oenb[81]" 527 415406 -800 415518 480 m2
+port "la_data_out[81]" 399 414224 -800 414336 480 m2
+port "la_data_in[81]" 271 413042 -800 413154 480 m2
+port "la_oenb[80]" 526 411860 -800 411972 480 m2
+port "la_data_out[80]" 398 410678 -800 410790 480 m2
+port "la_data_in[80]" 270 409496 -800 409608 480 m2
+port "la_oenb[79]" 524 408314 -800 408426 480 m2
+port "la_data_out[79]" 396 407132 -800 407244 480 m2
+port "la_data_in[79]" 268 405950 -800 406062 480 m2
+port "la_oenb[78]" 523 404768 -800 404880 480 m2
+port "la_data_out[78]" 395 403586 -800 403698 480 m2
+port "la_data_in[78]" 267 402404 -800 402516 480 m2
+port "la_oenb[77]" 522 401222 -800 401334 480 m2
+port "la_data_out[77]" 394 400040 -800 400152 480 m2
+port "la_data_in[77]" 266 398858 -800 398970 480 m2
+port "la_oenb[76]" 521 397676 -800 397788 480 m2
+port "la_data_out[76]" 393 396494 -800 396606 480 m2
+port "la_data_in[76]" 265 395312 -800 395424 480 m2
+port "la_oenb[75]" 520 394130 -800 394242 480 m2
+port "la_data_out[75]" 392 392948 -800 393060 480 m2
+port "la_data_in[75]" 264 391766 -800 391878 480 m2
+port "la_oenb[74]" 519 390584 -800 390696 480 m2
+port "la_data_out[74]" 391 389402 -800 389514 480 m2
+port "la_data_in[74]" 263 388220 -800 388332 480 m2
+port "la_oenb[73]" 518 387038 -800 387150 480 m2
+port "la_data_out[73]" 390 385856 -800 385968 480 m2
+port "la_data_in[73]" 262 384674 -800 384786 480 m2
+port "la_oenb[72]" 517 383492 -800 383604 480 m2
+port "la_data_out[72]" 389 382310 -800 382422 480 m2
+port "la_data_in[72]" 261 381128 -800 381240 480 m2
+port "la_oenb[71]" 516 379946 -800 380058 480 m2
+port "la_data_out[71]" 388 378764 -800 378876 480 m2
+port "la_data_in[71]" 260 377582 -800 377694 480 m2
+port "la_oenb[70]" 515 376400 -800 376512 480 m2
+port "la_data_out[70]" 387 375218 -800 375330 480 m2
+port "la_data_in[70]" 259 374036 -800 374148 480 m2
+port "la_oenb[69]" 513 372854 -800 372966 480 m2
+port "la_data_out[69]" 385 371672 -800 371784 480 m2
+port "la_data_in[69]" 257 370490 -800 370602 480 m2
+port "la_oenb[68]" 512 369308 -800 369420 480 m2
+port "la_data_out[68]" 384 368126 -800 368238 480 m2
+port "la_data_in[68]" 256 366944 -800 367056 480 m2
+port "la_oenb[67]" 511 365762 -800 365874 480 m2
+port "la_data_out[67]" 383 364580 -800 364692 480 m2
+port "la_data_in[67]" 255 363398 -800 363510 480 m2
+port "la_oenb[66]" 510 362216 -800 362328 480 m2
+port "la_data_out[66]" 382 361034 -800 361146 480 m2
+port "la_data_in[66]" 254 359852 -800 359964 480 m2
+port "la_oenb[65]" 509 358670 -800 358782 480 m2
+port "la_data_out[65]" 381 357488 -800 357600 480 m2
+port "la_data_in[65]" 253 356306 -800 356418 480 m2
+port "la_oenb[64]" 508 355124 -800 355236 480 m2
+port "la_data_out[64]" 380 353942 -800 354054 480 m2
+port "la_data_in[64]" 252 352760 -800 352872 480 m2
+port "la_oenb[63]" 507 351578 -800 351690 480 m2
+port "la_data_out[63]" 379 350396 -800 350508 480 m2
+port "la_data_in[63]" 251 349214 -800 349326 480 m2
+port "la_oenb[62]" 506 348032 -800 348144 480 m2
+port "la_data_out[62]" 378 346850 -800 346962 480 m2
+port "la_data_in[62]" 250 345668 -800 345780 480 m2
+port "la_oenb[61]" 505 344486 -800 344598 480 m2
+port "la_data_out[61]" 377 343304 -800 343416 480 m2
+port "la_data_in[61]" 249 342122 -800 342234 480 m2
+port "la_oenb[60]" 504 340940 -800 341052 480 m2
+port "la_data_out[60]" 376 339758 -800 339870 480 m2
+port "la_data_in[60]" 248 338576 -800 338688 480 m2
+port "la_oenb[59]" 502 337394 -800 337506 480 m2
+port "la_data_out[59]" 374 336212 -800 336324 480 m2
+port "la_data_in[59]" 246 335030 -800 335142 480 m2
+port "la_oenb[58]" 501 333848 -800 333960 480 m2
+port "la_data_out[58]" 373 332666 -800 332778 480 m2
+port "la_data_in[58]" 245 331484 -800 331596 480 m2
+port "la_oenb[57]" 500 330302 -800 330414 480 m2
+port "la_data_out[57]" 372 329120 -800 329232 480 m2
+port "la_data_in[57]" 244 327938 -800 328050 480 m2
+port "la_oenb[56]" 499 326756 -800 326868 480 m2
+port "la_data_out[56]" 371 325574 -800 325686 480 m2
+port "la_data_in[56]" 243 324392 -800 324504 480 m2
+port "la_oenb[55]" 498 323210 -800 323322 480 m2
+port "la_data_out[55]" 370 322028 -800 322140 480 m2
+port "la_data_in[55]" 242 320846 -800 320958 480 m2
+port "la_oenb[54]" 497 319664 -800 319776 480 m2
+port "la_data_out[54]" 369 318482 -800 318594 480 m2
+port "la_data_in[54]" 241 317300 -800 317412 480 m2
+port "la_oenb[53]" 496 316118 -800 316230 480 m2
+port "la_data_out[53]" 368 314936 -800 315048 480 m2
+port "la_data_in[53]" 240 313754 -800 313866 480 m2
+port "la_oenb[52]" 495 312572 -800 312684 480 m2
+port "la_data_out[52]" 367 311390 -800 311502 480 m2
+port "la_data_in[52]" 239 310208 -800 310320 480 m2
+port "la_oenb[51]" 494 309026 -800 309138 480 m2
+port "la_data_out[51]" 366 307844 -800 307956 480 m2
+port "la_data_in[51]" 238 306662 -800 306774 480 m2
+port "la_oenb[50]" 493 305480 -800 305592 480 m2
+port "la_data_out[50]" 365 304298 -800 304410 480 m2
+port "la_data_in[50]" 237 303116 -800 303228 480 m2
+port "la_oenb[49]" 491 301934 -800 302046 480 m2
+port "la_data_out[49]" 363 300752 -800 300864 480 m2
+port "la_data_in[49]" 235 299570 -800 299682 480 m2
+port "la_oenb[48]" 490 298388 -800 298500 480 m2
+port "la_data_out[48]" 362 297206 -800 297318 480 m2
+port "la_data_in[48]" 234 296024 -800 296136 480 m2
+port "la_oenb[47]" 489 294842 -800 294954 480 m2
+port "la_data_out[47]" 361 293660 -800 293772 480 m2
+port "la_data_in[47]" 233 292478 -800 292590 480 m2
+port "la_oenb[46]" 488 291296 -800 291408 480 m2
+port "la_data_out[46]" 360 290114 -800 290226 480 m2
+port "la_data_in[46]" 232 288932 -800 289044 480 m2
+port "la_oenb[45]" 487 287750 -800 287862 480 m2
+port "la_data_out[45]" 359 286568 -800 286680 480 m2
+port "la_data_in[45]" 231 285386 -800 285498 480 m2
+port "la_oenb[44]" 486 284204 -800 284316 480 m2
+port "la_data_out[44]" 358 283022 -800 283134 480 m2
+port "la_data_in[44]" 230 281840 -800 281952 480 m2
+port "la_oenb[43]" 485 280658 -800 280770 480 m2
+port "la_data_out[43]" 357 279476 -800 279588 480 m2
+port "la_data_in[43]" 229 278294 -800 278406 480 m2
+port "la_oenb[42]" 484 277112 -800 277224 480 m2
+port "la_data_out[42]" 356 275930 -800 276042 480 m2
+port "la_data_in[42]" 228 274748 -800 274860 480 m2
+port "la_oenb[41]" 483 273566 -800 273678 480 m2
+port "la_data_out[41]" 355 272384 -800 272496 480 m2
+port "la_data_in[41]" 227 271202 -800 271314 480 m2
+port "la_oenb[40]" 482 270020 -800 270132 480 m2
+port "la_data_out[40]" 354 268838 -800 268950 480 m2
+port "la_data_in[40]" 226 267656 -800 267768 480 m2
+port "la_oenb[39]" 480 266474 -800 266586 480 m2
+port "la_data_out[39]" 352 265292 -800 265404 480 m2
+port "la_data_in[39]" 224 264110 -800 264222 480 m2
+port "la_oenb[38]" 479 262928 -800 263040 480 m2
+port "la_data_out[38]" 351 261746 -800 261858 480 m2
+port "la_data_in[38]" 223 260564 -800 260676 480 m2
+port "la_oenb[37]" 478 259382 -800 259494 480 m2
+port "la_data_out[37]" 350 258200 -800 258312 480 m2
+port "la_data_in[37]" 222 257018 -800 257130 480 m2
+port "la_oenb[36]" 477 255836 -800 255948 480 m2
+port "la_data_out[36]" 349 254654 -800 254766 480 m2
+port "la_data_in[36]" 221 253472 -800 253584 480 m2
+port "la_oenb[35]" 476 252290 -800 252402 480 m2
+port "la_data_out[35]" 348 251108 -800 251220 480 m2
+port "la_data_in[35]" 220 249926 -800 250038 480 m2
+port "la_oenb[34]" 475 248744 -800 248856 480 m2
+port "la_data_out[34]" 347 247562 -800 247674 480 m2
+port "la_data_in[34]" 219 246380 -800 246492 480 m2
+port "la_oenb[33]" 474 245198 -800 245310 480 m2
+port "la_data_out[33]" 346 244016 -800 244128 480 m2
+port "la_data_in[33]" 218 242834 -800 242946 480 m2
+port "la_oenb[32]" 473 241652 -800 241764 480 m2
+port "la_data_out[32]" 345 240470 -800 240582 480 m2
+port "la_data_in[32]" 217 239288 -800 239400 480 m2
+port "la_oenb[31]" 472 238106 -800 238218 480 m2
+port "la_data_out[31]" 344 236924 -800 237036 480 m2
+port "la_data_in[31]" 216 235742 -800 235854 480 m2
+port "la_oenb[30]" 471 234560 -800 234672 480 m2
+port "la_data_out[30]" 343 233378 -800 233490 480 m2
+port "la_data_in[30]" 215 232196 -800 232308 480 m2
+port "la_oenb[29]" 469 231014 -800 231126 480 m2
+port "la_data_out[29]" 341 229832 -800 229944 480 m2
+port "la_data_in[29]" 213 228650 -800 228762 480 m2
+port "la_oenb[28]" 468 227468 -800 227580 480 m2
+port "la_data_out[28]" 340 226286 -800 226398 480 m2
+port "la_data_in[28]" 212 225104 -800 225216 480 m2
+port "la_oenb[27]" 467 223922 -800 224034 480 m2
+port "la_data_out[27]" 339 222740 -800 222852 480 m2
+port "la_data_in[27]" 211 221558 -800 221670 480 m2
+port "la_oenb[26]" 466 220376 -800 220488 480 m2
+port "la_data_out[26]" 338 219194 -800 219306 480 m2
+port "la_data_in[26]" 210 218012 -800 218124 480 m2
+port "la_oenb[25]" 465 216830 -800 216942 480 m2
+port "la_data_out[25]" 337 215648 -800 215760 480 m2
+port "la_data_in[25]" 209 214466 -800 214578 480 m2
+port "la_oenb[24]" 464 213284 -800 213396 480 m2
+port "la_data_out[24]" 336 212102 -800 212214 480 m2
+port "la_data_in[24]" 208 210920 -800 211032 480 m2
+port "la_oenb[23]" 463 209738 -800 209850 480 m2
+port "la_data_out[23]" 335 208556 -800 208668 480 m2
+port "la_data_in[23]" 207 207374 -800 207486 480 m2
+port "la_oenb[22]" 462 206192 -800 206304 480 m2
+port "la_data_out[22]" 334 205010 -800 205122 480 m2
+port "la_data_in[22]" 206 203828 -800 203940 480 m2
+port "la_oenb[21]" 461 202646 -800 202758 480 m2
+port "la_data_out[21]" 333 201464 -800 201576 480 m2
+port "la_data_in[21]" 205 200282 -800 200394 480 m2
+port "la_oenb[20]" 460 199100 -800 199212 480 m2
+port "la_data_out[20]" 332 197918 -800 198030 480 m2
+port "la_data_in[20]" 204 196736 -800 196848 480 m2
+port "la_oenb[19]" 458 195554 -800 195666 480 m2
+port "la_data_out[19]" 330 194372 -800 194484 480 m2
+port "la_data_in[19]" 202 193190 -800 193302 480 m2
+port "la_oenb[18]" 457 192008 -800 192120 480 m2
+port "la_data_out[18]" 329 190826 -800 190938 480 m2
+port "la_data_in[18]" 201 189644 -800 189756 480 m2
+port "la_oenb[17]" 456 188462 -800 188574 480 m2
+port "la_data_out[17]" 328 187280 -800 187392 480 m2
+port "la_data_in[17]" 200 186098 -800 186210 480 m2
+port "la_oenb[16]" 455 184916 -800 185028 480 m2
+port "la_data_out[16]" 327 183734 -800 183846 480 m2
+port "la_data_in[16]" 199 182552 -800 182664 480 m2
+port "la_oenb[15]" 454 181370 -800 181482 480 m2
+port "la_data_out[15]" 326 180188 -800 180300 480 m2
+port "la_data_in[15]" 198 179006 -800 179118 480 m2
+port "la_oenb[14]" 453 177824 -800 177936 480 m2
+port "la_data_out[14]" 325 176642 -800 176754 480 m2
+port "la_data_in[14]" 197 175460 -800 175572 480 m2
+port "la_oenb[13]" 452 174278 -800 174390 480 m2
+port "la_data_out[13]" 324 173096 -800 173208 480 m2
+port "la_data_in[13]" 196 171914 -800 172026 480 m2
+port "la_oenb[12]" 451 170732 -800 170844 480 m2
+port "la_data_out[12]" 323 169550 -800 169662 480 m2
+port "la_data_in[12]" 195 168368 -800 168480 480 m2
+port "la_oenb[11]" 442 167186 -800 167298 480 m2
+port "la_data_out[11]" 314 166004 -800 166116 480 m2
+port "la_data_in[11]" 186 164822 -800 164934 480 m2
+port "la_oenb[10]" 431 163640 -800 163752 480 m2
+port "la_data_out[10]" 303 162458 -800 162570 480 m2
+port "la_data_in[10]" 175 161276 -800 161388 480 m2
+port "la_oenb[9]" 547 160094 -800 160206 480 m2
+port "la_data_out[9]" 419 158912 -800 159024 480 m2
+port "la_data_in[9]" 291 157730 -800 157842 480 m2
+port "la_oenb[8]" 536 156548 -800 156660 480 m2
+port "la_data_out[8]" 408 155366 -800 155478 480 m2
+port "la_data_in[8]" 280 154184 -800 154296 480 m2
+port "la_oenb[7]" 525 153002 -800 153114 480 m2
+port "la_data_out[7]" 397 151820 -800 151932 480 m2
+port "la_data_in[7]" 269 150638 -800 150750 480 m2
+port "la_oenb[6]" 514 149456 -800 149568 480 m2
+port "la_data_out[6]" 386 148274 -800 148386 480 m2
+port "la_data_in[6]" 258 147092 -800 147204 480 m2
+port "la_oenb[5]" 503 145910 -800 146022 480 m2
+port "la_data_out[5]" 375 144728 -800 144840 480 m2
+port "la_data_in[5]" 247 143546 -800 143658 480 m2
+port "la_oenb[4]" 492 142364 -800 142476 480 m2
+port "la_data_out[4]" 364 141182 -800 141294 480 m2
+port "la_data_in[4]" 236 140000 -800 140112 480 m2
+port "la_oenb[3]" 481 138818 -800 138930 480 m2
+port "la_data_out[3]" 353 137636 -800 137748 480 m2
+port "la_data_in[3]" 225 136454 -800 136566 480 m2
+port "la_oenb[2]" 470 135272 -800 135384 480 m2
+port "la_data_out[2]" 342 134090 -800 134202 480 m2
+port "la_data_in[2]" 214 132908 -800 133020 480 m2
+port "la_oenb[1]" 459 131726 -800 131838 480 m2
+port "la_data_out[1]" 331 130544 -800 130656 480 m2
+port "la_data_in[1]" 203 129362 -800 129474 480 m2
+port "la_oenb[0]" 420 128180 -800 128292 480 m2
+port "la_data_out[0]" 292 126998 -800 127110 480 m2
+port "la_data_in[0]" 164 125816 -800 125928 480 m2
+port "wbs_dat_o[31]" 664 124634 -800 124746 480 m2
+port "wbs_dat_i[31]" 632 123452 -800 123564 480 m2
+port "wbs_adr_i[31]" 599 122270 -800 122382 480 m2
+port "wbs_dat_o[30]" 663 121088 -800 121200 480 m2
+port "wbs_dat_i[30]" 631 119906 -800 120018 480 m2
+port "wbs_adr_i[30]" 598 118724 -800 118836 480 m2
+port "wbs_dat_o[29]" 661 117542 -800 117654 480 m2
+port "wbs_dat_i[29]" 629 116360 -800 116472 480 m2
+port "wbs_adr_i[29]" 596 115178 -800 115290 480 m2
+port "wbs_dat_o[28]" 660 113996 -800 114108 480 m2
+port "wbs_dat_i[28]" 628 112814 -800 112926 480 m2
+port "wbs_adr_i[28]" 595 111632 -800 111744 480 m2
+port "wbs_dat_o[27]" 659 110450 -800 110562 480 m2
+port "wbs_dat_i[27]" 627 109268 -800 109380 480 m2
+port "wbs_adr_i[27]" 594 108086 -800 108198 480 m2
+port "wbs_dat_o[26]" 658 106904 -800 107016 480 m2
+port "wbs_dat_i[26]" 626 105722 -800 105834 480 m2
+port "wbs_adr_i[26]" 593 104540 -800 104652 480 m2
+port "wbs_dat_o[25]" 657 103358 -800 103470 480 m2
+port "wbs_dat_i[25]" 625 102176 -800 102288 480 m2
+port "wbs_adr_i[25]" 592 100994 -800 101106 480 m2
+port "wbs_dat_o[24]" 656 99812 -800 99924 480 m2
+port "wbs_dat_i[24]" 624 98630 -800 98742 480 m2
+port "wbs_adr_i[24]" 591 97448 -800 97560 480 m2
+port "wbs_dat_o[23]" 655 96266 -800 96378 480 m2
+port "wbs_dat_i[23]" 623 95084 -800 95196 480 m2
+port "wbs_adr_i[23]" 590 93902 -800 94014 480 m2
+port "wbs_dat_o[22]" 654 92720 -800 92832 480 m2
+port "wbs_dat_i[22]" 622 91538 -800 91650 480 m2
+port "wbs_adr_i[22]" 589 90356 -800 90468 480 m2
+port "wbs_dat_o[21]" 653 89174 -800 89286 480 m2
+port "wbs_dat_i[21]" 621 87992 -800 88104 480 m2
+port "wbs_adr_i[21]" 588 86810 -800 86922 480 m2
+port "wbs_dat_o[20]" 652 85628 -800 85740 480 m2
+port "wbs_dat_i[20]" 620 84446 -800 84558 480 m2
+port "wbs_adr_i[20]" 587 83264 -800 83376 480 m2
+port "wbs_dat_o[19]" 650 82082 -800 82194 480 m2
+port "wbs_dat_i[19]" 618 80900 -800 81012 480 m2
+port "wbs_adr_i[19]" 585 79718 -800 79830 480 m2
+port "wbs_dat_o[18]" 649 78536 -800 78648 480 m2
+port "wbs_dat_i[18]" 617 77354 -800 77466 480 m2
+port "wbs_adr_i[18]" 584 76172 -800 76284 480 m2
+port "wbs_dat_o[17]" 648 74990 -800 75102 480 m2
+port "wbs_dat_i[17]" 616 73808 -800 73920 480 m2
+port "wbs_adr_i[17]" 583 72626 -800 72738 480 m2
+port "wbs_dat_o[16]" 647 71444 -800 71556 480 m2
+port "wbs_dat_i[16]" 615 70262 -800 70374 480 m2
+port "wbs_adr_i[16]" 582 69080 -800 69192 480 m2
+port "wbs_dat_o[15]" 646 67898 -800 68010 480 m2
+port "wbs_dat_i[15]" 614 66716 -800 66828 480 m2
+port "wbs_adr_i[15]" 581 65534 -800 65646 480 m2
+port "wbs_dat_o[14]" 645 64352 -800 64464 480 m2
+port "wbs_dat_i[14]" 613 63170 -800 63282 480 m2
+port "wbs_adr_i[14]" 580 61988 -800 62100 480 m2
+port "wbs_dat_o[13]" 644 60806 -800 60918 480 m2
+port "wbs_dat_i[13]" 612 59624 -800 59736 480 m2
+port "wbs_adr_i[13]" 579 58442 -800 58554 480 m2
+port "wbs_dat_o[12]" 643 57260 -800 57372 480 m2
+port "wbs_dat_i[12]" 611 56078 -800 56190 480 m2
+port "wbs_adr_i[12]" 578 54896 -800 55008 480 m2
+port "wbs_dat_o[11]" 642 53714 -800 53826 480 m2
+port "wbs_dat_i[11]" 610 52532 -800 52644 480 m2
+port "wbs_adr_i[11]" 577 51350 -800 51462 480 m2
+port "wbs_dat_o[10]" 641 50168 -800 50280 480 m2
+port "wbs_dat_i[10]" 609 48986 -800 49098 480 m2
+port "wbs_adr_i[10]" 576 47804 -800 47916 480 m2
+port "wbs_dat_o[9]" 671 46622 -800 46734 480 m2
+port "wbs_dat_i[9]" 639 45440 -800 45552 480 m2
+port "wbs_adr_i[9]" 606 44258 -800 44370 480 m2
+port "wbs_dat_o[8]" 670 43076 -800 43188 480 m2
+port "wbs_dat_i[8]" 638 41894 -800 42006 480 m2
+port "wbs_adr_i[8]" 605 40712 -800 40824 480 m2
+port "wbs_dat_o[7]" 669 39530 -800 39642 480 m2
+port "wbs_dat_i[7]" 637 38348 -800 38460 480 m2
+port "wbs_adr_i[7]" 604 37166 -800 37278 480 m2
+port "wbs_dat_o[6]" 668 35984 -800 36096 480 m2
+port "wbs_dat_i[6]" 636 34802 -800 34914 480 m2
+port "wbs_adr_i[6]" 603 33620 -800 33732 480 m2
+port "wbs_dat_o[5]" 667 32438 -800 32550 480 m2
+port "wbs_dat_i[5]" 635 31256 -800 31368 480 m2
+port "wbs_adr_i[5]" 602 30074 -800 30186 480 m2
+port "wbs_dat_o[4]" 666 28892 -800 29004 480 m2
+port "wbs_dat_i[4]" 634 27710 -800 27822 480 m2
+port "wbs_adr_i[4]" 601 26528 -800 26640 480 m2
+port "wbs_sel_i[3]" 675 25346 -800 25458 480 m2
+port "wbs_dat_o[3]" 665 24164 -800 24276 480 m2
+port "wbs_dat_i[3]" 633 22982 -800 23094 480 m2
+port "wbs_adr_i[3]" 600 21800 -800 21912 480 m2
+port "wbs_sel_i[2]" 674 20618 -800 20730 480 m2
+port "wbs_dat_o[2]" 662 19436 -800 19548 480 m2
+port "wbs_dat_i[2]" 630 18254 -800 18366 480 m2
+port "wbs_adr_i[2]" 597 17072 -800 17184 480 m2
+port "wbs_sel_i[1]" 673 15890 -800 16002 480 m2
+port "wbs_dat_o[1]" 651 14708 -800 14820 480 m2
+port "wbs_dat_i[1]" 619 13526 -800 13638 480 m2
+port "wbs_adr_i[1]" 586 12344 -800 12456 480 m2
+port "wbs_sel_i[0]" 672 11162 -800 11274 480 m2
+port "wbs_dat_o[0]" 640 9980 -800 10092 480 m2
+port "wbs_dat_i[0]" 608 8798 -800 8910 480 m2
+port "wbs_adr_i[0]" 575 7616 -800 7728 480 m2
+port "wbs_we_i" 677 6434 -800 6546 480 m2
+port "wbs_stb_i" 676 5252 -800 5364 480 m2
+port "wbs_cyc_i" 607 4070 -800 4182 480 m2
+port "wbs_ack_o" 574 2888 -800 3000 480 m2
+port "wb_rst_i" 573 1706 -800 1818 480 m2
+port "wb_clk_i" 572 524 -800 636 480 m2
+port "io_in[14]" 61 -800 507984 480 508096 m3
+port "io_in_3v3[15]" 89 -800 465944 480 466056 m3
+port "io_in[16]" 63 -800 421540 480 421652 m3
+port "io_in[17]" 64 -800 378318 480 378430 m3
+port "io_in[18]" 65 -800 335096 480 335208 m3
+node "io_analog[4]" 0 2913.75 329294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[4]" 0 2913.75 318994 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[5]" 0 2913.75 227594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[5]" 0 2913.75 217294 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[6]" 0 2913.75 175894 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[6]" 0 2913.75 165594 702300 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0
+node "io_analog[4]" 0 2751 329294 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[4]" 0 2751 318994 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
+node "io_analog[5]" 0 2751 227594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12500000 15000 0 0 0 0
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+node "wbs_adr_i[6]" 1 522.256 33620 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[5]" 1 522.256 32438 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[5]" 1 522.256 31256 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[5]" 1 522.256 30074 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[4]" 1 522.256 28892 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[4]" 1 522.256 27710 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[4]" 1 522.256 26528 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[3]" 1 522.256 25346 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[3]" 1 522.256 24164 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[3]" 1 522.256 22982 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[3]" 1 522.256 21800 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[2]" 1 522.256 20618 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[2]" 1 522.256 19436 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[2]" 1 522.256 18254 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[2]" 1 522.256 17072 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[1]" 1 522.256 15890 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[1]" 1 522.256 14708 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[1]" 1 522.256 13526 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[1]" 1 522.256 12344 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_sel_i[0]" 1 522.256 11162 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_o[0]" 1 522.256 9980 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_dat_i[0]" 1 522.256 8798 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_adr_i[0]" 1 522.256 7616 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_we_i" 1 522.256 6434 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_stb_i" 1 522.256 5252 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_cyc_i" 1 522.256 4070 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wbs_ack_o" 1 522.256 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_rst_i" 1 522.256 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_clk_i" 1 554.223 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "REF" 2 34721.3 23190 671420 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 442000 4820 596000 6360 31850400 139760 0 0 0 0
+node "CTRL1" 0 67951.9 56980 660080 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 21316400 304800 10353520 116200 0 0 0 0 0 0
+equiv "CTRL1" "io_in[14]"
+node "CTRL2" 0 53314.9 56720 660440 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 27252400 389600 10305360 115680 0 0 0 0 0 0
+equiv "CTRL2" "io_in_3v3[15]"
+node "CTRL3" 0 66303.8 56480 660960 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 33544000 479480 10256720 115200 0 0 0 0 0 0
+equiv "CTRL3" "io_in[16]"
+node "CTRL4" 0 79104.1 56200 661560 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 39676000 567080 10203600 114640 0 0 0 0 0 0
+equiv "CTRL4" "io_in[17]"
+node "CTRL5" 0 150194 55960 662480 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 45858400 655400 10169920 114160 0 0 0 0 0 0
+equiv "CTRL5" "io_in[18]"
+node "VCTRL" 1 32248.2 14920 668060 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9217200 47540 460000 2840 25122400 42440 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "la_data_out[59]" "la_data_in[59]" 46.7738
+cap "io_oeb[8]" "io_out[8]" 67.2299
+cap "VCTRL" "REF" 143.005
+cap "la_data_in[111]" "la_oenb[110]" 46.7738
+cap "la_data_in[43]" "la_data_out[43]" 46.7738
+cap "wbs_adr_i[21]" "wbs_dat_o[20]" 46.7738
+cap "wbs_dat_i[7]" "wbs_adr_i[7]" 46.7738
+cap "io_in_3v3[23]" "gpio_noesd[16]" 67.2299
+cap "la_data_in[57]" "la_oenb[56]" 46.7738
+cap "la_data_out[0]" "la_data_in[0]" 46.7738
+cap "io_in[25]" "io_out[25]" 67.2299
+cap "io_in[24]" "io_in_3v3[24]" 67.2299
+cap "la_data_out[98]" "la_oenb[98]" 46.7738
+cap "la_data_in[2]" "la_oenb[1]" 46.7738
+cap "la_data_out[17]" "la_oenb[17]" 46.7738
+cap "la_oenb[102]" "la_data_out[102]" 46.7738
+cap "la_data_in[40]" "la_data_out[40]" 46.7738
+cap "wbs_dat_i[13]" "wbs_adr_i[13]" 46.7738
+cap "io_in[2]" "io_in_3v3[2]" 67.2299
+cap "gpio_noesd[14]" "gpio_analog[14]" 67.2299
+cap "OUTB" "OUTA" 86.5302
+cap "la_oenb[43]" "la_data_in[44]" 46.7738
+cap "la_data_in[30]" "la_data_out[30]" 46.7738
+cap "wbs_adr_i[24]" "wbs_dat_o[23]" 46.7738
+cap "la_oenb[75]" "la_data_out[75]" 46.7738
+cap "la_data_out[41]" "la_oenb[41]" 46.7738
+cap "gpio_noesd[17]" "gpio_analog[17]" 67.2299
+cap "la_data_out[87]" "la_data_in[87]" 46.7738
+cap "wbs_adr_i[28]" "wbs_dat_i[28]" 46.7738
+cap "io_in[5]" "io_out[5]" 67.2299
+cap "la_data_out[105]" "la_data_in[105]" 46.7738
+cap "la_data_out[39]" "la_data_in[39]" 46.7738
+cap "io_in[1]" "io_in_3v3[1]" 67.2299
+cap "la_oenb[46]" "la_data_out[46]" 46.7738
+cap "io_in_3v3[19]" "gpio_noesd[12]" 67.2299
+cap "la_data_in[50]" "la_oenb[49]" 46.7738
+cap "la_data_in[34]" "la_oenb[33]" 46.7738
+cap "la_data_in[31]" "la_oenb[30]" 46.7738
+cap "la_data_in[54]" "la_oenb[53]" 46.7738
+cap "wbs_dat_o[24]" "wbs_adr_i[25]" 46.7738
+cap "wbs_dat_i[10]" "wbs_adr_i[10]" 46.7738
+cap "la_data_out[112]" "la_oenb[112]" 46.7738
+cap "la_data_out[95]" "la_data_in[95]" 46.7738
+cap "la_data_in[58]" "la_oenb[57]" 46.7738
+cap "la_oenb[54]" "la_data_out[54]" 46.7738
+cap "CTRL1" "CTRL5" 6982.64
+cap "la_oenb[126]" "la_data_out[126]" 46.7738
+cap "la_data_out[34]" "la_oenb[34]" 46.7738
+cap "wbs_dat_i[14]" "wbs_adr_i[14]" 46.7738
+cap "io_out[26]" "io_oeb[26]" 67.2299
+cap "io_out[19]" "io_oeb[19]" 67.2299
+cap "la_oenb[125]" "la_data_out[125]" 46.7738
+cap "la_data_in[33]" "la_oenb[32]" 46.7738
+cap "la_data_in[43]" "la_oenb[42]" 46.7738
+cap "wbs_adr_i[19]" "wbs_dat_o[18]" 46.7738
+cap "io_out[3]" "io_oeb[3]" 67.2299
+cap "gpio_noesd[2]" "gpio_analog[2]" 67.2299
+cap "la_data_out[110]" "la_oenb[110]" 46.7738
+cap "la_oenb[109]" "la_data_out[109]" 46.7738
+cap "la_data_in[79]" "la_oenb[78]" 46.7738
+cap "la_oenb[74]" "la_data_out[74]" 46.7738
+cap "la_oenb[111]" "la_data_out[111]" 46.7738
+cap "la_data_in[41]" "la_oenb[40]" 46.7738
+cap "la_data_in[22]" "la_data_out[22]" 46.7738
+cap "wbs_dat_o[3]" "wbs_sel_i[3]" 46.7738
+cap "la_data_out[77]" "la_oenb[77]" 46.7738
+cap "la_data_in[4]" "la_oenb[3]" 46.7738
+cap "wbs_adr_i[31]" "wbs_dat_o[30]" 46.7738
+cap "la_data_in[64]" "la_oenb[63]" 46.7738
+cap "wbs_dat_o[15]" "wbs_adr_i[16]" 46.7738
+cap "io_in[4]" "io_out[4]" 67.2299
+cap "la_oenb[121]" "la_data_out[121]" 46.7738
+cap "la_data_in[101]" "la_oenb[100]" 46.7738
+cap "la_data_in[70]" "la_data_out[70]" 46.7738
+cap "la_data_out[28]" "la_data_in[28]" 46.7738
+cap "la_data_in[28]" "la_oenb[27]" 46.7738
+cap "la_oenb[4]" "la_data_in[5]" 46.7738
+cap "io_oeb[2]" "io_in_3v3[3]" 67.2299
+cap "la_data_in[110]" "la_oenb[109]" 46.7738
+cap "la_data_in[66]" "la_oenb[65]" 46.7738
+cap "wbs_dat_i[14]" "wbs_dat_o[14]" 46.7738
+cap "io_analog[4]" "io_analog[4]" 26259.4
+cap "io_in_3v3[13]" "gpio_noesd[6]" 67.2299
+cap "la_oenb[86]" "la_data_out[86]" 46.7738
+cap "la_oenb[101]" "la_data_out[101]" 46.7738
+cap "la_oenb[34]" "la_data_in[35]" 46.7738
+cap "io_oeb[7]" "io_out[7]" 67.2299
+cap "la_data_out[6]" "la_data_in[6]" 46.7738
+cap "la_data_in[2]" "la_data_out[2]" 46.7738
+cap "la_data_out[12]" "la_data_in[12]" 46.7738
+cap "la_data_out[1]" "la_oenb[1]" 46.7738
+cap "la_oenb[51]" "la_data_out[51]" 46.7738
+cap "la_data_out[8]" "la_oenb[8]" 46.7738
+cap "wbs_adr_i[6]" "wbs_dat_o[5]" 46.7738
+cap "wbs_ack_o" "wb_rst_i" 46.7738
+cap "la_data_out[16]" "la_data_in[16]" 46.7738
+cap "la_data_in[92]" "la_oenb[91]" 46.7738
+cap "la_data_in[53]" "la_data_out[53]" 46.7738
+cap "wbs_dat_i[13]" "wbs_dat_o[13]" 46.7738
+cap "io_analog[6]" "io_analog[6]" 21353.1
+cap "la_data_out[110]" "la_data_in[110]" 46.7738
+cap "la_data_in[55]" "la_oenb[54]" 46.7738
+cap "io_in[11]" "io_out[11]" 67.2299
+cap "la_data_in[76]" "la_data_out[76]" 46.7738
+cap "la_oenb[14]" "la_data_out[14]" 46.7738
+cap "la_data_out[36]" "la_oenb[36]" 46.7738
+cap "la_oenb[6]" "la_data_in[7]" 46.7738
+cap "CTRL2" "CTRL3" 76281.3
+cap "CTRL2" "gpio_noesd[8]" 67.6804
+cap "la_data_out[48]" "la_oenb[48]" 46.7738
+cap "io_in[5]" "io_in_3v3[5]" 67.2299
+cap "io_in[20]" "io_out[20]" 67.2299
+cap "la_data_out[100]" "la_data_in[100]" 46.7738
+cap "wbs_adr_i[28]" "wbs_dat_o[27]" 46.7738
+cap "io_in[6]" "io_in_3v3[6]" 67.2299
+cap "la_data_out[102]" "la_data_in[102]" 46.7738
+cap "la_oenb[72]" "la_data_out[72]" 46.7738
+cap "wbs_adr_i[2]" "wbs_sel_i[1]" 46.7738
+cap "io_analog[5]" "io_analog[5]" 26259.4
+cap "la_data_in[58]" "la_data_out[58]" 46.7738
+cap "wbs_dat_i[16]" "wbs_dat_o[16]" 46.7738
+cap "io_oeb[13]" "io_out[13]" 67.2299
+cap "VCCD" "GND" 16651.9
+cap "la_oenb[94]" "la_data_in[95]" 46.7738
+cap "wbs_dat_i[23]" "wbs_dat_o[23]" 46.7738
+cap "wbs_dat_i[8]" "wbs_adr_i[8]" 46.7738
+cap "io_out[24]" "io_in[24]" 67.2299
+cap "la_data_in[29]" "la_oenb[28]" 46.7738
+cap "wbs_adr_i[5]" "wbs_dat_i[5]" 46.7738
+cap "la_data_out[19]" "la_oenb[19]" 46.7738
+cap "io_in[3]" "io_in_3v3[3]" 67.2299
+cap "la_oenb[74]" "la_data_in[75]" 46.7738
+cap "la_oenb[23]" "la_data_out[23]" 46.7738
+cap "wbs_dat_o[28]" "wbs_adr_i[29]" 46.7738
+cap "CTRL1" "io_in_3v3[14]" 67.7254
+cap "la_oenb[43]" "la_data_out[43]" 46.7738
+cap "wbs_dat_i[4]" "wbs_adr_i[4]" 46.7738
+cap "user_clock2" "la_oenb[127]" 46.7738
+cap "gpio_noesd[13]" "gpio_analog[13]" 67.2299
+cap "la_oenb[121]" "la_data_in[122]" 46.7738
+cap "la_data_in[9]" "la_oenb[8]" 46.7738
+cap "la_oenb[87]" "la_data_in[88]" 46.7738
+cap "la_data_in[60]" "la_oenb[59]" 46.7738
+cap "la_oenb[52]" "la_data_in[53]" 46.7738
+cap "wbs_dat_i[1]" "wbs_dat_o[1]" 46.7738
+cap "wbs_dat_o[22]" "wbs_dat_i[22]" 46.7738
+cap "gpio_noesd[15]" "gpio_analog[15]" 67.2299
+cap "la_oenb[122]" "la_data_in[123]" 46.7738
+cap "la_oenb[16]" "la_data_out[16]" 46.7738
+cap "la_oenb[126]" "la_data_in[127]" 46.7738
+cap "la_oenb[116]" "la_data_out[116]" 46.7738
+cap "la_data_in[114]" "la_data_out[114]" 46.7738
+cap "la_oenb[90]" "la_data_in[91]" 46.7738
+cap "io_analog[5]" "io_analog[5]" 26259.4
+cap "gpio_noesd[0]" "io_in_3v3[7]" 67.2299
+cap "wbs_dat_i[29]" "wbs_adr_i[29]" 46.7738
+cap "io_in[3]" "io_out[3]" 67.2299
+cap "io_clamp_low[0]" "io_clamp_high[0]" 468.333
+cap "la_data_in[118]" "la_data_out[118]" 46.7738
+cap "la_oenb[98]" "la_data_in[99]" 46.7738
+cap "wbs_adr_i[31]" "wbs_dat_i[31]" 46.7738
+cap "wbs_dat_o[10]" "wbs_adr_i[11]" 46.7738
+cap "la_data_out[124]" "la_oenb[124]" 46.7738
+cap "la_data_in[119]" "la_oenb[118]" 46.7738
+cap "io_out[0]" "io_oeb[0]" 67.2299
+cap "io_out[17]" "CTRL4" 67.3018
+cap "io_in[11]" "io_in_3v3[11]" 67.2299
+cap "la_oenb[37]" "la_data_in[38]" 46.7738
+cap "la_oenb[11]" "la_data_in[12]" 46.7738
+cap "la_data_out[32]" "la_oenb[32]" 46.7738
+cap "la_data_out[120]" "la_data_in[120]" 46.7738
+cap "la_oenb[75]" "la_data_in[76]" 46.7738
+cap "la_data_in[69]" "la_oenb[68]" 46.7738
+cap "la_data_in[59]" "la_oenb[58]" 46.7738
+cap "la_data_out[49]" "la_oenb[49]" 46.7738
+cap "la_data_out[48]" "la_data_in[48]" 46.7738
+cap "la_data_out[20]" "la_data_in[20]" 46.7738
+cap "io_in[10]" "io_in_3v3[10]" 67.2299
+cap "la_oenb[29]" "la_data_out[29]" 46.7738
+cap "io_oeb[25]" "io_in_3v3[26]" 67.2299
+cap "la_data_out[119]" "la_data_in[119]" 46.7738
+cap "la_oenb[68]" "la_data_out[68]" 46.7738
+cap "la_data_out[52]" "la_oenb[52]" 46.7738
+cap "la_data_out[18]" "la_oenb[18]" 46.7738
+cap "wbs_dat_i[15]" "wbs_dat_o[15]" 46.7738
+cap "io_out[9]" "io_oeb[9]" 67.2299
+cap "la_oenb[90]" "la_data_out[90]" 46.7738
+cap "la_data_in[23]" "la_data_out[23]" 46.7738
+cap "la_data_in[20]" "la_oenb[19]" 46.7738
+cap "wbs_dat_i[9]" "wbs_adr_i[9]" 46.7738
+cap "GND" "CTRL3" 425.435
+cap "io_out[18]" "CTRL5" 67.6322
+cap "la_oenb[70]" "la_data_in[71]" 46.7738
+cap "la_oenb[25]" "la_data_in[26]" 46.7738
+cap "wbs_dat_i[29]" "wbs_dat_o[29]" 46.7738
+cap "wbs_adr_i[6]" "wbs_dat_i[6]" 46.7738
+cap "CTRL2" "CTRL4" 20205.1
+cap "gpio_noesd[10]" "gpio_analog[10]" 67.2299
+cap "io_analog[5]" "io_clamp_low[1]" 468.333
+cap "la_oenb[4]" "la_data_out[4]" 46.7738
+cap "la_data_in[66]" "la_data_out[66]" 46.7738
+cap "la_data_in[19]" "la_data_out[19]" 46.7738
+cap "io_analog[5]" "io_analog[5]" 21353.1
+cap "io_oeb[22]" "io_out[22]" 67.2299
+cap "la_oenb[117]" "la_data_in[118]" 46.7738
+cap "la_data_out[86]" "la_data_in[86]" 46.7738
+cap "la_data_in[97]" "la_oenb[96]" 46.7738
+cap "la_data_out[62]" "la_oenb[62]" 46.7738
+cap "wbs_adr_i[9]" "wbs_dat_o[8]" 46.7738
+cap "la_data_in[117]" "la_oenb[116]" 46.7738
+cap "la_oenb[111]" "la_data_in[112]" 46.7738
+cap "la_data_out[81]" "la_data_in[81]" 46.7738
+cap "la_data_in[47]" "la_oenb[46]" 46.7738
+cap "io_oeb[5]" "io_out[5]" 67.2299
+cap "gpio_noesd[3]" "io_in_3v3[10]" 67.2299
+cap "io_in_3v3[25]" "io_oeb[24]" 67.2299
+cap "la_data_in[117]" "la_data_out[117]" 46.7738
+cap "la_data_out[76]" "la_oenb[76]" 46.7738
+cap "wbs_adr_i[3]" "wbs_sel_i[2]" 46.7738
+cap "io_clamp_high[2]" "io_analog[6]" 468.333
+cap "la_data_in[78]" "la_oenb[77]" 46.7738
+cap "la_data_in[18]" "la_data_out[18]" 46.7738
+cap "la_data_out[17]" "la_data_in[17]" 46.7738
+cap "la_data_out[12]" "la_oenb[12]" 46.7738
+cap "la_data_in[104]" "la_oenb[103]" 46.7738
+cap "la_oenb[36]" "la_data_in[37]" 46.7738
+cap "la_oenb[31]" "la_data_in[32]" 46.7738
+cap "la_data_out[21]" "la_data_in[21]" 46.7738
+cap "io_in[22]" "io_out[22]" 67.2299
+cap "la_data_in[106]" "la_oenb[105]" 46.7738
+cap "la_oenb[69]" "la_data_out[69]" 46.7738
+cap "la_oenb[66]" "la_data_out[66]" 46.7738
+cap "la_data_in[125]" "la_data_out[125]" 46.7738
+cap "la_oenb[51]" "la_data_in[52]" 46.7738
+cap "wbs_dat_i[11]" "wbs_adr_i[11]" 46.7738
+cap "io_in[1]" "io_out[1]" 67.2299
+cap "gpio_noesd[7]" "io_in_3v3[14]" 67.2299
+cap "la_data_in[82]" "la_data_out[82]" 46.7738
+cap "la_oenb[64]" "la_data_in[65]" 46.7738
+cap "la_data_in[31]" "la_data_out[31]" 46.7738
+cap "gpio_noesd[3]" "gpio_analog[3]" 67.2299
+cap "la_oenb[15]" "la_data_out[15]" 46.7738
+cap "wbs_stb_i" "wbs_we_i" 46.7738
+cap "la_oenb[26]" "la_data_in[27]" 46.7738
+cap "io_in[0]" "io_in_3v3[0]" 67.2299
+cap "user_irq[1]" "user_irq[0]" 46.7738
+cap "la_data_in[99]" "la_data_out[99]" 46.7738
+cap "la_data_out[62]" "la_data_in[62]" 46.7738
+cap "wbs_adr_i[17]" "wbs_dat_i[17]" 46.7738
+cap "CTRL1" "CTRL3" 16706.3
+cap "gpio_noesd[1]" "io_in_3v3[8]" 67.2299
+cap "la_data_out[15]" "la_data_in[15]" 46.7738
+cap "io_in[6]" "io_out[6]" 67.2299
+cap "la_oenb[95]" "la_data_out[95]" 46.7738
+cap "wbs_sel_i[2]" "wbs_dat_o[2]" 46.7738
+cap "gpio_analog[6]" "gpio_noesd[6]" 67.2299
+cap "io_in_3v3[16]" "CTRL3" 67.3993
+cap "la_data_in[108]" "la_data_out[108]" 46.7738
+cap "la_oenb[2]" "la_data_in[3]" 46.7738
+cap "io_out[6]" "io_oeb[6]" 67.2299
+cap "la_data_in[56]" "la_oenb[55]" 46.7738
+cap "la_data_in[109]" "la_oenb[108]" 46.7738
+cap "la_data_in[89]" "la_data_out[89]" 46.7738
+cap "la_oenb[20]" "la_data_out[20]" 46.7738
+cap "wbs_dat_i[16]" "wbs_adr_i[16]" 46.7738
+cap "la_data_out[115]" "la_data_in[115]" 46.7738
+cap "la_oenb[45]" "la_data_in[46]" 46.7738
+cap "la_oenb[16]" "la_data_in[17]" 46.7738
+cap "la_data_out[10]" "la_data_in[10]" 46.7738
+cap "gpio_noesd[12]" "gpio_analog[12]" 67.2299
+cap "wbs_dat_o[22]" "wbs_adr_i[23]" 46.7738
+cap "wbs_dat_i[9]" "wbs_dat_o[9]" 46.7738
+cap "GND" "CTRL4" 487.012
+cap "wbs_dat_o[3]" "wbs_dat_i[3]" 46.7738
+cap "wbs_dat_o[1]" "wbs_sel_i[1]" 46.7738
+cap "la_data_in[114]" "la_oenb[113]" 46.7738
+cap "la_data_in[37]" "la_data_out[37]" 46.7738
+cap "io_analog[4]" "io_analog[4]" 26259.4
+cap "io_analog[4]" "io_clamp_high[0]" 468.333
+cap "la_data_out[59]" "la_oenb[59]" 46.7738
+cap "la_data_out[13]" "la_data_in[13]" 46.7738
+cap "wbs_dat_i[30]" "wbs_adr_i[30]" 46.7738
+cap "wbs_adr_i[1]" "wbs_sel_i[0]" 46.7738
+cap "io_analog[6]" "io_analog[6]" 26259.4
+cap "io_in[15]" "io_out[15]" 67.2299
+cap "io_out[14]" "io_oeb[14]" 67.2299
+cap "la_data_in[7]" "la_data_out[7]" 46.7738
+cap "la_data_in[109]" "la_data_out[109]" 46.7738
+cap "io_out[19]" "io_in[19]" 67.2299
+cap "io_in[8]" "io_out[8]" 67.2299
+cap "la_oenb[106]" "la_data_in[107]" 46.7738
+cap "la_oenb[88]" "la_data_out[88]" 46.7738
+cap "la_data_in[22]" "la_oenb[21]" 46.7738
+cap "io_out[23]" "io_in[23]" 67.2299
+cap "la_data_out[85]" "la_data_in[85]" 46.7738
+cap "la_data_out[38]" "la_data_in[38]" 46.7738
+cap "gpio_noesd[2]" "io_in_3v3[9]" 67.2299
+cap "la_oenb[23]" "la_data_in[24]" 46.7738
+cap "la_data_in[97]" "la_data_out[97]" 46.7738
+cap "la_data_in[74]" "la_data_out[74]" 46.7738
+cap "la_oenb[41]" "la_data_in[42]" 46.7738
+cap "la_data_in[35]" "la_data_out[35]" 46.7738
+cap "wbs_dat_i[25]" "wbs_dat_o[25]" 46.7738
+cap "la_data_in[80]" "la_data_out[80]" 46.7738
+cap "la_data_in[49]" "la_oenb[48]" 46.7738
+cap "la_oenb[12]" "la_data_in[13]" 46.7738
+cap "la_data_out[11]" "la_oenb[11]" 46.7738
+cap "gpio_noesd[4]" "io_in_3v3[11]" 67.2299
+cap "la_data_out[122]" "la_data_in[122]" 46.7738
+cap "la_oenb[113]" "la_data_out[113]" 46.7738
+cap "la_data_out[92]" "la_oenb[92]" 46.7738
+cap "la_data_out[79]" "la_data_in[79]" 46.7738
+cap "la_oenb[38]" "la_data_out[38]" 46.7738
+cap "wbs_stb_i" "wbs_cyc_i" 46.7738
+cap "io_in[10]" "io_out[10]" 67.2299
+cap "la_oenb[122]" "la_data_out[122]" 46.7738
+cap "la_oenb[61]" "la_data_in[62]" 46.7738
+cap "la_data_out[10]" "la_oenb[10]" 46.7738
+cap "io_in_3v3[18]" "gpio_noesd[11]" 67.2299
+cap "la_data_in[116]" "la_data_out[116]" 46.7738
+cap "la_data_out[101]" "la_data_in[101]" 46.7738
+cap "la_data_out[88]" "la_data_in[88]" 46.7738
+cap "la_data_out[27]" "la_oenb[27]" 46.7738
+cap "la_oenb[22]" "la_data_out[22]" 46.7738
+cap "la_data_out[127]" "la_data_in[127]" 46.7738
+cap "la_oenb[67]" "la_data_in[68]" 46.7738
+cap "la_data_out[36]" "la_data_in[36]" 46.7738
+cap "la_data_in[126]" "la_data_out[126]" 46.7738
+cap "la_data_out[96]" "la_oenb[96]" 46.7738
+cap "la_data_in[29]" "la_data_out[29]" 46.7738
+cap "wbs_dat_i[30]" "wbs_dat_o[30]" 46.7738
+cap "CTRL1" "CTRL4" 9477.69
+cap "la_oenb[104]" "la_data_in[105]" 46.7738
+cap "wbs_adr_i[20]" "wbs_dat_o[19]" 46.7738
+cap "la_oenb[104]" "la_data_out[104]" 46.7738
+cap "la_data_in[81]" "la_oenb[80]" 46.7738
+cap "la_data_out[11]" "la_data_in[11]" 46.7738
+cap "wbs_dat_i[18]" "wbs_adr_i[18]" 46.7738
+cap "wbs_dat_o[0]" "wbs_sel_i[0]" 46.7738
+cap "la_data_in[94]" "la_oenb[93]" 46.7738
+cap "la_data_out[73]" "la_data_in[73]" 46.7738
+cap "la_data_out[39]" "la_oenb[39]" 46.7738
+cap "la_data_in[24]" "la_data_out[24]" 46.7738
+cap "la_data_in[14]" "la_oenb[13]" 46.7738
+cap "gpio_noesd[17]" "io_in_3v3[24]" 67.2299
+cap "la_data_in[77]" "la_oenb[76]" 46.7738
+cap "la_oenb[38]" "la_data_in[39]" 46.7738
+cap "io_in[20]" "io_in_3v3[20]" 67.2299
+cap "io_in[9]" "io_out[9]" 67.2299
+cap "la_data_out[57]" "la_oenb[57]" 46.7738
+cap "la_data_out[33]" "la_oenb[33]" 46.7738
+cap "la_data_out[30]" "la_oenb[30]" 46.7738
+cap "la_oenb[14]" "la_data_in[15]" 46.7738
+cap "wbs_dat_o[25]" "wbs_adr_i[26]" 46.7738
+cap "la_data_in[90]" "la_data_out[90]" 46.7738
+cap "wbs_dat_i[8]" "wbs_dat_o[8]" 46.7738
+cap "CTRL5" "CTRL3" 24871.1
+cap "io_out[16]" "io_oeb[16]" 67.2299
+cap "la_data_in[104]" "la_data_out[104]" 46.7738
+cap "la_oenb[85]" "la_data_in[86]" 46.7738
+cap "la_data_in[56]" "la_data_out[56]" 46.7738
+cap "la_oenb[31]" "la_data_out[31]" 46.7738
+cap "la_data_out[14]" "la_data_in[14]" 46.7738
+cap "la_data_out[63]" "la_oenb[63]" 46.7738
+cap "la_oenb[60]" "la_data_out[60]" 46.7738
+cap "la_oenb[10]" "la_data_in[11]" 46.7738
+cap "la_oenb[102]" "la_data_in[103]" 46.7738
+cap "la_data_out[28]" "la_oenb[28]" 46.7738
+cap "wbs_dat_i[18]" "wbs_dat_o[18]" 46.7738
+cap "la_data_in[32]" "la_data_out[32]" 46.7738
+cap "wbs_sel_i[3]" "wbs_adr_i[4]" 46.7738
+cap "io_oeb[23]" "io_out[23]" 67.2299
+cap "la_oenb[123]" "la_data_out[123]" 46.7738
+cap "la_oenb[103]" "la_data_out[103]" 46.7738
+cap "la_data_out[96]" "la_data_in[96]" 46.7738
+cap "la_data_in[72]" "la_data_out[72]" 46.7738
+cap "la_data_in[93]" "la_oenb[92]" 46.7738
+cap "la_data_out[8]" "la_data_in[8]" 46.7738
+cap "wbs_dat_i[31]" "wbs_dat_o[31]" 46.7738
+cap "la_data_out[65]" "la_data_in[65]" 46.7738
+cap "la_oenb[47]" "la_data_out[47]" 46.7738
+cap "wbs_dat_o[28]" "wbs_dat_i[28]" 46.7738
+cap "wbs_adr_i[20]" "wbs_dat_i[20]" 46.7738
+cap "wbs_dat_i[12]" "wbs_adr_i[12]" 46.7738
+cap "la_data_in[50]" "la_data_out[50]" 46.7738
+cap "user_clock2" "user_irq[0]" 46.7738
+cap "wbs_adr_i[14]" "wbs_dat_o[13]" 46.7738
+cap "io_oeb[1]" "io_out[1]" 67.2299
+cap "la_oenb[123]" "la_data_in[124]" 46.7738
+cap "la_data_out[27]" "la_data_in[27]" 46.7738
+cap "gpio_noesd[8]" "gpio_analog[8]" 67.2299
+cap "la_oenb[108]" "la_data_out[108]" 46.7738
+cap "la_oenb[105]" "la_data_out[105]" 46.7738
+cap "la_oenb[119]" "la_data_out[119]" 46.7738
+cap "la_data_out[49]" "la_data_in[49]" 46.7738
+cap "wbs_adr_i[30]" "wbs_dat_o[29]" 46.7738
+cap "wbs_dat_i[20]" "wbs_dat_o[20]" 46.7738
+cap "CTRL2" "GND" 343.549
+cap "io_out[14]" "CTRL1" 67.495
+cap "la_data_out[40]" "la_oenb[40]" 46.7738
+cap "wbs_dat_i[5]" "wbs_dat_o[5]" 46.7738
+cap "la_data_out[106]" "la_oenb[106]" 46.7738
+cap "la_data_in[89]" "la_oenb[88]" 46.7738
+cap "la_oenb[53]" "la_data_out[53]" 46.7738
+cap "la_data_out[3]" "la_data_in[3]" 46.7738
+cap "la_data_in[80]" "la_oenb[79]" 46.7738
+cap "la_oenb[64]" "la_data_out[64]" 46.7738
+cap "la_data_in[0]" "wbs_dat_o[31]" 46.7738
+cap "wbs_dat_o[0]" "wbs_dat_i[0]" 46.7738
+cap "la_oenb[117]" "la_data_out[117]" 46.7738
+cap "la_oenb[42]" "la_data_out[42]" 46.7738
+cap "wbs_adr_i[12]" "wbs_dat_o[11]" 46.7738
+cap "gpio_noesd[4]" "gpio_analog[4]" 67.2299
+cap "la_oenb[101]" "la_data_in[102]" 46.7738
+cap "la_oenb[85]" "la_data_out[85]" 46.7738
+cap "la_data_in[83]" "la_oenb[82]" 46.7738
+cap "la_data_in[25]" "la_oenb[24]" 46.7738
+cap "wbs_adr_i[3]" "wbs_dat_i[3]" 46.7738
+cap "gpio_noesd[10]" "io_in_3v3[17]" 67.2299
+cap "la_oenb[100]" "la_data_out[100]" 46.7738
+cap "la_data_in[63]" "la_oenb[62]" 46.7738
+cap "la_oenb[9]" "la_data_in[10]" 46.7738
+cap "wbs_adr_i[27]" "wbs_dat_o[26]" 46.7738
+cap "la_oenb[95]" "la_data_in[96]" 46.7738
+cap "la_oenb[44]" "la_data_out[44]" 46.7738
+cap "wbs_dat_o[16]" "wbs_adr_i[17]" 46.7738
+cap "io_in[0]" "io_out[0]" 67.2299
+cap "la_data_in[108]" "la_oenb[107]" 46.7738
+cap "la_oenb[78]" "la_data_out[78]" 46.7738
+cap "io_out[16]" "CTRL3" 67.4747
+cap "io_oeb[15]" "io_out[15]" 67.2299
+cap "la_data_in[18]" "la_oenb[17]" 46.7738
+cap "io_in_3v3[21]" "gpio_noesd[14]" 67.2299
+cap "la_data_out[118]" "la_oenb[118]" 46.7738
+cap "la_oenb[58]" "la_data_out[58]" 46.7738
+cap "wb_rst_i" "wb_clk_i" 46.7738
+cap "io_in[13]" "io_out[13]" 67.2299
+cap "user_irq[2]" "user_irq[1]" 46.7738
+cap "la_oenb[9]" "la_data_out[9]" 46.7738
+cap "wbs_dat_i[15]" "wbs_adr_i[15]" 46.7738
+cap "la_oenb[37]" "la_data_out[37]" 46.7738
+cap "CTRL5" "CTRL4" 111027
+cap "gpio_analog[16]" "gpio_noesd[16]" 67.2299
+cap "io_in_3v3[18]" "CTRL5" 67.5861
+cap "la_data_in[74]" "la_oenb[73]" 46.7738
+cap "io_analog[4]" "io_analog[4]" 21353.1
+cap "io_in_3v3[25]" "io_in[25]" 67.2299
+cap "io_analog[6]" "io_clamp_low[2]" 468.333
+cap "la_data_out[57]" "la_data_in[57]" 46.7738
+cap "la_data_out[55]" "la_oenb[55]" 46.7738
+cap "la_oenb[2]" "la_data_out[2]" 46.7738
+cap "wbs_dat_o[7]" "wbs_adr_i[8]" 46.7738
+cap "io_in_3v3[19]" "io_in[19]" 67.2299
+cap "la_data_out[83]" "la_data_in[83]" 46.7738
+cap "la_data_in[121]" "la_data_out[121]" 46.7738
+cap "la_data_in[54]" "la_data_out[54]" 46.7738
+cap "la_data_in[47]" "la_data_out[47]" 46.7738
+cap "io_out[20]" "io_oeb[20]" 67.2299
+cap "la_data_in[41]" "la_data_out[41]" 46.7738
+cap "la_data_in[113]" "la_data_out[113]" 46.7738
+cap "la_data_out[75]" "la_data_in[75]" 46.7738
+cap "la_data_in[51]" "la_oenb[50]" 46.7738
+cap "la_oenb[35]" "la_data_out[35]" 46.7738
+cap "io_analog[4]" "io_analog[4]" 21353.1
+cap "la_data_out[84]" "la_data_in[84]" 46.7738
+cap "wbs_adr_i[1]" "wbs_dat_i[1]" 46.7738
+cap "CTRL2" "CTRL1" 49772.1
+cap "io_in_3v3[8]" "io_in[8]" 67.2299
+cap "la_data_in[113]" "la_oenb[112]" 46.7738
+cap "la_data_in[90]" "la_oenb[89]" 46.7738
+cap "la_data_in[84]" "la_oenb[83]" 46.7738
+cap "la_oenb[67]" "la_data_out[67]" 46.7738
+cap "la_data_out[3]" "la_oenb[3]" 46.7738
+cap "la_data_out[26]" "la_data_in[26]" 46.7738
+cap "la_data_in[55]" "la_data_out[55]" 46.7738
+cap "la_data_out[13]" "la_oenb[13]" 46.7738
+cap "wbs_dat_i[2]" "wbs_adr_i[2]" 46.7738
+cap "wbs_adr_i[0]" "wbs_we_i" 46.7738
+cap "la_oenb[24]" "la_data_out[24]" 46.7738
+cap "wbs_dat_o[14]" "wbs_adr_i[15]" 46.7738
+cap "io_oeb[4]" "io_out[4]" 67.2299
+cap "la_data_in[72]" "la_oenb[71]" 46.7738
+cap "wbs_dat_o[26]" "wbs_dat_i[26]" 46.7738
+cap "wbs_dat_i[25]" "wbs_adr_i[25]" 46.7738
+cap "wbs_adr_i[21]" "wbs_dat_i[21]" 46.7738
+cap "gpio_analog[0]" "gpio_noesd[0]" 67.2299
+cap "la_data_out[84]" "la_oenb[84]" 46.7738
+cap "la_oenb[22]" "la_data_in[23]" 46.7738
+cap "wbs_dat_o[24]" "wbs_dat_i[24]" 46.7738
+cap "io_analog[5]" "io_analog[5]" 21353.1
+cap "la_data_in[60]" "la_data_out[60]" 46.7738
+cap "wbs_dat_i[27]" "wbs_adr_i[27]" 46.7738
+cap "wbs_adr_i[10]" "wbs_dat_o[9]" 46.7738
+cap "la_data_in[85]" "la_oenb[84]" 46.7738
+cap "wbs_adr_i[0]" "wbs_dat_i[0]" 46.7738
+cap "io_in_3v3[21]" "io_in[21]" 67.2299
+cap "la_data_in[16]" "la_oenb[15]" 46.7738
+cap "io_in_3v3[12]" "io_in[12]" 67.2299
+cap "la_data_out[77]" "la_data_in[77]" 46.7738
+cap "gpio_noesd[5]" "gpio_analog[5]" 67.2299
+cap "la_data_in[30]" "la_oenb[29]" 46.7738
+cap "wbs_dat_i[10]" "wbs_dat_o[10]" 46.7738
+cap "io_in[26]" "io_in_3v3[26]" 67.2299
+cap "gpio_analog[11]" "gpio_noesd[11]" 67.2299
+cap "io_in[4]" "io_in_3v3[4]" 67.2299
+cap "la_data_in[67]" "la_oenb[66]" 46.7738
+cap "la_data_in[64]" "la_data_out[64]" 46.7738
+cap "la_data_in[61]" "la_data_out[61]" 46.7738
+cap "wbs_dat_i[27]" "wbs_dat_o[27]" 46.7738
+cap "wbs_dat_i[19]" "wbs_adr_i[19]" 46.7738
+cap "io_in_3v3[9]" "io_in[9]" 67.2299
+cap "la_data_in[126]" "la_oenb[125]" 46.7738
+cap "la_data_in[121]" "la_oenb[120]" 46.7738
+cap "la_data_out[71]" "la_oenb[71]" 46.7738
+cap "wbs_dat_i[12]" "wbs_dat_o[12]" 46.7738
+cap "wbs_dat_o[4]" "wbs_dat_i[4]" 46.7738
+cap "io_in_3v3[23]" "io_in[23]" 67.2299
+cap "la_oenb[26]" "la_data_out[26]" 46.7738
+cap "wbs_adr_i[13]" "wbs_dat_o[12]" 46.7738
+cap "io_oeb[1]" "io_in_3v3[2]" 67.2299
+cap "la_data_in[111]" "la_data_out[111]" 46.7738
+cap "la_data_in[94]" "la_data_out[94]" 46.7738
+cap "la_data_in[51]" "la_data_out[51]" 46.7738
+cap "io_out[24]" "io_oeb[24]" 67.2299
+cap "io_clamp_low[2]" "io_clamp_high[2]" 468.333
+cap "la_data_out[21]" "la_oenb[21]" 46.7738
+cap "wbs_dat_o[11]" "wbs_dat_i[11]" 46.7738
+cap "io_in_3v3[13]" "io_in[13]" 67.2299
+cap "la_data_out[68]" "la_data_in[68]" 46.7738
+cap "la_data_in[21]" "la_oenb[20]" 46.7738
+cap "wbs_adr_i[24]" "wbs_dat_i[24]" 46.7738
+cap "wbs_dat_i[23]" "wbs_adr_i[23]" 46.7738
+cap "io_out[2]" "io_in[2]" 67.2299
+cap "la_oenb[70]" "la_data_out[70]" 46.7738
+cap "la_data_in[9]" "la_data_out[9]" 46.7738
+cap "la_oenb[5]" "la_data_out[5]" 46.7738
+cap "la_data_in[4]" "la_data_out[4]" 46.7738
+cap "la_data_out[0]" "la_oenb[0]" 46.7738
+cap "io_in_3v3[1]" "io_oeb[0]" 67.2299
+cap "gpio_noesd[13]" "io_in_3v3[20]" 67.2299
+cap "la_data_out[79]" "la_oenb[79]" 46.7738
+cap "la_data_out[45]" "la_data_in[45]" 46.7738
+cap "GND" "CTRL1" 691.721
+cap "io_in_3v3[4]" "io_oeb[3]" 67.2299
+cap "la_oenb[80]" "la_data_out[80]" 46.7738
+cap "wbs_dat_i[19]" "wbs_dat_o[19]" 46.7738
+cap "la_oenb[50]" "la_data_out[50]" 46.7738
+cap "la_data_in[46]" "la_data_out[46]" 46.7738
+cap "la_oenb[35]" "la_data_in[36]" 46.7738
+cap "la_data_in[112]" "la_data_out[112]" 46.7738
+cap "la_data_in[78]" "la_data_out[78]" 46.7738
+cap "la_data_out[71]" "la_data_in[71]" 46.7738
+cap "la_data_in[124]" "la_data_out[124]" 46.7738
+cap "io_in_3v3[17]" "CTRL4" 67.4359
+cap "la_oenb[47]" "la_data_in[48]" 46.7738
+cap "io_oeb[25]" "io_out[25]" 67.2299
+cap "la_oenb[81]" "la_data_in[82]" 46.7738
+cap "la_data_in[45]" "la_oenb[44]" 46.7738
+cap "la_data_out[82]" "la_oenb[82]" 46.7738
+cap "la_data_out[56]" "la_oenb[56]" 46.7738
+cap "CTRL2" "CTRL5" 12493.6
+cap "VCCD" "REF" 4239.12
+cap "io_out[26]" "io_in[26]" 67.2299
+cap "io_in_3v3[16]" "gpio_noesd[9]" 67.2299
+cap "la_oenb[99]" "la_data_out[99]" 46.7738
+cap "la_data_out[83]" "la_oenb[83]" 46.7738
+cap "la_data_out[63]" "la_data_in[63]" 46.7738
+cap "wbs_adr_i[18]" "wbs_dat_o[17]" 46.7738
+cap "la_data_out[106]" "la_data_in[106]" 46.7738
+cap "la_data_out[25]" "la_data_in[25]" 46.7738
+cap "wbs_ack_o" "wbs_cyc_i" 46.7738
+cap "la_data_out[127]" "la_oenb[127]" 46.7738
+cap "la_data_in[44]" "la_data_out[44]" 46.7738
+cap "la_oenb[119]" "la_data_in[120]" 46.7738
+cap "la_data_in[98]" "la_oenb[97]" 46.7738
+cap "io_clamp_high[1]" "io_clamp_low[1]" 468.333
+cap "la_data_out[120]" "la_oenb[120]" 46.7738
+cap "la_data_out[115]" "la_oenb[115]" 46.7738
+cap "la_data_out[25]" "la_oenb[25]" 46.7738
+cap "la_data_out[123]" "la_data_in[123]" 46.7738
+cap "la_data_out[52]" "la_data_in[52]" 46.7738
+cap "io_clamp_low[0]" "io_analog[4]" 468.333
+cap "la_data_in[5]" "la_data_out[5]" 46.7738
+cap "wbs_dat_i[26]" "wbs_adr_i[26]" 46.7738
+cap "la_oenb[69]" "la_data_in[70]" 46.7738
+cap "wbs_dat_o[4]" "wbs_adr_i[5]" 46.7738
+cap "wbs_dat_i[2]" "wbs_dat_o[2]" 46.7738
+cap "io_in_3v3[22]" "io_in[22]" 67.2299
+cap "wbs_dat_o[21]" "wbs_adr_i[22]" 46.7738
+cap "io_in_3v3[12]" "gpio_noesd[5]" 67.2299
+cap "la_data_in[107]" "la_data_out[107]" 46.7738
+cap "la_data_out[98]" "la_data_in[98]" 46.7738
+cap "la_data_out[89]" "la_oenb[89]" 46.7738
+cap "la_data_in[61]" "la_oenb[60]" 46.7738
+cap "wbs_dat_o[17]" "wbs_dat_i[17]" 46.7738
+cap "wbs_dat_i[6]" "wbs_dat_o[6]" 46.7738
+cap "io_in_3v3[22]" "gpio_noesd[15]" 67.2299
+cap "CTRL2" "io_in[15]" 67.4709
+cap "io_oeb[17]" "io_out[17]" 67.2299
+cap "la_oenb[99]" "la_data_in[100]" 46.7738
+cap "la_data_out[65]" "la_oenb[65]" 46.7738
+cap "la_data_out[33]" "la_data_in[33]" 46.7738
+cap "la_oenb[114]" "la_data_out[114]" 46.7738
+cap "io_in_3v3[7]" "io_in[7]" 67.2299
+cap "la_data_out[73]" "la_oenb[73]" 46.7738
+cap "wbs_dat_o[21]" "wbs_dat_i[21]" 46.7738
+cap "la_data_in[92]" "la_data_out[92]" 46.7738
+cap "la_data_in[73]" "la_oenb[72]" 46.7738
+cap "la_data_in[67]" "la_data_out[67]" 46.7738
+cap "io_out[11]" "io_oeb[11]" 67.2299
+cap "la_oenb[61]" "la_data_out[61]" 46.7738
+cap "la_data_in[40]" "la_oenb[39]" 46.7738
+cap "io_out[21]" "io_oeb[21]" 67.2299
+cap "la_oenb[18]" "la_data_in[19]" 46.7738
+cap "la_oenb[7]" "la_data_in[8]" 46.7738
+cap "io_analog[5]" "io_clamp_high[1]" 468.333
+cap "la_data_out[42]" "la_data_in[42]" 46.7738
+cap "io_in[7]" "io_out[7]" 67.2299
+cap "la_data_out[45]" "la_oenb[45]" 46.7738
+cap "la_oenb[6]" "la_data_out[6]" 46.7738
+cap "la_data_in[69]" "la_data_out[69]" 46.7738
+cap "la_oenb[107]" "la_data_out[107]" 46.7738
+cap "la_data_in[93]" "la_data_out[93]" 46.7738
+cap "la_data_in[91]" "la_data_out[91]" 46.7738
+cap "wbs_dat_i[22]" "wbs_adr_i[22]" 46.7738
+cap "io_analog[6]" "io_analog[6]" 21353.1
+cap "la_data_out[7]" "la_oenb[7]" 46.7738
+cap "la_oenb[5]" "la_data_in[6]" 46.7738
+cap "la_oenb[97]" "la_data_out[97]" 46.7738
+cap "la_data_out[93]" "la_oenb[93]" 46.7738
+cap "la_oenb[86]" "la_data_in[87]" 46.7738
+cap "CTRL4" "CTRL3" 67092.4
+cap "io_oeb[18]" "io_out[18]" 67.2299
+cap "io_oeb[10]" "io_out[10]" 67.2299
+cap "io_out[12]" "io_oeb[12]" 67.2299
+cap "gpio_analog[7]" "gpio_noesd[7]" 67.2299
+cap "la_data_out[103]" "la_data_in[103]" 46.7738
+cap "la_oenb[91]" "la_data_out[91]" 46.7738
+cap "la_oenb[87]" "la_data_out[87]" 46.7738
+cap "la_data_in[115]" "la_oenb[114]" 46.7738
+cap "wbs_dat_i[7]" "wbs_dat_o[7]" 46.7738
+cap "GND" "CTRL5" 892.254
+cap "la_data_in[125]" "la_oenb[124]" 46.7738
+cap "la_data_in[116]" "la_oenb[115]" 46.7738
+cap "la_data_in[34]" "la_data_out[34]" 46.7738
+cap "la_data_in[1]" "la_data_out[1]" 46.7738
+cap "gpio_noesd[9]" "gpio_analog[9]" 67.2299
+cap "io_analog[6]" "io_analog[6]" 26259.4
+cap "io_out[2]" "io_oeb[2]" 67.2299
+cap "io_out[21]" "io_in[21]" 67.2299
+cap "la_oenb[81]" "la_data_out[81]" 46.7738
+cap "gpio_noesd[1]" "gpio_analog[1]" 67.2299
+cap "wbs_dat_o[6]" "wbs_adr_i[7]" 46.7738
+cap "io_out[12]" "io_in[12]" 67.2299
+cap "la_oenb[94]" "la_data_out[94]" 46.7738
+cap "la_data_in[1]" "la_oenb[0]" 46.7738
+cap "VCO_0/X3/X6/XC2/m3_n2150_n3100#" "GND" 2.22118
+cap "GND" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 15.9549
+cap "VCO_0/X3/X6/XC2/m3_n2150_n3100#" "GND" 1.96667
+cap "VCCD" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" -28.7028
+cap "VCCD" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 262.547
+cap "VCO_0/X3/X3/VDD" "VCCD" 43.6855
+cap "VCO_0/X3/OUT270" "VCCD" 184.714
+cap "VCO_0/X3/X3/XR1/a_n703_n3602#" "VCCD" 13.9627
+cap "VCCD" "VCO_0/X3/X3/VDD" -56.7018
+cap "VCO_0/X3/X3/XR1/a_n703_n3602#" "VCCD" -370.984
+cap "VCO_0/X3/X2/VDD" "VCCD" -413.471
+cap "VCO_0/X3/X3/XR2/a_n703_n3602#" "VCCD" -47.9494
+cap "VCCD" "VCO_0/X3/X2/VDD" 78.1848
+cap "VCO_0/X3/X2/VDD" "VCCD" 0.196652
+cap "VCO_0/X3/X2/XR1/a_n703_n3602#" "VCO_0/X3/X2/VDD" 24.2986
+cap "VCO_0/CTRL4" "VCO_0/X9/GND" 16.1874
+cap "VCO_0/X9/ctrll3" "VCO_0/X9/GND" 12.6464
+cap "CTRL5" "VCO_0/X9/GND" 21.2992
+cap "VCO_0/X9/ctrll2" "VCO_0/X9/GND" 10.6496
+cap "VCO_0/X9/ctrll1" "VCO_0/X9/GND" 11.2262
+cap "VCO_0/X9/ctrll2" "VCO_0/X9/GND" 13.6957
+cap "CTRL5" "VCO_0/X9/GND" 76.7371
+cap "VCO_0/X9/GND" "VCO_0/CTRL4" 48.9109
+cap "VCO_0/X9/ctrll3" "VCO_0/X9/GND" 34.3709
+cap "VCO_0/X9/GND" "VCO_0/CTRL1" 11.2262
+cap "VCO_0/X9/GND" "VCO_0/CTRL3" 15.2434
+cap "VCO_0/X9/GND" "VCO_0/CTRL2" 13.6957
+cap "VCO_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 27.5642
+cap "VCO_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 80.1763
+cap "VCO_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" -171.196
+cap "VCO_0/X3/X6/XC2/m3_n2150_n3100#" "VCCD" 2.86192
+cap "VCCD" "VCO_0/X3/X6/IN" 1143.99
+cap "VCCD" "VCO_0/X3/X6/IN" 818.044
+cap "VCCD" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 44.0365
+cap "VCO_0/X3/OUT270" "VCCD" 819.326
+cap "VCO_0/X3/VDD" "VCCD" 105.995
+cap "VCO_0/X3/X3/VDD" "VCCD" 6.62753
+cap "VCO_0/X3/X3/XR1/a_n703_n3602#" "VCCD" -96.804
+cap "VCCD" "VCO_0/X3/X2/VDD" -293.512
+cap "VCCD" "VCO_0/X3/X3/XR2/a_n703_n3602#" 258.095
+cap "VCCD" "VCO_0/X3/X2/VDD" 239.193
+cap "VCCD" "VCO_0/GND" 4.28043
+cap "VCO_0/GND" "VCCD" 4.28043
+cap "VCO_0/X3/X2/VDD" "VCCD" 1.74752
+cap "VCO_0/X9/ctrll3" "VCO_0/X9/GND" 6.06355
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll1" -57.8744
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/XM1/a_n73_n100#" 4.88072
+cap "VCO_0/X9/GND" "VCO_0/X9/XM1/a_n73_n100#" 3.20199
+cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/GND" -424.729
+cap "VCO_0/X9/ctrll3" "VCO_0/X9/ctrll2" -0.710526
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll4" 7.76135
+cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll2" 2.61823
+cap "VCO_0/X9/ctrll5" "VCO_0/X9/XM1/a_n73_n100#" 5.85524
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll2" -46.6496
+cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll1" 3.99942
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll5" 10.2123
+cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll3" 22.2922
+cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll2" -2.68039
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll5" 132.708
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll4" 88.0701
+cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/X9/GND" 20.2705
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll1" 10.9173
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll2" 20.4991
+cap "VCO_0/X9/ctrll5" "VCO_0/X9/ctrll3" 75.3513
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll3" 71.2374
+cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/X9/ctrll3" 0.813521
+cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll5" 218.064
+cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll4" 55.7537
+cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll3" 38.6516
+cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll5" 125.679
+cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll3" 57.2105
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/XM2/a_15_n100#" 39.9886
+cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll2" 0.0672592
+cap "VCO_0/X9/ctrll1" "VCO_0/X9/XM2/a_15_n100#" 0.852687
+cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/X9/ctrll2" 6.46822
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll3" 61.7021
+cap "VCO_0/X9/GND" "VCO_0/X9/XM3/a_n33_n100#" 35.8368
+cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/X9/ctrll5" 147.97
+cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/X9/ctrll4" 37.9037
+cap "VCO_0/X9/GND" "VCO_0/X9/XM2/a_15_n100#" 39.6025
+cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll5" 82.2334
+cap "VCO_0/X9/ctrll1" "VCO_0/X9/ctrll4" 77.0876
+cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll5" 61.1752
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll2" 56.2738
+cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll4" 4.88072
+cap "VCO_0/X9/XM1/a_n73_n100#" "VCO_0/X9/ctrll5" 5.85524
+cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/X9/ctrll3" 26.3372
+cap "VCO_0/CTRL1" "VCO_0/CTRL4" -1.77636e-15
+cap "VCO_0/CTRL1" "VCO_0/CTRL3" 164.077
+cap "VCO_0/CTRL2" "VCO_0/X9/XM3/a_n33_n100#" 0.0672592
+cap "VCO_0/CTRL2" "VCO_0/X9/XM2/a_15_n100#" 8.0711
+cap "VCO_0/X9/GND" "VCO_0/CTRL3" 18.5716
+cap "VCO_0/CTRL2" "VCO_0/CTRL3" 87.9504
+cap "VCO_0/X9/XM3/a_n33_n100#" "VCO_0/CTRL3" 10.9015
+cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/CTRL3" 9.35904
+cap "VCO_0/X9/GND" "VCO_0/CTRL1" 2.99698
+cap "VCO_0/CTRL2" "VCO_0/CTRL1" 98.0572
+cap "VCO_0/X9/XM4/a_111_n100#" "VCO_0/CTRL3" 0.341206
+cap "VCO_0/X9/XM2/a_15_n100#" "VCO_0/CTRL1" 1.43344
+cap "VCO_0/CTRL2" "VCO_0/X9/GND" 9.66521
+cap "VCO_0/bias_calc_0/GND" "VCO_0/X3/X6/XC2/c1_n2050_n3000#" 13.9294
+cap "VCO_0/X3/X6/XC2/c1_n2050_n3000#" "VCO_0/GND" 40.5166
+cap "VCO_0/X3/X6/XC2/c1_n2050_n3000#" "VCO_0/GND" -86.5127
+cap "VCCD" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" -62.4405
+cap "VCO_0/X3/X6/IN" "VCCD" 1267.29
+cap "VCO_0/X3/BIAS" "VCCD" -28.0735
+cap "VCCD" "VCO_0/X3/BIAS" 28.4782
+cap "VCCD" "VCO_0/X3/X6/IN" 879.552
+cap "VCCD" "VCO_0/X3/X6/XC2/m3_n2150_n3100#" 183.03
+cap "VCCD" "VCO_0/X3/GND" -199.819
+cap "VCCD" "VCO_0/X3/OUT270" 728.659
+cap "VCO_0/X3/GND" "VCCD" 239.086
+cap "VCCD" "VCO_0/X3/X3/XR1/a_n703_n3602#" -96.804
+cap "VCO_0/X3/X3/XR2/a_n703_n3602#" "VCCD" 345.113
+cap "VCO_0/GND" "VCCD" 43.4247
+cap "VCO_0/GND" "VCCD" 43.4247
+cap "VCO_0/X9/ctrll3" "VCO_0/X9/ctrll4" -0.84633
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll5" -1.06136
+cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll5" -0.710526
+cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll4" -0.710526
+cap "VCO_0/X9/ctrll3" "VCO_0/X9/ctrll5" -0.84633
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll5" 88.1184
+cap "VCO_0/X9/GND" "VCO_0/X9/ctrll5" 117.967
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll1" 1.68684
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/GND" 27.0257
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/XM2/a_15_n100#" -0.0301646
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/XM3/a_n33_n100#" -0.00216877
+cap "VCO_0/X9/ctrll2" "VCO_0/X9/ctrll5" 0.90401
+cap "VCO_0/X9/ctrll3" "VCO_0/X9/ctrll5" 3.62945
+cap "VCO_0/X9/XM5/a_159_n100#" "VCO_0/X9/ctrll5" 392.841
+cap "VCO_0/X9/ctrll4" "VCO_0/X9/ctrll3" 13.8638
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+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM4/a_n2817_n100#" -899.13
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM33/a_n989_n100#" -696.567
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM33/a_n609_n100#" 485.544
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XR3/a_n703_n2202#" 34.8299
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM4/a_n2817_n100#" 698.398
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/BIAS" 213.767
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/VDD" 42.446
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM33/a_n945_n188#" -257.601
+cap "VCO_0/output_buffer_0/XM33/a_735_n100#" "VCO_0/output_buffer_0/VDD" -15.3971
+cap "VCO_0/output_buffer_0/VDD" "OUTB" 42.446
+cap "VCO_0/output_buffer_0/VDD" "VCO_0/output_buffer_0/XM4/a_n2817_n100#" -29.0178
+cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/XM33/a_n989_n100#" 7.75379
+cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/XR1/a_n285_760#" 2.11687
+cap "VCO_0/output_buffer_0/XR1/a_n285_760#" "VCO_0/output_buffer_0/OUTB" -728.735
+cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/OUTB" -636.195
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM3/a_n2817_n100#" -899.13
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/OUTA" 262.613
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM32/a_n945_n188#" -19.2706
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM33/a_n989_n100#" -721.424
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/BIAS" -2406.73
+cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/XM32/a_n945_n188#" 24.688
+cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/XM33/a_n989_n100#" 85.4033
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/SUB" -1310.7
+cap "VCO_0/output_buffer_0/XM33/a_n609_n100#" "VCO_0/output_buffer_0/OUTB" 712.485
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XR3/a_n703_n2202#" 30.0731
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM32/a_n945_n188#" -255.932
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/OUTA" 112.637
+cap "VCO_0/output_buffer_0/OUTB" "VCO_0/output_buffer_0/XM3/a_n2817_n100#" 779.345
+cap "VCO_0/output_buffer_0/BIAS" "VCO_0/output_buffer_0/OUTB" 49.4527
+cap "VCO_0/output_buffer_0/VDD" "VCO_0/output_buffer_0/OUTB" 42.446
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+cap "VCO_0/output_buffer_0/VDD" "OUTB" 42.446
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+cap "VCO_0/output_buffer_0/OUTA" "VCO_0/output_buffer_0/SUB" -594.285
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+cap "VCO_0/output_buffer_0/SUB" "OUTB" -310.58
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+cap "OUTB" "VCO_0/output_buffer_0/VDD" 19.6161
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+merge "VCO_0/VSUBS" "VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "VCO_0/output_buffer_0/OUTA" "OUTA" -1931.58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -6025110 -3474 0 0 0 0 0 0
+merge "VCO_0/output_buffer_0/OUTB" "OUTB" 8805.54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7812870 -3346 1533400 -5782 0 0 0 0
+merge "VCO_0/bias_calc_0/GND" "VCO_0/GND" -1985.94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 217442 -10058 0 0 0 0
+merge "VCO_0/GND" "GND"
+merge "VCO_0/CTRL1" "VCO_0/X9/ctrll1" 1614.57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2735142 -412 0 0 0 0 0 0 0 0 0 0
+merge "VCO_0/X9/ctrll1" "CTRL1"
+merge "VCO_0/bias_calc_0/VCTRL" "VCTRL" -2108.53 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4542100 -684 0 0 0 0 0 0 0 0 0 0
+merge "VCO_0/CTRL2" "VCO_0/X9/ctrll2" 2956.02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4878108 -422 0 0 0 0 0 0 0 0 0 0
+merge "VCO_0/X9/ctrll2" "CTRL2"
+merge "VCO_0/CTRL3" "VCO_0/X9/ctrll3" 2987.22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4787312 -362 0 0 0 0 0 0 0 0 0 0
+merge "VCO_0/X9/ctrll3" "CTRL3"
+merge "VCO_0/X9/ctrll4" "VCO_0/CTRL4" 1575 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2654862 -412 0 0 0 0 0 0 0 0 0 0
+merge "VCO_0/CTRL4" "CTRL4"
+merge "VCO_0/output_buffer_0/VDD" "VCO_0/X3/X4/VDD" -14103.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 101956436 -158022 0 0
+merge "VCO_0/X3/X4/VDD" "VCO_0/VDD"
+merge "VCO_0/VDD" "VCO_0/X3/X2/VDD"
+merge "VCO_0/X3/X2/VDD" "VCCD"
+merge "VCO_0/CTRL5" "VCO_0/X9/ctrll5" 989.931 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2428160 -442 0 0 0 0 0 0 0 0 0 0
+merge "VCO_0/X9/ctrll5" "CTRL5"
+merge "VCO_0/m1_33455_32800#" "VCO_0/bias_calc_0/BIAS2V" -10946.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -22097996 -778 -1880900 0 0 0 0 0 0 0
+merge "VCO_0/bias_calc_0/BIAS2V" "REF"

mag/user_analog_project_wrapper.mag

diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index f1198f1..34a5473 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,33 +1,86 @@
 magic
-tech $PDK
+tech sky130A
 magscale 1 2
-timestamp 1639841760
-<< mvpsubdiff >>
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-rect 371078 628255 371102 629032
-<< mvpsubdiffcont >>
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-<< locali >>
-rect 345748 628255 345764 629032
-rect 371078 628255 371094 629032
-<< viali >>
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+timestamp 1662923024
 << metal1 >>
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 << via1 >>
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 << metal2 >>
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@@ -523,147 +576,149 @@
 rect 582068 -800 582180 480
 rect 583250 -800 583362 480
 << via2 >>
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 << metal3 >>
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@@ -706,9 +766,7 @@
 rect 582340 225230 584800 230030
 rect -800 214888 1660 219688
 rect -800 204888 1660 209688
-rect 13406 191430 13991 196230
-rect 17427 191430 573605 196230
-rect 576629 191430 584800 196230
+rect 582340 191430 584800 196230
 rect 582340 181430 584800 186230
 rect -800 172888 1660 177688
 rect -800 162888 1660 167688
@@ -774,46 +832,12 @@
 rect 583520 2726 584800 2838
 rect -800 1544 480 1656
 rect 583520 1544 584800 1656
-<< rmetal3 >>
-rect 170894 700738 173094 700788
-rect 173394 700736 175594 700786
-rect 222594 700786 224794 700836
-rect 225094 700796 227294 700846
-rect 324294 701080 326494 701130
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-rect 660 462398 780 462510
-rect 676 419176 738 419288
-rect 583220 500050 583318 500162
-rect 583180 455628 583296 455740
 << via3 >>
-rect 170894 684327 173094 690603
-rect 173394 684327 175594 690603
-rect 222594 684360 224794 690636
-rect 225094 684360 227294 690636
-rect 324294 684344 326494 690618
-rect 318994 643740 323994 649497
-rect 329294 643740 334294 649497
-rect 510594 684332 515394 690564
-rect 510594 631780 515394 637598
-rect 520594 684332 525394 690564
-rect 560566 639784 566742 644584
-rect 520594 631780 525394 637598
-rect 560566 629784 566742 634584
-rect 357538 628057 359388 629399
-rect 341739 619574 341849 619684
-rect 533095 619583 533159 619647
-rect 533111 619218 533175 619282
-rect 341738 618520 341850 618632
-rect 13894 462398 17564 462510
-rect 13887 419176 17599 419288
-rect 533894 619583 533958 619647
-rect 533904 619218 533968 619282
-rect 556229 550562 562346 555362
-rect 556229 540562 562346 545362
-rect 573548 500050 576743 500162
-rect 573556 455628 576731 455740
-rect 13991 191430 17427 196230
-rect 573605 191430 576629 196230
+rect 42560 688410 43180 689440
+rect 40770 676130 41640 677240
+rect 23210 668680 23370 669080
+rect 1680 643970 4680 648410
+rect 860 559570 4260 564080
 << metal4 >>
 rect 165594 702300 170594 704800
 rect 175894 702300 180894 704800
@@ -821,125 +845,43 @@
 rect 227594 702300 232594 704800
 rect 318994 702300 323994 704800
 rect 329294 702300 334294 704800
-rect 170628 690636 526162 690737
-rect 170628 690603 222594 690636
-rect 170628 684327 170894 690603
-rect 173094 684327 173394 690603
-rect 175594 684360 222594 690603
-rect 224794 684360 225094 690636
-rect 227294 690618 526162 690636
-rect 227294 684360 324294 690618
-rect 175594 684344 324294 684360
-rect 326494 690564 526162 690618
-rect 326494 684344 510594 690564
-rect 175594 684332 510594 684344
-rect 515394 684332 520594 690564
-rect 525394 684332 526162 690564
-rect 175594 684327 526162 684332
-rect 170628 684183 526162 684327
-rect 318330 649837 359973 649898
-rect 318330 649497 357559 649837
-rect 318330 643740 318994 649497
-rect 323994 643740 329294 649497
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-rect 359314 643394 359973 649837
-rect 318330 643344 359973 643394
-rect 560425 644584 566979 644980
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-rect 566742 639784 566979 644584
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-rect 560425 634584 566979 639784
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-rect 533893 619645 533894 619647
-rect 533159 619585 533894 619645
-rect 533159 619583 533160 619585
-rect 533094 619582 533160 619583
-rect 533893 619583 533894 619585
-rect 533958 619583 533959 619647
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-rect 364987 615255 365157 617835
-rect 363328 615131 365157 615255
-rect 369823 613756 370980 618859
-rect 560425 613756 566979 629784
-rect 345256 607202 566979 613756
-rect 362658 601572 562613 601756
-rect 362658 597231 363414 601572
-rect 364992 597231 562613 601572
-rect 362658 595202 562613 597231
-rect 556059 555362 562613 595202
-rect 556059 550562 556229 555362
-rect 562346 550562 562613 555362
-rect 556059 545362 562613 550562
-rect 556059 540562 556229 545362
-rect 562346 540562 562613 545362
-rect 556059 540155 562613 540562
-rect 573464 500162 576816 500473
-rect 573464 500050 573548 500162
-rect 576743 500050 576816 500162
-rect 13814 462510 17684 462771
-rect 13814 462398 13894 462510
-rect 17564 462398 17684 462510
-rect 13814 419288 17684 462398
-rect 13814 419176 13887 419288
-rect 17599 419176 17684 419288
-rect 13814 227257 17684 419176
-rect 573464 455740 576816 500050
-rect 573464 455628 573556 455740
-rect 576731 455628 576816 455740
-rect 13811 196230 17688 227257
-rect 13811 191430 13991 196230
-rect 17427 191430 17688 196230
-rect 13811 191098 17688 191430
-rect 573464 196230 576816 455628
-rect 573464 191430 573605 196230
-rect 576629 191430 576816 196230
-rect 573464 191191 576816 191430
+rect 42500 689440 43450 689470
+rect 42500 688410 42560 689440
+rect 43180 688410 43450 689440
+rect 42500 677320 43450 688410
+rect 40720 677240 43450 677320
+rect 40720 676130 40770 677240
+rect 41640 676130 43450 677240
+rect 40720 676090 43450 676130
+rect 40720 676080 43220 676090
+rect 60220 676010 65450 676030
+rect 56870 675970 65450 676010
+rect 56870 675440 60910 675970
+rect 65380 675440 65450 675970
+rect 56870 675370 65450 675440
+rect 23190 669080 23390 669110
+rect 23190 668680 23210 669080
+rect 23370 668680 23390 669080
+rect 1380 648410 5010 648620
+rect 1380 643970 1680 648410
+rect 4680 643970 5010 648410
+rect 1380 643770 5010 643970
+rect 23190 608120 23390 668680
+rect 26600 633690 28120 662640
+rect 26090 633500 28790 633690
+rect 26090 631620 26270 633500
+rect 28580 631620 28790 633500
+rect 26090 631490 28790 631620
+rect 21660 603350 25780 608120
+rect 690 564080 4450 564270
+rect 690 559570 860 564080
+rect 4260 559570 4450 564080
+rect 690 559400 4450 559570
 << via4 >>
-rect 357559 643394 359314 649837
-rect 352028 615249 353603 617829
-rect 363412 615255 364987 617835
-rect 363414 597231 364992 601572
+rect 60910 675440 65380 675970
+rect 1680 643970 4680 648410
+rect 26270 631620 28580 633500
+rect 860 559570 4260 564080
 << metal5 >>
 rect 165594 702300 170594 704800
 rect 175894 702300 180894 704800
@@ -947,31 +889,41 @@
 rect 227594 702300 232594 704800
 rect 318994 702300 323994 704800
 rect 329294 702300 334294 704800
-rect 357521 649837 359350 649991
-rect 357521 643394 357559 649837
-rect 359314 643394 359350 649837
-rect 351918 617829 353747 617929
-rect 351918 615249 352028 617829
-rect 353603 615249 353747 617829
-rect 351918 614900 353747 615249
-rect 357521 614900 359350 643394
-rect 351918 613071 359350 614900
-rect 363318 617835 365147 617929
-rect 363318 615255 363412 617835
-rect 364987 615255 365147 617835
-rect 363318 601572 365147 615255
-rect 363318 597231 363414 601572
-rect 364992 597231 365147 601572
-rect 363318 597052 365147 597231
+rect 60790 675970 65590 676060
+rect 60790 675440 60910 675970
+rect 65380 675440 65590 675970
+rect 33890 648790 34330 675040
+rect 39240 648790 39680 674940
+rect 42370 648790 42840 674830
+rect 44740 648790 45180 675000
+rect 45790 648790 46240 663160
+rect 60790 652300 65590 675440
+rect 1390 648620 46250 648790
+rect 1380 648410 46250 648620
+rect 1380 643970 1680 648410
+rect 4680 643970 46250 648410
+rect 1380 643770 46250 643970
+rect 26080 633500 28810 633710
+rect 26080 631620 26270 633500
+rect 28580 631620 28810 633500
+rect 26080 564330 28810 631620
+rect 60820 564330 65590 652300
+rect 26080 564320 65590 564330
+rect 1770 564270 65590 564320
+rect 690 564080 65590 564270
+rect 690 559570 860 564080
+rect 4260 559570 65590 564080
+rect 690 559400 65590 559570
+rect 1770 559390 30940 559400
 << comment >>
 rect -100 704000 584100 704100
 rect -100 0 0 704000
 rect 584000 0 584100 704000
 rect -100 -100 584100 0
-use user_analog_proj_example  user_analog_proj_example_0
-timestamp 1639841760
-transform 1 0 345668 0 -1 627114
-box -59 -22 25476 8324
+use VCO  VCO_0
+timestamp 1662920576
+transform 1 0 -7837 0 1 638742
+box 31141 20430 65400 41673
 << labels >>
 flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
 port 0 nsew signal bidirectional
@@ -1047,8 +999,7 @@
 port 35 nsew signal bidirectional
 flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
 port 36 nsew signal bidirectional
-flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
-port 37 nsew signal bidirectional
+flabel metal3 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
 flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
 port 38 nsew signal bidirectional
 flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
@@ -2353,10 +2304,17 @@
 port 676 nsew signal input
 flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
 port 677 nsew signal input
-flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
-flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
-flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
-flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
+flabel metal5 4680 643770 46250 648790 0 FreeSans 16000 0 0 0 VCCD
+flabel metal5 26080 559400 65590 564330 0 FreeSans 16000 0 0 0 GND
+rlabel metal2 56980 508120 57120 660100 1 CTRL1
+rlabel metal2 56720 466080 56860 660460 1 CTRL2
+rlabel metal2 56480 421660 56620 660980 1 CTRL3
+rlabel metal2 56200 378460 56340 661580 1 CTRL4
+rlabel metal2 55960 335220 56100 662500 1 CTRL5
+flabel metal3 17070 688210 41870 689330 0 FreeSans 8000 0 0 0 OUTA
+flabel metal3 43180 688360 70760 689480 0 FreeSans 8000 0 0 0 OUTB
+flabel metal1 14920 668060 15420 682040 0 FreeSans 8000 0 0 0 VCTRL
+flabel metal4 21660 603350 25780 608120 0 FreeSans 8000 0 0 0 REF
 << properties >>
 string FIXED_BBOX 0 0 584000 704000
 << end >>

mag/user_analog_project_wrapper.spice

diff --git a/mag/user_analog_project_wrapper.spice b/mag/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..ffbd819
--- /dev/null
+++ b/mag/user_analog_project_wrapper.spice
@@ -0,0 +1,612 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_648S5X a_n73_n100# a_n33_n188# a_15_n100# a_n175_n274#
+X0 a_15_n100# a_n33_n188# a_n73_n100# a_n175_n274# sky130_fd_pr__nfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_DJ7QE5 a_15_122# a_n227_n274# a_n125_n100# a_n81_n188#
++ a_63_n100# a_n33_n100#
+X0 a_63_n100# a_15_122# a_n33_n100# a_n227_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n188# a_n125_n100# a_n227_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_BX7S53 a_n275_n274# a_n173_n100# a_15_n100# a_n33_122#
++ a_111_n100# a_n81_n100# a_n129_n188# a_63_n188#
+X0 a_15_n100# a_n33_122# a_n81_n100# a_n275_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n81_n100# a_n129_n188# a_n173_n100# a_n275_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+X2 a_111_n100# a_63_n188# a_15_n100# a_n275_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B6HS5D a_159_n100# a_111_n188# a_15_122# a_n273_n188#
++ a_255_n100# a_207_122# a_n129_n100# a_n81_n188# a_63_n100# a_n177_122# a_n225_n100#
++ a_n33_n100# a_n419_n274# a_n317_n100#
+X0 a_63_n100# a_15_122# a_n33_n100# a_n419_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n188# a_n129_n100# a_n419_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_159_n100# a_111_n188# a_63_n100# a_n419_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_207_122# a_159_n100# a_n419_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n273_n188# a_n317_n100# a_n419_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+X5 a_n129_n100# a_n177_122# a_n225_n100# a_n419_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_WCTBV5 m4_n551_n300# c2_n451_n200#
+X0 c2_n451_n200# m4_n551_n300# sky130_fd_pr__cap_mim_m3_2 l=2e+06u w=2e+06u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_WCTZRP c2_n551_n200# m4_n651_n300#
+X0 c2_n551_n200# m4_n651_n300# sky130_fd_pr__cap_mim_m3_2 l=2e+06u w=3e+06u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_3ZFDVT c2_n551_n400# m4_n651_n500#
+X0 c2_n551_n400# m4_n651_n500# sky130_fd_pr__cap_mim_m3_2 l=4e+06u w=3e+06u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_VCH7EQ c2_n851_n400# m4_n951_n500#
+X0 c2_n851_n400# m4_n951_n500# sky130_fd_pr__cap_mim_m3_2 l=4e+06u w=6e+06u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_FJFAMD m4_n551_n300# c2_n451_n200#
+X0 c2_n451_n200# m4_n551_n300# sky130_fd_pr__cap_mim_m3_2 l=2e+06u w=2e+06u
+.ends
+
+.subckt cap_bank ctrll5 ctrll4 ctrll2 ctrll3 ctrll1 IN GND
+XXM1 m1_3910_n1320# ctrll1 GND GND sky130_fd_pr__nfet_01v8_lvt_648S5X
+XXM2 GND ctrll2 m1_4820_n1420# GND sky130_fd_pr__nfet_01v8_lvt_648S5X
+XXM3 ctrll3 GND GND ctrll3 GND m1_4820_n890# sky130_fd_pr__nfet_01v8_lvt_DJ7QE5
+XXM4 GND GND GND ctrll4 m1_4820_n460# m1_4820_n460# ctrll4 ctrll4 sky130_fd_pr__nfet_01v8_lvt_BX7S53
+XXM5 m1_4700_270# ctrll5 ctrll5 ctrll5 GND ctrll5 GND ctrll5 GND ctrll5 m1_4700_270#
++ m1_4700_270# GND GND sky130_fd_pr__nfet_01v8_lvt_B6HS5D
+XXC1 m1_4820_n1420# IN sky130_fd_pr__cap_mim_m3_2_WCTBV5
+XXC2 IN m1_4820_n890# sky130_fd_pr__cap_mim_m3_2_WCTZRP
+XXC3 IN m1_4820_n460# sky130_fd_pr__cap_mim_m3_2_3ZFDVT
+XXC4 IN m1_4700_270# sky130_fd_pr__cap_mim_m3_2_VCH7EQ
+XXC6 m1_3910_n1320# IN sky130_fd_pr__cap_mim_m3_2_FJFAMD
+.ends
+
+.subckt sky130_fd_pr__res_high_po_2p85_P79JE3 a_n285_n1192# a_n285_760# a_n415_n1322#
+X0 a_n285_n1192# a_n285_760# a_n415_n1322# sky130_fd_pr__res_high_po_2p85 l=7.6e+06u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_W59YBA a_n573_1640# a_n573_n2072# a_n703_n2202#
+X0 a_n573_n2072# a_n573_1640# a_n703_n2202# sky130_fd_pr__res_high_po_5p73 l=1.64e+07u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_YTLFGX a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n801_n100# a_n129_n100# a_n513_n100# a_n989_n100#
++ a_63_n100# a_n225_n100# a_n945_n188# a_927_n100# a_n1091_n274# a_n321_n100# a_639_n100#
++ a_735_n100# a_n33_n100# a_n897_n100# a_831_n100# a_447_n100#
+X0 a_63_n100# a_n945_n188# a_n33_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_n945_n188# a_831_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n945_n188# a_n129_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_n945_n188# a_255_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_159_n100# a_n945_n188# a_63_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_255_n100# a_n945_n188# a_159_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_n945_n188# a_351_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_543_n100# a_n945_n188# a_447_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_n945_n188# a_639_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_831_n100# a_n945_n188# a_735_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_639_n100# a_n945_n188# a_543_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n100# a_n945_n188# a_n417_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_n801_n100# a_n945_n188# a_n897_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_n705_n100# a_n945_n188# a_n801_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n513_n100# a_n945_n188# a_n609_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X15 a_n417_n100# a_n945_n188# a_n513_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_n225_n100# a_n945_n188# a_n321_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n129_n100# a_n945_n188# a_n225_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n897_n100# a_n945_n188# a_n989_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+X19 a_n609_n100# a_n945_n188# a_n705_n100# a_n1091_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_LELFGX a_543_n100# a_n609_n100# a_159_n100# a_1695_n100#
++ a_n2001_122# a_879_122# a_2655_n100# a_n2481_n188# a_n273_122# a_n1953_n100# a_n2097_n188#
++ a_n1569_n100# a_n1521_n188# a_1839_122# a_n2529_n100# a_n1137_n188# a_n705_n100#
++ a_1791_n100# a_n1233_122# a_255_n100# a_975_n188# a_2751_n100# a_2367_n100# a_1407_n100#
++ a_1071_122# a_n1665_n100# a_n2625_n100# a_n2577_122# a_n801_n100# a_351_n100# a_n417_n100#
++ a_2463_n100# a_2079_n100# a_n465_122# a_1503_n100# a_2031_122# a_n1761_n100# a_1119_n100#
++ a_n2721_n100# a_n1377_n100# a_n2337_n100# a_n1425_122# a_n513_n100# a_783_n188#
++ a_n129_n100# a_399_n188# a_2175_n100# a_1263_122# a_1215_n100# a_n1473_n100# a_63_n100#
++ a_1935_n188# a_n2433_n100# a_n1089_n100# a_n2049_n100# a_n2769_122# a_n2909_n100#
++ a_n225_n100# a_2271_n100# a_n657_122# a_n945_n188# a_2223_122# a_927_n100# a_1311_n100#
++ a_n1185_n100# a_n2145_n100# a_495_122# a_n2865_n188# a_n1617_122# a_n3011_n274#
++ a_111_122# a_n321_n100# a_n1905_n188# a_591_n188# a_1455_122# a_639_n100# a_1023_n100#
++ a_207_n188# a_1743_n188# a_n1281_n100# a_1359_n188# a_2703_n188# a_n2241_n100# a_2319_n188#
++ a_n849_122# a_2799_122# a_n753_n188# a_n369_n188# a_2415_122# a_n33_n100# a_735_n100#
++ a_1887_n100# a_n2193_122# a_2847_n100# a_687_122# a_n1809_122# a_303_122# a_n2673_n188#
++ a_n2289_n188# a_n1713_n188# a_n897_n100# a_n1329_n188# a_1647_122# a_831_n100# a_447_n100#
++ a_1983_n100# a_1599_n100# a_1551_n188# a_n1041_122# a_1167_n188# a_2511_n188# a_2559_n100#
++ a_2127_n188# a_n1857_n100# a_n81_122# a_15_n188# a_n2817_n100# a_n993_n100# a_2607_122#
++ a_n561_n188# a_n177_n188# a_n2385_122#
+X0 a_63_n100# a_15_n188# a_n33_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n2721_n100# a_n2769_122# a_n2817_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n2433_n100# a_n2481_n188# a_n2529_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_n2241_n100# a_n2289_n188# a_n2337_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n2145_n100# a_n2193_122# a_n2241_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n2049_n100# a_n2097_n188# a_n2145_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n2817_n100# a_n2865_n188# a_n2909_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+X7 a_n2625_n100# a_n2673_n188# a_n2721_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n2529_n100# a_n2577_122# a_n2625_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n2337_n100# a_n2385_122# a_n2433_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_2175_n100# a_2127_n188# a_2079_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_2271_n100# a_2223_122# a_2175_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_2463_n100# a_2415_122# a_2367_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_2751_n100# a_2703_n188# a_2655_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X14 a_2079_n100# a_2031_122# a_1983_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X15 a_2367_n100# a_2319_n188# a_2271_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_2559_n100# a_2511_n188# a_2463_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X17 a_2655_n100# a_2607_122# a_2559_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_2847_n100# a_2799_122# a_2751_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X19 a_1023_n100# a_975_n188# a_927_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X20 a_927_n100# a_879_122# a_831_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X21 a_n1761_n100# a_n1809_122# a_n1857_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X22 a_n1953_n100# a_n2001_122# a_n2049_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n1857_n100# a_n1905_n188# a_n1953_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_n1665_n100# a_n1713_n188# a_n1761_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1569_n100# a_n1617_122# a_n1665_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X26 a_1215_n100# a_1167_n188# a_1119_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X27 a_1311_n100# a_1263_122# a_1215_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1503_n100# a_1455_122# a_1407_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X29 a_1791_n100# a_1743_n188# a_1695_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X30 a_1119_n100# a_1071_122# a_1023_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1407_n100# a_1359_n188# a_1311_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1599_n100# a_1551_n188# a_1503_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1695_n100# a_1647_122# a_1599_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_1887_n100# a_1839_122# a_1791_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X35 a_1983_n100# a_1935_n188# a_1887_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_n100# a_n81_122# a_n129_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X37 a_351_n100# a_303_122# a_255_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X38 a_159_n100# a_111_122# a_63_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X39 a_255_n100# a_207_n188# a_159_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n100# a_399_n188# a_351_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X41 a_543_n100# a_495_122# a_447_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X42 a_735_n100# a_687_122# a_639_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X43 a_831_n100# a_783_n188# a_735_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_639_n100# a_591_n188# a_543_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n1473_n100# a_n1521_n188# a_n1569_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1281_n100# a_n1329_n188# a_n1377_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X47 a_n1185_n100# a_n1233_122# a_n1281_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n100# a_n1041_122# a_n1089_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X49 a_n1377_n100# a_n1425_122# a_n1473_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n1089_n100# a_n1137_n188# a_n1185_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_n321_n100# a_n369_n188# a_n417_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X52 a_n801_n100# a_n849_122# a_n897_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X53 a_n705_n100# a_n753_n188# a_n801_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_n100# a_n561_n188# a_n609_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X55 a_n417_n100# a_n465_122# a_n513_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_n100# a_n273_122# a_n321_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_n100# a_n177_n188# a_n225_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n897_n100# a_n945_n188# a_n993_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n609_n100# a_n657_122# a_n705_n100# a_n3011_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_HNLS5R a_159_n100# a_n323_n274# a_n129_n100# a_n221_n100#
++ a_63_n100# a_n33_n100# a_n81_122# a_n177_n188#
+X0 a_63_n100# a_n177_n188# a_n33_n100# a_n323_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_122# a_n129_n100# a_n323_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_159_n100# a_n81_122# a_63_n100# a_n323_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n177_n188# a_n221_n100# a_n323_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt output_buffer INB INA VDD BIAS OUTB GND OUTA SUB
+XXR1 VDD m1_12140_1165# SUB sky130_fd_pr__res_high_po_2p85_P79JE3
+XXR2 VDD m1_12140_n1090# SUB sky130_fd_pr__res_high_po_2p85_P79JE3
+XXR3 VDD OUTB SUB sky130_fd_pr__res_high_po_5p73_W59YBA
+XXM1 m1_9850_15# m1_9850_15# m1_9850_15# GND GND m1_9850_15# m1_9850_15# m1_9850_15#
++ GND GND m1_9850_15# GND m1_9850_15# BIAS m1_9850_15# SUB GND GND m1_9850_15# m1_9850_15#
++ GND GND GND sky130_fd_pr__nfet_01v8_lvt_YTLFGX
+XXM2 m1_9850_15# m1_9850_15# m1_9850_15# GND GND m1_9850_15# m1_9850_15# m1_9850_15#
++ GND GND m1_9850_15# GND m1_9850_15# BIAS m1_9850_15# SUB GND GND m1_9850_15# m1_9850_15#
++ GND GND GND sky130_fd_pr__nfet_01v8_lvt_YTLFGX
+XXM3 m1_13690_15# m1_13690_15# m1_13690_15# m1_13690_15# BIAS BIAS m1_13690_15# BIAS
++ BIAS m1_13690_15# BIAS m1_13690_15# BIAS BIAS m1_13690_15# BIAS GND GND BIAS GND
++ BIAS GND GND GND BIAS GND GND BIAS m1_13690_15# m1_13690_15# m1_13690_15# m1_13690_15#
++ m1_13690_15# BIAS m1_13690_15# BIAS m1_13690_15# m1_13690_15# m1_13690_15# m1_13690_15#
++ m1_13690_15# BIAS GND BIAS GND BIAS GND BIAS GND GND GND BIAS GND GND GND BIAS m1_13690_15#
++ m1_13690_15# m1_13690_15# BIAS BIAS BIAS m1_13690_15# m1_13690_15# m1_13690_15#
++ m1_13690_15# BIAS BIAS BIAS SUB BIAS GND BIAS BIAS BIAS GND GND BIAS BIAS GND BIAS
++ BIAS GND BIAS BIAS BIAS BIAS BIAS BIAS m1_13690_15# m1_13690_15# m1_13690_15# BIAS
++ m1_13690_15# BIAS BIAS BIAS BIAS BIAS BIAS GND BIAS BIAS GND GND GND GND BIAS BIAS
++ BIAS BIAS GND BIAS GND BIAS BIAS GND m1_13690_15# BIAS BIAS BIAS BIAS sky130_fd_pr__nfet_01v8_lvt_LELFGX
+XXM4 m1_13690_15# m1_13690_15# m1_13690_15# m1_13690_15# BIAS BIAS m1_13690_15# BIAS
++ BIAS m1_13690_15# BIAS m1_13690_15# BIAS BIAS m1_13690_15# BIAS GND GND BIAS GND
++ BIAS GND GND GND BIAS GND GND BIAS m1_13690_15# m1_13690_15# m1_13690_15# m1_13690_15#
++ m1_13690_15# BIAS m1_13690_15# BIAS m1_13690_15# m1_13690_15# m1_13690_15# m1_13690_15#
++ m1_13690_15# BIAS GND BIAS GND BIAS GND BIAS GND GND GND BIAS GND GND GND BIAS m1_13690_15#
++ m1_13690_15# m1_13690_15# BIAS BIAS BIAS m1_13690_15# m1_13690_15# m1_13690_15#
++ m1_13690_15# BIAS BIAS BIAS SUB BIAS GND BIAS BIAS BIAS GND GND BIAS BIAS GND BIAS
++ BIAS GND BIAS BIAS BIAS BIAS BIAS BIAS m1_13690_15# m1_13690_15# m1_13690_15# BIAS
++ m1_13690_15# BIAS BIAS BIAS BIAS BIAS BIAS GND BIAS BIAS GND GND GND GND BIAS BIAS
++ BIAS BIAS GND BIAS GND BIAS BIAS GND m1_13690_15# BIAS BIAS BIAS BIAS sky130_fd_pr__nfet_01v8_lvt_LELFGX
+XXR29 VDD OUTA SUB sky130_fd_pr__res_high_po_5p73_W59YBA
+XXM42 m1_9850_15# SUB m1_12140_1165# m1_9850_15# m1_12140_1165# m1_9850_15# INA INA
++ sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXM43 m1_9850_15# SUB m1_12140_n1090# m1_9850_15# m1_12140_n1090# m1_9850_15# INB
++ INB sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXM32 m1_13690_15# m1_13690_15# m1_13690_15# OUTA OUTA m1_13690_15# m1_13690_15# m1_13690_15#
++ OUTA OUTA m1_13690_15# OUTA m1_13690_15# m1_12140_1165# m1_13690_15# SUB OUTA OUTA
++ m1_13690_15# m1_13690_15# OUTA OUTA OUTA sky130_fd_pr__nfet_01v8_lvt_YTLFGX
+XXM33 m1_13690_15# m1_13690_15# m1_13690_15# OUTB OUTB m1_13690_15# m1_13690_15# m1_13690_15#
++ OUTB OUTB m1_13690_15# OUTB m1_13690_15# m1_12140_n1090# m1_13690_15# SUB OUTB OUTB
++ m1_13690_15# m1_13690_15# OUTB OUTB OUTB sky130_fd_pr__nfet_01v8_lvt_YTLFGX
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3M934 a_35_n100# a_n547_n197# a_n931_n197# a_931_n100#
++ a_547_n100# a_605_n197# a_n477_n100# a_n861_n100# a_n291_n197# a_291_n100# w_n1127_n319#
++ a_n221_n100# a_n989_n100# a_n803_n197# a_861_n197# a_n419_n197# a_477_n197# a_803_n100#
++ a_419_n100# a_n349_n100# a_n733_n100# a_n163_n197# a_163_n100# a_221_n197# a_n93_n100#
++ a_n675_n197# a_675_n100# a_733_n197# a_349_n197# a_n605_n100# a_n35_n197# a_93_n197#
+X0 a_291_n100# a_221_n197# a_163_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X1 a_675_n100# a_605_n197# a_547_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X2 a_n221_n100# a_n291_n197# a_n349_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X3 a_n605_n100# a_n675_n197# a_n733_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X4 a_931_n100# a_861_n197# a_803_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X5 a_547_n100# a_477_n197# a_419_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X6 a_n93_n100# a_n163_n197# a_n221_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X7 a_163_n100# a_93_n197# a_35_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X8 a_n861_n100# a_n931_n197# a_n989_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X9 a_n477_n100# a_n547_n197# a_n605_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X10 a_419_n100# a_349_n197# a_291_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X11 a_803_n100# a_733_n197# a_675_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X12 a_35_n100# a_n35_n197# a_n93_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X13 a_n733_n100# a_n803_n197# a_n861_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X14 a_n349_n100# a_n419_n197# a_n477_n100# w_n1127_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3Z634 a_483_n100# a_1693_n197# a_541_n197# a_157_n197#
++ a_1635_n100# a_1309_n197# a_99_n100# a_n413_n100# a_n995_n197# a_n1891_n197# a_n29_n100#
++ a_n1507_n197# a_995_n100# a_1053_n197# a_669_n197# a_n925_n100# a_n1437_n100# a_n1821_n100#
++ w_n2087_n319# a_n355_n197# a_n1251_n197# a_413_n197# a_1891_n100# a_355_n100# a_n1181_n100#
++ a_1565_n197# a_1507_n100# a_n285_n100# a_29_n197# a_n1949_n100# a_n1763_n197# a_n867_n197#
++ a_n1379_n197# a_1251_n100# a_867_n100# a_925_n197# a_n797_n100# a_n1693_n100# a_n1309_n100#
++ a_n227_n197# a_n611_n197# a_n1123_n197# a_285_n197# a_1763_n100# a_1379_n100# a_611_n100#
++ a_227_n100# a_1821_n197# a_1437_n197# a_n157_n100# a_n541_n100# a_n1053_n100# a_n1635_n197#
++ a_n739_n197# a_1181_n197# a_797_n197# a_739_n100# a_1123_n100# a_n1565_n100# a_n669_n100#
++ a_n483_n197# a_n99_n197#
+X0 a_483_n100# a_413_n197# a_355_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X1 a_n1181_n100# a_n1251_n197# a_n1309_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X2 a_n1565_n100# a_n1635_n197# a_n1693_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X3 a_n413_n100# a_n483_n197# a_n541_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X4 a_n797_n100# a_n867_n197# a_n925_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X5 a_355_n100# a_285_n197# a_227_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X6 a_739_n100# a_669_n197# a_611_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X7 a_n1821_n100# a_n1891_n197# a_n1949_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X8 a_1123_n100# a_1053_n197# a_995_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X9 a_1507_n100# a_1437_n197# a_1379_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X10 a_1891_n100# a_1821_n197# a_1763_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X11 a_99_n100# a_29_n197# a_n29_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X12 a_1763_n100# a_1693_n197# a_1635_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X13 a_n1053_n100# a_n1123_n197# a_n1181_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X14 a_n1437_n100# a_n1507_n197# a_n1565_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X15 a_n285_n100# a_n355_n197# a_n413_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X16 a_n669_n100# a_n739_n197# a_n797_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X17 a_611_n100# a_541_n197# a_483_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X18 a_227_n100# a_157_n197# a_99_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X19 a_995_n100# a_925_n197# a_867_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X20 a_n1693_n100# a_n1763_n197# a_n1821_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X21 a_n1309_n100# a_n1379_n197# a_n1437_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X22 a_n925_n100# a_n995_n197# a_n1053_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X23 a_1379_n100# a_1309_n197# a_1251_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X24 a_867_n100# a_797_n197# a_739_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X25 a_1251_n100# a_1181_n197# a_1123_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X26 a_1635_n100# a_1565_n197# a_1507_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X27 a_n541_n100# a_n611_n197# a_n669_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X28 a_n157_n100# a_n227_n197# a_n285_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X29 a_n29_n100# a_n99_n197# a_n157_n100# w_n2087_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9DHFGX a_159_n100# a_111_n188# a_15_122# a_n273_n188#
++ a_255_n100# a_n611_n274# a_351_n100# a_n417_n100# a_207_122# a_n129_n100# a_n81_n188#
++ a_63_n100# a_n177_122# a_n225_n100# a_n321_n100# a_n369_122# a_n33_n100# a_n509_n100#
++ a_303_n188# a_n465_n188# a_447_n100# a_399_122#
+X0 a_63_n100# a_15_122# a_n33_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n188# a_n129_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_351_n100# a_303_n188# a_255_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_159_n100# a_111_n188# a_63_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n100# a_207_122# a_159_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_447_n100# a_399_122# a_351_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n321_n100# a_n369_122# a_n417_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X7 a_n417_n100# a_n465_n188# a_n509_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+X8 a_n225_n100# a_n273_n188# a_n321_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n129_n100# a_n177_122# a_n225_n100# a_n611_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__res_high_po_2p85_MM89SS a_n285_n1572# a_n415_n1702# a_n285_1140#
+X0 a_n285_n1572# a_n285_1140# a_n415_n1702# sky130_fd_pr__res_high_po_2p85 l=1.14e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4 a_483_n100# a_541_n197# a_157_n197# a_99_n100#
++ a_n413_n100# a_n29_n100# a_n355_n197# a_413_n197# a_355_n100# a_n285_n100# a_29_n197#
++ w_n807_n319# a_n227_n197# a_n611_n197# a_285_n197# a_611_n100# a_227_n100# a_n157_n100#
++ a_n541_n100# a_n669_n100# a_n483_n197# a_n99_n197#
+X0 a_483_n100# a_413_n197# a_355_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X1 a_n413_n100# a_n483_n197# a_n541_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X2 a_355_n100# a_285_n197# a_227_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X3 a_99_n100# a_29_n197# a_n29_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X4 a_n285_n100# a_n355_n197# a_n413_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X5 a_611_n100# a_541_n197# a_483_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X6 a_227_n100# a_157_n197# a_99_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+X7 a_n541_n100# a_n611_n197# a_n669_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X8 a_n157_n100# a_n227_n197# a_n285_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=350000u
+X9 a_n29_n100# a_n99_n197# a_n157_n100# w_n807_n319# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+.ends
+
+.subckt bias_calc AMP VCTRL PSUB BIASOUT VOP VDD BIAS2V GND SUB
+XXM36 m1_17310_5240# BIAS2V BIAS2V VDD m1_17310_5240# BIAS2V m1_17310_5240# VDD BIAS2V
++ m1_17310_5240# PSUB m1_17310_5240# m1_17310_5240# BIAS2V BIAS2V BIAS2V BIAS2V m1_17310_5240#
++ VDD VDD m1_17310_5240# BIAS2V VDD BIAS2V VDD BIAS2V VDD BIAS2V BIAS2V VDD BIAS2V
++ BIAS2V sky130_fd_pr__pfet_01v8_lvt_D3M934
+XXM37 m1_17310_5240# VCTRL VCTRL VCTRL m1_17860_4190# VCTRL m1_17860_4190# m1_17860_4190#
++ VCTRL VCTRL m1_17310_5240# VCTRL m1_17310_5240# VCTRL VCTRL m1_17860_4190# m1_17860_4190#
++ m1_17310_5240# PSUB VCTRL VCTRL VCTRL m1_17860_4190# m1_17860_4190# m1_17860_4190#
++ VCTRL m1_17310_5240# m1_17310_5240# VCTRL m1_17860_4190# VCTRL VCTRL VCTRL m1_17310_5240#
++ m1_17860_4190# VCTRL m1_17310_5240# m1_17860_4190# m1_17310_5240# VCTRL VCTRL VCTRL
++ VCTRL m1_17310_5240# m1_17860_4190# m1_17860_4190# m1_17310_5240# VCTRL VCTRL m1_17860_4190#
++ m1_17310_5240# m1_17310_5240# VCTRL VCTRL VCTRL VCTRL m1_17310_5240# m1_17860_4190#
++ m1_17310_5240# m1_17860_4190# VCTRL VCTRL sky130_fd_pr__pfet_01v8_lvt_D3Z634
+XXM38 m1_17310_5240# m1_18270_400# m1_18270_400# m1_18270_400# BIASOUT m1_18270_400#
++ BIASOUT BIASOUT m1_18270_400# m1_18270_400# m1_17310_5240# m1_18270_400# m1_17310_5240#
++ m1_18270_400# m1_18270_400# BIASOUT BIASOUT m1_17310_5240# PSUB m1_18270_400# m1_18270_400#
++ m1_18270_400# BIASOUT BIASOUT BIASOUT m1_18270_400# m1_17310_5240# m1_17310_5240#
++ m1_18270_400# BIASOUT m1_18270_400# m1_18270_400# m1_18270_400# m1_17310_5240# BIASOUT
++ m1_18270_400# m1_17310_5240# BIASOUT m1_17310_5240# m1_18270_400# m1_18270_400#
++ m1_18270_400# m1_18270_400# m1_17310_5240# BIASOUT BIASOUT m1_17310_5240# m1_18270_400#
++ m1_18270_400# BIASOUT m1_17310_5240# m1_17310_5240# m1_18270_400# m1_18270_400#
++ m1_18270_400# m1_18270_400# m1_17310_5240# BIASOUT m1_17310_5240# BIASOUT m1_18270_400#
++ m1_18270_400# sky130_fd_pr__pfet_01v8_lvt_D3Z634
+XXM39 m1_17860_4190# m1_17860_4190# m1_17860_4190# m1_17860_4190# GND SUB m1_17860_4190#
++ m1_17860_4190# m1_17860_4190# GND m1_17860_4190# GND m1_17860_4190# m1_17860_4190#
++ GND m1_17860_4190# m1_17860_4190# GND m1_17860_4190# m1_17860_4190# GND m1_17860_4190#
++ sky130_fd_pr__nfet_01v8_lvt_9DHFGX
+XXM29 VDD BIAS2V BIAS2V m1_20160_2025# VDD BIAS2V VDD m1_20160_2025# BIAS2V VDD PSUB
++ VDD VDD BIAS2V BIAS2V BIAS2V BIAS2V VDD m1_20160_2025# m1_20160_2025# VDD BIAS2V
++ m1_20160_2025# BIAS2V m1_20160_2025# BIAS2V m1_20160_2025# BIAS2V BIAS2V m1_20160_2025#
++ BIAS2V BIAS2V sky130_fd_pr__pfet_01v8_lvt_D3M934
+XXR20 m1_18270_400# SUB GND sky130_fd_pr__res_high_po_2p85_MM89SS
+XXM1 m1_20160_2025# BIAS2V BIAS2V VDD m1_20160_2025# BIAS2V m1_20160_2025# VDD BIAS2V
++ m1_20160_2025# PSUB m1_20160_2025# m1_20160_2025# BIAS2V BIAS2V BIAS2V BIAS2V m1_20160_2025#
++ VDD VDD m1_20160_2025# BIAS2V VDD BIAS2V VDD BIAS2V VDD BIAS2V BIAS2V VDD BIAS2V
++ BIAS2V sky130_fd_pr__pfet_01v8_lvt_D3M934
+XXM2 m1_17310_5240# BIAS2V BIAS2V VDD m1_17310_5240# BIAS2V m1_17310_5240# VDD BIAS2V
++ m1_17310_5240# PSUB m1_17310_5240# m1_17310_5240# BIAS2V BIAS2V BIAS2V BIAS2V m1_17310_5240#
++ VDD VDD m1_17310_5240# BIAS2V VDD BIAS2V VDD BIAS2V VDD BIAS2V BIAS2V VDD BIAS2V
++ BIAS2V sky130_fd_pr__pfet_01v8_lvt_D3M934
+XXM3 m1_17310_5240# BIAS2V BIAS2V VDD m1_17310_5240# BIAS2V m1_17310_5240# VDD BIAS2V
++ m1_17310_5240# PSUB m1_17310_5240# m1_17310_5240# BIAS2V BIAS2V BIAS2V BIAS2V m1_17310_5240#
++ VDD VDD m1_17310_5240# BIAS2V VDD BIAS2V VDD BIAS2V VDD BIAS2V BIAS2V VDD BIAS2V
++ BIAS2V sky130_fd_pr__pfet_01v8_lvt_D3M934
+XXR19 GND m1_19235_6325# SUB sky130_fd_pr__res_high_po_2p85_P79JE3
+XXM40 BIASOUT m1_17860_4190# m1_17860_4190# m1_17860_4190# GND SUB BIASOUT BIASOUT
++ m1_17860_4190# GND m1_17860_4190# GND m1_17860_4190# BIASOUT GND m1_17860_4190#
++ BIASOUT GND m1_17860_4190# m1_17860_4190# GND m1_17860_4190# sky130_fd_pr__nfet_01v8_lvt_9DHFGX
+XXM30 m1_18270_400# VOP VOP m1_20160_2025# m1_20160_2025# m1_18270_400# VOP VOP m1_20160_2025#
++ m1_18270_400# VOP PSUB VOP VOP VOP m1_20160_2025# m1_18270_400# m1_20160_2025# m1_18270_400#
++ m1_20160_2025# VOP VOP sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4
+XXM31 m1_19235_6325# AMP AMP m1_20160_2025# m1_20160_2025# m1_19235_6325# AMP AMP
++ m1_20160_2025# m1_19235_6325# AMP PSUB AMP AMP AMP m1_20160_2025# m1_19235_6325#
++ m1_20160_2025# m1_19235_6325# m1_20160_2025# AMP AMP sky130_fd_pr__pfet_01v8_lvt_D3ZSZ4
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_75KH85 a_n93_n64# a_n35_n161# a_93_n161# w_n359_n284#
++ a_35_n64# a_n163_n161# a_n221_n64# a_163_n64#
+X0 a_n93_n64# a_n163_n161# a_n221_n64# w_n359_n284# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X1 a_163_n64# a_93_n161# a_35_n64# w_n359_n284# sky130_fd_pr__pfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=350000u
+X2 a_35_n64# a_n35_n161# a_n93_n64# w_n359_n284# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=350000u
+.ends
+
+.subckt core_osc_amp INB INA VDD BIAS GND OUTB OUTA SUB
+XXM1 m1_3550_1144# m1_3550_1144# m1_3550_1144# GND GND m1_3550_1144# m1_3550_1144#
++ m1_3550_1144# GND GND m1_3550_1144# GND m1_3550_1144# BIAS m1_3550_1144# SUB GND
++ GND m1_3550_1144# m1_3550_1144# GND GND GND sky130_fd_pr__nfet_01v8_lvt_YTLFGX
+XXM2 OUTA SUB m1_3550_1144# OUTA m1_3550_1144# OUTA INA INA sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXM3 OUTB SUB m1_3550_1144# OUTB m1_3550_1144# OUTB INB INB sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXR16 VDD OUTA SUB sky130_fd_pr__res_high_po_2p85_P79JE3
+XXM4 m1_3550_1144# m1_3550_1144# m1_3550_1144# GND GND m1_3550_1144# m1_3550_1144#
++ m1_3550_1144# GND GND m1_3550_1144# GND m1_3550_1144# BIAS m1_3550_1144# SUB GND
++ GND m1_3550_1144# m1_3550_1144# GND GND GND sky130_fd_pr__nfet_01v8_lvt_YTLFGX
+XXR17 VDD OUTB SUB sky130_fd_pr__res_high_po_2p85_P79JE3
+.ends
+
+.subckt core_osc VDD GND S1B S1A S3A S3B S4B S4A BIAS S2B S2A SUB
+XX4 S3B S3A VDD BIAS GND S4B S4A SUB core_osc_amp
+XX1 S4A S4B VDD BIAS GND S1B S1A SUB core_osc_amp
+XX2 S1B S1A VDD BIAS GND S2B S2A SUB core_osc_amp
+XX3 S2B S2A VDD BIAS GND S3B S3A SUB core_osc_amp
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_YZEQ6M a_n573_n3472# a_n703_n3602# a_n573_3040#
+X0 a_n573_n3472# a_n573_3040# a_n703_n3602# sky130_fd_pr__res_high_po_5p73 l=3.04e+07u
+.ends
+
+.subckt buffer_amp INB INA VDD BIAS OUTB GND OUTA SUB
+XXR1 OUTB SUB VDD sky130_fd_pr__res_high_po_5p73_YZEQ6M
+XXR2 OUTA SUB VDD sky130_fd_pr__res_high_po_5p73_YZEQ6M
+XXM1 m1_6810_1630# BIAS BIAS BIAS GND SUB m1_6810_1630# m1_6810_1630# BIAS GND BIAS
++ GND BIAS m1_6810_1630# GND BIAS m1_6810_1630# GND BIAS BIAS GND BIAS sky130_fd_pr__nfet_01v8_lvt_9DHFGX
+XXM2 m1_6810_1630# INB OUTB SUB sky130_fd_pr__nfet_01v8_lvt_648S5X
+XXM3 m1_6810_1630# INA OUTA SUB sky130_fd_pr__nfet_01v8_lvt_648S5X
+XXM4 m1_6810_1630# BIAS BIAS BIAS GND SUB m1_6810_1630# m1_6810_1630# BIAS GND BIAS
++ GND BIAS m1_6810_1630# GND BIAS m1_6810_1630# GND BIAS BIAS GND BIAS sky130_fd_pr__nfet_01v8_lvt_9DHFGX
+.ends
+
+.subckt sky130_fd_pr__res_high_po_2p85_MXEQGY a_n285_4200# a_n285_n4632# a_n415_n4762#
+X0 a_n285_n4632# a_n285_4200# a_n415_n4762# sky130_fd_pr__res_high_po_2p85 l=4.2e+07u
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_4RCNTW c1_n2050_n3000# m3_n2150_n3100#
+X0 c1_n2050_n3000# m3_n2150_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=2e+07u
+.ends
+
+.subckt amp_dec AMP IN4 IN3 IN2 IN1 VDD GND SUB
+XXM25 AMP SUB VDD AMP VDD AMP IN3 IN3 sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXM26 AMP SUB VDD AMP VDD AMP IN4 IN4 sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXM27 AMP SUB VDD AMP VDD AMP IN2 IN2 sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXM28 AMP SUB VDD AMP VDD AMP IN1 IN1 sky130_fd_pr__nfet_01v8_lvt_HNLS5R
+XXR18 AMP GND SUB sky130_fd_pr__res_high_po_2p85_MXEQGY
+XXC1 AMP GND sky130_fd_pr__cap_mim_m3_1_4RCNTW
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_6BNFGK a_543_n100# a_159_n100# a_n273_122# a_255_n100#
++ a_351_n100# a_n417_n100# a_n465_122# a_n129_n100# a_n513_n100# a_399_n188# a_63_n100#
++ a_n225_n100# a_495_122# a_111_122# a_n321_n100# a_207_n188# a_n369_n188# a_n33_n100#
++ a_n707_n274# a_303_122# a_n605_n100# a_447_n100# a_15_n188# a_n81_122# a_n177_n188#
++ a_n561_n188#
+X0 a_63_n100# a_15_n188# a_n33_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_122# a_n129_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_351_n100# a_303_122# a_255_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_159_n100# a_111_122# a_63_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n100# a_207_n188# a_159_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_447_n100# a_399_n188# a_351_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X6 a_543_n100# a_495_122# a_447_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n321_n100# a_n369_n188# a_n417_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n513_n100# a_n561_n188# a_n605_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+X9 a_n417_n100# a_n465_122# a_n513_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n225_n100# a_n273_122# a_n321_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n129_n100# a_n177_n188# a_n225_n100# a_n707_n274# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt vop_dec VOP VDD IN GND SUB
+XXR21 VOP GND SUB sky130_fd_pr__res_high_po_2p85_MXEQGY
+XXC2 IN GND sky130_fd_pr__cap_mim_m3_1_4RCNTW
+XXM41 VDD VDD IN VOP VDD VDD IN VOP VOP IN VOP VDD IN IN VOP IN IN VDD SUB IN VDD
++ VOP IN IN IN IN sky130_fd_pr__nfet_01v8_lvt_6BNFGK
+.ends
+
+.subckt buffer_amp_vop I1A I1B AMP I3B I3A I4B I4A OUT0 I2B I2A VOP OUT180 BIAS GND
++ VDD SUB
+XX4 I4B I4A VDD BIAS X6/IN GND X6/IN SUB buffer_amp
+XX5 AMP OUT270 OUT90 OUT0 OUT180 VDD GND SUB amp_dec
+XX6 VOP VDD X6/IN GND SUB vop_dec
+XX1 I1B I1A VDD BIAS OUT180 GND OUT0 SUB buffer_amp
+XX2 I2B I2A VDD BIAS X6/IN GND X6/IN SUB buffer_amp
+XX3 I3B I3A VDD BIAS OUT270 GND OUT90 SUB buffer_amp
+.ends
+
+.subckt VCO bias_calc_0/BIAS2V CTRL5 CTRL4 VDD CTRL3 bias_calc_0/VCTRL CTRL2 output_buffer_0/OUTB
++ CTRL1 output_buffer_0/OUTA GND
+XX4 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X4/IN GND cap_bank
+XX5 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X5/IN GND cap_bank
+XX6 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X6/IN GND cap_bank
+Xoutput_buffer_0 X3/OUT180 X3/OUT0 VDD X3/BIAS output_buffer_0/OUTB GND output_buffer_0/OUTA
++ GND output_buffer
+XX10 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X3/I4B GND cap_bank
+XX7 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X7/IN GND cap_bank
+XX8 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X8/IN GND cap_bank
+XX11 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X3/I4A GND cap_bank
+XX9 CTRL5 CTRL4 CTRL2 CTRL3 CTRL1 X9/IN GND cap_bank
+Xbias_calc_0 X3/AMP bias_calc_0/VCTRL VDD X3/BIAS X3/VOP VDD bias_calc_0/BIAS2V GND
++ GND bias_calc
+Xsky130_fd_pr__pfet_01v8_lvt_75KH85_0 VDD bias_calc_0/BIAS2V bias_calc_0/BIAS2V VDD
++ bias_calc_0/BIAS2V bias_calc_0/BIAS2V bias_calc_0/BIAS2V VDD sky130_fd_pr__pfet_01v8_lvt_75KH85
+XX1 VDD GND X4/IN X5/IN X9/IN X8/IN X3/I4B X3/I4A X3/BIAS X6/IN X7/IN GND core_osc
+XX3 X5/IN X4/IN X3/AMP X8/IN X9/IN X3/I4B X3/I4A X3/OUT0 X6/IN X7/IN X3/VOP X3/OUT180
++ X3/BIAS GND VDD GND buffer_amp_vop
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[1]
++ io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4] io_analog[5]
++ io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+XVCO_0 REF io_in[18] io_in[17] vccd2 io_in[16] VCTRL io_in_3v3[15] io_analog[8] io_in[14]
++ io_analog[9] vssa2 VCO
+.ends
+

mag/user_analog_project_wrapper_empty.mag

diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/user_analog_project_wrapper_empty.mag
index 0dc5bd5..02dbe79 100644
--- a/mag/user_analog_project_wrapper_empty.mag
+++ b/mag/user_analog_project_wrapper_empty.mag
@@ -1,5 +1,5 @@
 magic
-tech $PDK
+tech sky130A
 timestamp 1632839657
 << checkpaint >>
 rect -680 351370 292680 352680

mag/vop_dec.ext

diff --git a/mag/vop_dec.ext b/mag/vop_dec.ext
new file mode 100644
index 0000000..17302c2
--- /dev/null
+++ b/mag/vop_dec.ext
@@ -0,0 +1,83 @@
+timestamp 1662515827
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__res_high_po_2p85_MXEQGY XR21 1 0 6051 0 1 5198
+use sky130_fd_pr__nfet_01v8_lvt_6BNFGK XM41 0 1 6970 -1 0 9063
+use sky130_fd_pr__cap_mim_m3_1_4RCNTW XC2 1 0 8750 0 1 3500
+node "GND" 0 1703.66 5720 520 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 343200 2360 499200 2840 488800 2920 0 0 0 0 0 0
+node "VDD" 6 836.989 6870 8460 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82400 3780 452400 3700 0 0 0 0 0 0 0 0
+node "IN" 8 3644.15 6780 8340 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 239800 7480 48400 1100 1300000 7300 344000 2520 0 0 0 0
+node "VOP" 3 1727.62 5770 9400 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 315900 5240 871500 5500 0 0 0 0 0 0 0 0
+node "SUB" 96 147.502 6430 8350 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12000 680 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_6430_9730#" 96 147.502 6430 9730 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12000 680 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_6430_9730#" "VOP" 84.1288
+cap "SUB" "li_6430_9730#" 6.26866
+cap "VDD" "VOP" 4770.98
+cap "IN" "VOP" 1690.75
+cap "VDD" "IN" 1924.28
+cap "XR21/a_n285_n4632#" "XR21/a_n415_n4762#" 333.254
+cap "XR21/a_n285_n4632#" "XC2/c1_n2050_n3000#" -733.408
+cap "IN" "XC2/m3_n2150_n3100#" 15.1892
+cap "XM41/a_111_122#" "XC2/m3_n2150_n3100#" 265.005
+cap "XR21/a_n285_4200#" "XM41/a_n561_n188#" 9.97343
+cap "XR21/a_n285_4200#" "XM41/a_n707_n274#" 53.2991
+cap "XM41/a_n707_n274#" "XM41/a_n561_n188#" 88.9029
+cap "XM41/a_n605_n100#" "XR21/a_n285_4200#" -431.126
+cap "XM41/a_n605_n100#" "XM41/a_n561_n188#" -2.03943
+cap "XM41/a_n605_n100#" "XM41/a_n707_n274#" 6.35197
+cap "XM41/a_n561_n188#" "XM41/a_n605_n100#" 14.0271
+cap "XM41/a_n707_n274#" "XR21/a_n285_4200#" 1.42109e-14
+cap "XM41/a_n561_n188#" "XR21/a_n285_4200#" -10.1361
+cap "XM41/a_n707_n274#" "XM41/a_n561_n188#" -9.1662
+cap "XM41/a_n605_n100#" "XR21/a_n285_4200#" -237.852
+cap "XM41/a_n707_n274#" "XM41/a_n605_n100#" 69.0627
+cap "XM41/a_n561_n188#" "XM41/a_n605_n100#" -13.749
+cap "XM41/a_n561_n188#" "XR21/a_n285_4200#" 89.1313
+cap "XM41/a_n561_n188#" "XM41/a_n707_n274#" 43.2585
+cap "XM41/a_n605_n100#" "XR21/a_n285_4200#" -1062.68
+cap "XM41/a_n605_n100#" "XM41/a_n707_n274#" 19.2494
+cap "XR21/a_n285_4200#" "XM41/a_n707_n274#" 380.255
+cap "XM41/a_n605_n100#" "XR21/a_n285_4200#" -578.48
+cap "XM41/a_n707_n274#" "XR21/a_n285_4200#" 5.41419
+cap "XM41/a_n561_n188#" "XR21/a_n285_4200#" -16.8613
+cap "XM41/a_n605_n100#" "XM41/a_n707_n274#" 217.015
+cap "XM41/a_n605_n100#" "XM41/a_n561_n188#" 98.2017
+cap "XM41/a_n707_n274#" "XM41/a_n561_n188#" 8.32725
+merge "XM41/a_n81_122#" "XM41/a_n177_n188#" -13417 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -17368648 -2496 0 0 -3580000 0 -3843400 -1562 0 0 0 0
+merge "XM41/a_n177_n188#" "XM41/a_n273_122#"
+merge "XM41/a_n273_122#" "XM41/a_n369_n188#"
+merge "XM41/a_n369_n188#" "XM41/a_n465_122#"
+merge "XM41/a_n465_122#" "XM41/a_n561_n188#"
+merge "XM41/a_n561_n188#" "XM41/a_495_122#"
+merge "XM41/a_495_122#" "XM41/a_399_n188#"
+merge "XM41/a_399_n188#" "XM41/a_303_122#"
+merge "XM41/a_303_122#" "XM41/a_207_n188#"
+merge "XM41/a_207_n188#" "XM41/a_111_122#"
+merge "XM41/a_111_122#" "XM41/a_15_n188#"
+merge "XM41/a_15_n188#" "XC2/c1_n2050_n3000#"
+merge "XC2/c1_n2050_n3000#" "IN"
+merge "XM41/a_n707_n274#" "li_6430_9730#" 432.966 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 818628 -580 0 0 0 0 0 0 0 0 0 0 0 0
+merge "li_6430_9730#" "XC2/VSUBS"
+merge "XC2/VSUBS" "SUB"
+merge "SUB" "XR21/a_n415_n4762#"
+merge "XR21/a_n415_n4762#" "VSUBS"
+merge "XC2/m3_n2150_n3100#" "XR21/a_n285_n4632#" -3053.37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -95734 -1942 0 0 -7982400 -1160 0 0 0 0 0 0
+merge "XR21/a_n285_n4632#" "GND"
+merge "XM41/a_n33_n100#" "XM41/a_n225_n100#" 6770.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11813060 -3444 0 0 0 0 0 0 0 0 0 0
+merge "XM41/a_n225_n100#" "XM41/a_n417_n100#"
+merge "XM41/a_n417_n100#" "XM41/a_n605_n100#"
+merge "XM41/a_n605_n100#" "XM41/a_543_n100#"
+merge "XM41/a_543_n100#" "XM41/a_351_n100#"
+merge "XM41/a_351_n100#" "XM41/a_159_n100#"
+merge "XM41/a_159_n100#" "VDD"
+merge "XM41/a_n129_n100#" "XM41/a_n321_n100#" 8103.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14337168 -4894 0 0 0 0 0 0 0 0 0 0
+merge "XM41/a_n321_n100#" "XM41/a_n513_n100#"
+merge "XM41/a_n513_n100#" "XR21/a_n285_4200#"
+merge "XR21/a_n285_4200#" "XM41/a_447_n100#"
+merge "XM41/a_447_n100#" "XM41/a_255_n100#"
+merge "XM41/a_255_n100#" "XM41/a_63_n100#"
+merge "XM41/a_63_n100#" "VOP"

mag/vop_dec.mag

diff --git a/mag/vop_dec.mag b/mag/vop_dec.mag
new file mode 100644
index 0000000..1ae4ea2
--- /dev/null
+++ b/mag/vop_dec.mag
@@ -0,0 +1,186 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1662515827
+<< locali >>
+rect 6430 9730 6730 9770
+rect 6430 8350 6730 8390
+<< metal1 >>
+rect 5770 9810 6340 9830
+rect 5770 9420 5780 9810
+rect 6320 9420 6340 9810
+rect 5770 9400 6340 9420
+rect 6780 8400 6840 9670
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+rect 7420 8310 7860 8320
+rect 5720 1000 6380 1040
+rect 5720 560 5760 1000
+rect 6340 560 6380 1000
+rect 5720 520 6380 560
+<< via1 >>
+rect 5780 9420 6320 9810
+rect 7000 9610 7060 9670
+rect 6880 9510 6940 9570
+rect 7000 9420 7060 9480
+rect 6880 9320 6940 9380
+rect 7000 9230 7060 9290
+rect 6880 9130 6940 9190
+rect 7000 9030 7060 9090
+rect 6880 8940 6940 9000
+rect 7000 8840 7060 8900
+rect 6880 8750 6940 8810
+rect 7000 8650 7060 8710
+rect 6880 8550 6940 8610
+rect 7000 8450 7060 8510
+rect 7440 8320 7840 8410
+rect 5760 560 6340 1000
+<< metal2 >>
+rect 5600 9810 6950 9830
+rect 5600 9420 5780 9810
+rect 6320 9570 6950 9810
+rect 6320 9510 6880 9570
+rect 6940 9510 6950 9570
+rect 6320 9420 6950 9510
+rect 5600 9400 6950 9420
+rect 6650 9380 6950 9400
+rect 6650 9320 6880 9380
+rect 6940 9320 6950 9380
+rect 6650 9190 6950 9320
+rect 6650 9130 6880 9190
+rect 6940 9130 6950 9190
+rect 6650 9000 6950 9130
+rect 6650 8940 6880 9000
+rect 6940 8940 6950 9000
+rect 6650 8810 6950 8940
+rect 6650 8750 6880 8810
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+rect 6650 8610 6950 8750
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+rect 7420 8310 7860 8320
+rect 5600 1000 6380 1040
+rect 5600 560 5760 1000
+rect 6340 560 6380 1000
+rect 5600 400 6380 560
+<< via2 >>
+rect 7460 8320 7820 8410
+rect 5760 560 6340 1000
+<< metal3 >>
+rect 7440 8410 7840 9990
+rect 7440 8320 7460 8410
+rect 7820 8320 7840 8410
+rect 7440 6920 7840 8320
+rect 7440 6760 7460 6920
+rect 7820 6760 7840 6920
+rect 7440 6740 7840 6760
+rect 5720 1000 6660 1040
+rect 5720 560 5760 1000
+rect 6340 560 6660 1000
+rect 5720 520 6660 560
+<< via3 >>
+rect 7460 6760 7820 6920
+<< metal4 >>
+rect 7440 6920 7840 6940
+rect 7440 6760 7460 6920
+rect 7820 6760 7840 6920
+rect 7440 6080 7840 6760
+use sky130_fd_pr__cap_mim_m3_1_4RCNTW  XC2
+timestamp 1662404926
+transform 1 0 8750 0 1 3500
+box -2150 -3100 2149 3100
+use sky130_fd_pr__nfet_01v8_lvt_6BNFGK  XM41
+timestamp 1662404926
+transform 0 1 6970 -1 0 9063
+box -743 -310 743 310
+use sky130_fd_pr__res_high_po_2p85_MXEQGY  XR21
+timestamp 1662404926
+transform 1 0 6051 0 1 5198
+box -451 -4798 451 4798
+<< labels >>
+rlabel metal2 5600 400 5760 1040 1 GND
+rlabel metal2 5600 9400 5780 9830 1 VOP
+rlabel metal2 6990 9680 7280 9990 1 VDD
+rlabel metal3 7440 8410 7840 9990 1 IN
+rlabel locali 6430 8350 6730 8390 1 SUB
+<< end >>