commit	6300d2ad1d6ff7ed51ea6c4e0aabe4d293dc8c46	[log] [tgz]
author	DaveX13342 <zeweix@andrew.cmu.edu>	Sun Sep 11 19:58:13 2022 +0000
committer	DaveX13342 <zeweix@andrew.cmu.edu>	Sun Sep 11 19:58:13 2022 +0000
tree	89473e6651b1c04b083b54462c61cf3fcdbeb8e5
parent	7d5d46aa8658b38ccf4624e76ff4761bcc4d32a8 [diff]

xschem file updated with top level made

xschem/VCO.sch[Added - diff]
xschem/VCO.sym[Added - diff]
xschem/amp_dec.sch[Added - diff]
xschem/amp_dec.sym[Added - diff]
xschem/analog_wrapper_tb.sch[Deleted - diff]
xschem/analog_wrapper_tb.spice[Deleted - diff]
xschem/bias_calc.sch[Added - diff]
xschem/bias_calc.sym[Added - diff]
xschem/buffer_amp.sch[Added - diff]
xschem/buffer_amp.sym[Added - diff]
xschem/buffer_amp_vop.sch[Added - diff]
xschem/buffer_amp_vop.sym[Added - diff]
xschem/cap_bank.sch[Added - diff]
xschem/cap_bank.sym[Added - diff]
xschem/core_osc.sch[Added - diff]
xschem/core_osc.sym[Added - diff]
xschem/core_osc_amp.sch[Added - diff]
xschem/core_osc_amp.sym[Added - diff]
xschem/current_test.spice[Deleted - diff]
xschem/example_por.sch[Deleted - diff]
xschem/example_por.sym[Deleted - diff]
xschem/example_por_tb.sch[Deleted - diff]
xschem/example_por_tb.spice[Deleted - diff]
xschem/example_por_tb.spice.orig[Deleted - diff]
xschem/output_buffer.sch[Added - diff]
xschem/output_buffer.sym[Added - diff]
xschem/test.data[Deleted - diff]
xschem/threshold_test_tb.spice[Deleted - diff]
xschem/user_analog_project_wrapper.sch[diff]
xschem/user_analog_project_wrapper.spice[diff]
xschem/vop_dec.sch[Added - diff]
xschem/vop_dec.sym[Added - diff]

32 files changed

tree: 89473e6651b1c04b083b54462c61cf3fcdbeb8e5

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.