testbench fixes

verilog/dv/la_test1/la_test1_tb.v

diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index 971b238..930278a 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -38,7 +38,7 @@
 		clock = 0;
 	end
 
-	``ifdef ENABLE_SDF
+	`ifdef ENABLE_SDF
 		initial begin
 			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
 			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;

verilog/dv/mprj_stimulus/mprj_stimulus_tb.v

diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 5b9d858..233fd11 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -175,7 +175,7 @@
         RSTB <= 1'b0;
         #2000;
         RSTB <= 1'b1;       	// Release reset
-        #1_100_000;
+        #1_300_000;
         CSB <= 1'b0;		// Stop driving CSB
     end
 
@@ -242,4 +242,4 @@
     );
 
 endmodule
-`default_nettype wire
\ No newline at end of file
+`default_nettype wire