updated sdf back annotation
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v index f929a95..0ccc511 100644 --- a/verilog/dv/io_ports/io_ports_tb.v +++ b/verilog/dv/io_ports/io_ports_tb.v
@@ -63,6 +63,7 @@ $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v index b75f5b8..6aeceb1 100644 --- a/verilog/dv/la_test1/la_test1_tb.v +++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -56,6 +56,7 @@ $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v index 45cd6cc..fff3b72 100644 --- a/verilog/dv/la_test2/la_test2_tb.v +++ b/verilog/dv/la_test2/la_test2_tb.v
@@ -57,6 +57,7 @@ $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v index 1d90ef5..a012b91 100644 --- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v +++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -35,7 +35,7 @@ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - always #16 clock <= (clock === 1'b0); + always #12.5 clock <= (clock === 1'b0); initial begin clock = 0; @@ -43,8 +43,7 @@ `ifdef ENABLE_SDF initial begin - $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ; - $sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ; + $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj.mprj) ; $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ; $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ; $sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ; @@ -59,6 +58,7 @@ $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ; @@ -175,7 +175,7 @@ RSTB <= 1'b0; #2000; RSTB <= 1'b1; // Release reset - #1_300_000; + #900_000; CSB <= 1'b0; // Stop driving CSB end
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index 99cdb34..26ff469 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -31,7 +31,7 @@ assign checkbits = mprj_io[31:16]; - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + assign mprj_io[3] = 1'b1; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -61,6 +61,7 @@ $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ; $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ; @@ -142,7 +143,7 @@ $dumpvars(0, wb_port_tb); // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (40) begin + repeat (70) begin repeat (1000) @(posedge clock); // $display("+1000 cycles"); end @@ -173,7 +174,7 @@ CSB <= 1'b1; // Force CSB high #2000; RSTB <= 1'b1; // Release reset - #1_000_000; + #100000; CSB = 1'b0; // CSB can be released end