commit 1836cff85d9ac640e22f9345ceb2b7131aa2a88d
author jeffdi <jeffdi@efabless.com> Wed Oct 12 17:28:45 2022 -0700
committer jeffdi <jeffdi@efabless.com> Wed Oct 12 17:28:45 2022 -0700
tree 2909ce063c4ecac00a7508a7c2facc1147480b8b
parent b4d0b47c67907a4d7a17cb72818939cdfd04f000

update config.json

openlane/user_project_wrapper/config.json

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 1ddcc07..5bc34d9 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -6,7 +6,7 @@
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
     "MACRO_PLACEMENT_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_proj_example/macro.cfg",
-    "VERILOG_FILES_BLACKBOX": "/home/jeffdi/caravel-gf180mcu/verilog/rtl/defines.v /home/jeffdi/caravel_user_project_gf/verilog/rtl/user_project_wrapper.v",
+    "VERILOG_FILES_BLACKBOX": "/home/jeffdi/caravel-gf180mcu/verilog/rtl/defines.v /home/jeffdi/caravel_user_project_gf/verilog/rtl/user_proj_example.v",
     "EXTRA_LEFS": "/home/jeffdi/caravel_user_project_gf/lef/user_proj_example.lef",
     "EXTRA_GDS_FILES": "/home/jeffdi/caravel_user_project_gf/gds/user_proj_example.gds",
     "FP_PDN_CHECK_NODES": 0,