correction, chaos_automoton_full is backup, chaos_automoton now utilizes subarray
diff --git a/gds/chaos_subarray.gds b/gds/chaos_subarray.gds
index 99e039f..c94f279 100644
--- a/gds/chaos_subarray.gds
+++ b/gds/chaos_subarray.gds
Binary files differ
diff --git a/mag/chaos_subarray.mag b/mag/chaos_subarray.mag
index bcd9085..052f497 100644
--- a/mag/chaos_subarray.mag
+++ b/mag/chaos_subarray.mag
@@ -1,7 +1,7 @@
magic
tech sky130B
magscale 1 2
-timestamp 1659665621
+timestamp 1659713156
<< viali >>
rect 1869 117249 1903 117283
rect 5549 117249 5583 117283
diff --git a/maglef/chaos_subarray.mag b/maglef/chaos_subarray.mag
index c1b9388..910cd35 100644
--- a/maglef/chaos_subarray.mag
+++ b/maglef/chaos_subarray.mag
@@ -1,7 +1,7 @@
magic
tech sky130B
magscale 1 2
-timestamp 1659665645
+timestamp 1659713179
<< obsli1 >>
rect 1104 2159 178848 117521
<< obsm1 >>
@@ -415,7 +415,7 @@
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 36487886
-string GDS_FILE /home/alex/chaos_automaton_Summer_2022/openlane/chaos_subarray/runs/22_08_04_22_09/results/signoff/chaos_subarray.magic.gds
+string GDS_FILE /home/alex/chaos_automaton_Summer_2022/openlane/chaos_subarray/runs/22_08_05_11_21/results/signoff/chaos_subarray.magic.gds
string GDS_START 141920
<< end >>
diff --git a/openlane/chaos_automaton/config.tcl b/openlane/chaos_automaton/config.tcl
index 647f51c..1650552 100755
--- a/openlane/chaos_automaton/config.tcl
+++ b/openlane/chaos_automaton/config.tcl
@@ -33,7 +33,7 @@
# 100 ns is 10 MHz
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 900"
+set ::env(DIE_AREA) "0 0 3006 3596"
# "0 0 3006 3596"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -61,4 +61,16 @@
set ::env(RUN_CVC) 1
set ::env(ROUTING_CORES) 10
-# Number of threads to be used during routing processes
\ No newline at end of file
+# Number of threads to be used during routing processes
+
+# Internal macros
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $script_dir/../../verilog/rtl/chaos_subarray.v"
+
+set ::env(EXTRA_LEFS) "\
+ $script_dir/../../lef/chaos_subarray.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/../../gds/chaos_subarray.gds"
\ No newline at end of file
diff --git a/openlane/chaos_automaton/macro_placement.cfg b/openlane/chaos_automaton/macro_placement.cfg
new file mode 100644
index 0000000..35b9e83
--- /dev/null
+++ b/openlane/chaos_automaton/macro_placement.cfg
@@ -0,0 +1,19 @@
+chaos_subarray 100.0 120.0 N
+chaos_subarray 1053.0 120.0 N
+chaos_subarray 2006.0 120.0 N
+
+chaos_subarray 100.0 819.0 N
+chaos_subarray 1053.0 819.0 N
+chaos_subarray 2006.0 819.0 N
+
+chaos_subarray 100.0 1518.0 N
+chaos_subarray 1053.0 1518.0 N
+chaos_subarray 2006.0 1518.0 N
+
+chaos_subarray 100.0 2217.0 N
+chaos_subarray 1053.0 2217.0 N
+chaos_subarray 2006.0 2217.0 N
+
+chaos_subarray 100.0 2916.0 N
+chaos_subarray 1053.0 2916.0 N
+chaos_subarray 2006.0 2916.0 N
\ No newline at end of file
diff --git a/sdc/chaos_subarray.sdc b/sdc/chaos_subarray.sdc
index bace6d6..c1e2fba 100644
--- a/sdc/chaos_subarray.sdc
+++ b/sdc/chaos_subarray.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Fri Aug 5 02:10:37 2022
+# Fri Aug 5 15:23:22 2022
###############################################################################
current_design chaos_subarray
###############################################################################
diff --git a/sdf/chaos_subarray.sdf b/sdf/chaos_subarray.sdf
index 5b9f203..14761d9 100644
--- a/sdf/chaos_subarray.sdf
+++ b/sdf/chaos_subarray.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "chaos_subarray")
- (DATE "Fri Aug 5 02:13:16 2022")
+ (DATE "Fri Aug 5 15:25:31 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.1")
diff --git a/signoff/chaos_subarray/metrics.csv b/signoff/chaos_subarray/metrics.csv
index 7faa037..dd120c2 100644
--- a/signoff/chaos_subarray/metrics.csv
+++ b/signoff/chaos_subarray/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-/home/alex/chaos_automaton_Summer_2022/openlane/chaos_subarray,chaos_subarray,22_08_04_22_09,flow completed,0h10m3s0ms,0h3m9s0ms,-2.0,0.54,-1,39.46,3266.2,-1,0,0,0,0,0,0,0,7,0,-1,-1,339084,103313,-26.09,-26.09,0.0,0.0,-1,-26.09,-26.09,0.0,0.0,-1,132918716.0,0.0,31.47,19.28,0.8,0.26,-1,1040,7346,1040,7346,0,0,0,6500,0,100,0,0,0,0,0,0,2,6600,5,424,7276,0,7700,514032.2304,0.012,0.00293,0.000174,0.0154,0.00382,2.02e-07,0.0179,0.00456,3.87e-07,1.9400000000000004,26.0,38.46153846153846,25,AREA 0,12,50,1,153.6,153.18,0.48,0.3,sky130_fd_sc_hd,4,4
+/home/alex/chaos_automaton_Summer_2022/openlane/chaos_subarray,chaos_subarray,22_08_05_11_21,flow completed,0h10m5s0ms,0h2m41s0ms,-2.0,0.54,-1,39.46,3587.66,-1,0,0,0,0,0,0,0,7,0,-1,-1,339084,103313,-26.09,-26.09,0.0,0.0,-1,-26.09,-26.09,0.0,0.0,-1,132918716.0,0.0,31.47,19.28,0.8,0.26,-1,1040,7346,1040,7346,0,0,0,6500,0,100,0,0,0,0,0,0,2,6600,5,424,7276,0,7700,514032.2304,0.012,0.00293,0.000174,0.0154,0.00382,2.02e-07,0.0179,0.00456,3.87e-07,1.9400000000000004,26.0,38.46153846153846,25,AREA 0,12,50,1,153.6,153.18,0.48,0.3,sky130_fd_sc_hd,4,4
diff --git a/verilog/rtl/chaos_automaton.v b/verilog/rtl/chaos_automaton.v
index 7d63c06..7e38d40 100644
--- a/verilog/rtl/chaos_automaton.v
+++ b/verilog/rtl/chaos_automaton.v
@@ -13,6 +13,9 @@
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
+// NOTE: Remove the following line before synthesizing
+// `define MPRJ_IO_PADS 38
+
`default_nettype none
/*
*-------------------------------------------------------------
@@ -81,9 +84,14 @@
* the cell address, (2) Apply the shift cycle, (3) Read the configuration
* data, (4) Apply the finish cycle.
*
+ *
+ * This version uses the chaos_subarray, which is intended to be
+ * prehardened as a macro and tiled in the top level.
*-------------------------------------------------------------
*/
+`include "chaos_subarray.v"
+
/*
*-----------------------------------------------------------------
* User project top level
@@ -91,9 +99,11 @@
*/
module chaos_automaton #(
- parameter XSIZE = 10, // Number of cells left to right
- parameter YSIZE = 10, // Number of cells top to bottom
- parameter ASIZE = 9, // Enough bits to count XSIZE * YSIZE
+ parameter XSIZE = 30, // Total number of cells left to right
+ parameter YSIZE = 30, // Total number of cells top to bottom
+ parameter XTOP = 3, // Number of sub-arrays left to right
+ parameter YTOP = 3, // Number of sub-arrays top to bottom
+ parameter ASIZE = 10, // Enough bits to count XSIZE * YSIZE
parameter BASE_ADR = 32'h 3000_0000 // Wishbone base address
)(
`ifdef USE_POWER_PINS
@@ -208,6 +218,8 @@
chaos_array #(
.XSIZE(XSIZE),
.YSIZE(YSIZE),
+ .XTOP(XTOP),
+ .YTOP(YTOP),
.BASE_ADR(BASE_ADR)
) chaos_array_inst (
`ifdef USE_POWER_PINS
@@ -391,110 +403,16 @@
endmodule
/*
- * Chaos automaton base cell definitions: Map directions to
- * array indexes, in clockwise order
- */
-
-`define NORTH 3
-`define EAST 2
-`define SOUTH 1
-`define WEST 0
-
-/*
- *-----------------------------------------------------------------
- * Chaos base cell (four 4-input LUTs + data load circuitry)
- *-----------------------------------------------------------------
- */
-
-module chaos_cell (
-`ifdef USE_POWER_PINS
- inout vccd1, // User area 1 1.8V supply
- inout vssd1, // User area 1 digital ground
-`endif
-
- input inorth, isouth, ieast, iwest,
- output onorth, osouth, oeast, owest,
- input clk, /* Serial load clock */
- input reset, /* System reset */
- input hold, /* Data latch signal */
- input idata, /* Shift register input */
- output odata /* Shift register output */
-);
-
- reg [15:0] lutfunc [3:0]; /* LUT configuration data */
- reg [15:0] lutdata [3:0]; /* Latched LUT configuration data */
- wire [3:0] inesw;
- wire [3:0] ieswn;
- wire [3:0] iswne;
- wire [3:0] iwnes;
-
- /* Gather inputsinto arrays. There is one array per direction, so */
- /* that the array is always oriented relative to the position of */
- /* the output being generated. */
-
- assign inesw = {inorth, ieast, isouth, iwest};
- assign ieswn = {ieast, isouth, iwest, inorth};
- assign iswne = {isouth, iwest, inorth, ieast};
- assign iwnes = {iwest, inorth, ieast, isouth};
-
- /* Core functions */
- /* The four LUTs define each output as a function of the four inputs */
- /* To do: Make everything rotationally symmetric */
-
- /* NOTE: condition of zeroing on hold == 0 is needed to make */
- /* simulation run; otherwise outputs are all X. The system will */
- /* work without it. */
-
- assign onorth = (!hold) ? 0 : lutdata[`NORTH][inesw];
- assign oeast = (!hold) ? 0 : lutdata[`EAST][ieswn];
- assign osouth = (!hold) ? 0 : lutdata[`SOUTH][iswne];
- assign owest = (!hold) ? 0 : lutdata[`WEST][iwnes];
-
- /* Inferred latches from shift register */
-
- always @* begin
- if (!hold) begin
- lutdata[0] = lutfunc[0];
- lutdata[1] = lutfunc[1];
- lutdata[2] = lutfunc[2];
- lutdata[3] = lutfunc[3];
- end
- end
-
- /* Implement the shift register operation */
-
- always @(posedge clk or posedge reset) begin
- if (reset == 1'b1) begin
- lutfunc[`NORTH] <= 16'd0;
- lutfunc[`SOUTH] <= 16'd0;
- lutfunc[`EAST] <= 16'd0;
- lutfunc[`WEST] <= 16'd0;
- end else begin
- lutfunc[`NORTH][15:1] <= lutfunc[`NORTH][14:0];
- lutfunc[`EAST][15:1] <= lutfunc[`EAST][14:0];
- lutfunc[`SOUTH][15:1] <= lutfunc[`SOUTH][14:0];
- lutfunc[`WEST][15:1] <= lutfunc[`WEST][14:0];
-
- lutfunc[`NORTH][0] <= idata;
- lutfunc[`EAST][0] <= lutfunc[`NORTH][15];
- lutfunc[`SOUTH][0] <= lutfunc[`EAST][15];
- lutfunc[`WEST][0] <= lutfunc[`SOUTH][15];
- end
- end
-
- assign odata = lutfunc[`WEST][15];
-
-endmodule
-
-/*
*-----------------------------------------------------------------
* Chaos array (XSIZE * YSIZE)
*-----------------------------------------------------------------
*/
module chaos_array #(
- parameter XSIZE = 20,
- parameter YSIZE = 20,
+ parameter XSIZE = 30, /* Total number of cells in X */
+ parameter YSIZE = 30, /* Total number of cells in Y */
+ parameter XTOP = 3, /* Number of sub-arrays in X */
+ parameter YTOP = 3, /* Number of sub-arrays in Y */
parameter BASE_ADR = 32'h3000_0000
)(
`ifdef USE_POWER_PINS
@@ -508,51 +426,71 @@
input write,
input [63:0] wdata,
output [63:0] rdata,
- input [2*XSIZE + 2*YSIZE - 1:0] data_in,
- output [2*XSIZE + 2*YSIZE - 1:0] data_out
+ input [2*XSIZE + 2*YSIZE - 1:0] data_in, // Perimeter I/O
+ output [2*XSIZE + 2*YSIZE - 1:0] data_out // Perimeter I/O
);
- wire [XSIZE - 1: 0] uconn [YSIZE: 0];
- wire [XSIZE - 1: 0] dconn [YSIZE: 0];
- wire [YSIZE - 1: 0] rconn [XSIZE: 0];
- wire [YSIZE - 1: 0] lconn [XSIZE: 0];
+ wire [XSIZE - 1: 0] uconn [YTOP: 0];
+ wire [XSIZE - 1: 0] dconn [YTOP: 0];
+ wire [YSIZE - 1: 0] rconn [XTOP: 0];
+ wire [YSIZE - 1: 0] lconn [XTOP: 0];
- wire [YSIZE - 1: 0] shiftreg [XSIZE: 0];
+ wire [YTOP - 1: 0] shiftreg [XTOP: 0];
+ wire [YTOP - 1: 0] clkarray [XTOP: 0];
wire io_data_sel; // wishbone select data
wire xfer_sel; // wishbone select transfer
- // TEST: Recast some shift register columns for testing; this is
- // easier to pull into gtkwave than a 2D array.
- // wire [YSIZE - 1: 0] testshiftreg0 = shiftreg[0];
- // wire [YSIZE - 1: 0] testshiftreg10 = shiftreg[10];
- // wire [YSIZE - 1: 0] testshiftreg20 = shiftreg[20];
+ assign clkarray[0][0] = clk;
- // TEST: Recast some LUT columns for testing
- // wire [YSIZE - 1: 0] testdconn0 = dconn[0];
- // wire [YSIZE - 1: 0] testuconn20 = uconn[20];
- // wire [YSIZE - 1: 0] testlconn0 = lconn[0];
- // wire [YSIZE - 1: 0] testrconn20 = rconn[20];
+ // Sub-array architecture:
+ //
+ // dudu dudu dudu
+ // |^|^ |^|^ |^|^
+ // v|v| v|v| v|v|
+ // +------+ +------+ +------+
+ // l->| |->| |->| |->l
+ // r<-| |<-| |<-| |<-r
+ // l->| |->| |->| |->l
+ // r<-| |<-| |<-| |<-r
+ // +------+ +------+ +------+
+ // |^|^ |^|^ |^|^
+ // v|v| v|v| v|v|
+ // +------+ +------+ +------+
+ // l->| |->| |->| |->l
+ // r<-| |<-| |<-| |<-r
+ // l->| |->| |->| |->l
+ // r<-| |<-| |<-| |<-r
+ // +------+ +------+ +------+
+ // |^|^ |^|^ |^|^
+ // v|v| v|v| v|v|
+ // dudu dudu dudu
+ //
+ // Each box in the above diagram is a sub-array size 2x2.
+ // The top level has XSIZE = 6, YSIZE = 4 with XTOP = 3
+ // and YTOP = 2.
+ //
+ // The top-level inputs and outputs are the perimeter values
+ // on the four edges of the top level array.
+ //
+ // To represent all the connections among the sub-arrays, it
+ // can be seen from the above that d and u (dconn and uconn)
+ // are arrays of size (XSIZE, YTOP + 1), while l and r (lconn
+ // and rconn) are arrays of size (XTOP + 1, YSIZE).
- // wire [YSIZE - 1: 0] testdconn1 = dconn[1];
- // wire [YSIZE - 1: 0] testuconn19 = uconn[19];
- // wire [YSIZE - 1: 0] testlconn1 = lconn[1];
- // wire [YSIZE - 1: 0] testrconn19 = rconn[19];
-
- // wire [YSIZE - 1: 0] testdconn19 = dconn[19];
- // wire [YSIZE - 1: 0] testuconn1 = uconn[1];
- // wire [YSIZE - 1: 0] testlconn19 = lconn[19];
- // wire [YSIZE - 1: 0] testrconn1 = rconn[1];
+ // NOTE: For viewing internal signals in gtkwave,
+ // some 2D arrays may need to be copied into 1D arrays.
+ // See the original verilog for examples.
/* The perimeter inputs and outputs connect to the logic analyzer */
/* (To do: multiplex inputs between the chip I/O and logic analyzer */
- assign data_out = {uconn[YSIZE][XSIZE - 1:0], dconn[0][XSIZE - 1:0],
- rconn[XSIZE][YSIZE - 1:0], lconn[0][YSIZE - 1:0]};
+ assign data_out = {uconn[YTOP][XSIZE - 1:0], dconn[0][XSIZE - 1:0],
+ rconn[XTOP][YSIZE - 1:0], lconn[0][YSIZE - 1:0]};
- assign dconn[YSIZE][XSIZE - 1:0] = data_in[2*XSIZE+2*YSIZE - 1: 2*YSIZE + XSIZE];
+ assign dconn[YTOP][XSIZE - 1:0] = data_in[2*XSIZE+2*YSIZE - 1: 2*YSIZE + XSIZE];
assign uconn[0][XSIZE - 1:0] = data_in[2*YSIZE + XSIZE - 1:2*YSIZE];
assign rconn[0][YSIZE - 1:0] = data_in[2*YSIZE-1:YSIZE];
- assign lconn[XSIZE][YSIZE - 1:0] = data_in[YSIZE-1:0];
+ assign lconn[XTOP][YSIZE - 1:0] = data_in[YSIZE-1:0];
genvar i, j;
@@ -563,22 +501,30 @@
* i = 0 to N - 1 with j set to zero.
*/
- /* Connected array of cells */
+ /* Connected array of subarrays */
generate
- for (j = 0; j < YSIZE; j=j+1) begin: celly
- for (i = 0; i < XSIZE; i=i+1) begin: cellx
- chaos_cell chaos_cell_inst (
- .inorth(dconn[j+1][i]),
- .isouth(uconn[j][i]),
- .ieast(lconn[i+1][j]),
- .iwest(rconn[i][j]),
- .onorth(uconn[j+1][i]),
- .osouth(dconn[j][i]),
- .oeast(rconn[i+1][j]),
- .owest(lconn[i][j]),
- .clk(clk),
+ for (j = 0; j < YTOP; j=j+1) begin: subarrayx
+ for (i = 0; i < XTOP; i=i+1) begin: subarray
+ chaos_subarray #(
+ .XSIZE(XSIZE / XTOP),
+ .YSIZE(YSIZE / YTOP)
+ ) chaos_subarray_inst (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ `endif
+ .inorth(dconn[j+1][(i+1)*(XSIZE/XTOP)-1:i*(XSIZE/XTOP)]),
+ .isouth(uconn[j][(i+1)*(XSIZE/XTOP)-1:i*(XSIZE/XTOP)]),
+ .ieast(lconn[i+1][(j+1)*(YSIZE/YTOP)-1:j*(YSIZE/YTOP)]),
+ .iwest(rconn[i][(j+1)*(YSIZE/YTOP)-1:j*(YSIZE/YTOP)]),
+ .onorth(uconn[j+1][(i+1)*(XSIZE/XTOP)-1:i*(XSIZE/XTOP)]),
+ .osouth(dconn[j][(i+1)*(XSIZE/XTOP)-1:i*(XSIZE/XTOP)]),
+ .oeast(rconn[i+1][(j+1)*(YSIZE/YTOP)-1:j*(YSIZE/YTOP)]),
+ .owest(lconn[i][(j+1)*(YSIZE/YTOP)-1:j*(YSIZE/YTOP)]),
.reset(reset),
.hold(hold),
+ .iclk(clkarray[i][j]),
+ .oclk(clkarray[i+1][j]),
.idata(shiftreg[i][j]),
.odata(shiftreg[i+1][j])
);
@@ -588,8 +534,9 @@
/* NOTE: This would work better topologically if each */
/* row switched the direction of the shift register. */
- for (j = 0; j < YSIZE - 1; j=j+1) begin: shifty
- assign shiftreg[0][j+1] = shiftreg[XSIZE][j];
+ for (j = 0; j < YTOP - 1; j=j+1) begin: shifty
+ assign shiftreg[0][j+1] = shiftreg[XTOP][j];
+ assign clkarray[0][j+1] = clkarray[XTOP][j];
end
endgenerate
@@ -608,7 +555,7 @@
end else begin
/* Shift data on clock when "write" is not raised */
lutdata[63:1] <= lutdata[62:0];
- lutdata[0] <= shiftreg[XSIZE][YSIZE-1];
+ lutdata[0] <= shiftreg[XTOP][YTOP-1];
end
end
diff --git a/verilog/rtl/chaos_automaton.v:Zone.Identifier b/verilog/rtl/chaos_automaton.v:Zone.Identifier
new file mode 100644
index 0000000..47dbc1f
--- /dev/null
+++ b/verilog/rtl/chaos_automaton.v:Zone.Identifier
@@ -0,0 +1,3 @@
+[ZoneTransfer]
+ZoneId=3
+HostUrl=https://files.slack.com/files-pri/T0156RWKTRA-F03SLDUP59A/download/chaos_automaton.v?origin_team=T0156RWKTRA
