addition of chaos_subarray
diff --git a/openlane/chaos_subarray/base.sdc b/openlane/chaos_subarray/base.sdc new file mode 100644 index 0000000..0568075 --- /dev/null +++ b/openlane/chaos_subarray/base.sdc
@@ -0,0 +1,1237 @@ +############################################################################### +# Created by write_sdc +# Tue Aug 2 14:05:31 2022 +############################################################################### +current_design chaos_automaton +############################################################################### +# Timing Constraints +############################################################################### +create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}] +set_clock_transition 0.1500 [get_clocks {wb_clk_i}] +set_clock_uncertainty 0.2500 wb_clk_i +set_propagated_clock [get_clocks {wb_clk_i}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[0]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[100]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[101]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[102]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[103]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[104]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[105]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[106]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[107]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[108]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[109]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[10]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[110]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[111]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[112]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[113]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[114]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[115]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[116]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[117]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[118]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[119]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[11]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[120]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[121]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[122]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[123]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[124]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[125]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[126]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[127]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[12]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[13]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[14]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[15]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[16]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[17]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[18]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[19]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[1]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[20]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[21]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[22]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[23]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[24]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[25]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[26]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[27]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[28]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[29]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[2]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[30]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[31]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[32]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[33]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[34]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[35]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[36]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[37]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[38]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[39]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[3]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[40]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[41]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[42]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[43]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[44]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[45]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[46]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[47]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[48]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[49]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[4]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[50]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[51]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[52]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[53]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[54]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[55]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[56]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[57]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[58]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[59]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[5]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[60]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[61]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[62]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[63]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[64]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[65]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[66]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[67]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[68]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[69]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[6]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[70]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[71]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[72]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[73]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[74]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[75]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[76]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[77]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[78]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[79]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[7]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[80]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[81]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[82]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[83]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[84]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[85]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[86]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[87]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[88]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[89]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[8]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[90]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[91]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[92]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[93]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[94]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[95]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[96]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[97]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[98]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[99]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[9]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[0]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[100]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[101]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[102]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[103]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[104]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[105]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[106]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[107]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[108]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[109]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[10]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[110]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[111]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[112]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[113]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[114]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[115]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[116]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[117]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[118]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[119]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[11]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[120]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[121]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[122]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[123]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[124]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[125]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[126]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[127]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[12]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[13]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[14]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[15]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[16]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[17]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[18]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[19]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[1]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[20]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[21]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[22]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[23]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[24]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[25]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[26]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[27]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[28]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[29]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[2]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[30]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[31]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[32]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[33]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[34]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[35]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[36]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[37]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[38]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[39]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[3]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[40]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[41]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[42]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[43]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[44]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[45]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[46]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[47]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[48]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[49]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[4]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[50]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[51]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[52]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[53]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[54]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[55]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[56]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[57]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[58]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[59]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[5]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[60]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[61]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[62]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[63]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[64]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[65]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[66]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[67]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[68]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[69]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[6]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[70]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[71]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[72]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[73]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[74]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[75]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[76]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[77]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[78]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[79]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[7]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[80]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[81]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[82]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[83]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[84]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[85]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[86]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[87]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[88]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[89]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[8]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[90]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[91]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[92]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[93]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[94]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[95]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[96]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[97]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[98]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[99]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[9]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}] +set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[0]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[100]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[101]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[102]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[103]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[104]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[105]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[106]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[107]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[108]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[109]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[10]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[110]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[111]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[112]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[113]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[114]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[115]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[116]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[117]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[118]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[119]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[11]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[120]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[121]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[122]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[123]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[124]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[125]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[126]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[127]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[12]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[13]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[14]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[15]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[16]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[17]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[18]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[19]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[1]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[20]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[21]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[22]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[23]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[24]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[25]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[26]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[27]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[28]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[29]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[2]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[30]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[31]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[32]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[33]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[34]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[35]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[36]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[37]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[38]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[39]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[3]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[40]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[41]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[42]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[43]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[44]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[45]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[46]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[47]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[48]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[49]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[4]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[50]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[51]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[52]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[53]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[54]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[55]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[56]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[57]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[58]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[59]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[5]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[60]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[61]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[62]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[63]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[64]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[65]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[66]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[67]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[68]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[69]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[6]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[70]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[71]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[72]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[73]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[74]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[75]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[76]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[77]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[78]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[79]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[7]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[80]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[81]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[82]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[83]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[84]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[85]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[86]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[87]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[88]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[89]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[8]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[90]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[91]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[92]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[93]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[94]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[95]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[96]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[97]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[98]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[99]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[9]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] +set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] +############################################################################### +# Environment +############################################################################### +set_load -pin_load 0.0334 [get_ports {wbs_ack_o}] +set_load -pin_load 0.0334 [get_ports {io_oeb[37]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[36]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[35]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[34]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[33]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[32]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[31]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[30]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[29]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[28]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[27]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[26]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[25]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[24]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[23]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[22]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[21]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[20]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[19]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[18]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[17]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[16]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[15]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[14]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[13]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[12]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[11]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[10]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[9]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[8]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[7]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[6]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[5]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[4]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[3]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[2]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[1]}] +set_load -pin_load 0.0334 [get_ports {io_oeb[0]}] +set_load -pin_load 0.0334 [get_ports {io_out[37]}] +set_load -pin_load 0.0334 [get_ports {io_out[36]}] +set_load -pin_load 0.0334 [get_ports {io_out[35]}] +set_load -pin_load 0.0334 [get_ports {io_out[34]}] +set_load -pin_load 0.0334 [get_ports {io_out[33]}] +set_load -pin_load 0.0334 [get_ports {io_out[32]}] +set_load -pin_load 0.0334 [get_ports {io_out[31]}] +set_load -pin_load 0.0334 [get_ports {io_out[30]}] +set_load -pin_load 0.0334 [get_ports {io_out[29]}] +set_load -pin_load 0.0334 [get_ports {io_out[28]}] +set_load -pin_load 0.0334 [get_ports {io_out[27]}] +set_load -pin_load 0.0334 [get_ports {io_out[26]}] +set_load -pin_load 0.0334 [get_ports {io_out[25]}] +set_load -pin_load 0.0334 [get_ports {io_out[24]}] +set_load -pin_load 0.0334 [get_ports {io_out[23]}] +set_load -pin_load 0.0334 [get_ports {io_out[22]}] +set_load -pin_load 0.0334 [get_ports {io_out[21]}] +set_load -pin_load 0.0334 [get_ports {io_out[20]}] +set_load -pin_load 0.0334 [get_ports {io_out[19]}] +set_load -pin_load 0.0334 [get_ports {io_out[18]}] +set_load -pin_load 0.0334 [get_ports {io_out[17]}] +set_load -pin_load 0.0334 [get_ports {io_out[16]}] +set_load -pin_load 0.0334 [get_ports {io_out[15]}] +set_load -pin_load 0.0334 [get_ports {io_out[14]}] +set_load -pin_load 0.0334 [get_ports {io_out[13]}] +set_load -pin_load 0.0334 [get_ports {io_out[12]}] +set_load -pin_load 0.0334 [get_ports {io_out[11]}] +set_load -pin_load 0.0334 [get_ports {io_out[10]}] +set_load -pin_load 0.0334 [get_ports {io_out[9]}] +set_load -pin_load 0.0334 [get_ports {io_out[8]}] +set_load -pin_load 0.0334 [get_ports {io_out[7]}] +set_load -pin_load 0.0334 [get_ports {io_out[6]}] +set_load -pin_load 0.0334 [get_ports {io_out[5]}] +set_load -pin_load 0.0334 [get_ports {io_out[4]}] +set_load -pin_load 0.0334 [get_ports {io_out[3]}] +set_load -pin_load 0.0334 [get_ports {io_out[2]}] +set_load -pin_load 0.0334 [get_ports {io_out[1]}] +set_load -pin_load 0.0334 [get_ports {io_out[0]}] +set_load -pin_load 0.0334 [get_ports {irq[2]}] +set_load -pin_load 0.0334 [get_ports {irq[1]}] +set_load -pin_load 0.0334 [get_ports {irq[0]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[127]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[126]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[125]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[124]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[123]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[122]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[121]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[120]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[119]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[118]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[117]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[116]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[115]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[114]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[113]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[112]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[111]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[110]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[109]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[108]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[107]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[106]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[105]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[104]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[103]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[102]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[101]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[100]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[99]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[98]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[97]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[96]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[95]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[94]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[93]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[92]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[91]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[90]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[89]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[88]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[87]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[86]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[85]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[84]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[83]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[82]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[81]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[80]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[79]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[78]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[77]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[76]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[75]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[74]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[73]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[72]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[71]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[70]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[69]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[68]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[67]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[66]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[65]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[64]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[63]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[62]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[61]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[60]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[59]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[58]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[57]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[56]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[55]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[54]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[53]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[52]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[51]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[50]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[49]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[48]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[47]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[46]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[45]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[44]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[43]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[42]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[41]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[40]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[39]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[38]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[37]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[36]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[35]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[34]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[33]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[32]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[31]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[30]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[29]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[28]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[27]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[26]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[25]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[24]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[23]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[22]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[21]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[20]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[19]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[18]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[17]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[16]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[15]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[14]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[13]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[12]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[11]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[10]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[9]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[8]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[7]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[6]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[5]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[4]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[3]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[2]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[1]}] +set_load -pin_load 0.0334 [get_ports {la_data_out[0]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}] +set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} 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0.0000 [get_ports {wbs_adr_i[9]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}] +set_timing_derate -early 0.9500 +set_timing_derate -late 1.0500 +############################################################################### +# Design Rules +############################################################################### +set_max_fanout 12.0000 [current_design] + +set_false_path -to [get_ports {io_out[*] la_data_out[*]}] +set_false_path -from [get_ports {io_in[*] la_oenb[*] la_data_in[*]}] \ No newline at end of file
diff --git a/openlane/chaos_subarray/config.tcl b/openlane/chaos_subarray/config.tcl new file mode 100755 index 0000000..d4e0da5 --- /dev/null +++ b/openlane/chaos_subarray/config.tcl
@@ -0,0 +1,61 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set ::env(PDK) $::env(PDK) +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" + +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) chaos_automaton + +set ::env(VERILOG_FILES) "\ + $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/chaos_automaton.v" + +set ::env(DESIGN_IS_CORE) 0 + +set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_NET) "counter.clk" +set ::env(CLOCK_PERIOD) "25" +# 25 ns is 40 MHz +# 100 ns is 10 MHz + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 900 900" +# "0 0 3006 3596" + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg + +set ::env(PL_BASIC_PLACEMENT) 0 +set ::env(PL_TARGET_DENSITY) 0.49 + +set ::env(SYNTH_EXTRA_MAPPING_FILE) $script_dir/yosys_mapping.v +set ::env(SYNTH_MAX_FANOUT) 12 +set ::env(BASE_SDC_FILE) $script_dir/base.sdc + +# Maximum layer used for routing is metal 4. +# This is because this macro will be inserted in a top level (user_project_wrapper) +# where the PDN is planned on metal 5. So, to avoid having shorts between routes +# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. +# +set ::env(RT_MAX_LAYER) {met4} + +# You can draw more power domains if you need to +set ::env(VDD_NETS) [list {vccd1}] +set ::env(GND_NETS) [list {vssd1}] + +set ::env(DIODE_INSERTION_STRATEGY) 4 +# If you're going to use multiple power domains, then disable cvc run. +set ::env(RUN_CVC) 1
diff --git a/openlane/chaos_subarray/config.tcl.save b/openlane/chaos_subarray/config.tcl.save new file mode 100755 index 0000000..ae3d3c1 --- /dev/null +++ b/openlane/chaos_subarray/config.tcl.save
@@ -0,0 +1,44 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) chaos_automaton + +set ::env(VERILOG_FILES) "\ + $script_dir/../../caravel/verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/chaos_automaton.v" + +set ::env(CLOCK_PORT) "" +set ::env(CLOCK_NET) "counter.clk" +set ::env(CLOCK_PERIOD) "10" + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 900 600" +set ::env(DESIGN_IS_CORE) 0 + +set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}] +set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}] + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg + +set ::env(PL_BASIC_PLACEMENT) 1 +set ::env(PL_TARGET_DENSITY) 0.40 + + +set ::env(SYNTH_EXTRA_MAPPING_FILE) $script_dir/yosys_mapping.v + +# If you're going to use multiple power domains, then keep this disabled. +set ::env(RUN_CVC) 0
diff --git a/openlane/chaos_subarray/pin_order.cfg b/openlane/chaos_subarray/pin_order.cfg new file mode 100644 index 0000000..98feb1b --- /dev/null +++ b/openlane/chaos_subarray/pin_order.cfg
@@ -0,0 +1,157 @@ +#BUS_SORT +#NR +analog_io\[8\] +io_in\[15\] +io_out\[15\] +io_oeb\[15\] +analog_io\[9\] +io_in\[16\] +io_out\[16\] +io_oeb\[16\] +analog_io\[10\] +io_in\[17\] +io_out\[17\] +io_oeb\[17\] +analog_io\[11\] +io_in\[18\] +io_out\[18\] +io_oeb\[18\] +analog_io\[12\] +io_in\[19\] +io_out\[19\] +io_oeb\[19\] +analog_io\[13\] +io_in\[20\] +io_out\[20\] +io_oeb\[20\] +analog_io\[14\] +io_in\[21\] +io_out\[21\] +io_oeb\[21\] +analog_io\[15\] +io_in\[22\] +io_out\[22\] +io_oeb\[22\] +analog_io\[16\] +io_in\[23\] +io_out\[23\] +io_oeb\[23\] + +#S +wb_.* +wbs_.* +la_.* +user_clock2 +user_irq.* +irq.* + +#E +io_in\[0\] +io_out\[0\] +io_oeb\[0\] +io_in\[1\] +io_out\[1\] +io_oeb\[1\] +io_in\[2\] +io_out\[2\] +io_oeb\[2\] +io_in\[3\] +io_out\[3\] +io_oeb\[3\] +io_in\[4\] +io_out\[4\] +io_oeb\[4\] +io_in\[5\] +io_out\[5\] +io_oeb\[5\] +io_in\[6\] +io_out\[6\] +io_oeb\[6\] +analog_io\[0\] +io_in\[7\] +io_out\[7\] +io_oeb\[7\] +analog_io\[1\] +io_in\[8\] +io_out\[8\] +io_oeb\[8\] +analog_io\[2\] +io_in\[9\] +io_out\[9\] +io_oeb\[9\] +analog_io\[3\] +io_in\[10\] +io_out\[10\] +io_oeb\[10\] +analog_io\[4\] +io_in\[11\] +io_out\[11\] +io_oeb\[11\] +analog_io\[5\] +io_in\[12\] +io_out\[12\] +io_oeb\[12\] +analog_io\[6\] +io_in\[13\] +io_out\[13\] +io_oeb\[13\] +analog_io\[7\] +io_in\[14\] +io_out\[14\] +io_oeb\[14\] + +#WR +analog_io\[17\] +io_in\[24\] +io_out\[24\] +io_oeb\[24\] +analog_io\[18\] +io_in\[25\] +io_out\[25\] +io_oeb\[25\] +analog_io\[19\] +io_in\[26\] +io_out\[26\] +io_oeb\[26\] +analog_io\[20\] +io_in\[27\] +io_out\[27\] +io_oeb\[27\] +analog_io\[21\] +io_in\[28\] +io_out\[28\] +io_oeb\[28\] +analog_io\[22\] +io_in\[29\] +io_out\[29\] +io_oeb\[29\] +analog_io\[23\] +io_in\[30\] +io_out\[30\] +io_oeb\[30\] +analog_io\[24\] +io_in\[31\] +io_out\[31\] +io_oeb\[31\] +analog_io\[25\] +io_in\[32\] +io_out\[32\] +io_oeb\[32\] +analog_io\[26\] +io_in\[33\] +io_out\[33\] +io_oeb\[33\] +analog_io\[27\] +io_in\[34\] +io_out\[34\] +io_oeb\[34\] +analog_io\[28\] +io_in\[35\] +io_out\[35\] +io_oeb\[35\] +io_in\[36\] +io_out\[36\] +io_oeb\[36\] +io_in\[37\] +io_out\[37\] +io_oeb\[37\]
diff --git a/openlane/chaos_subarray/yosys_mapping.v b/openlane/chaos_subarray/yosys_mapping.v new file mode 100644 index 0000000..c829b86 --- /dev/null +++ b/openlane/chaos_subarray/yosys_mapping.v
@@ -0,0 +1,40 @@ + +module \$_ALDFF_PN_ (D, C, L, AD, Q); +input D, C, L, AD; +output reg Q; + +wire RN, SN; +wire L_N; + +\$_OR_ R_NAND ( .Y(RN), .A(L), .B(AD) ); +\$_NOT_ NAND_NOT ( .A(L), .Y(L_N)); +\$_NAND_ S_NAND ( .Y(SN), .A(L_N), .B(AD) ); + +\$_DFFSR_PNN_ SRFF (.C(C), + .S(SN), + .R(RN), + .D(D), + .Q(Q) +); + +endmodule + +module \$_ALDFF_PP_ (D, C, L, AD, Q); +input D, C, L, AD; +output reg Q; + +wire RN, SN; +wire L_N; + +\$_OR_ R_NAND ( .Y(RN), .A(L_N), .B(AD) ); +\$_NOT_ NAND_NOT ( .A(L), .Y(L_N)); +\$_NAND_ S_NAND ( .Y(SN), .A(L), .B(AD) ); + +\$_DFFSR_PNN_ SRFF (.C(C), + .S(SN), + .R(RN), + .D(D), + .Q(Q) +); + +endmodule
diff --git a/openlane/chaos_subarray/yosys_mapping.v:Zone.Identifier b/openlane/chaos_subarray/yosys_mapping.v:Zone.Identifier new file mode 100644 index 0000000..31d6ea0 --- /dev/null +++ b/openlane/chaos_subarray/yosys_mapping.v:Zone.Identifier
@@ -0,0 +1,3 @@ +[ZoneTransfer] +ZoneId=3 +HostUrl=https://files.slack.com/files-pri/T0156RWKTRA-F03R7DBMYH5/download/yosys_mapping.v?origin_team=T0156RWKTRA
diff --git a/verilog/rtl/chaos_subarray.v b/verilog/rtl/chaos_subarray.v new file mode 100755 index 0000000..b9bf395 --- /dev/null +++ b/verilog/rtl/chaos_subarray.v
@@ -0,0 +1,265 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * chaos_subarray + * + * This is a portion of the chaos_automaton array. The array + * has been broken up into smaller sub-arrays because the + * full design runs out of memory on a relatively ample 16GB + * machine. However, a 10x10 array could be synthesized, so + * the revised approach is to generate a macro out of the + * 10x10 array, and then tile that macro in the final design. + * For an example, the 10x10 array can be synthesized into a + * 900x900 micron area in Sky130, so there is room for a 3x3 + * array of these macros, for a total cell count of 30x30. + * + * NOTE: The programming of each cell follows the same + * method used by the GPIO control block programming in + * caravel with respect to clock and data: The clock is + * propagated from cell to cell through the array so that + * each cell's clock has a (relatively) fixed timing relative + * to the data, and does not require a massive clock tree. + * The last data bit from the cell's shift register is + * reclocked on the clock's falling edge so that the timing + * of the clock to the following cell has a large margin. + * Reset and hold, however, are global signals because the + * data update needs to be as simultaneous as the synthesis + * tools can make it. + * + *------------------------------------------------------------- + */ + +/* + * Chaos automaton base cell definitions: Map directions to + * array indexes, in clockwise order + */ + +`define NORTH 3 +`define EAST 2 +`define SOUTH 1 +`define WEST 0 + +/* + *----------------------------------------------------------------- + * Chaos base cell (four 4-input LUTs + data load circuitry) + * + * NOTE: The last data bit out is clocked on the falling edge + * of the clock so that there is no possibility of a hold + * violation between cells. + *----------------------------------------------------------------- + */ + +module chaos_cell ( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif + + input inorth, isouth, ieast, iwest, + output onorth, osouth, oeast, owest, + input iclk, /* Serial load clock (in) */ + output oclk, /* Serial load clock (out) */ + input reset, /* System reset */ + input hold, /* Data latch signal */ + input idata, /* Shift register input */ + output odata /* Shift register output */ +); + + reg [15:0] lutfunc [3:0]; /* LUT configuration data */ + reg [15:0] lutdata [3:0]; /* Latched LUT configuration data */ + reg odata; /* Latched shift register output */ + wire [3:0] inesw; + wire [3:0] ieswn; + wire [3:0] iswne; + wire [3:0] iwnes; + + /* Gather inputs into arrays. There is one array per direction, so */ + /* that the array is always oriented relative to the position of */ + /* the output being generated. */ + + assign inesw = {inorth, ieast, isouth, iwest}; + assign ieswn = {ieast, isouth, iwest, inorth}; + assign iswne = {isouth, iwest, inorth, ieast}; + assign iwnes = {iwest, inorth, ieast, isouth}; + + /* Core functions */ + /* The four LUTs define each output as a function of the four inputs */ + /* To do: Make everything rotationally symmetric */ + + /* NOTE: condition of zeroing on hold == 0 is needed to make */ + /* simulation run; otherwise outputs are all X. The system will */ + /* work without it. */ + + assign onorth = (!hold) ? 0 : lutdata[`NORTH][inesw]; + assign oeast = (!hold) ? 0 : lutdata[`EAST][ieswn]; + assign osouth = (!hold) ? 0 : lutdata[`SOUTH][iswne]; + assign owest = (!hold) ? 0 : lutdata[`WEST][iwnes]; + + /* Inferred latches from shift register */ + + always @* begin + if (!hold) begin + lutdata[0] = lutfunc[0]; + lutdata[1] = lutfunc[1]; + lutdata[2] = lutfunc[2]; + lutdata[3] = lutfunc[3]; + end + end + + /* Implement the shift register operation */ + + always @(posedge iclk or posedge reset) begin + if (reset == 1'b1) begin + lutfunc[`NORTH] <= 16'd0; + lutfunc[`SOUTH] <= 16'd0; + lutfunc[`EAST] <= 16'd0; + lutfunc[`WEST] <= 16'd0; + end else begin + lutfunc[`NORTH][15:1] <= lutfunc[`NORTH][14:0]; + lutfunc[`EAST][15:1] <= lutfunc[`EAST][14:0]; + lutfunc[`SOUTH][15:1] <= lutfunc[`SOUTH][14:0]; + lutfunc[`WEST][15:1] <= lutfunc[`WEST][14:0]; + + lutfunc[`NORTH][0] <= idata; + lutfunc[`EAST][0] <= lutfunc[`NORTH][15]; + lutfunc[`SOUTH][0] <= lutfunc[`EAST][15]; + lutfunc[`WEST][0] <= lutfunc[`SOUTH][15]; + end + end + + always @(negedge iclk or posedge reset) begin + if (reset == 1'b1) begin + odata <= 1'b0; + end else begin + odata <= lutfunc[`WEST][15]; + end + end + + /* Propagate clock */ + assign oclk = iclk; + +endmodule + +/* + *----------------------------------------------------------------- + * Chaos sub-array (XSIZE * YSIZE) + *----------------------------------------------------------------- + */ + +module chaos_subarray #( + parameter XSIZE = 10, + parameter YSIZE = 10 +)( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif + + input [XSIZE-1:0] inorth, isouth, + input [YSIZE-1:0] ieast, iwest, + output [XSIZE-1:0] onorth, osouth, + output [YSIZE-1:0] oeast, owest, + input iclk, /* Serial load clock (in) */ + output oclk, /* Serial load clock (out) */ + input reset, /* System reset */ + input hold, /* Data latch signal */ + input idata, /* Shift register input */ + output odata /* Shift register output */ +); + + wire [XSIZE - 1: 0] uconn [YSIZE: 0]; + wire [XSIZE - 1: 0] dconn [YSIZE: 0]; + wire [YSIZE - 1: 0] rconn [XSIZE: 0]; + wire [YSIZE - 1: 0] lconn [XSIZE: 0]; + + /* The shift register (data) and clock wind through the cells */ + /* to maintain consistent timing. Hold and reset are applied */ + /* simultaneously. */ + + wire [YSIZE - 1: 0] shiftreg [XSIZE: 0]; + wire [YSIZE - 1: 0] clkarray [XSIZE: 0]; + + genvar i, j; + + /* Connected array of cells */ + generate + for (j = 0; j < YSIZE; j=j+1) begin: celly + for (i = 0; i < XSIZE; i=i+1) begin: cellx + chaos_cell chaos_cell_inst ( + `ifdef USE_POWER_PINS + .vccd1(vccd1), + .vssd1(vssd1), + `endif + .inorth(dconn[j+1][i]), + .isouth(uconn[j][i]), + .ieast(lconn[i+1][j]), + .iwest(rconn[i][j]), + .onorth(uconn[j+1][i]), + .osouth(dconn[j][i]), + .oeast(rconn[i+1][j]), + .owest(lconn[i][j]), + .iclk(clkarray[i][j]), + .oclk(clkarray[i+1][j]), + .reset(reset), + .hold(hold), + .idata(shiftreg[i][j]), + .odata(shiftreg[i+1][j]) + ); + end + end + + /* NOTE: This would work better topologically if each */ + /* row switched the direction of clock and data. */ + + for (j = 0; j < YSIZE - 1; j=j+1) begin: shifty + assign shiftreg[0][j+1] = shiftreg[XSIZE][j]; + assign clkarray[0][j+1] = clkarray[XSIZE][j]; + end + + /* Connect the endpoints of the array to the inputs and outputs of the module */ + + for (j = 0; j < YSIZE; j=j+1) begin: connx + assign rconn[XSIZE][j] = ieast[j]; + assign lconn[0][j] = iwest[j]; + assign oeast[j] = rconn[XSIZE][j]; + assign owest[j] = lconn[0][j]; + end + + for (i = 0; i < XSIZE; i=i+1) begin: conny + assign uconn[YSIZE][i] = inorth[i]; + assign dconn[0][i] = isouth[i]; + assign onorth[i] = uconn[YSIZE][i]; + assign osouth[i] = dconn[0][i]; + end + + endgenerate + + /* Connect the shift register endpoints to the input and output of the module */ + assign shiftreg[0][0] = idata; + assign odata = shiftreg[XSIZE][YSIZE-1]; + + /* Do the same to the clock array endpoints */ + assign clkarray[0][0] = iclk; + assign oclk = clkarray[XSIZE][YSIZE-1]; + + /* Propagate clock */ + assign oclk = iclk; + +endmodule +`default_nettype wire