leaf rtl
diff --git a/verilog/rtl/leaf_chip.v b/verilog/rtl/leaf_chip.v
new file mode 100644
index 0000000..c8e22a7
--- /dev/null
+++ b/verilog/rtl/leaf_chip.v
@@ -0,0 +1,2501 @@
+/* Generated by Yosys 0.9+4303 (git sha1 c88eaea6, clang 11.0.1-2 -fPIC -Os) */
+
+module alu(opd0, opd1, op, res);
+ wire [31:0] _00_;
+ wire [31:0] _01_;
+ wire _02_;
+ wire [31:0] _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire [31:0] _12_;
+ wire _13_;
+ wire [31:0] _14_;
+ wire _15_;
+ wire [31:0] _16_;
+ wire _17_;
+ wire [31:0] _18_;
+ wire _19_;
+ wire [31:0] _20_;
+ wire _21_;
+ wire [31:0] _22_;
+ wire _23_;
+ wire arith_op;
+ wire [31:0] arith_res;
+ wire [31:0] comp_res;
+ wire [31:0] logic_res;
+ input [5:0] op;
+ input [31:0] opd0;
+ input [31:0] opd1;
+ output [31:0] res;
+ wire [31:0] shifter_res;
+ assign arith_op = op[4] | op[5];
+ assign _00_ = ~ opd1;
+ assign _01_ = arith_op ? _00_ : opd1;
+ assign _02_ = arith_op ? 1'h1 : 1'h0;
+ assign _03_ = opd0 + _01_;
+ assign arith_res = _03_ + { 31'h00000000, _02_ };
+ assign _04_ = opd0[31] == opd1[31];
+ assign _05_ = ~ op[4];
+ assign _06_ = ~ opd1[31];
+ assign _07_ = opd0[31] & _06_;
+ assign _08_ = ~ opd0[31];
+ assign _09_ = _08_ & opd1[31];
+ assign _10_ = _05_ ? _07_ : _09_;
+ assign _11_ = _04_ ? arith_res[31] : _10_;
+ assign comp_res = op[5] ? { 31'h00000000, _11_ } : arith_res;
+ assign _12_ = opd0 ^ opd1;
+ assign _13_ = op[3:2] == 2'h0;
+ assign _14_ = opd0 | opd1;
+ assign _15_ = op[3:2] == 2'h1;
+ assign _16_ = opd0 & opd1;
+ assign _17_ = op[3:2] == 2'h2;
+ function [31:0] \1841 ;
+ input [31:0] a;
+ input [95:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \1841 = b[31:0];
+ 3'b?1?:
+ \1841 = b[63:32];
+ 3'b1??:
+ \1841 = b[95:64];
+ default:
+ \1841 = a;
+ endcase
+ endfunction
+ assign logic_res = \1841 (comp_res, { _16_, _14_, _12_ }, { _17_, _15_, _13_ });
+ assign _18_ = opd0 << { 26'h0000000, opd1[4:0] };
+ assign _19_ = op[1:0] == 2'h0;
+ assign _20_ = opd0 >> { 26'h0000000, opd1[4:0] };
+ assign _21_ = op[1:0] == 2'h1;
+ assign _22_ = $signed(opd0) >>> { 26'h0000000, opd1[4:0] };
+ assign _23_ = op[1:0] == 2'h2;
+ function [31:0] \1859 ;
+ input [31:0] a;
+ input [95:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \1859 = b[31:0];
+ 3'b?1?:
+ \1859 = b[63:32];
+ 3'b1??:
+ \1859 = b[95:64];
+ default:
+ \1859 = a;
+ endcase
+ endfunction
+ assign shifter_res = \1859 (logic_res, { _22_, _20_, _18_ }, { _23_, _21_, _19_ });
+ assign res = shifter_res;
+endmodule
+
+module alu_ctrl(alu_op_en, alu_func_type, func3, func7, alu_op);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire [5:0] _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire [5:0] _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire [5:0] _15_;
+ wire [5:0] _16_;
+ input alu_func_type;
+ output [5:0] alu_op;
+ input alu_op_en;
+ input [2:0] func3;
+ input [6:0] func7;
+ assign _00_ = ~ alu_op_en;
+ assign _01_ = func7 == 7'h20;
+ assign _02_ = ~ alu_func_type;
+ assign _03_ = _01_ & _02_;
+ assign _04_ = _03_ ? 6'h1f : 6'h0f;
+ assign _05_ = func3 == 3'h0;
+ assign _06_ = func3 == 3'h1;
+ assign _07_ = func3 == 3'h2;
+ assign _08_ = func3 == 3'h3;
+ assign _09_ = func3 == 3'h4;
+ assign _10_ = func7 == 7'h20;
+ assign _11_ = _10_ ? 6'h0e : 6'h0d;
+ assign _12_ = func3 == 3'h5;
+ assign _13_ = func3 == 3'h6;
+ assign _14_ = func3 == 3'h7;
+ function [5:0] \1747 ;
+ input [5:0] a;
+ input [47:0] b;
+ input [7:0] s;
+ (* parallel_case *)
+ casez (s)
+ 8'b???????1:
+ \1747 = b[5:0];
+ 8'b??????1?:
+ \1747 = b[11:6];
+ 8'b?????1??:
+ \1747 = b[17:12];
+ 8'b????1???:
+ \1747 = b[23:18];
+ 8'b???1????:
+ \1747 = b[29:24];
+ 8'b??1?????:
+ \1747 = b[35:30];
+ 8'b?1??????:
+ \1747 = b[41:36];
+ 8'b1???????:
+ \1747 = b[47:42];
+ default:
+ \1747 = a;
+ endcase
+ endfunction
+ assign _15_ = \1747 (6'h0f, { 12'h2c7, _11_, 24'h0ffbcc, _04_ }, { _14_, _13_, _12_, _09_, _08_, _07_, _06_, _05_ });
+ assign _16_ = _00_ ? 6'h0f : _15_;
+ assign alu_op = _16_;
+endmodule
+
+module br_detector(reg0, reg1, mode, en, branch);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ output branch;
+ wire branch_i;
+ input en;
+ wire equal;
+ wire less;
+ wire less_unsigned;
+ input [2:0] mode;
+ input [31:0] reg0;
+ input [31:0] reg1;
+ assign _00_ = reg0 == reg1;
+ assign equal = _00_ ? 1'h1 : 1'h0;
+ assign _01_ = $signed(reg0) < $signed(reg1);
+ assign less = _01_ ? 1'h1 : 1'h0;
+ assign _02_ = reg0 < reg1;
+ assign less_unsigned = _02_ ? 1'h1 : 1'h0;
+ assign _03_ = mode == 3'h0;
+ assign _04_ = ~ equal;
+ assign _05_ = mode == 3'h1;
+ assign _06_ = mode == 3'h4;
+ assign _07_ = ~ less;
+ assign _08_ = _07_ | equal;
+ assign _09_ = mode == 3'h5;
+ assign _10_ = mode == 3'h6;
+ assign _11_ = ~ less_unsigned;
+ assign _12_ = _11_ | equal;
+ assign _13_ = mode == 3'h7;
+ function [0:0] \1405 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1405 = b[0:0];
+ 6'b????1?:
+ \1405 = b[1:1];
+ 6'b???1??:
+ \1405 = b[2:2];
+ 6'b??1???:
+ \1405 = b[3:3];
+ 6'b?1????:
+ \1405 = b[4:4];
+ 6'b1?????:
+ \1405 = b[5:5];
+ default:
+ \1405 = a;
+ endcase
+ endfunction
+ assign branch_i = \1405 (1'h0, { _12_, less_unsigned, _08_, less, _04_, equal }, { _13_, _10_, _09_, _06_, _05_, _03_ });
+ assign _14_ = branch_i & en;
+ assign branch = _14_;
+endmodule
+
+module core_ca812405937f647b44fdbdb3a3bf576e759a7cf1(clk, reset, rd_instr_mem_data, rd_mem_data, ex_irq, sw_irq, tm_irq, rd_instr_mem_addr, wr_mem_data, rd_mem_en, wr_mem_en, rd_wr_mem_addr, wr_mem_byte_en);
+ wire [31:0] _0_;
+ wire [31:0] _1_;
+ wire [31:0] _2_;
+ wire _3_;
+ input clk;
+ wire [31:0] \core_id_ex_stage:433 ;
+ wire \core_id_ex_stage:434 ;
+ wire \core_id_ex_stage:435 ;
+ wire [31:0] \core_id_ex_stage:436 ;
+ wire [3:0] \core_id_ex_stage:437 ;
+ wire \core_id_ex_stage:438 ;
+ wire \core_id_ex_stage:439 ;
+ wire \core_id_ex_stage:440 ;
+ wire [31:0] \core_id_ex_stage:441 ;
+ wire [31:0] \core_if_stage:418 ;
+ wire [31:0] \core_if_stage:419 ;
+ wire [31:0] \core_if_stage:420 ;
+ wire [31:0] \core_if_stage:421 ;
+ wire \core_if_stage:422 ;
+ input ex_irq;
+ reg flush_reg;
+ reg [31:0] instr_reg;
+ reg [31:0] next_pc_reg;
+ reg [31:0] pc_reg;
+ output [31:0] rd_instr_mem_addr;
+ input [31:0] rd_instr_mem_data;
+ input [31:0] rd_mem_data;
+ output rd_mem_en;
+ output [31:0] rd_wr_mem_addr;
+ input reset;
+ input sw_irq;
+ input tm_irq;
+ output [3:0] wr_mem_byte_en;
+ output [31:0] wr_mem_data;
+ output wr_mem_en;
+ assign _0_ = reset ? 32'd0 : \core_if_stage:419 ;
+ assign _1_ = reset ? 32'd0 : \core_if_stage:420 ;
+ assign _2_ = reset ? 32'd0 : \core_if_stage:421 ;
+ assign _3_ = reset ? 1'h0 : \core_if_stage:422 ;
+ always @(posedge clk)
+ pc_reg <= _0_;
+ always @(posedge clk)
+ next_pc_reg <= _1_;
+ always @(posedge clk)
+ instr_reg <= _2_;
+ always @(posedge clk)
+ flush_reg <= _3_;
+ id_ex_stage core_id_ex_stage (
+ .branch(\core_id_ex_stage:438 ),
+ .clk(clk),
+ .ex_irq(ex_irq),
+ .flush(flush_reg),
+ .instr(instr_reg),
+ .jmp(\core_id_ex_stage:439 ),
+ .next_pc(next_pc_reg),
+ .pc(pc_reg),
+ .rd_mem_data(rd_mem_data),
+ .rd_mem_en(\core_id_ex_stage:434 ),
+ .rd_wr_mem_addr(\core_id_ex_stage:436 ),
+ .reset(reset),
+ .sw_irq(sw_irq),
+ .target(\core_id_ex_stage:441 ),
+ .tm_irq(tm_irq),
+ .trap(\core_id_ex_stage:440 ),
+ .wr_mem_byte_en(\core_id_ex_stage:437 ),
+ .wr_mem_data(\core_id_ex_stage:433 ),
+ .wr_mem_en(\core_id_ex_stage:435 )
+ );
+ if_stage_ca812405937f647b44fdbdb3a3bf576e759a7cf1 core_if_stage (
+ .branch(\core_id_ex_stage:438 ),
+ .clk(clk),
+ .flush(\core_if_stage:422 ),
+ .instr(\core_if_stage:421 ),
+ .jmp(\core_id_ex_stage:439 ),
+ .next_pc(\core_if_stage:420 ),
+ .pc(\core_if_stage:419 ),
+ .rd_instr_mem_addr(\core_if_stage:418 ),
+ .rd_instr_mem_data(rd_instr_mem_data),
+ .reset(reset),
+ .target(\core_id_ex_stage:441 ),
+ .trap(\core_id_ex_stage:440 )
+ );
+ assign rd_instr_mem_addr = \core_if_stage:418 ;
+ assign wr_mem_data = \core_id_ex_stage:433 ;
+ assign rd_mem_en = \core_id_ex_stage:434 ;
+ assign wr_mem_en = \core_id_ex_stage:435 ;
+ assign rd_wr_mem_addr = \core_id_ex_stage:436 ;
+ assign wr_mem_byte_en = \core_id_ex_stage:437 ;
+endmodule
+
+module csrs_b14a227a3c694ac3d0ad8c71b4ce4306403987f6(clk, reset, ex_irq, sw_irq, tm_irq, wr_mode, wr_en, rd_wr_addr, wr_reg_data, wr_imm_data, rd_data);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire [31:0] _11_;
+ wire _12_;
+ wire [31:0] _13_;
+ wire [31:0] _14_;
+ wire _15_;
+ wire _16_;
+ wire [31:0] _17_;
+ wire _18_;
+ wire [31:0] _19_;
+ wire [31:0] _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire [29:0] _38_;
+ wire [29:0] _39_;
+ wire _40_;
+ wire _41_;
+ wire [31:0] _42_;
+ wire [31:0] _43_;
+ wire _44_;
+ wire _45_;
+ wire [29:0] _46_;
+ wire [29:0] _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire [4:0] _51_;
+ wire _52_;
+ wire [4:0] _53_;
+ wire _54_;
+ wire _55_;
+ wire [31:0] _56_;
+ wire [31:0] _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ input clk;
+ input ex_irq;
+ reg [4:0] mcause_exc;
+ reg mcause_int;
+ reg [29:0] mepc;
+ reg mie_meie;
+ reg mie_msie;
+ reg mie_mtie;
+ reg mip_meip;
+ reg mip_msip;
+ reg mip_mtip;
+ reg [31:0] mscratch;
+ reg mstatus_mie;
+ reg mstatus_mpie;
+ reg [31:0] mtval;
+ reg [29:0] mtvec_base;
+ output [31:0] rd_data;
+ wire [31:0] rd_data_i;
+ input [11:0] rd_wr_addr;
+ input reset;
+ input sw_irq;
+ input tm_irq;
+ wire [31:0] wr_data_i;
+ input wr_en;
+ input [31:0] wr_imm_data;
+ input [2:0] wr_mode;
+ input [31:0] wr_reg_data;
+ assign _00_ = rd_wr_addr == 12'hf14;
+ assign _01_ = rd_wr_addr == 12'h301;
+ assign _02_ = rd_wr_addr == 12'h300;
+ assign _03_ = rd_wr_addr == 12'h304;
+ assign _04_ = rd_wr_addr == 12'h305;
+ assign _05_ = rd_wr_addr == 12'h340;
+ assign _06_ = rd_wr_addr == 12'h341;
+ assign _07_ = rd_wr_addr == 12'h342;
+ assign _08_ = rd_wr_addr == 12'h343;
+ assign _09_ = rd_wr_addr == 12'h344;
+ function [31:0] \1562 ;
+ input [31:0] a;
+ input [319:0] b;
+ input [9:0] s;
+ (* parallel_case *)
+ casez (s)
+ 10'b?????????1:
+ \1562 = b[31:0];
+ 10'b????????1?:
+ \1562 = b[63:32];
+ 10'b???????1??:
+ \1562 = b[95:64];
+ 10'b??????1???:
+ \1562 = b[127:96];
+ 10'b?????1????:
+ \1562 = b[159:128];
+ 10'b????1?????:
+ \1562 = b[191:160];
+ 10'b???1??????:
+ \1562 = b[223:192];
+ 10'b??1???????:
+ \1562 = b[255:224];
+ 10'b?1????????:
+ \1562 = b[287:256];
+ 10'b1?????????:
+ \1562 = b[319:288];
+ default:
+ \1562 = a;
+ endcase
+ endfunction
+ assign rd_data_i = \1562 (32'd0, { 20'h00000, mip_meip, 3'h0, mip_mtip, 3'h0, mip_msip, 3'h0, mtval, mcause_int, 26'h0000000, mcause_exc, mepc, 2'h0, mscratch, mtvec_base, 22'h000000, mie_meie, 3'h0, mie_mtie, 3'h0, mie_msie, 27'h0000000, mstatus_mpie, 3'h0, mstatus_mie, 67'h04000010000000000 }, { _09_, _08_, _07_, _06_, _05_, _04_, _03_, _02_, _01_, _00_ });
+ assign _10_ = wr_mode == 3'h1;
+ assign _11_ = rd_data_i | wr_reg_data;
+ assign _12_ = wr_mode == 3'h2;
+ assign _13_ = ~ wr_reg_data;
+ assign _14_ = rd_data_i & _13_;
+ assign _15_ = wr_mode == 3'h3;
+ assign _16_ = wr_mode == 3'h5;
+ assign _17_ = rd_data_i | wr_imm_data;
+ assign _18_ = wr_mode == 3'h6;
+ assign _19_ = ~ wr_imm_data;
+ assign _20_ = rd_data_i & _19_;
+ assign _21_ = wr_mode == 3'h7;
+ function [31:0] \1585 ;
+ input [31:0] a;
+ input [191:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1585 = b[31:0];
+ 6'b????1?:
+ \1585 = b[63:32];
+ 6'b???1??:
+ \1585 = b[95:64];
+ 6'b??1???:
+ \1585 = b[127:96];
+ 6'b?1????:
+ \1585 = b[159:128];
+ 6'b1?????:
+ \1585 = b[191:160];
+ default:
+ \1585 = a;
+ endcase
+ endfunction
+ assign wr_data_i = \1585 (32'd0, { _20_, _17_, wr_imm_data, _14_, _11_, wr_reg_data }, { _21_, _18_, _16_, _15_, _12_, _10_ });
+ assign _22_ = rd_wr_addr == 12'h300;
+ assign _23_ = _22_ & wr_en;
+ assign _24_ = _23_ ? wr_data_i[3] : mstatus_mie;
+ assign _25_ = _23_ ? wr_data_i[7] : mstatus_mpie;
+ assign _26_ = reset ? 1'h0 : _24_;
+ assign _27_ = reset ? 1'h1 : _25_;
+ always @(posedge clk)
+ mstatus_mie <= _26_;
+ always @(posedge clk)
+ mstatus_mpie <= _27_;
+ assign _28_ = rd_wr_addr == 12'h304;
+ assign _29_ = _28_ & wr_en;
+ assign _30_ = _29_ ? wr_data_i[11] : mie_meie;
+ assign _31_ = _29_ ? wr_data_i[7] : mie_mtie;
+ assign _32_ = _29_ ? wr_data_i[3] : mie_msie;
+ assign _33_ = reset ? 1'h0 : _30_;
+ assign _34_ = reset ? 1'h0 : _31_;
+ assign _35_ = reset ? 1'h0 : _32_;
+ always @(posedge clk)
+ mie_meie <= _33_;
+ always @(posedge clk)
+ mie_mtie <= _34_;
+ always @(posedge clk)
+ mie_msie <= _35_;
+ assign _36_ = rd_wr_addr == 12'h305;
+ assign _37_ = _36_ & wr_en;
+ assign _38_ = _37_ ? wr_data_i[31:2] : mtvec_base;
+ assign _39_ = reset ? 30'h00000000 : _38_;
+ always @(posedge clk)
+ mtvec_base <= _39_;
+ assign _40_ = rd_wr_addr == 12'h340;
+ assign _41_ = _40_ & wr_en;
+ assign _42_ = _41_ ? wr_data_i : mscratch;
+ assign _43_ = reset ? 32'd0 : _42_;
+ always @(posedge clk)
+ mscratch <= _43_;
+ assign _44_ = rd_wr_addr == 12'h341;
+ assign _45_ = _44_ & wr_en;
+ assign _46_ = _45_ ? wr_data_i[31:2] : mepc;
+ assign _47_ = reset ? 30'h00000000 : _46_;
+ always @(posedge clk)
+ mepc <= _47_;
+ assign _48_ = rd_wr_addr == 12'h342;
+ assign _49_ = _48_ & wr_en;
+ assign _50_ = _49_ ? wr_data_i[31] : mcause_int;
+ assign _51_ = _49_ ? wr_data_i[4:0] : mcause_exc;
+ assign _52_ = reset ? 1'h0 : _50_;
+ assign _53_ = reset ? 5'h00 : _51_;
+ always @(posedge clk)
+ mcause_int <= _52_;
+ always @(posedge clk)
+ mcause_exc <= _53_;
+ assign _54_ = rd_wr_addr == 12'h343;
+ assign _55_ = _54_ & wr_en;
+ assign _56_ = _55_ ? wr_data_i : mtval;
+ assign _57_ = reset ? 32'd0 : _56_;
+ always @(posedge clk)
+ mtval <= _57_;
+ assign _58_ = reset ? 1'h0 : ex_irq;
+ assign _59_ = reset ? 1'h0 : tm_irq;
+ assign _60_ = reset ? 1'h0 : sw_irq;
+ always @(posedge clk)
+ mip_meip <= _58_;
+ always @(posedge clk)
+ mip_mtip <= _59_;
+ always @(posedge clk)
+ mip_msip <= _60_;
+ assign rd_data = rd_data_i;
+endmodule
+
+module down_counter_16(clk, clr, en, mode, load, val);
+ wire _0_;
+ wire [15:0] _1_;
+ wire [15:0] _2_;
+ wire [15:0] _3_;
+ wire [15:0] _4_;
+ input clk;
+ input clr;
+ input en;
+ reg [15:0] inter_val;
+ input [15:0] load;
+ input mode;
+ output [15:0] val;
+ assign _4_ = en ? _3_ : inter_val;
+ always @(posedge clk, posedge clr)
+ if (clr) inter_val <= 16'hffff;
+ else inter_val <= _4_;
+ assign _0_ = inter_val == 16'h0000;
+ assign _1_ = inter_val - 16'h0001;
+ assign _2_ = _0_ ? 16'hffff : _1_;
+ assign _3_ = mode ? load : _2_;
+ assign val = inter_val;
+endmodule
+
+module down_counter_3(clk, clr, en, mode, load, val);
+ wire _0_;
+ wire [2:0] _1_;
+ wire [2:0] _2_;
+ wire [2:0] _3_;
+ wire [2:0] _4_;
+ input clk;
+ input clr;
+ input en;
+ reg [2:0] inter_val;
+ input [2:0] load;
+ input mode;
+ output [2:0] val;
+ assign _0_ = inter_val == 3'h0;
+ assign _1_ = inter_val - 3'h1;
+ assign _2_ = _0_ ? 3'h7 : _1_;
+ assign _3_ = mode ? load : _2_;
+ assign _4_ = en ? _3_ : inter_val;
+ always @(posedge clk, posedge clr)
+ if (clr) inter_val <= 3'h7;
+ else inter_val <= _4_;
+ assign val = inter_val;
+endmodule
+
+module fifo_8_8(clk, reset, wr, wr_data, rd, wr_en, rd_en, rd_data);
+ wire [7:0] _00_;
+ wire [7:0] _01_;
+ wire [7:0] _02_;
+ wire [7:0] _03_;
+ wire [2:0] _04_;
+ wire _05_;
+ wire _06_;
+ wire [31:0] _07_;
+ wire [2:0] _08_;
+ wire _09_;
+ wire _10_;
+ wire [2:0] _11_;
+ wire [31:0] _12_;
+ wire [2:0] _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire [7:0] _28_;
+ wire [7:0] _29_;
+ wire [7:0] _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire [7:0] _47_;
+ wire _48_;
+ wire [7:0] _49_;
+ wire _50_;
+ wire [7:0] _51_;
+ wire _52_;
+ wire [7:0] _53_;
+ wire _54_;
+ wire [7:0] _55_;
+ wire _56_;
+ wire [7:0] _57_;
+ wire _58_;
+ wire [7:0] _59_;
+ wire _60_;
+ wire [7:0] _61_;
+ input clk;
+ wire empty;
+ reg [63:0] fifo_data;
+ wire full;
+ reg last_op;
+ input rd;
+ output [7:0] rd_data;
+ output rd_en;
+ reg [2:0] rd_pointer;
+ input reset;
+ input wr;
+ input [7:0] wr_data;
+ output wr_en;
+ reg [2:0] wr_pointer;
+ assign _00_ = _04_[0] ? fifo_data[15:8] : fifo_data[7:0];
+ assign _01_ = _04_[0] ? fifo_data[47:40] : fifo_data[39:32];
+ assign _02_ = _04_[0] ? fifo_data[31:24] : fifo_data[23:16];
+ assign _03_ = _04_[0] ? fifo_data[63:56] : fifo_data[55:48];
+ assign _28_ = _04_[1] ? _02_ : _00_;
+ assign _29_ = _04_[1] ? _03_ : _01_;
+ assign _04_ = 3'h7 - rd_pointer;
+ assign _05_ = ~ empty;
+ assign _06_ = rd & _05_;
+ assign _07_ = { 29'h00000000, rd_pointer } + 32'd1;
+ assign _08_ = _06_ ? _07_[2:0] : rd_pointer;
+ always @(posedge clk, posedge reset)
+ if (reset) rd_pointer <= 3'h0;
+ else rd_pointer <= _08_;
+ assign _09_ = ~ full;
+ assign _10_ = wr & _09_;
+ assign _11_ = 3'h7 - wr_pointer;
+ assign _12_ = { 29'h00000000, wr_pointer } + 32'd1;
+ always @(posedge clk, posedge reset)
+ if (reset) fifo_data <= 64'h0000000000000000;
+ else fifo_data <= { _61_, _59_, _57_, _55_, _53_, _51_, _49_, _47_ };
+ assign _13_ = _10_ ? _12_[2:0] : wr_pointer;
+ always @(posedge clk, posedge reset)
+ if (reset) wr_pointer <= 3'h0;
+ else wr_pointer <= _13_;
+ assign _14_ = ~ wr;
+ assign _15_ = rd & _14_;
+ assign _16_ = ~ rd;
+ assign _17_ = _16_ & wr;
+ assign _18_ = _17_ ? 1'h1 : last_op;
+ assign _19_ = _15_ ? 1'h0 : _18_;
+ always @(posedge clk, posedge reset)
+ if (reset) last_op <= 1'h0;
+ else last_op <= _19_;
+ assign _20_ = { 29'h00000000, wr_pointer } == { 29'h00000000, rd_pointer };
+ assign _21_ = last_op == 1'h0;
+ assign _22_ = _20_ & _21_;
+ assign empty = _22_ ? 1'h1 : 1'h0;
+ assign _23_ = { 29'h00000000, wr_pointer } == { 29'h00000000, rd_pointer };
+ assign _24_ = last_op == 1'h1;
+ assign _25_ = _23_ & _24_;
+ assign full = _25_ ? 1'h1 : 1'h0;
+ assign _26_ = ~ empty;
+ assign _27_ = ~ full;
+ assign _30_ = _04_[2] ? _29_ : _28_;
+ assign _31_ = ~ _11_[2];
+ assign _32_ = ~ _11_[1];
+ assign _33_ = _31_ & _32_;
+ assign _34_ = _31_ & _11_[1];
+ assign _35_ = _11_[2] & _32_;
+ assign _36_ = _11_[2] & _11_[1];
+ assign _37_ = ~ _11_[0];
+ assign _38_ = _33_ & _37_;
+ assign _39_ = _33_ & _11_[0];
+ assign _40_ = _34_ & _37_;
+ assign _41_ = _34_ & _11_[0];
+ assign _42_ = _35_ & _37_;
+ assign _43_ = _35_ & _11_[0];
+ assign _44_ = _36_ & _37_;
+ assign _45_ = _36_ & _11_[0];
+ assign _46_ = _38_ & _10_;
+ assign _47_ = _46_ ? wr_data : fifo_data[7:0];
+ assign _48_ = _39_ & _10_;
+ assign _49_ = _48_ ? wr_data : fifo_data[15:8];
+ assign _50_ = _40_ & _10_;
+ assign _51_ = _50_ ? wr_data : fifo_data[23:16];
+ assign _52_ = _41_ & _10_;
+ assign _53_ = _52_ ? wr_data : fifo_data[31:24];
+ assign _54_ = _42_ & _10_;
+ assign _55_ = _54_ ? wr_data : fifo_data[39:32];
+ assign _56_ = _43_ & _10_;
+ assign _57_ = _56_ ? wr_data : fifo_data[47:40];
+ assign _58_ = _44_ & _10_;
+ assign _59_ = _58_ ? wr_data : fifo_data[55:48];
+ assign _60_ = _45_ & _10_;
+ assign _61_ = _60_ ? wr_data : fifo_data[63:56];
+ assign wr_en = _27_;
+ assign rd_en = _26_;
+ assign rd_data = _30_;
+endmodule
+
+module id_ex_stage(clk, reset, pc, next_pc, instr, flush, rd_mem_data, ex_irq, sw_irq, tm_irq, wr_mem_data, rd_mem_en, wr_mem_en, rd_wr_mem_addr, wr_mem_byte_en, branch, jmp, trap, target);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire _3_;
+ wire [31:0] _4_;
+ wire [31:0] _5_;
+ wire [31:0] alu_opd0;
+ wire [31:0] alu_opd1;
+ output branch;
+ input clk;
+ input ex_irq;
+ input flush;
+ input [31:0] instr;
+ output jmp;
+ input [31:0] next_pc;
+ input [31:0] pc;
+ input [31:0] rd_mem_data;
+ output rd_mem_en;
+ output [31:0] rd_wr_mem_addr;
+ input reset;
+ wire [31:0] rf_wr_reg_data;
+ wire [31:0] \stage_alu:966 ;
+ wire [5:0] \stage_alu_ctrl:963 ;
+ wire \stage_br_detector:957 ;
+ wire [31:0] \stage_csrs:960 ;
+ wire [31:0] \stage_ig:948 ;
+ wire [31:0] \stage_lsu:969 ;
+ wire \stage_lsu:970 ;
+ wire \stage_lsu:971 ;
+ wire [31:0] \stage_lsu:972 ;
+ wire [31:0] \stage_lsu:973 ;
+ wire [3:0] \stage_lsu:974 ;
+ wire [1:0] \stage_mc:906 ;
+ wire \stage_mc:907 ;
+ wire [2:0] \stage_mc:908 ;
+ wire \stage_mc:909 ;
+ wire \stage_mc:910 ;
+ wire \stage_mc:911 ;
+ wire \stage_mc:912 ;
+ wire \stage_mc:913 ;
+ wire \stage_mc:914 ;
+ wire \stage_mc:915 ;
+ wire \stage_mc:916 ;
+ wire \stage_mc:917 ;
+ wire \stage_mc:918 ;
+ wire \stage_mc:919 ;
+ wire [31:0] \stage_rf:951 ;
+ wire [31:0] \stage_rf:952 ;
+ input sw_irq;
+ output [31:0] target;
+ input tm_irq;
+ output trap;
+ output [3:0] wr_mem_byte_en;
+ output [31:0] wr_mem_data;
+ output wr_mem_en;
+ assign _0_ = \stage_mc:906 == 2'h0;
+ assign _1_ = \stage_mc:906 == 2'h1;
+ assign _2_ = \stage_mc:906 == 2'h2;
+ assign _3_ = \stage_mc:906 == 2'h3;
+ function [31:0] \894 ;
+ input [31:0] a;
+ input [127:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \894 = b[31:0];
+ 4'b??1?:
+ \894 = b[63:32];
+ 4'b?1??:
+ \894 = b[95:64];
+ 4'b1???:
+ \894 = b[127:96];
+ default:
+ \894 = a;
+ endcase
+ endfunction
+ assign rf_wr_reg_data = \894 (32'd0, { \stage_csrs:960 , next_pc, \stage_lsu:969 , \stage_alu:966 }, { _3_, _2_, _1_, _0_ });
+ assign _4_ = \stage_mc:909 ? pc : \stage_rf:951 ;
+ assign alu_opd0 = \stage_mc:911 ? _4_ : 32'd0;
+ assign _5_ = \stage_mc:910 ? \stage_ig:948 : \stage_rf:952 ;
+ assign alu_opd1 = \stage_mc:912 ? _5_ : 32'd0;
+ alu stage_alu (
+ .op(\stage_alu_ctrl:963 ),
+ .opd0(alu_opd0),
+ .opd1(alu_opd1),
+ .res(\stage_alu:966 )
+ );
+ alu_ctrl stage_alu_ctrl (
+ .alu_func_type(\stage_mc:914 ),
+ .alu_op(\stage_alu_ctrl:963 ),
+ .alu_op_en(\stage_mc:913 ),
+ .func3(instr[14:12]),
+ .func7(instr[31:25])
+ );
+ br_detector stage_br_detector (
+ .branch(\stage_br_detector:957 ),
+ .en(\stage_mc:917 ),
+ .mode(instr[14:12]),
+ .reg0(\stage_rf:951 ),
+ .reg1(\stage_rf:952 )
+ );
+ csrs_b14a227a3c694ac3d0ad8c71b4ce4306403987f6 stage_csrs (
+ .clk(clk),
+ .ex_irq(ex_irq),
+ .rd_data(\stage_csrs:960 ),
+ .rd_wr_addr(instr[31:20]),
+ .reset(reset),
+ .sw_irq(sw_irq),
+ .tm_irq(tm_irq),
+ .wr_en(\stage_mc:918 ),
+ .wr_imm_data(\stage_ig:948 ),
+ .wr_mode(instr[14:12]),
+ .wr_reg_data(\stage_rf:951 )
+ );
+ imm_gen stage_ig (
+ .imm(\stage_ig:948 ),
+ .imm_type(\stage_mc:908 ),
+ .payload(instr[31:7])
+ );
+ lsu stage_lsu (
+ .data_type(instr[14:12]),
+ .en(\stage_mc:916 ),
+ .mode(\stage_mc:915 ),
+ .rd_data(\stage_lsu:969 ),
+ .rd_mem_data(rd_mem_data),
+ .rd_mem_en(\stage_lsu:970 ),
+ .rd_wr_addr(\stage_alu:966 ),
+ .rd_wr_mem_addr(\stage_lsu:973 ),
+ .wr_data(\stage_rf:952 ),
+ .wr_mem_byte_en(\stage_lsu:974 ),
+ .wr_mem_data(\stage_lsu:972 ),
+ .wr_mem_en(\stage_lsu:971 )
+ );
+ main_ctrl stage_mc (
+ .alu_func_type(\stage_mc:914 ),
+ .alu_op_en(\stage_mc:913 ),
+ .alu_opd0_pass(\stage_mc:911 ),
+ .alu_opd1_pass(\stage_mc:912 ),
+ .alu_src0(\stage_mc:909 ),
+ .alu_src1(\stage_mc:910 ),
+ .brd_en(\stage_mc:917 ),
+ .csrs_wr_en(\stage_mc:918 ),
+ .flush(flush),
+ .if_jmp(\stage_mc:919 ),
+ .ig_imm_type(\stage_mc:908 ),
+ .lsu_en(\stage_mc:916 ),
+ .lsu_mode(\stage_mc:915 ),
+ .opcode(instr[6:0]),
+ .rf_wr_reg_en(\stage_mc:907 ),
+ .rf_wr_reg_src(\stage_mc:906 )
+ );
+ reg_file stage_rf (
+ .clk(clk),
+ .rd_reg_addr0(instr[19:15]),
+ .rd_reg_addr1(instr[24:20]),
+ .rd_reg_data0(\stage_rf:951 ),
+ .rd_reg_data1(\stage_rf:952 ),
+ .wr_reg_addr(instr[11:7]),
+ .wr_reg_data(rf_wr_reg_data),
+ .wr_reg_en(\stage_mc:907 )
+ );
+ assign wr_mem_data = \stage_lsu:972 ;
+ assign rd_mem_en = \stage_lsu:970 ;
+ assign wr_mem_en = \stage_lsu:971 ;
+ assign rd_wr_mem_addr = \stage_lsu:973 ;
+ assign wr_mem_byte_en = \stage_lsu:974 ;
+ assign branch = \stage_br_detector:957 ;
+ assign jmp = \stage_mc:919 ;
+ assign trap = 1'h0;
+ assign target = \stage_alu:966 ;
+endmodule
+
+module if_stage_ca812405937f647b44fdbdb3a3bf576e759a7cf1(clk, reset, jmp, branch, trap, target, rd_instr_mem_data, rd_instr_mem_addr, pc, next_pc, instr, flush);
+ wire _0_;
+ wire [31:0] _1_;
+ wire [31:0] _2_;
+ input branch;
+ input clk;
+ output flush;
+ output [31:0] instr;
+ input jmp;
+ output [31:0] next_pc;
+ wire [31:0] next_pc_i;
+ output [31:0] pc;
+ reg [31:0] pc_reg;
+ output [31:0] rd_instr_mem_addr;
+ input [31:0] rd_instr_mem_data;
+ input reset;
+ wire taken;
+ input [31:0] target;
+ input trap;
+ assign _0_ = branch | jmp;
+ assign taken = _0_ | trap;
+ assign next_pc_i = pc_reg + 32'd4;
+ assign _1_ = taken ? { target[31:2], 2'h0 } : next_pc_i;
+ assign _2_ = reset ? 32'd256 : _1_;
+ always @(posedge clk)
+ pc_reg <= _2_;
+ assign rd_instr_mem_addr = pc_reg;
+ assign pc = pc_reg;
+ assign next_pc = next_pc_i;
+ assign instr = rd_instr_mem_data;
+ assign flush = taken;
+endmodule
+
+module imm_gen(payload, imm_type, imm);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire _3_;
+ wire _4_;
+ wire _5_;
+ wire [31:0] _6_;
+ output [31:0] imm;
+ input [2:0] imm_type;
+ input [24:0] payload;
+ assign _0_ = imm_type == 3'h0;
+ assign _1_ = imm_type == 3'h1;
+ assign _2_ = imm_type == 3'h2;
+ assign _3_ = imm_type == 3'h3;
+ assign _4_ = imm_type == 3'h4;
+ assign _5_ = imm_type == 3'h5;
+ function [31:0] \1334 ;
+ input [31:0] a;
+ input [191:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1334 = b[31:0];
+ 6'b????1?:
+ \1334 = b[63:32];
+ 6'b???1??:
+ \1334 = b[95:64];
+ 6'b??1???:
+ \1334 = b[127:96];
+ 6'b?1????:
+ \1334 = b[159:128];
+ 6'b1?????:
+ \1334 = b[191:160];
+ default:
+ \1334 = a;
+ endcase
+ endfunction
+ assign _6_ = \1334 (32'hxxxxxxxx, { 27'h0000000, payload[19:15], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[12:5], payload[13], payload[23:14], 1'h0, payload[24:5], 12'h000, payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[0], payload[23:18], payload[4:1], 1'h0, payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24:18], payload[4:0], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24], payload[24:13] }, { _5_, _4_, _3_, _2_, _1_, _0_ });
+ assign imm = _6_;
+endmodule
+
+module leaf_chip(clk, reset, rx, tx);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire [3:0] _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire [3:0] _13_;
+ wire _14_;
+ wire [3:0] _15_;
+ wire _16_;
+ wire [3:0] _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire [31:0] _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire [15:0] _27_;
+ wire [15:0] _28_;
+ wire _29_;
+ input clk;
+ wire [31:0] core_rd_instr_mem_data;
+ wire [31:0] core_rd_mem_data;
+ wire [31:0] \leaf_core:149 ;
+ wire [31:0] \leaf_core:150 ;
+ wire \leaf_core:151 ;
+ wire \leaf_core:152 ;
+ wire [31:0] \leaf_core:153 ;
+ wire [3:0] \leaf_core:154 ;
+ wire [31:0] \leaf_ram:131 ;
+ wire [31:0] \leaf_ram:132 ;
+ wire [31:0] \leaf_rom:125 ;
+ wire [15:0] \leaf_uart:140 ;
+ wire \leaf_uart:141 ;
+ wire ram_wr;
+ wire [3:0] ram_wr_byte_en;
+ wire [31:0] ram_wr_data;
+ input reset;
+ input rx;
+ output tx;
+ wire uart_rd;
+ wire uart_wr;
+ function [31:0] \10 ;
+ input [31:0] a;
+ input [63:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \10 = b[31:0];
+ 2'b1?:
+ \10 = b[63:32];
+ default:
+ \10 = a;
+ endcase
+ endfunction
+ assign core_rd_instr_mem_data = \10 (32'd19, { \leaf_ram:131 , \leaf_rom:125 }, { _09_, _00_ });
+ assign _20_ = \leaf_core:153 [1:0] == 2'h1;
+ assign _21_ = \leaf_core:153 [1:0] == 2'h2;
+ assign _22_ = \leaf_core:153 [1:0] == 2'h3;
+ function [31:0] \113 ;
+ input [31:0] a;
+ input [95:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \113 = b[31:0];
+ 3'b?1?:
+ \113 = b[63:32];
+ 3'b1??:
+ \113 = b[95:64];
+ default:
+ \113 = a;
+ endcase
+ endfunction
+ assign _23_ = \113 (\leaf_core:150 , { \leaf_core:150 [7:0], \leaf_core:150 [31:8], \leaf_core:150 [15:0], \leaf_core:150 [31:16], \leaf_core:150 [23:0], \leaf_core:150 [31:24] }, { _22_, _21_, _20_ });
+ assign ram_wr_data = \leaf_core:152 ? _23_ : 32'd0;
+ assign ram_wr_byte_en = \leaf_core:152 ? _17_ : 4'h0;
+ assign ram_wr = \leaf_core:152 ? _18_ : 1'h0;
+ assign uart_wr = \leaf_core:152 ? _19_ : 1'h0;
+ assign _24_ = \leaf_core:153 [31:8] == 24'h000000;
+ assign _25_ = \leaf_core:153 [31:8] == 24'h000001;
+ assign _26_ = \leaf_core:153 [31:8] == 24'h000002;
+ function [15:0] \26 ;
+ input [15:0] a;
+ input [47:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \26 = b[15:0];
+ 3'b?1?:
+ \26 = b[31:16];
+ 3'b1??:
+ \26 = b[47:32];
+ default:
+ \26 = a;
+ endcase
+ endfunction
+ assign _27_ = \26 (16'h0000, { \leaf_ram:132 [15:0], \leaf_rom:125 [15:0], \leaf_uart:140 }, { _26_, _25_, _24_ });
+ function [15:0] \30 ;
+ input [15:0] a;
+ input [47:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \30 = b[15:0];
+ 3'b?1?:
+ \30 = b[31:16];
+ 3'b1??:
+ \30 = b[47:32];
+ default:
+ \30 = a;
+ endcase
+ endfunction
+ assign _28_ = \30 (16'h0000, { \leaf_ram:132 [31:16], \leaf_rom:125 [31:16], 16'h0000 }, { _26_, _25_, _24_ });
+ function [0:0] \35 ;
+ input [0:0] a;
+ input [2:0] b;
+ input [2:0] s;
+ (* parallel_case *)
+ casez (s)
+ 3'b??1:
+ \35 = b[0:0];
+ 3'b?1?:
+ \35 = b[1:1];
+ 3'b1??:
+ \35 = b[2:2];
+ default:
+ \35 = a;
+ endcase
+ endfunction
+ assign _29_ = \35 (1'h0, 3'h1, { _26_, _25_, _24_ });
+ assign core_rd_mem_data = \leaf_core:151 ? { _28_, _27_ } : 32'd0;
+ assign uart_rd = \leaf_core:151 ? _29_ : 1'h0;
+ assign _01_ = \leaf_core:153 [31:8] == 24'h000000;
+ assign _00_ = \leaf_core:149 [31:8] == 24'h000001;
+ assign _02_ = \leaf_core:153 [1:0] == 2'h0;
+ assign _03_ = \leaf_core:153 [1:0] == 2'h1;
+ assign _04_ = \leaf_core:153 [1:0] == 2'h2;
+ assign _05_ = \leaf_core:153 [1:0] == 2'h3;
+ function [3:0] \62 ;
+ input [3:0] a;
+ input [15:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \62 = b[3:0];
+ 4'b??1?:
+ \62 = b[7:4];
+ 4'b?1??:
+ \62 = b[11:8];
+ 4'b1???:
+ \62 = b[15:12];
+ default:
+ \62 = a;
+ endcase
+ endfunction
+ assign _06_ = \62 (ram_wr_byte_en, 16'h8421, { _05_, _04_, _03_, _02_ });
+ assign _07_ = \leaf_core:154 == 4'h1;
+ assign _08_ = \leaf_core:153 [1:0] == 2'h0;
+ assign _10_ = \leaf_core:153 [1:0] == 2'h1;
+ assign _09_ = \leaf_core:149 [31:8] == 24'h000002;
+ assign _11_ = \leaf_core:153 [1:0] == 2'h2;
+ assign _12_ = \leaf_core:153 [1:0] == 2'h3;
+ function [3:0] \78 ;
+ input [3:0] a;
+ input [15:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \78 = b[3:0];
+ 4'b??1?:
+ \78 = b[7:4];
+ 4'b?1??:
+ \78 = b[11:8];
+ 4'b1???:
+ \78 = b[15:12];
+ default:
+ \78 = a;
+ endcase
+ endfunction
+ assign _13_ = \78 (ram_wr_byte_en, 16'h8c63, { _12_, _11_, _10_, _08_ });
+ assign _14_ = \leaf_core:154 == 4'h3;
+ function [3:0] \82 ;
+ input [3:0] a;
+ input [7:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \82 = b[3:0];
+ 2'b1?:
+ \82 = b[7:4];
+ default:
+ \82 = a;
+ endcase
+ endfunction
+ assign _15_ = \82 (\leaf_core:154 , { _13_, _06_ }, { _14_, _07_ });
+ assign _16_ = \leaf_core:153 [31:8] == 24'h000002;
+ function [3:0] \88 ;
+ input [3:0] a;
+ input [7:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \88 = b[3:0];
+ 2'b1?:
+ \88 = b[7:4];
+ default:
+ \88 = a;
+ endcase
+ endfunction
+ assign _17_ = \88 (4'h0, { _15_, 4'h0 }, { _16_, _01_ });
+ function [0:0] \92 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \92 = b[0:0];
+ 2'b1?:
+ \92 = b[1:1];
+ default:
+ \92 = a;
+ endcase
+ endfunction
+ assign _18_ = \92 (1'h0, 2'h2, { _16_, _01_ });
+ function [0:0] \96 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \96 = b[0:0];
+ 2'b1?:
+ \96 = b[1:1];
+ default:
+ \96 = a;
+ endcase
+ endfunction
+ assign _19_ = \96 (1'h0, 2'h1, { _16_, _01_ });
+ core_ca812405937f647b44fdbdb3a3bf576e759a7cf1 leaf_core (
+ .clk(clk),
+ .ex_irq(1'h0),
+ .rd_instr_mem_addr(\leaf_core:149 ),
+ .rd_instr_mem_data(core_rd_instr_mem_data),
+ .rd_mem_data(core_rd_mem_data),
+ .rd_mem_en(\leaf_core:151 ),
+ .rd_wr_mem_addr(\leaf_core:153 ),
+ .reset(reset),
+ .sw_irq(1'h0),
+ .tm_irq(1'h0),
+ .wr_mem_byte_en(\leaf_core:154 ),
+ .wr_mem_data(\leaf_core:150 ),
+ .wr_mem_en(\leaf_core:152 )
+ );
+ ram_8 leaf_ram (
+ .clk(clk),
+ .rd_addr0(\leaf_core:149 [7:2]),
+ .rd_addr1(\leaf_core:153 [7:2]),
+ .rd_data0(\leaf_ram:131 ),
+ .rd_data1(\leaf_ram:132 ),
+ .wr(ram_wr),
+ .wr_addr(\leaf_core:153 [7:2]),
+ .wr_byte_en(ram_wr_byte_en),
+ .wr_data(ram_wr_data)
+ );
+ rom_8 leaf_rom (
+ .rd(1'h1),
+ .rd_addr(\leaf_core:149 [7:2]),
+ .rd_data(\leaf_rom:125 )
+ );
+ uart leaf_uart (
+ .clk(clk),
+ .rd(uart_rd),
+ .rd_addr(\leaf_core:153 [3:2]),
+ .rd_data(\leaf_uart:140 ),
+ .reset(reset),
+ .rx(rx),
+ .tx(\leaf_uart:141 ),
+ .wr(uart_wr),
+ .wr_addr(\leaf_core:153 [3:2]),
+ .wr_data(\leaf_core:150 [15:0])
+ );
+ assign tx = \leaf_uart:141 ;
+endmodule
+
+module lsu(wr_data, rd_wr_addr, data_type, mode, en, rd_mem_data, rd_data, rd_mem_en, wr_mem_en, wr_mem_data, rd_wr_mem_addr, wr_mem_byte_en);
+ wire _00_;
+ wire [31:0] _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire [31:0] _12_;
+ wire [31:0] _13_;
+ wire [31:0] _14_;
+ wire [3:0] _15_;
+ wire [31:0] data_in;
+ wire [31:0] data_out;
+ input [2:0] data_type;
+ input en;
+ input mode;
+ output [31:0] rd_data;
+ input [31:0] rd_mem_data;
+ output rd_mem_en;
+ wire rd_mem_en_i;
+ input [31:0] rd_wr_addr;
+ output [31:0] rd_wr_mem_addr;
+ input [31:0] wr_data;
+ output [3:0] wr_mem_byte_en;
+ wire [3:0] wr_mem_byte_en_i;
+ output [31:0] wr_mem_data;
+ output wr_mem_en;
+ wire wr_mem_en_i;
+ assign _00_ = ~ mode;
+ assign rd_mem_en_i = _00_ & en;
+ assign wr_mem_en_i = mode & en;
+ assign data_in = rd_mem_en_i ? rd_mem_data : _01_;
+ assign _01_ = wr_mem_en_i ? wr_data : 32'd0;
+ assign _02_ = data_type == 3'h0;
+ assign _03_ = data_type == 3'h4;
+ assign _04_ = data_type == 3'h1;
+ assign _05_ = data_type == 3'h5;
+ function [31:0] \1891 ;
+ input [31:0] a;
+ input [127:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \1891 = b[31:0];
+ 4'b??1?:
+ \1891 = b[63:32];
+ 4'b?1??:
+ \1891 = b[95:64];
+ 4'b1???:
+ \1891 = b[127:96];
+ default:
+ \1891 = a;
+ endcase
+ endfunction
+ assign data_out = \1891 (data_in, { 16'h0000, data_in[15:0], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15], data_in[15:0], 24'h000000, data_in[7:0], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7], data_in[7:0] }, { _05_, _04_, _03_, _02_ });
+ assign _06_ = data_type == 3'h0;
+ assign _07_ = data_type == 3'h4;
+ assign _08_ = _06_ | _07_;
+ assign _09_ = data_type == 3'h1;
+ assign _10_ = data_type == 3'h5;
+ assign _11_ = _09_ | _10_;
+ function [3:0] \1908 ;
+ input [3:0] a;
+ input [7:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1908 = b[3:0];
+ 2'b1?:
+ \1908 = b[7:4];
+ default:
+ \1908 = a;
+ endcase
+ endfunction
+ assign wr_mem_byte_en_i = \1908 (4'hf, 8'h31, { _11_, _08_ });
+ assign _12_ = rd_mem_en_i ? data_out : 32'd0;
+ assign _13_ = wr_mem_en_i ? data_out : 32'd0;
+ assign _14_ = en ? rd_wr_addr : 32'd0;
+ assign _15_ = wr_mem_en_i ? wr_mem_byte_en_i : 4'h0;
+ assign rd_data = _12_;
+ assign rd_mem_en = rd_mem_en_i;
+ assign wr_mem_en = wr_mem_en_i;
+ assign wr_mem_data = _13_;
+ assign rd_wr_mem_addr = _14_;
+ assign wr_mem_byte_en = _15_;
+endmodule
+
+module main_ctrl(opcode, flush, rf_wr_reg_src, rf_wr_reg_en, ig_imm_type, alu_src0, alu_src1, alu_opd0_pass, alu_opd1_pass, alu_op_en, alu_func_type, lsu_mode, lsu_en, brd_en, csrs_wr_en, if_jmp);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire [1:0] _12_;
+ wire _13_;
+ wire [1:0] _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire [2:0] _28_;
+ wire [2:0] _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _37_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
+ wire _43_;
+ wire _44_;
+ wire _45_;
+ wire _46_;
+ wire _47_;
+ wire _48_;
+ wire _49_;
+ wire _50_;
+ wire _51_;
+ wire _52_;
+ wire _53_;
+ wire _54_;
+ wire _55_;
+ wire _56_;
+ wire _57_;
+ wire _58_;
+ wire _59_;
+ wire _60_;
+ wire _61_;
+ wire _62_;
+ wire _63_;
+ wire _64_;
+ wire _65_;
+ wire _66_;
+ wire _67_;
+ wire _68_;
+ wire _69_;
+ output alu_func_type;
+ output alu_op_en;
+ output alu_opd0_pass;
+ output alu_opd1_pass;
+ output alu_src0;
+ output alu_src1;
+ output brd_en;
+ output csrs_wr_en;
+ input flush;
+ output if_jmp;
+ output [2:0] ig_imm_type;
+ output lsu_en;
+ output lsu_mode;
+ input [6:0] opcode;
+ output rf_wr_reg_en;
+ output [1:0] rf_wr_reg_src;
+ assign _00_ = opcode == 7'h33;
+ assign _01_ = opcode == 7'h13;
+ assign _02_ = _00_ | _01_;
+ assign _03_ = opcode == 7'h37;
+ assign _04_ = _02_ | _03_;
+ assign _05_ = opcode == 7'h17;
+ assign _06_ = _04_ | _05_;
+ assign _07_ = opcode == 7'h67;
+ assign _08_ = opcode == 7'h6f;
+ assign _09_ = _07_ | _08_;
+ assign _10_ = opcode == 7'h03;
+ assign _11_ = opcode == 7'h73;
+ function [1:0] \1090 ;
+ input [1:0] a;
+ input [7:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \1090 = b[1:0];
+ 4'b??1?:
+ \1090 = b[3:2];
+ 4'b?1??:
+ \1090 = b[5:4];
+ 4'b1???:
+ \1090 = b[7:6];
+ default:
+ \1090 = a;
+ endcase
+ endfunction
+ assign _12_ = \1090 (2'h0, 8'hd8, { _11_, _10_, _09_, _06_ });
+ function [0:0] \1096 ;
+ input [0:0] a;
+ input [3:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \1096 = b[0:0];
+ 4'b??1?:
+ \1096 = b[1:1];
+ 4'b?1??:
+ \1096 = b[2:2];
+ 4'b1???:
+ \1096 = b[3:3];
+ default:
+ \1096 = a;
+ endcase
+ endfunction
+ assign _13_ = \1096 (1'h0, 4'hf, { _11_, _10_, _09_, _06_ });
+ assign _14_ = flush ? 2'hx : _12_;
+ assign _15_ = flush ? 1'h0 : _13_;
+ assign _16_ = opcode == 7'h13;
+ assign _17_ = opcode == 7'h67;
+ assign _18_ = _16_ | _17_;
+ assign _19_ = opcode == 7'h03;
+ assign _20_ = _18_ | _19_;
+ assign _21_ = opcode == 7'h37;
+ assign _22_ = opcode == 7'h17;
+ assign _23_ = _21_ | _22_;
+ assign _24_ = opcode == 7'h23;
+ assign _25_ = opcode == 7'h63;
+ assign _26_ = opcode == 7'h6f;
+ assign _27_ = opcode == 7'h73;
+ function [2:0] \1132 ;
+ input [2:0] a;
+ input [17:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1132 = b[2:0];
+ 6'b????1?:
+ \1132 = b[5:3];
+ 6'b???1??:
+ \1132 = b[8:6];
+ 6'b??1???:
+ \1132 = b[11:9];
+ 6'b?1????:
+ \1132 = b[14:12];
+ 6'b1?????:
+ \1132 = b[17:15];
+ default:
+ \1132 = a;
+ endcase
+ endfunction
+ assign _28_ = \1132 (3'hx, 18'h2c458, { _27_, _26_, _25_, _24_, _23_, _20_ });
+ assign _29_ = flush ? 3'hx : _28_;
+ assign _30_ = opcode == 7'h33;
+ assign _31_ = opcode == 7'h13;
+ assign _32_ = opcode == 7'h67;
+ assign _33_ = opcode == 7'h63;
+ assign _34_ = opcode == 7'h17;
+ assign _35_ = _33_ | _34_;
+ assign _36_ = opcode == 7'h6f;
+ assign _37_ = _35_ | _36_;
+ assign _38_ = opcode == 7'h03;
+ assign _39_ = opcode == 7'h23;
+ assign _40_ = _38_ | _39_;
+ assign _41_ = opcode == 7'h37;
+ function [0:0] \1166 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1166 = b[0:0];
+ 6'b????1?:
+ \1166 = b[1:1];
+ 6'b???1??:
+ \1166 = b[2:2];
+ 6'b??1???:
+ \1166 = b[3:3];
+ 6'b?1????:
+ \1166 = b[4:4];
+ 6'b1?????:
+ \1166 = b[5:5];
+ default:
+ \1166 = a;
+ endcase
+ endfunction
+ assign _42_ = \1166 (1'h0, 6'bx01000, { _41_, _40_, _37_, _32_, _31_, _30_ });
+ function [0:0] \1174 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1174 = b[0:0];
+ 6'b????1?:
+ \1174 = b[1:1];
+ 6'b???1??:
+ \1174 = b[2:2];
+ 6'b??1???:
+ \1174 = b[3:3];
+ 6'b?1????:
+ \1174 = b[4:4];
+ 6'b1?????:
+ \1174 = b[5:5];
+ default:
+ \1174 = a;
+ endcase
+ endfunction
+ assign _43_ = \1174 (1'h0, 6'h3e, { _41_, _40_, _37_, _32_, _31_, _30_ });
+ function [0:0] \1182 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1182 = b[0:0];
+ 6'b????1?:
+ \1182 = b[1:1];
+ 6'b???1??:
+ \1182 = b[2:2];
+ 6'b??1???:
+ \1182 = b[3:3];
+ 6'b?1????:
+ \1182 = b[4:4];
+ 6'b1?????:
+ \1182 = b[5:5];
+ default:
+ \1182 = a;
+ endcase
+ endfunction
+ assign _44_ = \1182 (1'h0, 6'h1f, { _41_, _40_, _37_, _32_, _31_, _30_ });
+ function [0:0] \1190 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1190 = b[0:0];
+ 6'b????1?:
+ \1190 = b[1:1];
+ 6'b???1??:
+ \1190 = b[2:2];
+ 6'b??1???:
+ \1190 = b[3:3];
+ 6'b?1????:
+ \1190 = b[4:4];
+ 6'b1?????:
+ \1190 = b[5:5];
+ default:
+ \1190 = a;
+ endcase
+ endfunction
+ assign _45_ = \1190 (1'h0, 6'h3f, { _41_, _40_, _37_, _32_, _31_, _30_ });
+ function [0:0] \1198 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1198 = b[0:0];
+ 6'b????1?:
+ \1198 = b[1:1];
+ 6'b???1??:
+ \1198 = b[2:2];
+ 6'b??1???:
+ \1198 = b[3:3];
+ 6'b?1????:
+ \1198 = b[4:4];
+ 6'b1?????:
+ \1198 = b[5:5];
+ default:
+ \1198 = a;
+ endcase
+ endfunction
+ assign _46_ = \1198 (1'h0, 6'h03, { _41_, _40_, _37_, _32_, _31_, _30_ });
+ function [0:0] \1206 ;
+ input [0:0] a;
+ input [5:0] b;
+ input [5:0] s;
+ (* parallel_case *)
+ casez (s)
+ 6'b?????1:
+ \1206 = b[0:0];
+ 6'b????1?:
+ \1206 = b[1:1];
+ 6'b???1??:
+ \1206 = b[2:2];
+ 6'b??1???:
+ \1206 = b[3:3];
+ 6'b?1????:
+ \1206 = b[4:4];
+ 6'b1?????:
+ \1206 = b[5:5];
+ default:
+ \1206 = a;
+ endcase
+ endfunction
+ assign _47_ = \1206 (1'h0, 6'h02, { _41_, _40_, _37_, _32_, _31_, _30_ });
+ assign _48_ = flush ? 1'h0 : _42_;
+ assign _49_ = flush ? 1'h0 : _43_;
+ assign _50_ = flush ? 1'h0 : _44_;
+ assign _51_ = flush ? 1'h0 : _45_;
+ assign _52_ = flush ? 1'h0 : _46_;
+ assign _53_ = flush ? 1'h0 : _47_;
+ assign _54_ = opcode == 7'h03;
+ assign _55_ = opcode == 7'h23;
+ function [0:0] \1229 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1229 = b[0:0];
+ 2'b1?:
+ \1229 = b[1:1];
+ default:
+ \1229 = a;
+ endcase
+ endfunction
+ assign _56_ = \1229 (1'hx, 2'h2, { _55_, _54_ });
+ function [0:0] \1233 ;
+ input [0:0] a;
+ input [1:0] b;
+ input [1:0] s;
+ (* parallel_case *)
+ casez (s)
+ 2'b?1:
+ \1233 = b[0:0];
+ 2'b1?:
+ \1233 = b[1:1];
+ default:
+ \1233 = a;
+ endcase
+ endfunction
+ assign _57_ = \1233 (1'h0, 2'h3, { _55_, _54_ });
+ assign _58_ = flush ? 1'hx : _56_;
+ assign _59_ = flush ? 1'h0 : _57_;
+ assign _60_ = opcode == 7'h63;
+ assign _61_ = _60_ ? 1'h1 : 1'h0;
+ assign _62_ = flush ? 1'h0 : _61_;
+ assign _63_ = opcode == 7'h73;
+ assign _64_ = _63_ ? 1'h1 : 1'h0;
+ assign _65_ = opcode == 7'h67;
+ assign _66_ = opcode == 7'h6f;
+ assign _67_ = _65_ | _66_;
+ function [0:0] \1263 ;
+ input [0:0] a;
+ input [0:0] b;
+ input [0:0] s;
+ (* parallel_case *)
+ casez (s)
+ 1'b1:
+ \1263 = b[0:0];
+ default:
+ \1263 = a;
+ endcase
+ endfunction
+ assign _68_ = \1263 (1'h0, 1'h1, _67_);
+ assign _69_ = flush ? 1'h0 : _68_;
+ assign rf_wr_reg_src = _14_;
+ assign rf_wr_reg_en = _15_;
+ assign ig_imm_type = _29_;
+ assign alu_src0 = _48_;
+ assign alu_src1 = _49_;
+ assign alu_opd0_pass = _50_;
+ assign alu_opd1_pass = _51_;
+ assign alu_op_en = _52_;
+ assign alu_func_type = _53_;
+ assign lsu_mode = _58_;
+ assign lsu_en = _59_;
+ assign brd_en = _62_;
+ assign csrs_wr_en = _64_;
+ assign if_jmp = _69_;
+endmodule
+
+module piso_8(clk, clr, en, mode, load, ser);
+ wire [7:0] _0_;
+ wire [7:0] _1_;
+ input clk;
+ input clr;
+ input en;
+ reg [7:0] inter_val;
+ input [7:0] load;
+ input mode;
+ output ser;
+ assign _0_ = mode ? load : { 1'h1, inter_val[7:1] };
+ assign _1_ = en ? _0_ : inter_val;
+ always @(posedge clk, posedge clr)
+ if (clr) inter_val <= 8'hff;
+ else inter_val <= _1_;
+ assign ser = inter_val[0];
+endmodule
+
+module ram_8(clk, rd_addr0, rd_addr1, wr_addr, wr_data, wr_byte_en, wr, rd_data0, rd_data1);
+ wire _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire [511:0] _04_;
+ wire [7:0] _05_;
+ wire [511:0] _06_;
+ wire [7:0] _07_;
+ wire [511:0] _08_;
+ wire [7:0] _09_;
+ wire [511:0] _10_;
+ wire [7:0] _11_;
+ wire [511:0] _12_;
+ wire [7:0] _13_;
+ wire [511:0] _14_;
+ wire [7:0] _15_;
+ wire [511:0] _16_;
+ wire [7:0] _17_;
+ wire [511:0] _18_;
+ wire [7:0] _19_;
+ input clk;
+ input [5:0] rd_addr0;
+ input [5:0] rd_addr1;
+ output [31:0] rd_data0;
+ output [31:0] rd_data1;
+ input wr;
+ input [5:0] wr_addr;
+ input [3:0] wr_byte_en;
+ input [31:0] wr_data;
+ reg [7:0] mem0 [63:0];
+ always @(posedge clk) begin
+ if (_00_)
+ mem0[wr_addr] <= wr_data[7:0];
+ end
+ assign _05_ = mem0[rd_addr1];
+ assign _07_ = mem0[rd_addr0];
+ reg [7:0] mem1 [63:0];
+ always @(posedge clk) begin
+ if (_01_)
+ mem1[wr_addr] <= wr_data[15:8];
+ end
+ assign _09_ = mem1[rd_addr1];
+ assign _11_ = mem1[rd_addr0];
+ reg [7:0] mem2 [63:0];
+ always @(posedge clk) begin
+ if (_02_)
+ mem2[wr_addr] <= wr_data[23:16];
+ end
+ assign _13_ = mem2[rd_addr1];
+ assign _15_ = mem2[rd_addr0];
+ reg [7:0] mem3 [63:0];
+ always @(posedge clk) begin
+ if (_03_)
+ mem3[wr_addr] <= wr_data[31:24];
+ end
+ assign _17_ = mem3[rd_addr1];
+ assign _19_ = mem3[rd_addr0];
+ assign _00_ = wr_byte_en[0] & wr;
+ assign _01_ = wr_byte_en[1] & wr;
+ assign _02_ = wr_byte_en[2] & wr;
+ assign _03_ = wr_byte_en[3] & wr;
+ assign rd_data0 = { _19_, _15_, _11_, _07_ };
+ assign rd_data1 = { _17_, _13_, _09_, _05_ };
+endmodule
+
+module reg_file(clk, rd_reg_addr0, rd_reg_addr1, wr_reg_addr, wr_reg_data, wr_reg_en, rd_reg_data0, rd_reg_data1);
+ wire _0_;
+ wire _1_;
+ wire _2_;
+ wire [31:0] _3_;
+ wire _4_;
+ wire [31:0] _5_;
+ wire [1023:0] _6_;
+ wire [31:0] _7_;
+ wire [1023:0] _8_;
+ wire [31:0] _9_;
+ input clk;
+ input [4:0] rd_reg_addr0;
+ input [4:0] rd_reg_addr1;
+ output [31:0] rd_reg_data0;
+ output [31:0] rd_reg_data1;
+ input [4:0] wr_reg_addr;
+ input [31:0] wr_reg_data;
+ input wr_reg_en;
+ reg [31:0] regs [31:0];
+ always @(posedge clk) begin
+ if (_0_)
+ regs[wr_reg_addr] <= wr_reg_data;
+ end
+ assign _7_ = regs[rd_reg_addr1];
+ assign _9_ = regs[rd_reg_addr0];
+ assign _0_ = wr_reg_en & _1_;
+ assign _1_ = wr_reg_addr != 5'h00;
+ assign _2_ = rd_reg_addr0 == 5'h00;
+ assign _3_ = _2_ ? 32'd0 : _9_;
+ assign _4_ = rd_reg_addr1 == 5'h00;
+ assign _5_ = _4_ ? 32'd0 : _7_;
+ assign rd_reg_data0 = _3_;
+ assign rd_reg_data1 = _5_;
+endmodule
+
+module rom_8(rd, rd_addr, rd_data);
+ wire [5:0] _0_;
+ wire [31:0] _1_;
+ wire [2047:0] _2_;
+ wire [31:0] _3_;
+ input rd;
+ input [5:0] rd_addr;
+ output [31:0] rd_data;
+ reg [31:0] \178 [63:0];
+ initial begin
+ \178 [0] = 32'd19;
+ \178 [1] = 32'd19;
+ \178 [2] = 32'd19;
+ \178 [3] = 32'd19;
+ \178 [4] = 32'd19;
+ \178 [5] = 32'd19;
+ \178 [6] = 32'd19;
+ \178 [7] = 32'd19;
+ \178 [8] = 32'd19;
+ \178 [9] = 32'd19;
+ \178 [10] = 32'd19;
+ \178 [11] = 32'd19;
+ \178 [12] = 32'd19;
+ \178 [13] = 32'd19;
+ \178 [14] = 32'd19;
+ \178 [15] = 32'd19;
+ \178 [16] = 32'd19;
+ \178 [17] = 32'd19;
+ \178 [18] = 32'd19;
+ \178 [19] = 32'd19;
+ \178 [20] = 32'd19;
+ \178 [21] = 32'd19;
+ \178 [22] = 32'd19;
+ \178 [23] = 32'd19;
+ \178 [24] = 32'd19;
+ \178 [25] = 32'd19;
+ \178 [26] = 32'd19;
+ \178 [27] = 32'd19;
+ \178 [28] = 32'd19;
+ \178 [29] = 32'd19;
+ \178 [30] = 32'd19;
+ \178 [31] = 32'd19;
+ \178 [32] = 32'd19;
+ \178 [33] = 32'd19;
+ \178 [34] = 32'd19;
+ \178 [35] = 32'd19;
+ \178 [36] = 32'd19;
+ \178 [37] = 32'd32871;
+ \178 [38] = 32'd12592387;
+ \178 [39] = 32'd4291009763;
+ \178 [40] = 32'd4453267;
+ \178 [41] = 32'd17283;
+ \178 [42] = 32'd4197907;
+ \178 [43] = 32'd915;
+ \178 [44] = 32'd188743791;
+ \178 [45] = 32'd4266879715;
+ \178 [46] = 32'd1245971;
+ \178 [47] = 32'd547553315;
+ \178 [48] = 32'd20971759;
+ \178 [49] = 32'd787;
+ \178 [50] = 32'd4267700335;
+ \178 [51] = 32'd5469283;
+ \178 [52] = 32'd268436243;
+ \178 [53] = 32'd328339;
+ \178 [54] = 32'd46137583;
+ \178 [55] = 32'd4272069859;
+ \178 [56] = 32'd54526191;
+ \178 [57] = 32'd124781203;
+ \178 [58] = 32'd5248035;
+ \178 [59] = 32'd455082643;
+ \178 [60] = 32'd3603;
+ \178 [61] = 32'd915;
+ \178 [62] = 32'd787;
+ \178 [63] = 32'd659;
+ end
+ assign _3_ = \178 [_0_];
+ assign _0_ = 6'h3f - rd_addr;
+ assign _1_ = rd ? _3_ : 32'd0;
+ assign rd_data = _1_;
+endmodule
+
+module sipo_8(clk, clr, en, ser, val);
+ wire [7:0] _0_;
+ input clk;
+ input clr;
+ input en;
+ reg [7:0] inter_val;
+ input ser;
+ output [7:0] val;
+ assign _0_ = en ? { ser, inter_val[7:1] } : inter_val;
+ always @(posedge clk, posedge clr)
+ if (clr) inter_val <= 8'hff;
+ else inter_val <= _0_;
+ assign val = inter_val;
+endmodule
+
+module uart(clk, reset, rd, rd_addr, wr, wr_addr, wr_data, rx, rd_data, tx);
+ wire [1:0] _00_;
+ wire [7:0] _01_;
+ wire [15:0] _02_;
+ wire _03_;
+ wire _04_;
+ wire [15:0] _05_;
+ wire _06_;
+ wire _07_;
+ wire _08_;
+ wire _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire [5:0] _14_;
+ reg [15:0] baud_div;
+ input clk;
+ input rd;
+ input [1:0] rd_addr;
+ output [15:0] rd_data;
+ wire \receiver:323 ;
+ wire [7:0] \receiver:324 ;
+ wire \receiver:325 ;
+ input reset;
+ input rx;
+ wire \rx_fifo:314 ;
+ wire \rx_fifo:315 ;
+ wire [7:0] \rx_fifo:316 ;
+ wire rx_fifo_rd;
+ wire \transmitter:348 ;
+ wire \transmitter:349 ;
+ wire \transmitter:350 ;
+ output tx;
+ wire \tx_fifo:339 ;
+ wire \tx_fifo:340 ;
+ wire [7:0] \tx_fifo:341 ;
+ wire tx_fifo_wr;
+ input wr;
+ input [1:0] wr_addr;
+ input [15:0] wr_data;
+ assign _03_ = wr_addr == 2'h2;
+ assign _04_ = wr & _03_;
+ assign _05_ = _04_ ? wr_data : baud_div;
+ always @(posedge clk, posedge reset)
+ if (reset) baud_div <= 16'hffff;
+ else baud_div <= _05_;
+ assign _06_ = rd_addr == 2'h3;
+ assign _07_ = rd & _06_;
+ assign rx_fifo_rd = _07_ ? 1'h1 : 1'h0;
+ assign _08_ = wr_addr == 2'h3;
+ assign _09_ = wr & _08_;
+ assign tx_fifo_wr = _09_ ? 1'h1 : 1'h0;
+ assign _10_ = rd_addr == 2'h0;
+ assign _11_ = rd_addr == 2'h1;
+ assign _12_ = rd_addr == 2'h2;
+ assign _13_ = rd_addr == 2'h3;
+ function [5:0] \376 ;
+ input [5:0] a;
+ input [23:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \376 = b[5:0];
+ 4'b??1?:
+ \376 = b[11:6];
+ 4'b?1??:
+ \376 = b[17:12];
+ 4'b1???:
+ \376 = b[23:18];
+ default:
+ \376 = a;
+ endcase
+ endfunction
+ assign _14_ = \376 (6'h00, { \rx_fifo:316 [5:0], baud_div[5:0], 6'h00, \tx_fifo:339 , \rx_fifo:314 , \tx_fifo:340 , \rx_fifo:315 , \transmitter:349 , \receiver:325 }, { _13_, _12_, _11_, _10_ });
+ function [1:0] \382 ;
+ input [1:0] a;
+ input [7:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \382 = b[1:0];
+ 4'b??1?:
+ \382 = b[3:2];
+ 4'b?1??:
+ \382 = b[5:4];
+ 4'b1???:
+ \382 = b[7:6];
+ default:
+ \382 = a;
+ endcase
+ endfunction
+ assign _00_ = \382 (2'h0, { \rx_fifo:316 [7:6], baud_div[7:6], 4'h0 }, { _13_, _12_, _11_, _10_ });
+ function [7:0] \387 ;
+ input [7:0] a;
+ input [31:0] b;
+ input [3:0] s;
+ (* parallel_case *)
+ casez (s)
+ 4'b???1:
+ \387 = b[7:0];
+ 4'b??1?:
+ \387 = b[15:8];
+ 4'b?1??:
+ \387 = b[23:16];
+ 4'b1???:
+ \387 = b[31:24];
+ default:
+ \387 = a;
+ endcase
+ endfunction
+ assign _01_ = \387 (8'h00, { 8'h00, baud_div[15:8], 16'h0300 }, { _13_, _12_, _11_, _10_ });
+ assign _02_ = rd ? { _01_, _00_, _14_ } : 16'h0000;
+ uart_rx receiver (
+ .baud_div(baud_div),
+ .busy(\receiver:325 ),
+ .clk(clk),
+ .reset(reset),
+ .rx(rx),
+ .wr(\receiver:323 ),
+ .wr_data(\receiver:324 ),
+ .wr_en(\rx_fifo:314 )
+ );
+ fifo_8_8 rx_fifo (
+ .clk(clk),
+ .rd(rx_fifo_rd),
+ .rd_data(\rx_fifo:316 ),
+ .rd_en(\rx_fifo:315 ),
+ .reset(reset),
+ .wr(\receiver:323 ),
+ .wr_data(\receiver:324 ),
+ .wr_en(\rx_fifo:314 )
+ );
+ uart_tx transmitter (
+ .baud_div(baud_div),
+ .busy(\transmitter:349 ),
+ .clk(clk),
+ .rd(\transmitter:348 ),
+ .rd_data(\tx_fifo:341 ),
+ .rd_en(\tx_fifo:340 ),
+ .reset(reset),
+ .tx(\transmitter:350 )
+ );
+ fifo_8_8 tx_fifo (
+ .clk(clk),
+ .rd(\transmitter:348 ),
+ .rd_data(\tx_fifo:341 ),
+ .rd_en(\tx_fifo:340 ),
+ .reset(reset),
+ .wr(tx_fifo_wr),
+ .wr_data(wr_data[7:0]),
+ .wr_en(\tx_fifo:339 )
+ );
+ assign rd_data = _02_;
+ assign tx = \transmitter:350 ;
+endmodule
+
+module uart_rx(clk, reset, baud_div, wr_en, rx, wr, wr_data, busy);
+ wire [2:0] _00_;
+ wire _01_;
+ wire _02_;
+ wire _03_;
+ wire [2:0] _04_;
+ wire _05_;
+ wire [2:0] _06_;
+ wire _07_;
+ wire _08_;
+ wire [2:0] _09_;
+ wire _10_;
+ wire [2:0] _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire [15:0] \baud_counter:668 ;
+ wire baud_counter_clr;
+ wire baud_counter_en;
+ wire [15:0] baud_counter_load;
+ wire baud_counter_mode;
+ wire baud_counter_tc;
+ input [15:0] baud_div;
+ output busy;
+ input clk;
+ reg [2:0] curr_state;
+ wire [2:0] next_state;
+ input reset;
+ input rx;
+ wire [2:0] \rx_counter:687 ;
+ wire rx_counter_clr;
+ wire rx_counter_en;
+ wire rx_counter_tc;
+ wire [7:0] \rx_sipo:702 ;
+ wire rx_sipo_clr;
+ wire rx_sipo_en;
+ output wr;
+ output [7:0] wr_data;
+ input wr_en;
+ assign _00_ = reset ? 3'h0 : next_state;
+ always @(posedge clk)
+ curr_state <= _00_;
+ assign _01_ = curr_state == 3'h0;
+ assign _02_ = ~ rx;
+ assign _03_ = wr_en & _02_;
+ assign _04_ = _03_ ? 3'h2 : 3'h1;
+ assign _05_ = curr_state == 3'h1;
+ assign _06_ = baud_counter_tc ? 3'h3 : 3'h2;
+ assign _07_ = curr_state == 3'h2;
+ assign _08_ = baud_counter_tc & rx_counter_tc;
+ assign _09_ = _08_ ? 3'h4 : 3'h3;
+ assign _10_ = curr_state == 3'h3;
+ assign _11_ = baud_counter_tc ? 3'h1 : 3'h4;
+ assign _12_ = curr_state == 3'h4;
+ function [2:0] \639 ;
+ input [2:0] a;
+ input [14:0] b;
+ input [4:0] s;
+ (* parallel_case *)
+ casez (s)
+ 5'b????1:
+ \639 = b[2:0];
+ 5'b???1?:
+ \639 = b[5:3];
+ 5'b??1??:
+ \639 = b[8:6];
+ 5'b?1???:
+ \639 = b[11:9];
+ 5'b1????:
+ \639 = b[14:12];
+ default:
+ \639 = a;
+ endcase
+ endfunction
+ assign next_state = \639 (3'hx, { _11_, _09_, _06_, _04_, 3'h1 }, { _12_, _10_, _07_, _05_, _01_ });
+ assign _13_ = curr_state == 3'h2;
+ assign baud_counter_load = _13_ ? { 1'h0, baud_div[15:1] } : baud_div;
+ assign _14_ = \baud_counter:668 == 16'h0000;
+ assign baud_counter_tc = _14_ ? 1'h1 : 1'h0;
+ assign _15_ = curr_state == 3'h0;
+ assign baud_counter_clr = _15_ ? 1'h1 : 1'h0;
+ assign _16_ = curr_state == 3'h0;
+ assign baud_counter_en = _16_ ? 1'h0 : 1'h1;
+ assign _17_ = curr_state == 3'h1;
+ assign _18_ = _17_ | baud_counter_tc;
+ assign baud_counter_mode = _18_ ? 1'h1 : 1'h0;
+ assign _19_ = \rx_counter:687 == 3'h0;
+ assign rx_counter_tc = _19_ ? 1'h1 : 1'h0;
+ assign _20_ = curr_state == 3'h0;
+ assign rx_counter_clr = _20_ ? 1'h1 : 1'h0;
+ assign _21_ = curr_state == 3'h3;
+ assign rx_counter_en = _21_ ? baud_counter_tc : 1'h0;
+ assign _22_ = curr_state == 3'h0;
+ assign rx_sipo_clr = _22_ ? 1'h1 : 1'h0;
+ assign _23_ = curr_state == 3'h2;
+ assign _24_ = curr_state == 3'h3;
+ assign _25_ = _23_ | _24_;
+ assign rx_sipo_en = _25_ ? baud_counter_tc : 1'h0;
+ assign _26_ = curr_state == 3'h4;
+ assign _27_ = next_state == 3'h1;
+ assign _28_ = _26_ & _27_;
+ assign _29_ = _28_ ? 1'h1 : 1'h0;
+ assign _30_ = curr_state == 3'h1;
+ assign _31_ = _30_ ? 1'h0 : 1'h1;
+ down_counter_16 baud_counter (
+ .clk(clk),
+ .clr(baud_counter_clr),
+ .en(baud_counter_en),
+ .load(baud_counter_load),
+ .mode(baud_counter_mode),
+ .val(\baud_counter:668 )
+ );
+ down_counter_3 rx_counter (
+ .clk(clk),
+ .clr(rx_counter_clr),
+ .en(rx_counter_en),
+ .load(3'h7),
+ .mode(1'h0),
+ .val(\rx_counter:687 )
+ );
+ sipo_8 rx_sipo (
+ .clk(clk),
+ .clr(rx_sipo_clr),
+ .en(rx_sipo_en),
+ .ser(rx),
+ .val(\rx_sipo:702 )
+ );
+ assign wr = _29_;
+ assign wr_data = \rx_sipo:702 ;
+ assign busy = _31_;
+endmodule
+
+module uart_tx(clk, reset, baud_div, rd_en, rd_data, rd, busy, tx);
+ wire [2:0] _00_;
+ wire _01_;
+ wire [2:0] _02_;
+ wire _03_;
+ wire [2:0] _04_;
+ wire _05_;
+ wire _06_;
+ wire [2:0] _07_;
+ wire _08_;
+ wire [2:0] _09_;
+ wire _10_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _17_;
+ wire _18_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
+ wire _23_;
+ wire _24_;
+ wire _25_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire [15:0] \baud_counter:779 ;
+ wire baud_counter_clr;
+ wire baud_counter_en;
+ wire baud_counter_mode;
+ wire baud_counter_tc;
+ input [15:0] baud_div;
+ output busy;
+ input clk;
+ reg [2:0] curr_state;
+ wire [2:0] next_state;
+ output rd;
+ input [7:0] rd_data;
+ input rd_en;
+ input reset;
+ output tx;
+ wire tx_bit;
+ wire [2:0] \tx_counter:798 ;
+ wire tx_counter_clr;
+ wire tx_counter_en;
+ wire tx_counter_tc;
+ wire \tx_piso:818 ;
+ wire tx_piso_clr;
+ wire tx_piso_en;
+ wire tx_piso_mode;
+ assign _00_ = reset ? 3'h0 : next_state;
+ always @(posedge clk)
+ curr_state <= _00_;
+ assign _01_ = curr_state == 3'h0;
+ assign _02_ = rd_en ? 3'h2 : 3'h1;
+ assign _03_ = curr_state == 3'h1;
+ assign _04_ = baud_counter_tc ? 3'h3 : 3'h2;
+ assign _05_ = curr_state == 3'h2;
+ assign _06_ = baud_counter_tc & tx_counter_tc;
+ assign _07_ = _06_ ? 3'h4 : 3'h3;
+ assign _08_ = curr_state == 3'h3;
+ assign _09_ = baud_counter_tc ? 3'h1 : 3'h4;
+ assign _10_ = curr_state == 3'h4;
+ function [2:0] \756 ;
+ input [2:0] a;
+ input [14:0] b;
+ input [4:0] s;
+ (* parallel_case *)
+ casez (s)
+ 5'b????1:
+ \756 = b[2:0];
+ 5'b???1?:
+ \756 = b[5:3];
+ 5'b??1??:
+ \756 = b[8:6];
+ 5'b?1???:
+ \756 = b[11:9];
+ 5'b1????:
+ \756 = b[14:12];
+ default:
+ \756 = a;
+ endcase
+ endfunction
+ assign next_state = \756 (3'hx, { _09_, _07_, _04_, _02_, 3'h1 }, { _10_, _08_, _05_, _03_, _01_ });
+ assign _11_ = \baud_counter:779 == 16'h0000;
+ assign baud_counter_tc = _11_ ? 1'h1 : 1'h0;
+ assign _12_ = curr_state == 3'h0;
+ assign baud_counter_clr = _12_ ? 1'h1 : 1'h0;
+ assign _13_ = curr_state == 3'h0;
+ assign baud_counter_en = _13_ ? 1'h0 : 1'h1;
+ assign _14_ = curr_state == 3'h1;
+ assign _15_ = _14_ | baud_counter_tc;
+ assign baud_counter_mode = _15_ ? 1'h1 : 1'h0;
+ assign _16_ = \tx_counter:798 == 3'h0;
+ assign tx_counter_tc = _16_ ? 1'h1 : 1'h0;
+ assign _17_ = curr_state == 3'h0;
+ assign tx_counter_clr = _17_ ? 1'h1 : 1'h0;
+ assign _18_ = curr_state == 3'h3;
+ assign tx_counter_en = _18_ ? baud_counter_tc : 1'h0;
+ assign _19_ = curr_state == 3'h0;
+ assign tx_piso_clr = _19_ ? 1'h1 : 1'h0;
+ assign _20_ = curr_state == 3'h2;
+ assign _21_ = curr_state == 3'h3;
+ assign _22_ = _20_ | _21_;
+ assign tx_piso_en = _22_ ? baud_counter_tc : 1'h0;
+ assign _23_ = curr_state == 3'h2;
+ assign tx_piso_mode = _23_ ? 1'h1 : 1'h0;
+ assign _24_ = curr_state == 3'h1;
+ assign _25_ = next_state == 3'h2;
+ assign _26_ = _24_ & _25_;
+ assign _27_ = _26_ ? 1'h1 : 1'h0;
+ assign _28_ = curr_state == 3'h2;
+ assign tx_bit = _28_ ? 1'h0 : 1'h1;
+ assign _29_ = curr_state == 3'h3;
+ assign _30_ = _29_ ? \tx_piso:818 : tx_bit;
+ assign _31_ = curr_state == 3'h1;
+ assign _32_ = _31_ ? 1'h0 : 1'h1;
+ down_counter_16 baud_counter (
+ .clk(clk),
+ .clr(baud_counter_clr),
+ .en(baud_counter_en),
+ .load(baud_div),
+ .mode(baud_counter_mode),
+ .val(\baud_counter:779 )
+ );
+ down_counter_3 tx_counter (
+ .clk(clk),
+ .clr(tx_counter_clr),
+ .en(tx_counter_en),
+ .load(3'h7),
+ .mode(1'h0),
+ .val(\tx_counter:798 )
+ );
+ piso_8 tx_piso (
+ .clk(clk),
+ .clr(tx_piso_clr),
+ .en(tx_piso_en),
+ .load(rd_data),
+ .mode(tx_piso_mode),
+ .ser(\tx_piso:818 )
+ );
+ assign rd = _27_;
+ assign busy = _32_;
+ assign tx = _30_;
+endmodule
