wb_port working
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 425c115..4f59055 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -16,16 +16,14 @@
*/
// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
/*
Wishbone Test:
- Configures MPRJ lower 8-IO pins as outputs
- Checks counter value through the wishbone port
*/
-int i = 0;
-int clk = 0;
void main()
{
@@ -47,7 +45,9 @@
/* Set up the housekeeping SPI to be connected internally so */
/* that external pin changes don't affect it. */
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ reg_spi_enable = 1;
+ reg_wb_enable = 1;
+ // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
// Connect the housekeeping SPI to the SPI master
@@ -75,15 +75,13 @@
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
// Flag start of the test
reg_mprj_datal = 0xAB600000;
reg_mprj_slave = 0x00002710;
- if (reg_mprj_slave == 0x2752) {
+ if (reg_mprj_slave == 0x2B3D) {
reg_mprj_datal = 0xAB610000;
- } else {
- reg_mprj_datal = 0xAB600000;
}
}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index b32f900..60529dc 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -17,9 +17,9 @@
`timescale 1 ns / 1 ps
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
+// `include "uprj_netlists.v"
+// `include "caravel_netlists.v"
+// `include "spiflash.v"
module wb_port_tb;
reg clock;
@@ -35,7 +35,7 @@
assign checkbits = mprj_io[31:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = CSB;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -52,7 +52,7 @@
$dumpvars(0, wb_port_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (30) begin
+ repeat (50) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -67,9 +67,9 @@
end
initial begin
- wait(checkbits == 16'h AB60);
+ wait(checkbits == 16'hAB60);
$display("Monitor: MPRJ-Logic WB Started");
- wait(checkbits == 16'h AB61);
+ wait(checkbits == 16'hAB61);
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Passed");
`else
@@ -90,20 +90,10 @@
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
- power3 <= 1'b0;
- power4 <= 1'b0;
- #100;
+ #200;
power1 <= 1'b1;
- #100;
+ #200;
power2 <= 1'b1;
- #100;
- power3 <= 1'b1;
- #100;
- power4 <= 1'b1;
- end
-
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
end
wire flash_csb;
@@ -119,22 +109,26 @@
caravel uut (
.vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
.vssio (VSS),
+ .vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
- .vdda1 (USER_VDD3V3),
- .vdda2 (USER_VDD3V3),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
.vssa1 (VSS),
+ .vssa1_2 (VSS),
.vssa2 (VSS),
- .vccd1 (USER_VDD1V8),
- .vccd2 (USER_VDD1V8),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
- .clock (clock),
+ .clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
