cleanup
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index be842fc..d151b60 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,10 +19,6 @@
.SUFFIXES:
.SILENT: clean all
-export DESIGNS = $(CARAVEL_ROOT)
-export TOOLS = /opt/riscv32i/
-
-echo $TOOLS
PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
index 08843ce..4e526ba 100644
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ b/verilog/dv/io_ports/io_ports_tb.v
@@ -26,6 +26,7 @@
reg RSTB;
reg CSB;
reg power1, power2;
+ reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
@@ -35,13 +36,13 @@
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
// assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // assign mprj_io[3] = 1'b1;
+ // assign mprj_io[3] = CSB;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
- always #10 clock <= (clock === 1'b0);
+ always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
@@ -78,10 +79,6 @@
wait(mprj_io_0 == 8'h08);
wait(mprj_io_0 == 8'h09);
wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'h0A);
wait(mprj_io_0 == 8'hFF);
wait(mprj_io_0 == 8'h00);
@@ -95,18 +92,26 @@
initial begin
RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
+ CSB <= 1'b1; // Force CSB high
#2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
- #200;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
power1 <= 1'b1;
- #200;
+ #100;
power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
end
always @(mprj_io) begin
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index 93fafeb..4f251fa 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -50,24 +50,11 @@
$dumpvars(0, la_test1_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- // repeat (200) begin
- // repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- // end
- // $display("%c[1;31m",27);
- // `ifdef GL
- // $display ("Monitor: Timeout, Test LA (GL) Failed");
- // `else
- // $display ("Monitor: Timeout, Test LA (RTL) Failed");
- // `endif
- // $display("%c[0m",27);
- // $finish;
- // $display("Wait for UART o/p");
- repeat (450) begin
+ repeat (200) begin
repeat (1000) @(posedge clock);
- // Diagnostic. . . interrupts output pattern.
+ // $display("+1000 cycles");
end
- $display("%c[1;31m",27);
+ $display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test LA (GL) Failed");
`else
@@ -77,29 +64,22 @@
$finish;
end
- // initial begin
- // wait(checkbits == 16'hAB40);
- // $display("LA Test 1 started");
- // wait(checkbits == 16'hAB41);
- // wait(checkbits == 16'hAB51);
- // #10000;
- // $finish;
- // end
-
- // initial begin
- // RSTB <= 1'b0;
- // CSB <= 1'b1; // Force CSB high
- // #2000;
- // RSTB <= 1'b1; // Release reset
- // #170000;
- // CSB = 1'b0; // CSB can be released
- // end
+ initial begin
+ wait(checkbits == 16'hAB40);
+ $display("LA Test 1 started");
+ wait(checkbits == 16'hAB41);
+ wait(checkbits == 16'hAB51);
+ #10000;
+ $finish;
+ end
initial begin
RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
+ CSB <= 1'b1; // Force CSB high
#2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
@@ -111,23 +91,6 @@
power2 <= 1'b1;
end
- always @(checkbits) begin
- if(checkbits == 16'hAB40) begin
- $display("LA Test 1 started");
- end
- else if(checkbits == 16'hAB41) begin
- $display("First check passed");
- end
- else if(checkbits == 16'hAB51) begin
- `ifdef GL
- $display("UART Test (GL) passed");
- `else
- $display("UART Test (RTL) passed");
- `endif
- $finish;
- end
- end
-
wire flash_csb;
wire flash_clk;
wire flash_io0;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 8088ecc..1f956a3 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -33,14 +33,10 @@
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [3:0] status;
- wire [1:0] lol;
- wire [15:0] lol2;
// Signals Assignment
assign checkbits = mprj_io[31:16];
assign status = mprj_io[35:32];
- assign lol = mprj_io[37:36];
- assign lol2 = mprj_io[15:0];
// Force CSB high until simulation is underway
@@ -88,11 +84,11 @@
// Reset Operation
initial begin
- RSTB <= 1'b0;
+ RSTB <= 1'b0;
CSB <= 1'b1;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
+ #1000;
+ RSTB <= 1'b1; // Release reset
+ #2000;
end
initial begin // Power-up sequence
