wrapper modified
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..6c8619b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -81,41 +81,27 @@
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
+wire rx;
+wire tx;
-user_proj_example mprj (
-`ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
-`endif
+// assign wbs_ack_o = wbs_stb_i & wbs_cyc_i;
+assign wbs_ack_o = wbs_stb_i;
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
+assign wbs_dat_o = {(32){1'b0}};
- // MGMT SoC Wishbone Slave
+assign la_data_out = {(128){1'b0}};
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
+assign rx = io_in[0];
+assign io_out = {{(`MPRJ_IO_PADS-2){1'b0}}, tx, 1'b0};
+assign io_oeb = {(`MPRJ_IO_PADS){wb_rst_i}};
- // Logic Analyzer
+assign user_irq = 3'b000;
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
+leaf_chip mprj (
+ .clk(wb_clk_i),
+ .reset(wb_rst_i),
+ .rx(rx),
+ .tx(tx)
);
endmodule // user_project_wrapper
