new top level module with no M4 routing in macros

gds/user_project_wrapper.gds

diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
index 0405a3e..903fa2a 100644
--- a/gds/user_project_wrapper.gds
+++ b/gds/user_project_wrapper.gds
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verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 90c040e..1df9bd5 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
Binary files differ