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foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-019 / refs/heads/main
commite93bffd33e2fa3b588a5af8282d422a67de53055[log] [tgz]
authorJeff DiCorpo <jeffdi@efabless.com>Sat Dec 17 13:28:33 2022 -0800
committerJeff DiCorpo <jeffdi@efabless.com>Sat Dec 17 13:28:33 2022 -0800
tree29918b246966aa4654b81c3ea1a0e79d2efa4111
parent043a703f9b943dee17a2e3c42d24da6f6da23b1d [diff]
final gds oasis
70 files changed
tree: 29918b246966aa4654b81c3ea1a0e79d2efa4111
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. mpw_precheck/
  9. openlane/
  10. signoff/
  11. spi/
  12. tapeout/
  13. verilog/
  14. .gitignore
  15. LICENSE
  16. Makefile
  17. README.md
README.md

Marmot RISC-V SoC

A Customizable RISC-V Microcomputer

A custom microcomputer design is useful when off-the-shelf general-purpose microcontrollers fail to meet the system needs. The rocket SoC generator automatically generate an SoC. It circumvents labor-intensive, error-prone, top-level SoC design.

SoC Customization Flow

The Rocket SoC Generator and Caravel SoC Template are reused to create a twin (not identical) RISC-V SoC consisting of one Rocket RISC-V and one Caravel RISC-V. The objectives here is to save hours on design verification and reduce power consumption rather than saving die area or chip cost.

graph TD
A(A SoC Wish List) -- SoC Description in Chisel--> B
B[The Rocket SoC Generator] --SoC RTL--> D[The OpenLane Flow]
C[Caravel SoC Harness] --Harness RTL--> D
B --FPGA RTL--> L
P[RISC-V IDE Tools]--Code and Executables-->H
L[_Yosys_+nextpnr] --Bitstream--> K[Lattice ECP5 Eval Board]
E(Caravel Firmware)  --Init, Monitoring, Debug--> C
D --Sky130 GDS II Layout Data--> F[eFabless MPW]
O[Xschema]--Circuit schematics-->J
F --MPW Chips--> H
F --MPW Chips--> I
I[Caravel EVB] --Breadboarding-->H{User system}
J[KiCad]--Gerber and BOM-->H

Implementing low power operations

The following shows a scheme to manage clock, reset, power and low power state.

sequenceDiagram
Note right of System: Powers<br/>Caravel<br/>Chip.
System -->> Harness: Reset
System -->> Harness: Reset
System -->> Caravel SoC: Reset
Harness -->> Caravel SoC: core clock
Harness -->> Caravel SoC: core reset
Caravel SoC->>Harness: Configuration of clk, DLL
Caravel SoC->>Harness: Configure pad data routing and GPIO
Harness-->>Rocket SoC: Set user_clock full speed
Caravel SoC->>Rocket SoC: Reset user logic
Note left of Rocket SoC: Rocket boots<br/>from ROM logic<br/>XIP SPI flash<br/>runs on DTIM.
Rocket SoC -->> Caravel SoC: Rocket is running OK
Note left of Caravel SoC: Acknoleging <br/>Rocket OK<br/>tuns off External<br/>CPG power<br/>via GPIO or I2C.
Caravel SoC->>System: Turn off External CPG Power
Note left of Rocket SoC: Rocket sends message<br/>"Bring Caravel<br/>to lowest power state"<br/>e.g. wishbone mailbox<br/>and interrupt.
Rocket SoC->>Caravel SoC: "Go low on power"
Note left of Caravel SoC: Management SoC sets<br/>Clocking and DLL<br/> to Caravel's<br/>lowest power state<br/>via System control.
Caravel SoC->> Harness: Caravel goes low power.
Note left of Rocket SoC: Rocket gets<br/>wake up signal<br/>from RTC.
Rocket SoC->>Caravel SoC: "Go full power"
Caravel SoC->>Harness: Configure Clock, DLL via System control
Caravel SoC->>Rocket SoC: "Went full power".

Features

UnitDescription
RISC-V CPURV32IMAC, M/S/U-mode (Rocket)
I-CacheInstruction cache: 16 KiB
(Up to 8 KiB can be configured as Instruction Tightly Integrated Memory (ITIM))
D-CacheData cache: 8 KiB
GPIOGeneral Purpose Input/Output Controller
QSPI0Quad Serial Peripheral Interface (QSPI) for (Q)SPI-Flash memory (XIP supported)
QSPI1Quad Serial Peripheral Interface (QSPI) for (Q)SPI-Peripherals (CS x2)
QSPI2Quad Serial Peripheral Interface (QSPI) for (Q)SPI-PSRAM (XIP supported)
UART0-4Universal Asynchronous Receiver/Transmitter (UART) x5
I2C0-1Inter-Integrated Circuit (I2C) Master Interface x2
PWM0-2Pulse Width Modulator (PWM) (4x 16-bit comparators/unit) x3
DebugDebug functions, JTAG I/F

Refer to Freedom E310-G002 Manual for detailed specification of each unit except QSPI2. For QSPI2, refer to docs/SPI_with_PSRAM_Interface.pdf .

Pinouts

mprj_io[#]Mgmt. SoCMarmot IOF0Marmot IOF1Marmot GPIO
0JTAG---
1SDOTDO--
2SDITDI--
3CSBTMS--
4SCKTCK--
5ser_rxUART0_rx--
6ser_txUART0_tx--
7irqQSPI1_csb[1]-GPIO[24]
8flash2_csbQSPI0_flash_csb--
9flash2_sckQSPI0_flash_sck--
10flash2_io[0]QSPI0_flash_io[0]--
11flash2_io[1]QSPI0_flash_io[1]--
12-QSPI0_flash_io[2]--
13-QSPI0_flash_io[3]--
14-QSPI1_csb[0]-GPIO[0]
15-QSPI1_sck-GPIO[1]
16-QSPI1_io[0]-GPIO[2]
17-QSPI1_io[1]-GPIO[3]
18-QSPI1_io[2]-GPIO[4]
19-QSPI1_io[3]-GPIO[5]
20-QSPI2_csb--
21-QSPI2_sck--
22-QSPI2_io[0]--
23-QSPI2_io[1]--
24-QSPI2_io[2]--
25-QSPI2_io[3]--
26-I2C0_sdaPWM0_0GPIO[12]
27-I2C0_sclPWM0_1GPIO[13]
28-I2C1_sdaPWM0_2GPIO[14]
29-I2C1_sclPWM0_3GPIO[15]
30-UART1_rxPWM1_0GPIO[16]
31-UART1_txPWM1_1GPIO[17]
32-UART2_rxPWM1_2GPIO[18]
33-UART2_txPWM1_3GPIO[19]
34-UART3_rxPWM2_0GPIO[20]
35-UART3_txPWM2_1GPIO[21]
36-UART4_rxPWM2_2GPIO[22]
37-UART4_txPWM2_3GPIO[23]

Address Map

BaseTopAttributeUnitDescription
0x0000_00000x0000_0FFFRWX ADebugDebug Address Space
0x0000_10000x0000_2FFF-Reserved-
0x0000_30000x0000_3FFFRWX AError DeviceError Address Space
0x0000_40000x0000_FFFF-Reserved-
0x0001_00000x0001_1FFFR XCBoot ROMBoot ROM (8 KiB)
0x0001_20000x0002_1FFF-Reserved-
0x0200_00000x0200_FFFFRW ACLINTCore-Local Interruptor
0x0201_00000x07FF_FFFF-Reserved-
0x0800_00000x0800_1FFFRWX AITIMInstruction Tightly Integrated Memory (up to 8KiB)
0x0800_20000x0BFF_FFFF-Reserved-
0x0C00_00000x0FFF_FFFFRW APLICPlatform-Level Interrupt Controller
0x1000_00000x1000_0FFFRW AAONAlways-On Domain (WDT, RTC, PMU, etc.)
0x1000_10000x1001_1FFF-Reserved-
0x1001_20000x1001_2FFFRW AGPlOGeneral Purpose Input/Output Controller
0x1001_30000x1001_3FFFRW AUART0Universal Asynchronous Receiver/ Transmitter #0
0x1001_40000x1001_4FFFRW AQSPI0Quad Serial Peripheral Interface #0 for (Q)SPI-Flash memory (XIP supported)
0x1001_50000x1001_5FFFRW APWM0Pulse Width Modulator #0
0x1001_60000x1001_6FFFRW AI2C0Inter-Integrated Circuit Master Interface #0
0x1001_70000x1002_2FFF-Reserved-
0x1002_30000x1002_3FFFRW AUART1Universal Asynchronous Receiver/ Transmitter #1
0x1002_40000x1002_4FFFRW AQSPI1Quad Serial Peripheral Interface #1 for (Q)SPI-Peripherals
0x1002_50000x1002_5FFFRW APWM1Pulse Width Modulator #1
0x1002_60000x1002_6FFFRW AI2C1Inter-Integrated Circuit Master Interface #1
0x1002_70000x1003_2FFF-Reserved-
0x1003_30000x1003_3FFFRW AUART2Universal Asynchronous Receiver/ Transmitter #2
0x1003_40000x1003_4FFFRW AQSPI2Quad Serial Peripheral Interface #2 for (Q)SPI-PSRAM (XIP supported)
0x1003_50000x1FFF_FFFFRW APWM2Pulse Width Modulator #2
0x1004_30000x1005_2FFFRW AUART3Universal Asynchronous Receiver/ Transmitter #3
0x1004_40000x1005_2FFF-Reserved-
0x1005_30000x1005_3FFFRW AUART4Universal Asynchronous Receiver/ Transmitter #4
0x1005_40000x1FFF_FFFF-Reserved-
0x2000_00000x3FFF_FFFFR XC(Q)SPI-FlashOff-Chip (Q)SPI-Flash Memory (up to 512 MiB)
0x4000_00000x5FFF_FFFFRWXC(Q)SPI-PSRAMOff-Chip (Q)SPI-PSRAM (up to 512 MiB)
0x6000_00000xFFFF_FFFF-Reserved-

Reference

Marmot RISC-V ASIC for Motor Control (Efabless MPW-7 project)

Freedom E310-G002 Manual

Chipyard Framework

The Rocket Chip Generator

Efabless Caravel Architecture

Acknowledgements

This work is based on results obtained from project, JPNP16007, commissioned by The New Energy and Industrial Technology Development Organization (NEDO).