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foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-019 / ae0b8fd10c5175490f271c65dcf8698550b2094d
commitae0b8fd10c5175490f271c65dcf8698550b2094d[log] [tgz]
authorKesami Hagiwara <kesami.hagiwara@swhwc.com>Mon Sep 05 12:50:38 2022 +0900
committerKesami Hagiwara <kesami.hagiwara@swhwc.com>Mon Sep 05 12:50:38 2022 +0900
tree5b586fd628a194cc93fc5ee17ed94ecf0c7023c9
parent7e136e683ddd666919aa95cf5500a7821148e816 [diff]
Add verilog/gl/init_ff.v for GL simulation
1 file changed
tree: 5b586fd628a194cc93fc5ee17ed94ecf0c7023c9
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
  16. run_sim.csh
README.md

Marmot RISC-V SoC

A Customizable RISC-V Microcomputer

A custom microcomputer design is useful when off-the-shelf general-purpose microcontrollers fail to meet the system needs. The rocket SoC generator automatically generate an SoC. It circumvents labor-intensive, error-prone, top-level SoC design.

SoC Customization Flow

The Rocket SoC Generator and Caravel SoC Template are reused to create a twin (not identical) RISC-V SoC consisting of one Rocket RISC-V and one Caravel RISC-V. The objectives here is to save hours on design verification and reduce power consumption rather than saving die area or chip cost.

graph TD
A(A SoC Wish List) -- SoC Description in Chisel--> B
B[The Rocket SoC Generator] --SoC RTL--> D[The OpenLane Flow]
C[Caravel SoC Harness] --Harness RTL--> D
B --FPGA RTL--> L
P[RISC-V IDE Tools]--Code and Executables-->H
L[_Yosys_+nextpnr] --Bitstream--> K[Lattice ECP5 Eval Board]
E(Caravel Firmware)  --Init, Monitoring, Debug--> C
D --Sky130 GDS II Layout Data--> F[eFabless MPW]
O[Xschema]--Circuit schematics-->J
F --MPW Chips--> H
F --MPW Chips--> I
I[Caravel EVB] --Breadboarding-->H{User system}
J[KiCad]--Gerber and BOM-->H

Implementing low power operations

The following shows a scheme to manage clock, reset, power and low power state.

sequenceDiagram
Note right of System: Powers<br/>Caravel<br/>Chip.
System -->> Harness: Reset
System -->> Harness: Reset
System -->> Caravel SoC: Reset
Harness -->> Caravel SoC: core clock
Harness -->> Caravel SoC: core reset
Caravel SoC->>Harness: Configuration of clk, DLL
Caravel SoC->>Harness: Configure pad data routing and GPIO
Harness-->>Rocket SoC: Set user_clock full speed
Caravel SoC->>Rocket SoC: Reset user logic
Note left of Rocket SoC: Rocket boots<br/>from ROM logic<br/>XIP SPI flash<br/>runs on DTIM.
Rocket SoC -->> Caravel SoC: Rocket is running OK
Note left of Caravel SoC: Acknoleging <br/>Rocket OK<br/>tuns off External<br/>CPG power<br/>via GPIO or I2C.
Caravel SoC->>System: Turn off External CPG Power
Note left of Rocket SoC: Rocket sends message<br/>"Bring Caravel<br/>to lowest power state"<br/>e.g. wishbone mailbox<br/>and interrupt.
Rocket SoC->>Caravel SoC: "Go low on power"
Note left of Caravel SoC: Management SoC sets<br/>Clocking and DLL<br/> to Caravel's<br/>lowest power state<br/>via System control.
Caravel SoC->> Harness: Caravel goes low power.
Note left of Rocket SoC: Rocket gets<br/>wake up signal<br/>from RTC.
Rocket SoC->>Caravel SoC: "Go full power"
Caravel SoC->>Harness: Configure Clock, DLL via System control
Caravel SoC->>Rocket SoC: "Went full power".

Peripheral Overviews

PeripheralUnitsPins / unitTotal pinsMuxed with GPIONote
Clock110-From mgmt.SoC
Reset110-From mgmt.SoC
QSPI 0 (XIP)166NoFor Flash
QSPI 1 (no XIP)177YesFor ADC, etc. (CS x2)
QSPI 2 (XIP)166NoFor PSRAM
UART 0122No
UART 1-4428Yes
I2C 0-1224Yes
JTAG144No
Total37Max. 38

Pinouts

Caravel mprj_io[#]Caravel Mgmt. SoCMarmot IOF0Marmot GPIO
0JTAG--
1SDOTDO-
2SDITDI-
3CSBTMS-
4SCKTCK-
5ser_rxuart0_rx-
6ser_txuart0_tx-
7irqspi1_csb[1]gpio[24]
8flash2_csbspi0_flash_csb-
9flash2_sckspi0_flash_sck-
10flash2_io[0]spi0_flash_io[0]-
11flash2_io[1]spi0_flash_io[1]-
12-spi0_flash_io[2]-
13-spi0_flash_io[3]-
14-spi1_csb[0]gpio[0]
15-spi1_sckgpio[1]
16-spi1_io[0]gpio[2]
17-spi1_io[1]gpio[3]
18-spi1_io[2]gpio[4]
19-spi1_io[3]gpio[5]
20-spi2_csb-
21-spi2_sck-
22-spi2_io[0]-
23-spi2_io[1]-
24-spi2_io[2]-
25-spi2_io[3]-
26-i2c0_sdagpio[12]
27-i2c0_sclgpio[13]
28-i2c1_sdagpio[14]
29-i2c1_sclgpio[15]
30-uart1_rxgpio[16]
31-uart1_txgpio[17]
32-uart2_rxgpio[18]
33-uart2_txgpio[19]
34-uart3_rxgpio[20]
35-uart3_txgpio[21]
36-uart4_rxgpio[22]
37-uart4_txgpio[23]

Address Map

BaseTopAttributeDescriptionNotes
0x0000_00000x0000_0FFFRWX ADebugDebug Address Space
0x0000_10000x0000_2FFFReservedOn-Chip Non Volatile Memory
0x0000_30000x0000_3FFFRWX AError DeviceOn-Chip Non Volatile Memory
0x0000_40000x0000_FFFFReservedOn-Chip Non Volatile Memory
0x0001_00000x0001_1FFFR XCMask ROM (8 KiB)On-Chip Non Volatile Memory
0x0001_20000x0002_1FFFReservedOn-Chip Non Volatile Memory
0x0200_00000x0200_FFFFRW ACLINTOn-Chip Peripherals
0x0201_00000x07FF_FFFFReservedOn-Chip Peripherals
0x0800_00000x0800_1FFFRWX AITIM (8 KiB)On-Chip Volatile Memory
0x0800_20000x0BFF_FFFFReservedOn-Chip Volatile Memory
0x0C00_00000x0FFF_FFFFRW APLICOn-Chip Peripherals
0x1000_00000x1000_0FFFRW AAONOn-Chip Peripherals
0x1000_10000x1001_1FFFReservedOn-Chip Peripherals
0x1001_20000x1001_2FFFRW AGPlOOn-Chip Peripherals
0x1001_30000x1001_3FFFRW AUART 0On-Chip Peripherals
0x1001_40000x1001_4FFFRW AQSPI 0On-Chip Peripherals
0x1001_50000x1001_5FFFReservedOn-Chip Peripherals
0x1001_60000x1001_6FFFRW AI2C 0On-Chip Peripherals
0x1001_70000x1002_2FFFReservedOn-Chip Peripherals
0x1002_30000x1002_3FFFRW AUART 1On-Chip Peripherals
0x1002_40000x1002_4FFFRW AQSPI 1On-Chip Peripherals
0x1002_50000x1002_5FFFReservedOn-Chip Peripherals
0x1002_60000x1002_6FFFRW AI2C 1On-Chip Peripherals
0x1002_70000x1003_2FFFReservedOn-Chip Peripherals
0x1003_30000x1003_3FFFRW AUART 2On-Chip Peripherals
0x1003_40000x1003_4FFFRW AQSPI 2On-Chip Peripherals
0x1003_50000x1FFF_FFFFReservedOn-Chip Peripherals
0x1004_30000x1005_2FFFRW AUART3On-Chip Peripherals
0x1004_40000x1005_2FFFReservedOn-Chip Peripherals
0x1005_30000x1005_3FFFRW AUART 4On-Chip Peripherals
0x1005_40000x1FFF_FFFFReservedOn-Chip Peripherals
0x2000_00000x3FFF_FFFFR XCQSPI 0 Flash (512 MiB)Off-Chip Non-Volatile Memory
0x4000_00000x5FFF_FFFFRWX AQSPI 2 PSRAM (512 MiB)Off-Chip Volatile Memory
0x6000_00000x7FFF_FFFFReservedOff-Chip Memory
0x8000_00000x8000_3FFFRWX AReserved DTIM (16 KiB)On-Chip Volatile Memory
0x8000_40000xFFFF_FFFFReservedOn-Chip Volatile Memory

Reference

Freedom E300 Arty FPGA Dev Kit https://github.com/sifive/freedom#freedom-e300-arty-fpga-dev-kit

Freedom E310-G002 Manual https://sifive.cdn.prismic.io/sifive/b56b304f-cd2d-421b-9c14-6b35c33f172e_fe310-g002-manual-v1p4.pdf

Krste Asanović, Rimas Avižienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, The Rocket Chip Generator, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016

eFabless Caravel Architecture https://caravel-harness.readthedocs.io/en/latest/getting-started.html

Acknowledgements

This work is based on results obtained from project, JPNP16007, commissioned by The New Energy and Industrial Technology Development Organization (NEDO).