marmot_no_sram: Flow failed in Global Routing stage
diff --git a/openlane/marmot_no_sram/base.sdc b/openlane/marmot_no_sram/base.sdc
index f208423..4842b07 100644
--- a/openlane/marmot_no_sram/base.sdc
+++ b/openlane/marmot_no_sram/base.sdc
@@ -23,9 +23,15 @@
-source [get_ports wb_clk_i] -master_clock [get_clocks wb_clk_i] -divide_by 1 \
-comment {I-Cache Data RAM clk} [get_ports data_arrays_0_0_ext_ram_clk[*]]
+# For RTL
+#create_generated_clock -name slow_clock -add \
+# -source [get_ports wb_clk_i] -master_clock [get_clocks wb_clk_i] -divide_by 4 \
+# -comment {AON clk} [get_nets \MarmotCaravelChip.clockToggleReg ]
+
+# For gate
create_generated_clock -name slow_clock -add \
-source [get_ports wb_clk_i] -master_clock [get_clocks wb_clk_i] -divide_by 4 \
- -comment {AON clk} [get_nets \MarmotCaravelChip.clockToggleReg ]
+ -comment {AON clk} [get_nets \MarmotCaravelChip.dut_sys_aon_1_io_rtc ]
create_clock [get_ports $TCK_port] -name jtag_TCK -period 100.0
@@ -86,45 +92,45 @@
set_input_delay $input_delay_value -clock [get_clocks wb_clk_i] $all_inputs_wo_clk
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [all_outputs]
-# D-Cache Tag RAM port
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_csb0]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_web0]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_wmask0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_addr0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_din0[*]]
-set_input_delay $input_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_dout0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_csb1]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_addr1[*]]
-
-# D-Cache Data RAM port
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_csb0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_web0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_wmask0*[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_addr0*[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_din0*[*]]
-set_input_delay $input_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_dout0*[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_csb1[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_addr1*[*]]
-
-# I-Cache Tag RAM port
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_csb0]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_web0]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_wmask0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_addr0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_din0[*]]
-set_input_delay $input_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_dout0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_csb1]
-set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_addr1[*]]
-
-# I-Cache Data RAM port
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_csb0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_web0[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_wmask0*[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_addr0*[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_din0*[*]]
-set_input_delay $input_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_dout0*[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_csb1[*]]
-set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_addr1*[*]]
+## D-Cache Tag RAM port
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_csb0]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_web0]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_wmask0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_addr0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_din0[*]]
+#set_input_delay $input_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_dout0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_csb1]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_ext_ram_clk] [get_ports tag_array_ext_ram_addr1[*]]
+#
+## D-Cache Data RAM port
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_csb0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_web0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_wmask0*[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_addr0*[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_din0*[*]]
+#set_input_delay $input_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_dout0*[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_csb1[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_ext_ram_clk] [get_ports data_arrays_0_ext_ram_addr1*[*]]
+#
+## I-Cache Tag RAM port
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_csb0]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_web0]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_wmask0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_addr0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_din0[*]]
+#set_input_delay $input_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_dout0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_csb1]
+#set_output_delay $output_delay_value_ram -clock [get_clocks tag_array_0_ext_ram_clk] [get_ports tag_array_0_ext_ram_addr1[*]]
+#
+## I-Cache Data RAM port
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_csb0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_web0[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_wmask0*[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_addr0*[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_din0*[*]]
+#set_input_delay $input_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_dout0*[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_csb1[*]]
+#set_output_delay $output_delay_value_ram -clock [get_clocks data_arrays_0_0_ext_ram_clk] [get_ports data_arrays_0_0_ext_ram_addr1*[*]]
# JTAG port
set_input_delay $input_delay_value -clock [get_clocks jtag_TCK] [get_ports $TMS_port]
diff --git a/openlane/marmot_no_sram/config.tcl b/openlane/marmot_no_sram/config.tcl
index 69b96a6..d0a0888 100644
--- a/openlane/marmot_no_sram/config.tcl
+++ b/openlane/marmot_no_sram/config.tcl
@@ -32,15 +32,16 @@
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 1059 2096"
+set ::env(CELL_PAD) 1
#set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(DIODE_INSERTION_STRATEGY) 5
+set ::env(DIODE_INSERTION_STRATEGY) 3
set ::env(MAGIC_WRITE_FULL_LEF) 0
set ::env(SYNTH_FLAT_TOP) 1
#set ::env(SYNTH_NO_FLAT) 1
set ::env(CLOCK_TREE_SYNTH) 1
-set ::env(DESIGN_IS_CORE) 1
+set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PDN_CORE_RING) 0
set ::env(STA_REPORT_POWER) 0
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
@@ -48,7 +49,7 @@
set ::env(GND_NETS) {vssd1}
set ::env(VDD_PIN) "vccd1"
set ::env(GND_PIN) "vssd1"
-set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(PL_TARGET_DENSITY) 0.39
set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_* sky130_fd_sc_hd__decap_*}
#set ::env(FILL_CELL) {sky130_fd_sc_hd__fill_}
@@ -78,12 +79,12 @@
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../../verilog/rtl/marmot_no_sram]
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- [glob $script_dir/../../../verilog/rtl/marmot_no_sram/*.v]"
+ [glob $script_dir/../../../verilog/rtl/marmot_no_sram_gl/*.v]"
## SDC
set ::env(IO_PCT) 0.2
set ::env(IO_PCT_RAM) 0.3
-set ::env(BASE_SDC_FILE) $script_dir/../../../openlane/marmot_no_sram/base.sdc
+#set ::env(BASE_SDC_FILE) $script_dir/../../../openlane/marmot_no_sram/base.sdc
## Internal Macros
