commit a6a46e04ba7805a63541aee4aed2dad381c915f2
author mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:56:46 2022 +0300
committer mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:56:46 2022 +0300
tree 3790f8e824ef87e54c5e05278b4e69a5b181bb5d
parent 409a2671cbf48376815c8e7339f027307eab17b3

Update README.md

README.md

diff --git a/README.md b/README.md
index 40b31c5..dba87d5 100644
--- a/README.md
+++ b/README.md
@@ -28,4 +28,4 @@
 Original SystemVerilog implementation of Yonga-MCU is verified through modelsim environment provided with pulpino repo. We converted SV files to Verilog through sv2v and reverified the MCU.
 
 ## GDSII Images
-![AXI_NODE_INTF_WRAP](https://github.com/mbaykenar/mpw7_yonga_soc/tree/main/images/axi_node_intf_wrap.PNG?raw=true)
\ No newline at end of file
+![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/tree/main/images/axi_node_intf_wrap.PNG?raw=true)
\ No newline at end of file