Google Git
Sign in
foss-eda-tools/third_party/shuttle/sky130/mpw-007/slot-017/a2d2f4ad089bba676604549807647f61b9e8b270/./verilog/rtl/rtl
tree: 5e61c01ef72ba7a37c96d86d2e03d0f79aef0a68
  1. components/
  2. includes/
  3. apb_mock_uart.v
  4. axi2apb_wrap.v
  5. axi_mem_if_SP_wrap.v
  6. axi_node_intf_wrap.v
  7. axi_slice_wrap.v
  8. axi_spi_slave_wrap.v
  9. boot_code.v
  10. boot_rom_wrap.v
  11. centik_top.v
  12. clk_rst_gen.v
  13. core2axi_wrap.v
  14. core_region.v
  15. dp_ram_wrap.v
  16. instr_ram_wrap.v
  17. mba_core_region.v
  18. mba_instr_ram_wrap.v
  19. mba_sp_ram_wrap.v
  20. periph_bus_wrap.v
  21. peripherals.v
  22. pulpino_top.v
  23. pulpino_top_wrapper.v
  24. ram_mux.v
  25. sp_ram_wrap.v