commit 991806812a9677a8ead390aeb0066eeaa5fbb772
author mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:59:46 2022 +0300
committer mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:59:46 2022 +0300
tree 59b61a80e41cad9f207448f00647dddd777199b4
parent a2d2f4ad089bba676604549807647f61b9e8b270

Update README.md

README.md

diff --git a/README.md b/README.md
index 36aa0be..31aef5d 100644
--- a/README.md
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@@ -28,4 +28,10 @@
 Original SystemVerilog implementation of Yonga-MCU is verified through modelsim environment provided with pulpino repo. We converted SV files to Verilog through sv2v and reverified the MCU.
 
 ## GDSII Images
-![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/axi_node_intf_wrap.PNG "axi_node_intf_wrap")
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+![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/axi_node_intf_wrap.PNG "axi_node_intf_wrap")
+
+![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/mba_core_region.PNG "mba_core_region")
+
+![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/peripherals.PNG "peripherals")
+
+![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/user_project_wrapper.PNG "user_project_wrapper")
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