commit 4fc909fbc21c3aa972e1e5809c831b2444a96b0c
author mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:57:35 2022 +0300
committer mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:57:35 2022 +0300
tree c1005d30eba95b8073f0aed39f91245f1008c9fb
parent a6a46e04ba7805a63541aee4aed2dad381c915f2

Update README.md

README.md

diff --git a/README.md b/README.md
index dba87d5..2c32050 100644
--- a/README.md
+++ b/README.md
@@ -28,4 +28,4 @@
 Original SystemVerilog implementation of Yonga-MCU is verified through modelsim environment provided with pulpino repo. We converted SV files to Verilog through sv2v and reverified the MCU.
 
 ## GDSII Images
-![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/tree/main/images/axi_node_intf_wrap.PNG?raw=true)
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+![alt text](https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/images/axi_node_intf_wrap.PNG)
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