commit 409a2671cbf48376815c8e7339f027307eab17b3
author mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:55:37 2022 +0300
committer mbaykenar <aykenar.burak@gmail.com> Sun Sep 11 00:55:37 2022 +0300
tree 5b6333774370da79b0c5bf96e67286d6c9b36aeb
parent 75d18009b72cc953254a79b0a14bf5c8a158dccc

Update README.md

README.md

diff --git a/README.md b/README.md
index 68f6048..40b31c5 100644
--- a/README.md
+++ b/README.md
@@ -28,3 +28,4 @@
 Original SystemVerilog implementation of Yonga-MCU is verified through modelsim environment provided with pulpino repo. We converted SV files to Verilog through sv2v and reverified the MCU.
 
 ## GDSII Images
+![AXI_NODE_INTF_WRAP](https://github.com/mbaykenar/mpw7_yonga_soc/tree/main/images/axi_node_intf_wrap.PNG?raw=true)
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