Fixed Makefile and hardened sha1_top but get 5 Magic DRC issues
diff --git a/Makefile b/Makefile
index 98538f1..ab3e0f2 100644
--- a/Makefile
+++ b/Makefile
@@ -192,9 +192,9 @@
-e PDK_ROOT=$(PDK_ROOT) \
-e PDKPATH=$(PDKPATH) \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
- efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
+ efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"
-
+# TODO? --pdk_root $(PDK_ROOT) # instead of --pdk_path $(PDK_ROOT)/$(PDK)
.PHONY: clean
clean:
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
index 58d01d4..439b2a3 100644
--- a/gds/user_proj_example.gds
+++ b/gds/user_proj_example.gds
Binary files differ
diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag
index 1053699..a3acffe 100644
--- a/mag/user_proj_example.mag
+++ b/mag/user_proj_example.mag
@@ -1,7 +1,7 @@
magic
tech sky130B
magscale 1 2
-timestamp 1661547474
+timestamp 1665432302
<< viali >>
rect 4077 117249 4111 117283
rect 5089 117249 5123 117283
diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag
index f887a47..02a2299 100644
--- a/maglef/user_proj_example.mag
+++ b/maglef/user_proj_example.mag
@@ -1,7 +1,7 @@
magic
tech sky130B
magscale 1 2
-timestamp 1661547502
+timestamp 1665432310
<< nwell >>
rect 1066 116677 178886 117243
rect 1066 115589 178886 116155
@@ -2588,7 +2588,7 @@
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 7763560
-string GDS_FILE /Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example/runs/22_08_26_15_53/results/signoff/user_proj_example.magic.gds
+string GDS_FILE /home/somasz/Documents/github/bitcoin_asic/openlane/user_proj_example/runs/22_10_10_15_03/results/signoff/user_proj_example.magic.gds
string GDS_START 391678
<< end >>
diff --git a/signoff/user_proj_example/metrics.csv b/signoff/user_proj_example/metrics.csv
index f5e6155..59ddea6 100644
--- a/signoff/user_proj_example/metrics.csv
+++ b/signoff/user_proj_example/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-/Users/somasz/Documents/GitHub/mpw_6c/caravel_design/caravel_bitcoin_asic/openlane/user_proj_example,user_proj_example,22_08_26_15_53,flow completed,0h22m21s0ms,0h3m19s0ms,-2.0,0.54,-1,0.92,1732.05,-1,0,0,0,0,0,0,0,3,0,-1,-1,74321,5952,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,68512977.0,0.0,5.54,4.39,0.35,0.0,-1,342,1149,29,836,0,0,0,380,37,0,14,31,46,17,15,129,174,67,13,424,7276,0,7700,514032.2304,0.000437,0.000323,5.2e-06,0.000547,0.00041,3.26e-08,0.000626,0.000481,3.55e-08,5.45,11.0,90.9090909090909,10,AREA 0,5,50,1,153.6,153.18,0.05,0.3,sky130_fd_sc_hd,4,4
+/home/somasz/Documents/github/bitcoin_asic/openlane/user_proj_example,user_proj_example,22_10_10_15_03,flow completed,0h2m49s0ms,0h0m55s0ms,-2.0,0.54,-1,0.92,1758.12,-1,0,0,0,0,0,0,0,3,0,-1,-1,74321,5952,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,68512977.0,0.0,5.54,4.39,0.35,0.0,-1,342,1149,29,836,0,0,0,380,37,0,14,31,46,17,15,129,174,67,13,424,7276,0,7700,514032.2304,0.000437,0.000323,5.2e-06,0.000547,0.00041,3.26e-08,0.000626,0.000481,3.55e-08,5.45,11.0,90.9090909090909,10,AREA 0,5,50,1,153.6,153.18,0.05,0.3,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/sha1_top_test1/RTL-sha1_top_test1.vcd b/verilog/dv/sha1_top_test1/RTL-sha1_top_test1.vcd
new file mode 100644
index 0000000..92e60f9
--- /dev/null
+++ b/verilog/dv/sha1_top_test1/RTL-sha1_top_test1.vcd
Binary files differ
diff --git a/verilog/dv/sha1_top_test2/RTL-sha1_top_test2.vcd b/verilog/dv/sha1_top_test2/RTL-sha1_top_test2.vcd
new file mode 100644
index 0000000..291f213
--- /dev/null
+++ b/verilog/dv/sha1_top_test2/RTL-sha1_top_test2.vcd
Binary files differ
