Reconfigure parameters like in original submission
diff --git a/openlane/trainable_nn/config.json b/openlane/trainable_nn/config.json
index 45fee50..38cf537 100644
--- a/openlane/trainable_nn/config.json
+++ b/openlane/trainable_nn/config.json
@@ -12,11 +12,11 @@
"dir::../../verilog/rtl/interface.v",
"dir::../../verilog/rtl/trainable_nn.v"
],
- "CLOCK_PERIOD": 100,
+ "CLOCK_PERIOD": 200,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "i_nn.clk",
"FP_SIZING": "absolute",
- "DIE_AREA": "0 0 600 800",
+ "DIE_AREA": "0 0 1500 2000",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
"PL_BASIC_PLACEMENT": 0,
"PL_TARGET_DENSITY": 0.45,
diff --git a/verilog/rtl/config.v b/verilog/rtl/config.v
index e2c80d1..9b2fda2 100644
--- a/verilog/rtl/config.v
+++ b/verilog/rtl/config.v
@@ -20,10 +20,10 @@
`define POST_MUL_FRAC_WIDTH 16
// number of neurons in input, hidden 1, hidden 2 & output layers
-`define INPUT_SIZE 1
-`define HIDDEN1_SIZE 1
-`define HIDDEN2_SIZE 1
-`define OUTPUT_SIZE 1
+`define INPUT_SIZE 2
+`define HIDDEN1_SIZE 2
+`define HIDDEN2_SIZE 2
+`define OUTPUT_SIZE 2
// bits required to describe the sizes above
`define INDEX_WIDTH 10
