| commit | 5fb4a7fecbb2c2afbce1732c064901a29748c5df | [log] [tgz] |
|---|---|---|
| author | Simon Waid <simon.waid@oeaw.ac.at> | Thu Jun 09 08:49:42 2022 +0200 |
| committer | Simon Waid <simon.waid@oeaw.ac.at> | Thu Jun 09 08:49:42 2022 +0200 |
| tree | 8bc719c53e9639d76c1f20bf5530c42dc8ddb109 | |
| parent | 358781f5054994baba8f59bf87c0521e0651efb7 [diff] |
main layout LVS clean
This is a simple analog frontend for detecting single particles such as cosmic rays, alpha or beta particles. The user can attach a detector, such as a silicon PIN diode to the input. When a particle hits the detector, it will create a current pulse. The current pulse is amplified by the transimpedance amplifier and detected by the comparator. The output of the comparator is made available as an low voltage differential signalling (LVDS) signal at the output and can be further processed by an FPGA, e.g. to count the number of inpinging particles per second.
The ASIC contains the following blocks:
The overall bandwidth is intended to be approx. 1GHz. The design aims to enable the detection of pulses with a peak current of 5µA and length of 0.5 ns.
The blocks are inteded to be re-used as IP blocks in future projects. Therefore for each block both schematic as well as a magic layout are available.
License: 
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The Biasing circuit and TIA have been previously published and were submitted to the MPW-5. They are documented here:
The dark current of the detector may lead to saturation of the input TIA. To prevent this, an active dark current compensation circuit was implemente. The circuit is based on [1].
Schematic: Layout:
The functional blocks of the comparator are shown in the following:
The comparator is composed of saturation tollerant difference amplifiers stages. Each stage has a typical amplification of 10dB. By cascading 6 stages an overall amplification of approx. 60dB is attained. The threshold of the comparator is set by injecting an offset current into the 3rd difference amplifier stage. Prior to the 3rd aplifier stage AC coupling eliminates the offset introduced by the previous amplifer stages. After the difference amplifer stages, a schmidt trigger is used to convert the differential analog signal to a single ended digital signal. The schmidt trigger contains a difference amplifer with a positive feedback making it bi-stable. The output of this difference amplifer is converted to a digitial signal via current mirrors and 3 cascaded inverter stages.
From a user perspective, the threshold is set via an input current on one of the two input pins. Supplying the current can be attained e.g. via a resistor or a current DAC.
The following shows the reaction of the comparator to a voltage pulse of 1.5mV.
Schematic: Layout:
Schematic: Layout:
[1]