commit ef49b899fcbca822167ebc3bfabf9ab1791f4ad0
author Staf Verhaegen <staf@fibraservi.eu> Tue Mar 22 09:16:27 2022 +0100
committer Staf Verhaegen <staf@fibraservi.eu> Tue Mar 22 09:16:27 2022 +0100
tree a90e0e648cd642a5274bc9b2930c4809f2b9871d
parent 590196545153e363e62b5d860078fa4c398ab8ad

Another try to fix XOR errors

doitcode/sram.py

diff --git a/doitcode/sram.py b/doitcode/sram.py
index 2e322fe..bbb861c 100644
--- a/doitcode/sram.py
+++ b/doitcode/sram.py
@@ -203,9 +203,9 @@
             left=left, bottom=(top + 10.0), right=toppin_bb.right, top=(top+20.0),
         )
         layouter.add_wire(net=net, wire=m3, shape=shape)
-        shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
+        shape = _geo.Rect.from_rect(rect=toppin_bb, top=_frm.boundary.top, bottom=(top + 10.0))
         layouter.add_wire(net=net, wire=m3, shape=shape)
-        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+        # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # vdd
         spec = io_sig2spec["vdd"]
@@ -237,9 +237,9 @@
             left=toppin_bb.left, bottom=(top + 10.0), right=right, top=(top+20.0),
         )
         layouter.add_wire(net=net, wire=m3, shape=shape)
-        shape = _geo.Rect.from_rect(rect=toppin_bb, bottom=(top + 10.0))
+        shape = _geo.Rect.from_rect(rect=toppin_bb, top=_frm.boundary.top, bottom=(top + 10.0))
         layouter.add_wire(net=net, wire=m3, shape=shape)
-        layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+        # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # a
         col = 0
@@ -281,9 +281,11 @@
 
             shape = _geo.Rect.from_rect(rect=via_m2bb, bottom=via2_m2bb.bottom)
             layouter.add_wire(net=net, wire=m2, shape=shape)
-            shape = _geo.Rect.from_rect(rect=toppin_bb, right=via2_m3bb.right)
+            shape = _geo.Rect.from_rect(
+                rect=toppin_bb, left=_frm.boundary.left, right=via2_m3bb.right,
+            )
             layouter.add_wire(net=net, wire=m3, shape=shape)
-            layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+            # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # The rest of the pin on m2
         for sram_signame in (
@@ -313,11 +315,15 @@
             shape = _geo.Rect.from_rect(rect=sram_m2pinbb, bottom=via2_m2bb.bottom)
             layouter.add_wire(net=net, wire=m2, shape=shape)
             if toppin_bb.center.x > sram_m2pinbb.center.x:
-                shape = _geo.Rect.from_rect(rect=toppin_bb, left=via2_m3bb.left)
+                shape = _geo.Rect.from_rect(
+                    rect=toppin_bb, left=via2_m3bb.left, right=_frm.boundary.right,
+                )
             else:
-                shape = _geo.Rect.from_rect(rect=toppin_bb, right=via2_m3bb.right)
+                shape = _geo.Rect.from_rect(
+                    rect=toppin_bb, left=_frm.boundary.left, right=via2_m3bb.right,
+                )
             layouter.add_wire(net=net, wire=m3, shape=shape)
-            layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
+            # layouter.add_wire(net=net, wire=m3, pin=m3pin, shape=toppin_bb)
 
         # boundary
         layout.boundary = _frm.boundary

gds/user_analog_project_wrapper.gds.gz

diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index 39be064..93d8ebe 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ