Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-007
/
slot-010
/
be44abbabde98b60eb9947a806fd120ed5390484
commit
be44abbabde98b60eb9947a806fd120ed5390484
[
log
]
[
tgz
]
author
Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
Fri Sep 30 07:41:52 2022 -0700
committer
GitHub <noreply@github.com>
Fri Sep 30 07:41:52 2022 -0700
tree
0c37842242e4a153d65a3c859e8c26a700161642
parent
4e083b32de475d6403782bd8043b5b02247f9572
[
diff
]
Update user_defines.v
verilog/rtl/user_defines.v
[
diff
]
1 file changed
tree: 0c37842242e4a153d65a3c859e8c26a700161642
.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md
README.md
Caravel Analog User
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.