| commit | bfd401a927a57d5ac3b629d20b369ee7b047ca34 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Wed Oct 05 14:37:32 2022 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Wed Oct 05 14:37:32 2022 -0400 |
| tree | c939459732094d9ae49eacc10335d62be1b5afa3 | |
| parent | eedfbaed33eb69eb7f9d101e70bbfcff69e42b96 [diff] |
Corrected the pull-up and pull-down definitions in the user_defines verilog RTL, which were swapped.
| :exclamation: Important Note |
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| :warning: | Use this sample project for analog user projects. |
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Refer to README for this sample project documentation.