tree: 0cb9348abbff6defd2215e396d0b7b7f7029ce15 [path history] [tgz]
  1. .github/
  2. docs/
  3. doitcode/
  4. gds/
  5. netgen/
  6. verilog/
  7. xschem/
  8. .gitignore
  11. Makefile
  13. user_analog_project_wrapper.png

PDKMaster based memory compiler test chip



The top level is fully generated from python code in the doitcode subdirectory. pydoit is used to generate the desig with the provided file in the top directory. The code depends on some external modules that are assumed to be installed:

  • PDKMaster: python framework (under heavy development) to ease generation of circuits and corresponding DRC compliant layout. This based on a description of a technology with python souce code to allow easy porting to different technologies.
  • c4m-flexcell: a (currently minimal) standard cell library based on PDKMaster
  • c4m-flexmem: the source for the memory compiler
  • c4m-pdk-sky130: the source for the PDKMaster based PDK for the Sky130 technology.


The resulting GDS files is released under the LGPL 2.1 or later license. Some of the source code to generate the GDS is under the GPL 2.0 or later license.