commit | dea823abd9f7aba871ab6a40f75460ca5a7edd7f | [log] [tgz] |
---|---|---|
author | dineshannayya <dinesh.annayya@gmail.com> | Mon Sep 05 16:40:55 2022 +0530 |
committer | dineshannayya <dinesh.annayya@gmail.com> | Mon Sep 05 16:40:55 2022 +0530 |
tree | 75701ae9e0611f880bf1163362a178f27ee3619f | |
parent | af775b812a8ed78f7846653ac40b25f3f33036da [diff] |
defualt skew value fix
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh index 7664338..3436cae 100644 --- a/verilog/rtl/user_params.svh +++ b/verilog/rtl/user_params.svh
@@ -8,7 +8,7 @@ // Software Reg-2: Poject Revison 5.1 = 0005200 parameter CHIP_REVISION = 32'h0005_3000; -parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_1000; +parameter SKEW_RESET_VAL = 32'b0000_1000_1000_0111_1001_1000_1001_1000; parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1011_0000;