arduino spi compatibility design changes
diff --git a/Makefile b/Makefile
index ff82bc4..491109f 100644
--- a/Makefile
+++ b/Makefile
@@ -151,7 +151,7 @@
$(eval INPUT_DIRECTORY := $(shell pwd))
cd $(PRECHECK_ROOT) && \
docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
- -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)"
diff --git a/openlane/Makefile b/openlane/Makefile
index 865f452..c21989a 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -18,7 +18,7 @@
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
-OPENLANE_TAG = mpw5
+OPENLANE_TAG = mpw7
OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite -it -file ./$*/interactive.tcl"
@@ -43,15 +43,29 @@
@sleep 1
@if [ -f ./$*/interactive.tcl ]; then\
- docker run --rm \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
+ -v $(MCW_ROOT):$(MCW_ROOT) \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -e PDK=$(PDK) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
- docker run --rm \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -v $(MCW_ROOT):$(MCW_ROOT) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -e PDK=$(PDK) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux/base.sdc
index 91f9b40..2aa686d 100644
--- a/openlane/pinmux/base.sdc
+++ b/openlane/pinmux/base.sdc
@@ -10,7 +10,7 @@
set_propagated_clock [get_clocks {mclk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 491ef7d..c27d14e 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -41,24 +41,24 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \
- $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \
- $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \
- $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \
- $script_dir/../../verilog/rtl/pinmux/src/timer.sv \
- $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \
- $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \
- $script_dir/../../verilog/rtl/lib/registers.v \
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -72,7 +72,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 550 450"
+set ::env(DIE_AREA) "0 0 500 400"
# If you're going to use multiple power domains, then keep this disabled.
@@ -82,9 +82,12 @@
set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.38"
set ::env(CELL_PAD) "4"
+set ::env(FP_IO_VEXTEND) {6}
+set ::env(FP_IO_HEXTEND) {6}
+
# helps in anteena fix
set ::env(USE_ARC_ANTENNA_CHECK) "0"
@@ -99,7 +102,7 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/qspim_top/base.sdc b/openlane/qspim_top/base.sdc
index 327d1f4..c0e8993 100644
--- a/openlane/qspim_top/base.sdc
+++ b/openlane/qspim_top/base.sdc
@@ -24,7 +24,7 @@
set_propagated_clock [get_clocks {spiclk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index 187e486..0ce98bf 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -41,23 +41,23 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/lib/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_regs.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_fifo.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_clkgen.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_ctrl.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_rx.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_tx.sv \
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_if.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_regs.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_clkgen.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_ctrl.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_rx.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_tx.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -95,7 +95,7 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc
index 4a33fc5..35bba97 100644
--- a/openlane/uart_i2cm_usb_spi_top/base.sdc
+++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -12,7 +12,7 @@
create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
@@ -44,9 +44,9 @@
set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
-set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -max 5.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_be[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 5.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wdata[*]}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 802f0cf..39350c5 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -41,44 +41,45 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/uart/src/uart_core.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
- $script_dir/../../verilog/rtl/lib/async_wb.sv \
- $script_dir/../../verilog/rtl/lib/async_fifo.sv \
- $script_dir/../../verilog/rtl/lib/async_fifo_th.sv \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
- $script_dir/../../verilog/rtl/lib/double_sync_low.v \
- $script_dir/../../verilog/rtl/lib/clk_ctl.v \
- $script_dir/../../verilog/rtl/lib/registers.v \
- $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \
- $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \
- $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_core.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v \
- $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
- $script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_top.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_ctl.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_if.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_cfg.sv \
- $script_dir/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_cfg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo_th.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_top.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/top/usb1_host.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_ctl.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_if.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_cfg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_clkgen.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
"
set ::env(SYNTH_NO_FLAT) {1}
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/includes $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/includes ]
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -91,7 +92,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 510.0 725.0]
+set ::env(DIE_AREA) [list 0.0 0.0 520.0 725.0]
@@ -117,13 +118,14 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
-set ::env(GLB_RT_ADJUSTMENT) {0.25}
+#set ::env(GLB_RT_ADJUSTMENT) {0.25}
+set ::env(GLB_RT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0}
set ::env(CELL_PAD) {2}
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 9a342cd..a8d2721 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -31,9 +31,9 @@
set proj_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_wrapper
-set verilog_root $proj_dir/../../verilog/
-set lef_root $proj_dir/../../lef/
-set gds_root $proj_dir/../../gds/
+set verilog_root $::env(DESIGN_DIR)/../../verilog/
+set lef_root $::env(DESIGN_DIR)/../../lef/
+set gds_root $::env(DESIGN_DIR)/../../gds/
#section end
# User Configurations
@@ -44,8 +44,8 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $proj_dir/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv \
- $proj_dir/../../verilog/rtl/user_project_wrapper.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
@@ -57,28 +57,29 @@
## Internal Macros
### Macro Placement
set ::env(FP_SIZING) "absolute"
-set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
-set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl
+set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn_cfg.tcl
-set ::env(SDC_FILE) "$proj_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
- $proj_dir/../../verilog/gl/qspim_top.v \
- $proj_dir/../../verilog/gl/wb_interconnect.v \
- $proj_dir/../../verilog/gl/pinmux.v \
- $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \
- $proj_dir/../../verilog/gl/wb_host.v \
- $proj_dir/../../verilog/gl/ycr_intf.v \
- $proj_dir/../../verilog/gl/ycr_core_top.v \
- $proj_dir/../../verilog/gl/ycr_iconnect.v \
- $proj_dir/../../verilog/gl/digital_pll.v \
- $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
- "
+ $::env(DESIGN_DIR)/../../verilog/gl/qspim_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/pinmux.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/uart_i2c_usb_spi_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_iconnect.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sar_adc_10b/sar_adc_10b.v \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ "
set ::env(EXTRA_LEFS) "\
$lef_root/qspim_top.lef \
@@ -108,7 +109,7 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/includes ]
#set ::env(GLB_RT_MAXLAYER) 6
set ::env(RT_MAX_LAYER) {met5}
@@ -119,55 +120,48 @@
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
-set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
+#set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
-set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
-#
+set ::env(VDD_NET) {vccd1}
set ::env(VDD_PIN) {vccd1}
+set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
+set ::env(GND_NET) {vssd1}
set ::env(GND_PIN) {vssd1}
-set ::env(GLB_RT_OBS) " \
+
+set ::env(GRT_OBS) " \
li1 150 130 833.1 546.54,\
met1 150 130 833.1 546.54,\
met2 150 130 833.1 546.54,\
- met3 150 130 833.1 546.54,\
+ met3 150 130 833.1 546.54,\
li1 950 130 1633.1 546.54,\
met1 950 130 1633.1 546.54,\
met2 950 130 1633.1 546.54,\
- met3 950 130 1633.1 546.54,\
- li1 150 750 833.1 1166.54,\
- met1 150 750 833.1 1166.54,\
- met2 150 750 833.1 1166.54,\
- met3 150 750 833.1 1166.54,\
- met1 2250 2150 2800 2600,\
- met2 2250 2150 2800 2600,\
- met3 2250 2150 2800 2600,\
- met1 950 650 1760 1290,\
- met2 950 650 1760 1290,\
- met3 950 650 1760 1290,\
-
+ met3 950 130 1633.1 546.54,\
+ li1 150 750 833.1 1166.54,\
+ met1 150 750 833.1 1166.54,\
+ met2 150 750 833.1 1166.54,\
+ met3 150 750 833.1 1166.54,\
met5 0 0 2920 3520"
-set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
+#set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 1, vdda2 vssa2 1"
-#set ::env(FP_PDN_MACRO_HOOKS) " \
-# u_intercon vccd1 vssd1,\
-# u_pinmux vccd1 vssd1,\
-# u_qspi_master vccd1 vssd1,\
-# u_riscv_top vccd1 vssd1,\
-# u_tsram0_2kb vccd1 vssd1,\
-# u_icache_2kb vccd1 vssd1,\
-# u_dcache_2kb vccd1 vssd1,\
-# u_sram0_2kb vccd1 vssd1,\
-# u_sram1_2kb vccd1 vssd1,\
-# u_sram2_2kb vccd1 vssd1,\
-# u_sram3_2kb vccd1 vssd1,\
-# u_uart_i2c_usb_spi vccd1 vssd1,\
-# u_wb_host vccd1 vssd1,\
-# u_riscv_top.i_core_top_0 vccd1 vssd1, \
-# u_riscv_top.u_intf vccd1 vssd1 \
-# "
+set ::env(FP_PDN_MACRO_HOOKS) " \
+ u_pll vccd1 vssd1 VPWR VGND, \
+ u_intercon vccd1 vssd1 vccd1 vssd1,\
+ u_pinmux vccd1 vssd1 vccd1 vssd1,\
+ u_qspi_master vccd1 vssd1 vccd1 vssd1,\
+ u_tsram0_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_icache_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_dcache_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_uart_i2c_usb_spi vccd1 vssd1 vccd1 vssd1,\
+ u_wb_host vccd1 vssd1 vccd1 vssd1,\
+ u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1, \
+ u_riscv_top.u_connect vccd1 vssd1 VPWR VGND, \
+ u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1 \
+ "
+
# The following is because there are no std cells in the example wrapper project.
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
old mode 100644
new mode 100755
index ccfa729..1f6639d
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -1,7 +1,5 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -14,358 +12,335 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-package require openlane;
+package require openlane; # provides the utils as well
+
proc run_placement_step {args} {
if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
}
+
run_placement
}
+
proc run_cts_step {args} {
if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
}
+
run_cts
run_resizer_timing
}
+
proc run_routing_step {args} {
if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
}
- run_routing
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
proc run_diode_insertion_2_5_step {args} {
if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
}
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
proc run_lvs_step {{ lvs_enabled 1 }} {
if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
}
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
}
+
proc run_drc_step {{ drc_enabled 1 }} {
if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
}
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
}
+
proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
}
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-proc run_eco_step {args} {
- if { $::env(ECO_ENABLE) == 1 } {
- run_eco
+ if { $antenna_check_enabled } {
+ run_antenna_check
}
}
-proc save_final_views {args} {
- set options {
- {-save_path optional}
- }
- set flags {}
- parse_key_args "save_final_views" args arg_values $options flags_map $flags
- set arg_list [list]
- # If they don't exist, save_views will simply not copy them
- lappend arg_list -lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef
- lappend arg_list -gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds
- lappend arg_list -mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag
- lappend arg_list -maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag
- lappend arg_list -spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice
-
- # Guaranteed to have default values
- lappend arg_list -def_path $::env(CURRENT_DEF)
- lappend arg_list -verilog_path $::env(CURRENT_NETLIST)
- # Not guaranteed to have default values
- if { [info exists ::env(SPEF_TYPICAL)] } {
- lappend arg_list -spef_path $::env(SPEF_TYPICAL)
- }
- if { [info exists ::env(CURRENT_SDF)] } {
- lappend arg_list -sdf_path $::env(CURRENT_SDF)
- }
- if { [info exists ::env(CURRENT_SDC)] } {
- lappend arg_list -sdc_path $::env(CURRENT_SDC)
- }
- # Add the path if it exists...
- if { [info exists arg_values(-save_path) ] } {
- lappend arg_list -save_path $arg_values(-save_path)
- }
- # Aaand fire!
- save_views {*}$arg_list
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
proc run_post_run_hooks {} {
- if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
- puts_info "Running post run hook"
- set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
- puts_info "$result"
- } else {
- puts_info "hooks/post_run.py not found, skipping"
- }
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
}
-proc gen_pdn {args} {
- puts_info "Generating PDN..."
- TIMER::timer_start
-
- set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles).def]
- set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles).pga.rpt]
- run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
- |& -indexed_log [index_file $::env(floorplan_logs)/pdn.log]
- TIMER::timer_stop
- exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "pdn generation - openroad"
- quit_on_unconnected_pdn_nodes
- set_def $::env(SAVE_DEF)
+
+proc run_magic_drc_batch {args} {
+ set options {
+ {-magicrc optional}
+ {-tech optional}
+ {-report required}
+ {-design required}
+ {-gds required}
+ }
+ set flags {}
+ parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
+ if { [info exists arg_values(-magicrc)] } {
+ set magicrc [file normalize $arg_values(-magicrc)]
+ }
+ if { [info exists arg_values(-tech)] } {
+ set ::env(TECH) [file normalize $arg_values(-tech)]
+ }
+ set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+ set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+ set ::env(DESIGN_NAME) $arg_values(-design)
+
+ if { [info exists magicrc] } {
+ exec magic \
+ -noconsole \
+ -dnull \
+ -rcfile $magicrc \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ } else {
+ exec magic \
+ -noconsole \
+ -dnull \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ }
}
-proc run_power_grid_generation {args} {
- if {[info exists ::env(FP_PDN_POWER_STRAPS)]} {
- set power_domains [split $::env(FP_PDN_POWER_STRAPS) ","]
- }
- # internal macros power connections
- if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
- set macro_hooks [dict create]
- set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
- foreach pdn_hook $pdn_hooks {
- set instance_name [lindex $pdn_hook 0]
- set power_net [lindex $pdn_hook 1]
- set ground_net [lindex $pdn_hook 2]
- dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
- }
-
- set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
- set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
- # make sure that the specified power domains exist.
- if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
- puts_err "Can't find $power_net and $ground_net domain. \
- Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
- }
- }
-
- # generate multiple power grids per pair of (VDD,GND)
- # offseted by WIDTH + SPACING
- foreach domain $power_domains {
- set ::env(VDD_NET) [lindex $domain 0]
- set ::env(GND_NET) [lindex $domain 1]
- set ::env(_WITH_STRAPS) [lindex $domain 2]
- puts_info "Connecting Power: $::env(VDD_NET) & $::env(GND_NET) to All internal macros."
- # internal macros power connections
- set ::env(FP_PDN_MACROS) ""
- if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
- # if macros connections to power are explicitly set
- # default behavoir macro pins will be connected to the first power domain
- if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- foreach {instance_name hooks} $macro_hooks {
- set power [lindex $hooks 0]
- set ground [lindex $hooks 1]
- if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
- set ::env(FP_PDN_IRDROP) "0"
- puts_info "Connecting $instance_name to $power and $ground nets."
- lappend ::env(FP_PDN_MACROS) $instance_name
- }
- }
- }
- } else {
- puts_warn "All internal macros will not be connected to power $::env(VDD_NET) & $::env(GND_NET)."
- }
-
- gen_pdn
- set ::env(FP_PDN_ENABLE_RAILS) 0
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- set ::env(FP_PDN_IRDROP) "0"
- # allow failure until open_pdks is up to date...
- catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
- catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
- catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
- [expr $::env(FP_PDN_CORE_RING_VOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_VWIDTH)\
- +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
- max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
- puts "FP_PDN_HOFFSET: $::env(FP_PDN_HOFFSET)"
- puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
- puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
- }
- set ::env(FP_PDN_ENABLE_RAILS) 1
+
+proc run_lvs_batch {args} {
+ # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
+ # extracts gds only if EXT_NETLIST does not exist
+ set options {
+ {-design required}
+ {-gds optional}
+ {-net optional}
+ }
+ set flags {}
+ parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
+
+ prep {*}$args
+
+ if { [info exists arg_values(-gds)] } {
+ set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
+ } else {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ }
+ if { [info exists arg_values(-net)] } {
+ set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+ }
+
+ assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
+
+ set ::env(MAGIC_EXT_USE_GDS) 1
+ set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
+ if { [file exists $::env(EXT_NETLIST)] } {
+ puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
+ } else {
+ run_magic_spice_export
+ }
+
+ run_lvs
}
-proc run_floorplan {args} {
- puts_info "Running Floorplanning..."
- # |----------------------------------------------------|
- # |---------------- 2. FLOORPLAN ------------------|
- # |----------------------------------------------------|
- #
- # intial fp
- init_floorplan
- # check for deprecated io variables
- if { [info exists ::env(FP_IO_HMETAL)]} {
- set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
- puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
- puts_warn "We recommend you update your configuration as follows:"
- puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
- }
- if { [info exists ::env(FP_IO_VMETAL)]} {
- set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
- puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
- puts_warn "We recommend you update your configuration as follows:"
- puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
- }
- # place io
- if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
- place_io_ol
- } else {
- if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
- place_io
- global_placement_or
- place_contextualized_io \
- -lef $::env(FP_CONTEXT_LEF) \
- -def $::env(FP_CONTEXT_DEF)
- } else {
- place_io
- }
- }
- apply_def_template
- if { [info exist ::env(EXTRA_LEFS)] } {
- if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
- file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
- manual_macro_placement f
- } else {
- global_placement_or
- basic_macro_placement
- }
- }
- tap_decap_or
- scrot_klayout -layout $::env(CURRENT_DEF) $::env(floorplan_logs)/screenshot.log
- run_power_grid_generation
+
+
+proc run_file {args} {
+ set ::env(TCLLIBPATH) $::auto_path
+ exec tclsh {*}$args >&@stdout
}
+
+
+
proc run_flow {args} {
- set options {
- {-design required}
- {-from optional}
- {-to optional}
- {-save_path optional}
- {-override_env optional}
- }
- set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck }
- parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
- prep {*}$args
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
# signal trap SIGINT save_state;
- if { [info exists arg_values(-override_env)] } {
- set env_overrides [split $arg_values(-override_env) ',']
- foreach override $env_overrides {
- set kva [split $override '=']
- set key [lindex $kva 0]
- set value [lindex $kva 1]
- set ::env(${key}) $value
- }
- }
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
set LVS_ENABLED 1
set DRC_ENABLED 0
- set ANTENNACHECK_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
set steps [dict create \
- "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "eco" {run_eco_step ""} \
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
]
- set_if_unset arg_values(-to) "cvc";
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
} else {
- set ::env(CURRENT_STEP) "synthesis";
+ set ::env(CURRENT_STEP) "synthesis"
}
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
set exe 0;
dict for {step_name step_exe} $steps {
if { [ string equal $arg_values(-from) $step_name ] } {
set exe 1;
}
+
if { $exe } {
# For when it fails
set ::env(CURRENT_STEP) $step_name
[lindex $step_exe 0] [lindex $step_exe 1] ;
}
+
if { [ string equal $arg_values(-to) $step_name ] } {
set exe 0:
break;
}
+
}
+
# for when it resumes
set steps_as_list [dict keys $steps]
set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
- # Saves to <RUN_DIR>/results/final
- if { $::env(SAVE_FINAL_VIEWS) == "1" } {
- save_final_views
- }
- # Saves to design directory or custom
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) $::env(DESIGN_DIR)
- }
- save_final_views\
- -save_path $arg_values(-save_path)\
- -tag $::env(RUN_TAG)
- }
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- if { [info exists arg_values(-save_path)]\
- && $arg_values(-save_path) != "" } {
- set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
- } else {
- set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
- }
-
- if {[info exists flags_map(-run_hooks)]} {
- run_post_run_hooks
- }
-
- puts_success "Flow complete."
- show_warnings "Note that the following warnings have been generated:"
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
}
+
run_flow {*}$argv
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 7cc2709..91b751d 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -12,4 +12,4 @@
u_intercon 1850 650 N
u_wb_host 1750 100 N
-u_pll 2300 100 N
+u_pll 2305 105 N
diff --git a/openlane/user_project_wrapper/mpw6/config.tcl b/openlane/user_project_wrapper/mpw6/config.tcl
index 9b0d5f6..7465c71 100644
--- a/openlane/user_project_wrapper/mpw6/config.tcl
+++ b/openlane/user_project_wrapper/mpw6/config.tcl
@@ -31,9 +31,9 @@
set proj_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_wrapper
-set verilog_root $proj_dir/../../verilog/
-set lef_root $proj_dir/../../lef/
-set gds_root $proj_dir/../../gds/
+set verilog_root $::env(DESIGN_DIR)/../../verilog/
+set lef_root $::env(DESIGN_DIR)/../../lef/
+set gds_root $::env(DESIGN_DIR)/../../gds/
#section end
# User Configurations
@@ -44,8 +44,8 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $proj_dir/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv \
- $proj_dir/../../verilog/rtl/user_project_wrapper.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
@@ -57,26 +57,27 @@
## Internal Macros
### Macro Placement
set ::env(FP_SIZING) "absolute"
-set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl
-set ::env(SDC_FILE) "$proj_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
- $proj_dir/../../verilog/gl/qspim_top.v \
- $proj_dir/../../verilog/gl/wb_interconnect.v \
- $proj_dir/../../verilog/gl/pinmux.v \
- $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \
- $proj_dir/../../verilog/gl/wb_host.v \
- $proj_dir/../../verilog/gl/ycr_intf.v \
- $proj_dir/../../verilog/gl/ycr_core_top.v \
- $proj_dir/../../verilog/gl/ycr_iconnect.v \
- $proj_dir/../../verilog/gl/digital_pll.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/qspim_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/pinmux.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/uart_i2c_usb_spi_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_iconnect.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sar_adc_10b/sar_adc_10b.v \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
"
@@ -90,6 +91,7 @@
$lef_root/ycr_core_top.lef \
$lef_root/ycr_iconnect.lef \
$lef_root/digital_pll.lef \
+ $lef_root/sar_adc_10b.lef \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
"
@@ -103,12 +105,13 @@
$gds_root/ycr_core_top.gds \
$gds_root/ycr_iconnect.gds \
$gds_root/digital_pll.gds \
+ $gds_root/sar_adc_10b.gds \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/includes ]
#set ::env(GLB_RT_MAXLAYER) 6
set ::env(RT_MAX_LAYER) {met5}
@@ -124,25 +127,22 @@
set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
#
-set ::env(VDD_PIN) {vccd1}
-set ::env(GND_PIN) {vssd1}
+set ::env(VDD_PIN) {vccd1 vccd2 vdda1 vdda2}
+set ::env(GND_PIN) {vssd1 vssd2 vssa1 vssa2}
set ::env(GLB_RT_OBS) " \
li1 150 130 833.1 546.54,\
met1 150 130 833.1 546.54,\
met2 150 130 833.1 546.54,\
met3 150 130 833.1 546.54,\
-
li1 950 130 1633.1 546.54,\
met1 950 130 1633.1 546.54,\
met2 950 130 1633.1 546.54,\
met3 950 130 1633.1 546.54,\
-
li1 150 750 833.1 1166.54,\
met1 150 750 833.1 1166.54,\
met2 150 750 833.1 1166.54,\
met3 150 750 833.1 1166.54,\
-
met1 2250 2150 2800 2600,\
met2 2250 2150 2800 2600,\
met3 2250 2150 2800 2600,\
@@ -152,7 +152,6 @@
met5 0 0 2920 3520"
-set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
set ::env(FP_PDN_MACRO_HOOKS) " \
u_intercon vccd1 vssd1,\
@@ -174,51 +173,31 @@
# The following is because there are no std cells in the example wrapper project.
+set ::env(CELL_PAD) "4"
set ::env(SYNTH_TOP_LEVEL) 0
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-
set ::env(FP_PDN_ENABLE_RAILS) 0
-
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
-
set ::env(QUIT_ON_LVS_ERROR) "1"
set ::env(QUIT_ON_MAGIC_DRC) "0"
set ::env(QUIT_ON_NEGATIVE_WNS) "0"
set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-
set ::env(FP_PDN_IRDROP) "0"
set ::env(FP_PDN_HORIZONTAL_HALO) "10"
set ::env(FP_PDN_VERTICAL_HALO) "10"
-
-#
-
-set ::env(FP_PDN_CORE_RING_HOFFSET) {12.45}
-set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
-set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1}
-
-set ::env(FP_PDN_CORE_RING_VOFFSET) {12.45}
-set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
-set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1}
-
-
set ::env(FP_PDN_VOFFSET) "5"
set ::env(FP_PDN_VPITCH) "80"
set ::env(FP_PDN_VSPACING) "15.5"
set ::env(FP_PDN_VWIDTH) "3.1"
-
set ::env(FP_PDN_HOFFSET) "10"
set ::env(FP_PDN_HPITCH) "90"
set ::env(FP_PDN_HSPACING) "10"
set ::env(FP_PDN_HWIDTH) "3.1"
-
-
-
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index 552a90e..79a0f85 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -1,82 +1,161 @@
# Power nets
-if { ! [info exists ::env(VDD_NET)] } {
- set ::env(VDD_NET) $::env(VDD_PIN)
-}
-if { ! [info exists ::env(GND_NET)] } {
- set ::env(GND_NET) $::env(GND_PIN)
-}
-set ::power_nets $::env(VDD_NET)
-set ::ground_nets $::env(GND_NET)
if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
foreach power_pin $::env(STD_CELL_POWER_PINS) {
- add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
+ add_global_connection \
+ -net $::env(VDD_NET) \
+ -inst_pattern .* \
+ -pin_pattern $power_pin \
+ -power
}
foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
- add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
+ add_global_connection \
+ -net $::env(GND_NET) \
+ -inst_pattern .* \
+ -pin_pattern $ground_pin \
+ -ground
}
}
}
-set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
-# Assesses whether the deisgn is the core of the chip or not based on the
+
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
+ [info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+ set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+ foreach pdn_hook $pdn_hooks {
+ set instance_name [lindex $pdn_hook 0]
+ set power_net [lindex $pdn_hook 1]
+ set ground_net [lindex $pdn_hook 2]
+ set power_pin [lindex $pdn_hook 3]
+ set ground_pin [lindex $pdn_hook 4]
+
+ if { $power_pin == "" || $ground_pin == "" } {
+ puts "FP_PDN_MACRO_HOOKS missing power and ground pin names"
+ exit -1
+ }
+
+ add_global_connection \
+ -net $power_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $power_pin \
+ -power
+
+ add_global_connection \
+ -net $ground_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $ground_pin \
+ -ground
+ }
+}
+
+set secondary []
+
+foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+ if { $vdd != $::env(VDD_NET)} {
+ lappend secondary $vdd
+
+ set db_net [[ord::get_db_block] findNet $vdd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $vdd]
+ $net setSpecial
+ $net setSigType "POWER"
+ }
+ }
+
+ if { $gnd != $::env(GND_NET)} {
+ lappend secondary $gnd
+
+ set db_net [[ord::get_db_block] findNet $gnd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $gnd]
+ $net setSpecial
+ $net setSigType "GROUND"
+ }
+ }
+}
+
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
+ -secondary_power $secondary
+
+# Assesses whether the design is the core of the chip or not based on the
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
if { $::env(DESIGN_IS_CORE) == 1 } {
# Used if the design is the core of the chip
- define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
- if { $::env(_WITH_STRAPS) } {
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
- }
- add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_UPPER_LAYER) \
+ -width $::env(FP_PDN_HWIDTH) \
+ -pitch $::env(FP_PDN_HPITCH) \
+ -offset $::env(FP_PDN_HOFFSET) \
+ -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
} else {
# Used if the design is a macro in the core
- define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins $::env(FP_PDN_LOWER_LAYER)
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins $::env(FP_PDN_LOWER_LAYER)
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -starts_with POWER
}
+
# Adds the standard cell rails if enabled.
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
- add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
-}
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_RAILS_LAYER) \
+ -width $::env(FP_PDN_RAIL_WIDTH) \
+ -followpins \
+ -starts_with POWER
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
+}
+
+
# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
- add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
- -widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
- -spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
- -core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
+ add_pdn_ring \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \
+ -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
+ -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
+ -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
}
-# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
-# The macro power pin names are assumed to match the VDD and GND net names
-# TODO: parameterize the power pin names
-set macro {
- orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
- power_pins $::env(VDD_NET)
- ground_pins $::env(GND_NET)
- blockages $::env(MACRO_BLOCKAGES_LAYER)
- straps {
- }
- connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
-}
-if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1} {
- if { [llength $::env(FP_PDN_MACROS)] > 0 } {
- # generate automatically per instance:
- foreach macro_instance $::env(FP_PDN_MACROS) {
- set macro_instance_grid [subst $macro]
- dict append $macro_instance_grid instance $macro_instance
- set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
- pdngen::specify_grid macro [subst $macro_instance_grid]
- }
- } else {
- set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
- pdngen::specify_grid macro [subst $macro]
- }
- # CAN NOT ENABLE THE TCL COMMAND BECAUSE THERE IS NO ARGUMENT FOR SPECIFYING THE POWER AND GROUND PIN NAMES ON THE MACRO
- # define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -pin_direction vertical -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
- # add_pdn_connect -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
-} else {
- define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
-}
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
+
+define_pdn_grid \
+ -macro \
+ -default \
+ -name macro \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect \
+ -grid macro \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index a5b2325..3c8cdc9 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc
@@ -16,7 +16,7 @@
create_clock -name usb_ref_clk -period 10.0000 [get_pins {u_usb_ref_clkbuf.u_buf/X}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 559345a..527f4cc 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -24,8 +24,6 @@
set ::env(DESIGN_IS_CORE) "0"
-set ::env(OPENLANE_VERBOSE) {10}
-
# Timing configuration
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X"
@@ -42,31 +40,31 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
- $script_dir/../../verilog/rtl/lib/async_fifo.sv \
- $script_dir/../../verilog/rtl/lib/async_wb.sv \
- $script_dir/../../verilog/rtl/lib/clk_ctl.v \
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/lib/registers.v \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
- $script_dir/../../verilog/rtl/lib/async_reg_bus.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
- $script_dir/../../verilog/rtl/lib/double_sync_low.v \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
- $script_dir/../../verilog/rtl/uart2wb/src/uart2wb.sv \
- $script_dir/../../verilog/rtl/uart2wb/src/uart2_core.sv \
- $script_dir/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \
- $script_dir/../../verilog/rtl/sspis/src/sspis_top.sv \
- $script_dir/../../verilog/rtl/sspis/src/sspis_if.sv \
- $script_dir/../../verilog/rtl/sspis/src/spi2wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_reg_bus.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_if.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/spi2wb.sv \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -104,7 +102,7 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
index d815c04..d4e6271 100644
--- a/openlane/wb_interconnect/base.sdc
+++ b/openlane/wb_interconnect/base.sdc
@@ -9,7 +9,7 @@
create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
#Clock Skew adjustment
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 55b38f4..c58574a 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -40,23 +40,23 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/lib/sync_wbb.sv \
- $script_dir/../../verilog/rtl/lib/sync_fifo2.sv \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_wbb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_PARAMS) "CH_CLK_WD 4,\
- CH_DATA_WD 37 \
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
+ CH_DATA_WD=37 \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -88,7 +88,7 @@
set ::env(USE_ARC_ANTENNA_CHECK) "0"
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
## CTS
@@ -104,14 +104,17 @@
set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
## Routing
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.21
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.21
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
-set ::env(GLB_RT_OVERFLOW_ITERS) 200
+set ::env(GRT_ADJUSTMENT) 0.1
+set ::env(DPL_CELL_PADDING) 1
+
+#set ::env(GLB_RT_ADJUSTMENT) 0
+#set ::env(GLB_RT_L2_ADJUSTMENT) 0.21
+#set ::env(GLB_RT_L3_ADJUSTMENT) 0.21
+#set ::env(GLB_RT_L4_ADJUSTMENT) 0.1
+#set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+#set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+#set ::env(GLB_RT_ALLOW_CONGESTION) 0
+#set ::env(GLB_RT_OVERFLOW_ITERS) 200
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 0a05d50..5e26d19 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -5,7 +5,7 @@
set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
-set_clock_uncertainty -hold 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
@@ -15,7 +15,7 @@
#IMEM Constraints
set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
@@ -32,11 +32,11 @@
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
#DMEM Constraints
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index 59a9332..d669b67 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -33,38 +33,38 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_core_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dm.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_scu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dmi.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_core_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_scu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dmi.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo2.sv \
"
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/includes ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -72,17 +72,19 @@
set ::env(GND_PIN) [list {vssd1}]
## Floorplan
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 540 950 "
+set ::env(DIE_AREA) "0 0 550 950 "
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_TARGET_DENSITY) 0.43
+set ::env(PL_TARGET_DENSITY) 0.42
set ::env(CELL_PAD) "4"
+## Routing
+set ::env(GRT_ADJUSTMENT) 0.2
+
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_core_top/macro_placement.cfg b/openlane/ycr_core_top/macro_placement.cfg
index 8ec6301..e69de29 100644
--- a/openlane/ycr_core_top/macro_placement.cfg
+++ b/openlane/ycr_core_top/macro_placement.cfg
@@ -1,2 +0,0 @@
-u_icache.u_cmem_2kb 285.000 291.000 FS
-u_dcache.u_cmem_2kb 1185.000 291.000 N
diff --git a/openlane/ycr_iconnect/base.sdc b/openlane/ycr_iconnect/base.sdc
index a8461ed..d731daa 100644
--- a/openlane/ycr_iconnect/base.sdc
+++ b/openlane/ycr_iconnect/base.sdc
@@ -1,10 +1,10 @@
###############################################################################
# Timing Constraints
###############################################################################
-create_clock -name core_clk -period 8.0000 [get_ports {core_clk}]
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
@@ -13,10 +13,10 @@
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
#CORE-0 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
@@ -30,11 +30,11 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
#CORE-0 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
@@ -48,41 +48,6 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
-#CORE-1 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
-
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}]
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}]
-set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
-
-#CORE-1 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
-
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}]
-set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}]
-set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
###############################################################################
# Environment
diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl
index ceb1b04..0407ee8 100644
--- a/openlane/ycr_iconnect/config.tcl
+++ b/openlane/ycr_iconnect/config.tcl
@@ -34,40 +34,41 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_router.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_tcm.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_timer.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_arb.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo2.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_router.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_tcm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_timer.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_arb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv \
"
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/includes ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
## Floorplan
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 380 1100"
-#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl
-#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn_cfg.tcl
+#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.20
-set ::env(CELL_PAD) "2"
+set ::env(CELL_PAD) 2
+set ::env(GRT_ADJUSTMENT) {0.2}
-set ::env(GLB_RT_ADJUSTMENT) {0.2}
+#set ::env(GLB_RT_ADJUSTMENT) {0.2}
#set ::env(PL_ROUTABILITY_DRIVEN) "1"
set ::env(PL_TIME_DRIVEN) "1"
@@ -97,7 +98,7 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index 2774794..db8fbe6 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc
@@ -11,7 +11,7 @@
create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock1} [get_ports icache_mem_clk1]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index aacee26..51b6c8b 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -34,27 +34,27 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_intf.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/async_fifo.sv \
- $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_intf.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/async_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv \
"
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/includes ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -62,12 +62,11 @@
set ::env(GND_PIN) [list {vssd1}]
## Floorplan
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 810 640 "
set ::env(CELL_PAD) "6"
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.37
set ::env(FP_IO_VEXTEND) {6}
@@ -75,7 +74,7 @@
set ::env(RT_MAX_LAYER) {met4}
#set ::env(GLB_RT_MAXLAYER) "5"
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/signoff/pinmux/OPENLANE_VERSION b/signoff/pinmux/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/pinmux/OPENLANE_VERSION
+++ b/signoff/pinmux/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
+++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index 80c7664..d5588cd 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index 22e7dc1..e8e14ea 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr_iconnect/OPENLANE_VERSION b/signoff/ycr_iconnect/OPENLANE_VERSION
index 078e9d2..6aa8d2d 100644
--- a/signoff/ycr_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane f9b5781f5ef0bbdf39ab1c2bbd78be8db11b27f2
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
index 6553e32..d4dd6f5 100644
--- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
@@ -68,8 +68,8 @@
// take the SS pin low to select the chip:
digitalWrite(slaveSelectPin, LOW);
// send in the address and value via SPI:
- SPI.write_transfer(address);
- SPI.write_transfer(value);
+ SPI.transfer(address);
+ SPI.transfer(value);
// take the SS pin high to de-select the chip:
digitalWrite(slaveSelectPin, HIGH);
}
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
index d6b09bc..64d6d49 100644
--- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -208,7 +208,7 @@
fork
begin
- for (channel = 0; channel < 6; channel = channel+1) begin
+ for (channel = 0; channel < 1; channel = channel+1) begin
// change the resistance on this channel from min to max:
for (level = 0; level < 255; level = level+1) begin
wait(u_ad5205.channel == channel && u_ad5205.position == level);
@@ -234,7 +234,7 @@
if(test_fail == 0) begin
`ifdef GL
$display("Monitor: Ardunio Digital Port Control (GL) Passed");
- else
+ `else
$display("Monitor: Ardunio Digital Port Control (RTL) Passed");
`endif
end else begin
diff --git a/verilog/dv/arduino_i2c_scaner/Makefile b/verilog/dv/arduino_i2c_scaner/Makefile
new file mode 100644
index 0000000..e6d5947
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/Makefile
@@ -0,0 +1,142 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_i2c_scaner
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/Wire.cpp -o Wire.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/utility/twi.c -o twi.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o twi.c.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino
new file mode 100644
index 0000000..295edf7
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino
@@ -0,0 +1,75 @@
+// --------------------------------------
+// i2c_scanner
+//
+// Version 1
+// This program (or code that looks like it)
+// can be found in many places.
+// For example on the Arduino.cc forum.
+// The original author is not known.
+// Version 2, Juni 2012, Using Arduino 1.0.1
+// Adapted to be as simple as possible by Arduino.cc user Krodal
+// Version 3, Feb 26 2013
+// V3 by louarnold
+// Version 4, March 3, 2013, Using Arduino 1.0.3
+// by Arduino.cc user Krodal.
+// Changes by louarnold removed.
+// Scanning addresses changed from 0...127 to 1...119,
+// according to the i2c scanner by Nick Gammon
+// https://www.gammon.com.au/forum/?id=10896
+// Version 5, March 28, 2013
+// As version 4, but address scans now to 127.
+// A sensor seems to use address 120.
+// Version 6, November 27, 2015.
+// Added waiting for the Leonardo serial communication.
+//
+//
+// This sketch tests the standard 7-bit addresses
+// Devices with higher bit address might not be seen properly.
+//
+
+#include <Wire.h>
+
+void setup() {
+ Wire.begin();
+
+ Serial.begin(9600);
+ while (!Serial); // Leonardo: wait for Serial Monitor
+ Serial.println("\nI2C Scanner");
+}
+
+void loop() {
+ int nDevices = 0;
+
+ Serial.println("Scanning...");
+
+ for (byte address = 1; address < 127; ++address) {
+ // The i2c_scanner uses the return value of
+ // the Wire.endTransmission to see if
+ // a device did acknowledge to the address.
+ Wire.beginTransmission(address);
+ byte error = Wire.endTransmission();
+
+ if (error == 0) {
+ Serial.print("I2C device found at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.print(address, HEX);
+ Serial.println(" !");
+
+ ++nDevices;
+ } else if (error == 4) {
+ Serial.print("Unknown error at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.println(address, HEX);
+ }
+ }
+ if (nDevices == 0) {
+ Serial.println("No I2C devices found\n");
+ } else {
+ Serial.println("done\n");
+ }
+ delay(5000); // Wait 5 seconds for next scan
+}
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
new file mode 100644
index 0000000..dc656cb
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
@@ -0,0 +1,79 @@
+#include <Arduino.h>
+// --------------------------------------
+// i2c_scanner
+//
+// Version 1
+// This program (or code that looks like it)
+// can be found in many places.
+// For example on the Arduino.cc forum.
+// The original author is not known.
+// Version 2, Juni 2012, Using Arduino 1.0.1
+// Adapted to be as simple as possible by Arduino.cc user Krodal
+// Version 3, Feb 26 2013
+// V3 by louarnold
+// Version 4, March 3, 2013, Using Arduino 1.0.3
+// by Arduino.cc user Krodal.
+// Changes by louarnold removed.
+// Scanning addresses changed from 0...127 to 1...119,
+// according to the i2c scanner by Nick Gammon
+// https://www.gammon.com.au/forum/?id=10896
+// Version 5, March 28, 2013
+// As version 4, but address scans now to 127.
+// A sensor seems to use address 120.
+// Version 6, November 27, 2015.
+// Added waiting for the Leonardo serial communication.
+//
+//
+// This sketch tests the standard 7-bit addresses
+// Devices with higher bit address might not be seen properly.
+//
+
+#include <Wire.h>
+
+void setup();
+void loop();
+void setup() {
+ Wire.begin();
+
+ Serial.begin(1152000);
+ while (!Serial); // Leonardo: wait for Serial Monitor
+ Serial.println("\nI2C Scanner");
+}
+
+void loop() {
+ int nDevices = 0;
+
+ Serial.println("Scanning...");
+
+ for (byte address = 1; address < 127; ++address) {
+ // The i2c_scanner uses the return value of
+ // the Wire.endTransmission to see if
+ // a device did acknowledge to the address.
+ Wire.beginTransmission(address);
+ byte error = Wire.endTransmission();
+
+ if (error == 0) {
+ Serial.print("I2C device found at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.print(address, HEX);
+ Serial.println(" !");
+
+ ++nDevices;
+ } else if (error == 4) {
+ Serial.print("Unknown error at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.println(address, HEX);
+ }
+ }
+ if (nDevices == 0) {
+ Serial.println("No I2C devices found\n");
+ } else {
+ Serial.println("done\n");
+ }
+ delay(5000); // Wait 5 seconds for next scan
+}
+
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
new file mode 100644
index 0000000..98948a9
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -0,0 +1,538 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><Wire><i2c_scanner> ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 29th July 2022, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "i2c_slave_model.v"
+
+module arduino_i2c_scaner_tb;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+ reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+ reg [31:0] check_sum ;
+
+ integer d_risc_id;
+
+ integer i,j;
+
+
+
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ flag = 0;
+ compare_start = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(3, arduino_i2c_scaner_tb);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.i_core_top_0);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_connect);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_i2cm);
+ end
+ `endif
+
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
+ initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 2000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
+ check_sum = 0;
+ compare_start = 1;
+
+ fork
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
+ end
+ end
+ end
+ begin
+ repeat (200000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
+
+ $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+ // Check
+ // if all the 102 byte received
+ // if no error
+ if(uart_rx_nu != 102) test_fail = 1;
+ if(check_sum != 32'h1fab) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Standalone String (GL) Passed");
+ `else
+ $display("Monitor: Standalone String (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Standalone String (GL) Failed");
+ `else
+ $display("Monitor: Standalone String (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('1) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+//---------------------------
+// I2C
+// --------------------------
+tri scl,sda;
+
+assign sda = (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz;
+assign scl = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz;
+assign io_in[22] = sda;
+assign io_in[23] = scl;
+
+pullup p1(scl); // pullup scl line
+pullup p2(sda); // pullup sda line
+
+
+i2c_slave_model #(.I2C_ADR(7'h4)) u_i2c_slave (
+ .scl (scl),
+ .sda (sda)
+ );
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[29];
+ wire #1 io_oeb_30 = io_oeb[30];
+ wire #1 io_oeb_31 = io_oeb[31];
+ wire #1 io_oeb_32 = io_oeb[32];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+ assign io_in[29] = flash_io0;
+ assign io_in[30] = flash_io1;
+ assign io_in[31] = flash_io2;
+ assign io_in[32] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("arduino_i2c_scaner.ino.hex"),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/arduino_string/Makefile b/verilog/dv/arduino_string/Makefile
new file mode 100644
index 0000000..78fc16e
--- /dev/null
+++ b/verilog/dv/arduino_string/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_string
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_string/arduino_string.ino b/verilog/dv/arduino_string/arduino_string.ino
new file mode 100644
index 0000000..3a4ea08
--- /dev/null
+++ b/verilog/dv/arduino_string/arduino_string.ino
@@ -0,0 +1,28 @@
+void setup() {
+ String my_str = "This is my string.";
+
+ Serial.begin(9600);
+
+ // (1) print the string
+ Serial.println(my_str);
+
+ // (2) change the string to upper-case
+ my_str.toUpperCase();
+ Serial.println(my_str);
+
+ // (3) overwrite the string
+ my_str = "My new string.";
+ Serial.println(my_str);
+
+ // (4) replace a word in the string
+ my_str.replace("string", "Arduino sketch");
+ Serial.println(my_str);
+
+ // (5) get the length of the string
+ Serial.print("String length is: ");
+ Serial.println(my_str.length());
+}
+
+void loop() {
+}
+
diff --git a/verilog/dv/arduino_string/arduino_string.ino.cpp b/verilog/dv/arduino_string/arduino_string.ino.cpp
new file mode 100644
index 0000000..6cdd523
--- /dev/null
+++ b/verilog/dv/arduino_string/arduino_string.ino.cpp
@@ -0,0 +1,32 @@
+#include <Arduino.h>
+void setup();
+void loop();
+void setup() {
+ String my_str = "This is my string.";
+
+ Serial.begin(1152000);
+
+ // (1) print the string
+ Serial.println(my_str);
+
+ // (2) change the string to upper-case
+ my_str.toUpperCase();
+ Serial.println(my_str);
+
+ // (3) overwrite the string
+ my_str = "My new string.";
+ Serial.println(my_str);
+
+ // (4) replace a word in the string
+ my_str.replace("string", "Arduino sketch");
+ Serial.println(my_str);
+
+ // (5) get the length of the string
+ Serial.print("String length is: ");
+ Serial.println(my_str.length());
+}
+
+void loop() {
+}
+
+
diff --git a/verilog/dv/arduino_string/arduino_string_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v
new file mode 100644
index 0000000..8fabb59
--- /dev/null
+++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -0,0 +1,517 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><04.Communication><String> ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 29th July 2022, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+
+module arduino_string_tb;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+ reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+ reg [31:0] check_sum ;
+
+ integer d_risc_id;
+
+ integer i,j;
+
+
+
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ flag = 0;
+ compare_start = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(3, arduino_string_tb);
+ $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.i_core_top_0);
+ $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_connect);
+ $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_string_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+ end
+ `endif
+
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
+ initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 20000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ repeat (60000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
+ check_sum = 0;
+ compare_start = 1;
+
+ fork
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
+ end
+ end
+ end
+ begin
+ repeat (200000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
+
+ $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+ // Check
+ // if all the 102 byte received
+ // if no error
+ if(uart_rx_nu != 102) test_fail = 1;
+ if(check_sum != 32'h1fab) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Standalone String (GL) Passed");
+ `else
+ $display("Monitor: Standalone String (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Standalone String (GL) Failed");
+ `else
+ $display("Monitor: Standalone String (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('1) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[29];
+ wire #1 io_oeb_30 = io_oeb[30];
+ wire #1 io_oeb_31 = io_oeb[31];
+ wire #1 io_oeb_32 = io_oeb[32];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+ assign io_in[29] = flash_io0;
+ assign io_in[30] = flash_io1;
+ assign io_in[31] = flash_io2;
+ assign io_in[32] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("arduino_string.ino.hex"),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/bfm/bfm_ad5205.sv b/verilog/dv/bfm/bfm_ad5205.sv
new file mode 100644
index 0000000..d2ea131
--- /dev/null
+++ b/verilog/dv/bfm/bfm_ad5205.sv
@@ -0,0 +1,28 @@
+module bfm_ad5205 (
+ input logic sck ,
+ input logic sdi ,
+ input logic ssn ,
+
+ output logic [2:0] channel ,
+ output logic [7:0] position
+ );
+
+
+logic [10:0] shift_reg;
+logic [10:0] load_reg;
+
+
+always @(posedge ssn)
+ load_reg = shift_reg;
+
+
+always @(posedge sck)
+ shift_reg = {shift_reg[9:0],sdi};
+
+
+assign channel = load_reg[10:8];
+assign position = load_reg[7:0];
+
+
+endmodule
+
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board
index ffeb01c..bb4bce2 160000
--- a/verilog/dv/common/riscduino_board
+++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@
-Subproject commit ffeb01ccee8845842c3195b9cd877e2b2fe3377f
+Subproject commit bb4bce23c19c97fa80f57f89a4a6f023f5d38d95
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 463ee91..e5fea15 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -278,8 +278,8 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2007_2022);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_8000);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0508_2022);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_9000);
end
diff --git a/verilog/dv/user_i2cm/user_uart.c b/verilog/dv/user_i2cm/user_uart.c
deleted file mode 100644
index b86f23b..0000000
--- a/verilog/dv/user_i2cm/user_uart.c
+++ /dev/null
@@ -1,42 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021, Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
-// //////////////////////////////////////////////////////////////////////////
-#define SC_SIM_OUTPORT (0xf0000000)
-#define uint32_t long
-
-#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x30010000)
-#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x30010004)
-#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x30010008)
-#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x3001000C)
-#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x30010010)
-#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x30010014)
-#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x30010018)
-#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x3001001C)
-#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x30010020)
-
-int main()
-{
-
- while(1) {
- // Check UART RX fifo has data, if available loop back the data
- if(reg_mprj_uart_reg8 != 0) {
- reg_mprj_uart_reg5 = reg_mprj_uart_reg6;
- }
- }
-
- return 0;
-}
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index d803dab..2fce71e 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -45,6 +45,7 @@
-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv
-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv
-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_clkgen.sv
-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 32b812a..6c88ca7 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -716,7 +716,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h2007_2022) u_reg_23 (
+gen_32b_reg #(32'h0508_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -729,9 +729,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 4.7 = 0004800
+// Software Reg-3: Poject Revison 4.9 = 0004900
// ----------------------------------------
-gen_32b_reg #(32'h0004_8000) u_reg_24 (
+gen_32b_reg #(32'h0004_9000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/sspim/src/sspim_cfg.sv b/verilog/rtl/sspim/src/sspim_cfg.sv
index e849f81..cc81df0 100755
--- a/verilog/rtl/sspim/src/sspim_cfg.sv
+++ b/verilog/rtl/sspim/src/sspim_cfg.sv
@@ -46,17 +46,28 @@
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
+/*******************************************************************
+SPI Mode:
+ Mode 0 (the default)− Clock is normally low (CPOL = 0), and Data sampled on rising edge and shifted out on the falling edge. (CPHA = 0). - Supported
+ Mode 1 − Clock is normally low (CPOL = 0), and Data sampled on the falling edge and shifted out on the rising edge. (CPHA = 1). - Not Supported
+ Mode 2 − Clock is normally high (CPOL = 1), and Data sampled on the rising edge and shifted out on the falling edge. (CPHA = 0). - Supported
+ Mode 3 − Clock is normally high (CPOL = 1), and Data sampled on the falling edge and shifted out on the rising edge (CPHA = 1). - Not Supported
+********************************************************************/
+
module sspim_cfg (
input logic mclk ,
input logic reset_n ,
output logic [1:0] cfg_tgt_sel ,
-
+
+ output logic cfg_cpol , // spi clock idle phase
+ output logic cfg_cpha , // spi data sample and lanch phase
+ output logic cfg_bit_order , // SPI TX/RX Bit Order, 1 -> LSBFIRST or 0 -> MSBFIRST
output logic cfg_op_req , // SPI operation request
- output logic cfg_endian , // Endian selection
+ output logic cfg_endian , // Endian selection
output logic [1:0] cfg_op_type , // SPI operation type
output logic [1:0] cfg_transfer_size , // SPI transfer size
output logic [5:0] cfg_sck_period , // sck clock period
@@ -98,6 +109,7 @@
logic [31:0] reg_1; // Software-Reg_1
logic [31:0] reg_2; // Software-Reg_2
logic [31:0] reg_out;
+logic [1:0] cfg_spi_mode;
//-----------------------------------------------------------------------
// Main code starts here
@@ -168,7 +180,13 @@
//-----------------------------------------------------------------------
// Logic for Register 0 : SPI Control Register
//-----------------------------------------------------------------------
+
+assign cfg_cpha = cfg_spi_mode[0];
+assign cfg_cpol = cfg_spi_mode[1];
+
assign cfg_op_req = reg_0[31]; // cpu request
+assign cfg_bit_order = reg_0[28]; // 1 -> LSBFIRST or 0 -> MSBFIRST
+assign cfg_spi_mode = reg_0[27:26]; // spi mode
assign cfg_endian = reg_0[25]; // Endian, 0 - little, 1 - Big
assign cfg_tgt_sel = reg_0[24:23]; // target chip select
assign cfg_op_type = reg_0[22:21]; // SPI operation type
@@ -210,18 +228,17 @@
.data_out (reg_0[23:16] )
);
-generic_register #(2,0 ) u_spi_ctrl_be3 (
- .we ({2{sw_wr_en_0 &
+generic_register #(7,0 ) u_spi_ctrl_be3 (
+ .we ({7{sw_wr_en_0 &
wr_be[3] }} ),
- .data_in (reg_wdata[25:24] ),
+ .data_in (reg_wdata[30:24] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
- .data_out (reg_0[25:24] )
+ .data_out (reg_0[30:24] )
);
-assign reg_0[30:26] = 5'h0;
req_register #(0 ) u_spi_ctrl_req (
.cpu_we ({sw_wr_en_0 &
diff --git a/verilog/rtl/sspim/src/sspim_clkgen.sv b/verilog/rtl/sspim/src/sspim_clkgen.sv
new file mode 100755
index 0000000..bb1a8b4
--- /dev/null
+++ b/verilog/rtl/sspim/src/sspim_clkgen.sv
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Single SPI Master Interface Module ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// SPI Clock Gen module ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// V.0 - 06 Oct 2021 ////
+//// Initial SpI Module picked from ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/*********************************************************************
+ Design Implementation Reference
+ Reference: https://www.allaboutcircuits.com/technical-articles/spi-serial-peripheral-interface/
+*********************************************************************/
+
+
+module sspim_clkgen
+ (
+ input logic clk,
+ input logic reset_n,
+ input logic cfg_op_req,
+ input logic cfg_cpol, // CPOL : clock polarity CPOL :0- Clock Idle state low, 1 - Clock idle state high
+ input logic cfg_cpha, // CPHA : Clock Phase
+
+ input logic [5:0] cfg_sck_period,
+
+ input logic sck_active,
+
+ output logic sck_int, // SCLK
+ output logic shift, // Data Shift Phase
+ output logic sample, // Data Sample Phase
+ output logic sck_ne, // sclk negative phase
+ output logic sck_pe // sclk positive phase
+
+ );
+
+ //*************************************************************************
+
+
+ logic [5:0] clk_cnt;
+ logic [5:0] sck_half_period;
+
+
+
+ assign sck_ne = (cfg_cpha == 0) ? shift : sample;
+ assign sck_pe = (cfg_cpha == 0) ? sample : shift;
+
+ assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
+ // The first transition on the sck_toggle happens one SCK period
+ // after op_en or boot_en is asserted
+ always @(posedge clk or negedge reset_n) begin
+ if(!reset_n) begin
+ shift <= 1'b0;
+ sample <= 1'b0;
+ clk_cnt <= 6'h0;
+ sck_int <= 1'b1;
+ end // if (!reset_n)
+ else
+ begin
+ if(cfg_op_req)
+ begin
+ // clock counter
+ if(clk_cnt == cfg_sck_period) begin
+ clk_cnt <= 'h0;
+ end else begin
+ clk_cnt <= clk_cnt + 1'b1;
+ end
+
+ if(clk_cnt == sck_half_period)
+ begin
+ shift <= 1'b1;
+ sample <= 1'b0;
+ end // if (clk_cnt == sck_half_period)
+ else
+ begin
+ if(clk_cnt == cfg_sck_period)
+ begin
+ shift <= 1'b0;
+ sample <= 1'b1;
+ end // if (clk_cnt == cfg_sck_period)
+ else
+ begin
+ shift <= 1'b0;
+ sample <= 1'b0;
+ end // else: !if(clk_cnt == cfg_sck_period)
+ end // else: !if(clk_cnt == sck_half_period)
+ end // if (op_en)
+ else
+ begin
+ clk_cnt <= 6'h0;
+ shift <= 1'b0;
+ sample <= 1'b0;
+ end // else: !if(op_en)
+
+
+ if(sck_active) begin
+ if(sck_ne) sck_int <= 0;
+ else if(sck_pe) sck_int <= 1;
+ end else if (cfg_cpol == 0) begin // CPOL :0- Clock Idle state low
+ sck_int <= 0;
+ end else begin // CPOL :1- Clock Idle state High
+ sck_int <= 1;
+ end
+ end // else: !if(!reset_n)
+ end // always @ (posedge clk or negedge reset_n)
+
+
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_ctl.sv b/verilog/rtl/sspim/src/sspim_ctl.sv
index ea6aa1f..25971e0 100755
--- a/verilog/rtl/sspim/src/sspim_ctl.sv
+++ b/verilog/rtl/sspim/src/sspim_ctl.sv
@@ -52,25 +52,24 @@
(
input logic clk,
input logic reset_n,
+ input logic cfg_cpol,
input logic cfg_op_req,
input logic cfg_endian,
input logic [1:0] cfg_op_type,
input logic [1:0] cfg_transfer_size,
+ input logic [4:0] cfg_sck_cs_period,
- input logic [5:0] cfg_sck_period,
- input logic [4:0] cfg_sck_cs_period, // cs setup & hold period
input logic [7:0] cfg_cs_byte,
input logic [31:0] cfg_datain,
output logic [31:0] cfg_dataout,
output logic [7:0] byte_out, // Byte out for Serial Shifting out
input logic [7:0] byte_in, // Serial Received Byte
- output logic sck_int,
output logic cs_int_n,
- output logic sck_pe,
- output logic sck_ne,
- output logic shift_out,
- output logic shift_in,
+ input logic shift,
+ input logic sample,
+
+ output logic sck_active,
output logic load_byte,
output logic op_done
@@ -80,74 +79,25 @@
parameter LITTLE_ENDIAN = 1'b0;
parameter BIG_ENDIAN = 1'b1;
+
+ parameter SPI_WR = 2'b00;
+ parameter SPI_RD = 2'b01;
+ parameter SPI_WR_RD = 2'b10;
- logic [5:0] clk_cnt;
logic [5:0] sck_cnt;
logic [3:0] spiif_cs;
- logic shift_enb;
- logic clr_sck_cnt ;
- logic sck_out_en;
- logic [5:0] sck_half_period;
logic [2:0] byte_cnt;
`define SPI_IDLE 4'b0000
`define SPI_CS_SU 4'b0001
- `define SPI_WRITE 4'b0010
- `define SPI_READ 4'b0011
- `define SPI_CS_HLD 4'b0100
- `define SPI_WAIT 4'b0101
+ `define SPI_DATA 4'b0010
+ `define SPI_CS_HLD 4'b0011
+ `define SPI_WAIT 4'b0100
- assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
- // The first transition on the sck_toggle happens one SCK period
- // after op_en or boot_en is asserted
- always @(posedge clk or negedge reset_n) begin
- if(!reset_n) begin
- sck_ne <= 1'b0;
- clk_cnt <= 6'h1;
- sck_pe <= 1'b0;
- sck_int <= 1'b0;
- end // if (!reset_n)
- else
- begin
- if(cfg_op_req)
- begin
- if(clk_cnt == sck_half_period)
- begin
- sck_ne <= 1'b1;
- sck_pe <= 1'b0;
- if(sck_out_en) sck_int <= 0;
- clk_cnt <= clk_cnt + 1'b1;
- end // if (clk_cnt == sck_half_period)
- else
- begin
- if(clk_cnt == cfg_sck_period)
- begin
- sck_ne <= 1'b0;
- sck_pe <= 1'b1;
- if(sck_out_en) sck_int <= 1;
- clk_cnt <= 6'h1;
- end // if (clk_cnt == cfg_sck_period)
- else
- begin
- clk_cnt <= clk_cnt + 1'b1;
- sck_pe <= 1'b0;
- sck_ne <= 1'b0;
- end // else: !if(clk_cnt == cfg_sck_period)
- end // else: !if(clk_cnt == sck_half_period)
- end // if (op_en)
- else
- begin
- clk_cnt <= 6'h1;
- sck_pe <= 1'b0;
- sck_ne <= 1'b0;
- end // else: !if(op_en)
- end // else: !if(!reset_n)
- end // always @ (posedge clk or negedge reset_n)
-
wire [1:0] cs_data = (byte_cnt == 2'b00) ? cfg_cs_byte[7:6] :
(byte_cnt == 2'b01) ? cfg_cs_byte[5:4] :
@@ -162,104 +112,72 @@
(byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0]) ;
-assign shift_out = shift_enb && sck_ne;
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
spiif_cs <= `SPI_IDLE;
sck_cnt <= 6'h0;
- shift_in <= 1'b0;
- clr_sck_cnt <= 1'b1;
byte_cnt <= 2'b00;
cs_int_n <= 1'b1;
- sck_out_en <= 1'b0;
- shift_enb <= 1'b0;
cfg_dataout <= 32'h0;
load_byte <= 1'b0;
+ sck_active <= 1'b0;
end
else begin
- if(sck_ne)
- sck_cnt <= clr_sck_cnt ? 6'h0 : sck_cnt + 1 ;
-
case(spiif_cs)
`SPI_IDLE :
begin
+ sck_active <= 1'b0;
+ load_byte <= 1'b0;
op_done <= 0;
- clr_sck_cnt <= 1'b1;
- sck_out_en <= 1'b0;
- shift_enb <= 1'b0;
if(cfg_op_req)
begin
cfg_dataout <= 32'h0;
spiif_cs <= `SPI_CS_SU;
- end
- else begin
+ end else begin
spiif_cs <= `SPI_IDLE;
end
end
`SPI_CS_SU :
begin
- if(sck_ne) begin
+ if(shift) begin
cs_int_n <= cs_data[1];
if(sck_cnt == cfg_sck_cs_period) begin
- clr_sck_cnt <= 1'b1;
- if(cfg_op_type == 0) begin // Write Mode
+ sck_cnt <= 'h0;
+ if((cfg_op_type == SPI_WR) || (cfg_op_type == SPI_WR_RD )) begin // Write Mode
load_byte <= 1'b1;
- spiif_cs <= `SPI_WRITE;
- shift_enb <= 1'b0;
- end else begin
- shift_in <= 1;
- spiif_cs <= `SPI_READ;
- end
- end
- else begin
- clr_sck_cnt <= 1'b0;
- end
+ end
+ spiif_cs <= `SPI_DATA;
+ end else begin
+ sck_cnt <= sck_cnt + 1 ;
+ end
end
end
- `SPI_WRITE :
+ `SPI_DATA :
begin
load_byte <= 1'b0;
- if(sck_ne) begin
- if(sck_cnt == 3'h7 )begin
- clr_sck_cnt <= 1'b1;
- spiif_cs <= `SPI_CS_HLD;
- shift_enb <= 1'b0;
- sck_out_en <= 1'b0; // Disable clock output
- end
- else begin
- shift_enb <= 1'b1;
- sck_out_en <= 1'b1;
- clr_sck_cnt <= 1'b0;
- end
- end else begin
- shift_enb <= 1'b1;
- end
- end
-
- `SPI_READ :
- begin
- if(sck_ne) begin
- if( sck_cnt == 3'h7 ) begin
- clr_sck_cnt <= 1'b1;
- shift_in <= 0;
- spiif_cs <= `SPI_CS_HLD;
- sck_out_en <= 1'b0; // Disable clock output
- end
- else begin
- sck_out_en <= 1'b1; // Disable clock output
- clr_sck_cnt <= 1'b0;
- end
+ if((shift && (cfg_cpol == 1)) || (sample && (cfg_cpol == 0)) ) begin
+ sck_active <= 1'b1;
+ end else if((sample && (cfg_cpol == 1)) || (shift && (cfg_cpol == 0)) ) begin
+ if(sck_cnt == 4'h8 )begin
+ sck_active <= 1'b0;
+ sck_cnt <= 'h0;
+ spiif_cs <= `SPI_CS_HLD;
+ end
+ else begin
+ sck_active <= 1'b1;
+ sck_cnt <= sck_cnt + 1 ;
+ end
end
end
`SPI_CS_HLD : begin
- if(sck_ne) begin
+ if(shift) begin
cs_int_n <= cs_data[0];
if(sck_cnt == cfg_sck_cs_period) begin
- if(cfg_op_type == 1) begin // Read Mode
+ if((cfg_op_type == SPI_RD) || (cfg_op_type == SPI_WR_RD)) begin // Read Mode
cfg_dataout <= (cfg_endian == LITTLE_ENDIAN) ?
((byte_cnt[1:0] == 2'b00) ? { cfg_dataout[31:8],byte_in } :
(byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } :
@@ -270,7 +188,7 @@
(byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } :
{ cfg_dataout[31:8],byte_in}) ;
end
- clr_sck_cnt <= 1'b1;
+ sck_cnt <= 'h0;
if(byte_cnt == cfg_transfer_size) begin
spiif_cs <= `SPI_WAIT;
byte_cnt <= 0;
@@ -281,7 +199,7 @@
end
end
else begin
- clr_sck_cnt <= 1'b0;
+ sck_cnt <= sck_cnt + 1 ;
end
end
end // case: `SPI_CS_HLD
diff --git a/verilog/rtl/sspim/src/sspim_if.sv b/verilog/rtl/sspim/src/sspim_if.sv
index 42b18f2..ece9ffd 100755
--- a/verilog/rtl/sspim/src/sspim_if.sv
+++ b/verilog/rtl/sspim/src/sspim_if.sv
@@ -47,24 +47,25 @@
module sspim_if
(
- input logic clk,
- input logic reset_n,
- input logic sck_pe,
- input logic sck_int,
- input logic cs_int_n,
+ input logic clk,
+ input logic reset_n,
+ input logic sck_int,
+ input logic cs_int_n,
+ input logic cfg_bit_order, // 1 -> LSBFIRST or 0 -> MSBFIRST
input logic load_byte,
input logic [1:0] cfg_tgt_sel,
input logic [7:0] byte_out,
- input logic shift_out,
- input logic shift_in,
+ input logic sck_active,
+ input logic shift,
+ input logic sample,
- output logic [7:0] byte_in,
- output logic sck,
- output logic so,
- output logic [3:0] cs_n,
- input logic si
+ output logic [7:0]byte_in,
+ output logic sck,
+ output logic so,
+ output logic [3:0]cs_n,
+ input logic si
);
@@ -73,6 +74,9 @@
logic [7:0] si_reg;
+ wire shift_out = shift & sck_active;
+ wire sample_in = sample & sck_active;
+
//Output Shift Register
always @(posedge clk or negedge reset_n) begin
@@ -86,13 +90,19 @@
if(shift_out) begin
// Handling backto back case :
// Last Transfer bit + New Trasfer Load
- so <= so_reg[7];
+ if(cfg_bit_order) so <= so_reg[0]; // LSB FIRST
+ else so <= so_reg[7]; // MSB FIRST
end
end // if (load_byte)
else begin
if(shift_out) begin
- so <= so_reg[7];
- so_reg <= {so_reg[6:0],1'b0};
+ if(cfg_bit_order) begin // LSB FIRST
+ so <= so_reg[0];
+ so_reg <= {1'b0,so_reg[7:1]};
+ end else begin
+ so <= so_reg[7];
+ so_reg <= {so_reg[6:0],1'b0};
+ end
end // if (shift_out)
end // else: !if(load_byte)
end // else: !if(!reset_n)
@@ -103,11 +113,14 @@
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
si_reg <= 8'h0;
- end
- else begin
- if(sck_pe & shift_in) begin
- si_reg[7:0] <= {si_reg[6:0],si};
- end // if (sck_pe & shift_in)
+ end else begin
+ if(sample_in) begin
+ if(cfg_bit_order) begin // LSB FIRST
+ si_reg[7:0] <= {si,si_reg[7:1]};
+ end else begin // MSB FIRST
+ si_reg[7:0] <= {si_reg[6:0],si};
+ end
+ end // if (sample_in)
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
index 2a28d2e..6f0f17f 100755
--- a/verilog/rtl/sspim/src/sspim_top.sv
+++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -46,6 +46,9 @@
//// out is big endian, i.e bit[7],[6] ..[0] ////
//// 0.3 - April 6, 2022, Dinesh A ////
//// Four chip select are driven out ////
+//// 0.4 - Aug 5, 2022, Dinesh A ////
+//// A. SPI Mode 0 to 3 support added, ////
+//// B. SPI Duplex mode TX-RX Mode added ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -125,54 +128,81 @@
logic [31:0] cfg_datain ; // data for transfer
logic [31:0] cfg_dataout ; // data for received
logic hware_op_done ; // operation done
-
+logic cfg_bit_order ; // Bit order 1 -> LSBFIRST or 0 -> MSBFIRST
+logic cfg_cpol ; // spi clock idle phase
+logic cfg_cpha ; // spi data sample and lanch phase
sspim_if u_spi_if
(
. clk (clk ),
. reset_n (reset_n ),
- // towards ctrl i/f
- . sck_pe (sck_pe ),
+ // cfg
+ . cfg_bit_order (cfg_bit_order ),
+ . cfg_tgt_sel (cfg_tgt_sel ),
+
+ // clkgen
+ . shift (shift ),
+ . sample (sample ),
. sck_int (sck_int ),
+
+ // towards ctrl i/f
+ . sck_active (sck_active ),
. cs_int_n (cs_int_n ),
. byte_in (byte_in ),
. load_byte (load_byte ),
. byte_out (byte_out ),
- . shift_out (shift_out ),
- . shift_in (shift_in ),
- . cfg_tgt_sel (cfg_tgt_sel ),
-
+ // External I/F
. sck (sck ),
. so (so ),
. si (si ),
. cs_n (ssn )
);
+sspim_clkgen u_clkgen
+ (
+ . clk (clk ),
+ . reset_n (reset_n ),
+
+ // cfg
+ . cfg_cpol (cfg_cpol ),
+ . cfg_cpha (cfg_cpha ),
+ . cfg_sck_period (cfg_sck_period ),
+ . cfg_op_req (cfg_op_req ),
+
+ // ctrl
+ . sck_active (sck_active ),
+
+ . sck_int (sck_int ),
+ . shift (shift ),
+ . sample (sample ),
+ . sck_ne (),
+ . sck_pe ()
+
+ );
sspim_ctl u_spi_ctrl
(
. clk (clk ),
. reset_n (reset_n ),
+ // cfg
+ . cfg_cpol (cfg_cpol ),
. cfg_op_req (cfg_op_req ),
. cfg_endian (cfg_endian ),
. cfg_op_type (cfg_op_type ),
. cfg_transfer_size (cfg_transfer_size ),
- . cfg_sck_period (cfg_sck_period ),
. cfg_sck_cs_period (cfg_sck_cs_period ),
. cfg_cs_byte (cfg_cs_byte ),
. cfg_datain (cfg_datain ),
. cfg_dataout (cfg_dataout ),
. op_done (hware_op_done ),
- . sck_int (sck_int ),
+ . sck_active (sck_active ),
. cs_int_n (cs_int_n ),
- . sck_pe (sck_pe ),
- . sck_ne (sck_ne ),
- . shift_out (shift_out ),
- . shift_in (shift_in ),
+ . shift (shift ),
+ . sample (sample ),
. load_byte (load_byte ),
. byte_out (byte_out ),
. byte_in (byte_in )
@@ -200,6 +230,9 @@
// configuration signal
+ . cfg_cpol (cfg_cpol ),
+ . cfg_cpha (cfg_cpha ),
+ . cfg_bit_order (cfg_bit_order ),
. cfg_tgt_sel (cfg_tgt_sel ),
. cfg_op_req (cfg_op_req ), // SPI operation request
. cfg_endian (cfg_endian ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0800fb9..5cd9e0c 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -221,6 +221,10 @@
//// SPI ISP boot option added in wb_host, spi slave uses ////
//// same spi master interface, but will be active only ////
//// when internal SPI config disabled + RESET PIN = 0 ////
+//// 4.9 Aug 5 2022, Dinesh A ////
+//// changes in sspim ////
+//// A. SPI Mode 0 to 3 support added, ////
+//// B. SPI Duplex mode TX-RX Mode added ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
