Precheck fix for feol and consistancy
diff --git a/Makefile b/Makefile index 9eae04d..2090a6a 100644 --- a/Makefile +++ b/Makefile
@@ -327,3 +327,11 @@ @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow @echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/" + +#Added by Dinesh-A for Klayout Based DRC check +.PHONY: run-drc +run-drc: + @echo "run kalyout DRC checks" + mkdir -p signoff/user_project_wrapper/openlane-signoff/drc + docker run -ti --rm -v $(PROJECT_ROOT):/project riscduino/openlane:mpw7 sh -c "cd /project && ./scripts/klayout_drc.sh user_project_wrapper " +
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index f69ee1b..9bfe51c 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index 5a1770e..c15d4f1 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/openlane/Makefile b/openlane/Makefile index 3c48c94..c21989a 100644 --- a/openlane/Makefile +++ b/openlane/Makefile
@@ -43,15 +43,29 @@ @sleep 1 @if [ -f ./$*/interactive.tcl ]; then\ - docker run --rm \ + docker run --rm -v $(OPENLANE_ROOT):/openlane \ + -v $(PDK_ROOT):$(PDK_ROOT) \ -v $(PWD)/..:$(PWD)/.. \ + -v $(MCW_ROOT):$(MCW_ROOT) \ + -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ + -e MCW_ROOT=$(MCW_ROOT) \ + -e PDK_ROOT=$(PDK_ROOT) \ + -e CARAVEL_ROOT=$(CARAVEL_ROOT) \ + -e PDK=$(PDK) \ -e TEST_MISMATCHES=tools \ -e MISMATCHES_OK=1 \ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\ else\ - docker run --rm \ + docker run --rm -v $(OPENLANE_ROOT):/openlane \ + -v $(PDK_ROOT):$(PDK_ROOT) \ -v $(PWD)/..:$(PWD)/.. \ + -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ + -v $(MCW_ROOT):$(MCW_ROOT) \ + -e MCW_ROOT=$(MCW_ROOT) \ + -e PDK=$(PDK) \ + -e PDK_ROOT=$(PDK_ROOT) \ + -e CARAVEL_ROOT=$(CARAVEL_ROOT) \ -e TEST_MISMATCHES=tools \ -e MISMATCHES_OK=1 \ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
diff --git a/scripts/klayout_drc.sh b/scripts/klayout_drc.sh new file mode 100755 index 0000000..a29de15 --- /dev/null +++ b/scripts/klayout_drc.sh
@@ -0,0 +1,19 @@ +echo "################ Running Klayout FEOL ########################" +klayout -b -r '$PDK_ROOT/$PDK/libs.tech/klayout/drc/sky130A_mr.drc' -rd input=gds/$1.gds -rd report=/project/signoff/$1/openlane-signoff/drc/klayout_feol_check.xml -rd feol=true + +echo "################ Running Klayout BEOL ########################" +klayout -b -r '$PDK_ROOT/$PDK/libs.tech/klayout/drc/sky130A_mr.drc' -rd input=gds/$1.gds -rd report=/project/signoff/$1/openlane-signoff/drc/klayout_beol_check.xml -rd beol=true + +echo "################ Running Klayout Offgrid #####################" + klayout -b -r '$PDK_ROOT/$PDK/libs.tech/klayout/drc/sky130A_mr.drc' -rd input=gds/$1.gds -rd report=/project/signoff/$1/openlane-signoff/drc/klayout_offgrid_check.xml -rd offgrid=true + +echo "################ Klayout Metal Minimum Clear Area Density #####################" +klayout -b -r '$PDK_ROOT/$PDK/libs.tech/klayout/drc/met_min_ca_density.lydrc' -rd input=gds/$1.gds -rd report=/project/signoff/$1/openlane-signoff/drc/klayout_met_min_ca_density_check.xml + +echo "### Klayout Zero Area check command ####" +klayout -b -r '$PDK_ROOT/$PDK/libs.tech/klayout/drc/zeroarea.rb.drc' -rd input=gds/$1.gds -rd report=/project/signoff/$1/openlane-signoff/drc/klayout_zeroarea_check.xml -rd cleaned_output=outputs/dac_top_no_zero_areas.gds + +echo "## klayout_pin_label_purposes_overlapping_drawing_check" +klayout -b -r '$PDK_ROOT/$PDK/libs.tech/klayout/drc/pin_label_purposes_overlapping_drawing.rb.drc' -rd input=gds/$1.gds -rd report=/project/signoff/$1/openlane-signoff/drc/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=$1 +echo "You can find results for all corners in ./signoff/$1/openlane-signoff/drc/" +
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc index 7913d31..3a0fe8c 100644 --- a/sdc/user_project_wrapper.sdc +++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@ ############################################################################### # Created by write_sdc -# Thu Dec 8 16:36:06 2022 +# Fri Dec 9 15:55:05 2022 ############################################################################### current_design user_project_wrapper ###############################################################################
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION index 1234be5..1888caa 100644 --- a/signoff/user_project_wrapper/OPENLANE_VERSION +++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@ -OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483 +OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES index f8d3b3a..3b6c758 100644 --- a/signoff/user_project_wrapper/PDK_SOURCES +++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1 @@ -open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93 +open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz index f7ab685..d7543d3 100644 --- a/verilog/gl/user_project_wrapper.v.gz +++ b/verilog/gl/user_project_wrapper.v.gz Binary files differ
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index a2b6681..bad1917 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -1329,7 +1329,7 @@ .rst_n (cpu_intf_rst_n ), .cfg_cska (cfg_ccska_fpu_rp ), - .wbd_clk_int (cpu_clk_rp_fpu ), + .wbd_clk_int (cpu_clk_fpu ), .wbd_clk_out (cpu_clk_fpu_skew ), .dmem_req (fpu_dmem_req ),