pwm new rtl update
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master_test1/Makefile
similarity index 100%
rename from verilog/dv/uart_master/Makefile
rename to verilog/dv/uart_master_test1/Makefile
diff --git a/verilog/dv/uart_master/run_verilog b/verilog/dv/uart_master_test1/run_verilog
similarity index 100%
rename from verilog/dv/uart_master/run_verilog
rename to verilog/dv/uart_master_test1/run_verilog
diff --git a/verilog/dv/uart_master/uart_master.c b/verilog/dv/uart_master_test1/uart_master_test1.c
similarity index 100%
rename from verilog/dv/uart_master/uart_master.c
rename to verilog/dv/uart_master_test1/uart_master_test1.c
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master_test1/uart_master_test1_tb.v
similarity index 100%
rename from verilog/dv/uart_master/uart_master_tb.v
rename to verilog/dv/uart_master_test1/uart_master_test1_tb.v
diff --git a/verilog/rtl/gpio/src/gpio_dglicth.sv b/verilog/rtl/gpio/src/gpio_dglicth.sv
new file mode 100644
index 0000000..e843057
--- /dev/null
+++ b/verilog/rtl/gpio/src/gpio_dglicth.sv
@@ -0,0 +1,72 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// GPIO De-Glitch ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 13th Sept 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//
+
+
+module gpio_dglitch (
+ input logic reset_n,
+ input logic mclk,
+ input logic pulse_1us,
+ input logic cfg_mode, // 0 - 1 us, 1 - every system clock
+ input logic gpio_in,
+ output logic gpio_out
+ );
+
+logic [3:0] gpio_ss;
+logic gpio_reg;
+
+// Pass the input data , if there is no transition, else send old data
+assign gpio_out = ((gpio_ss[3] == gpio_ss[2]) && (gpio_ss[2] == gpio_ss[1])) ? gpio_ss[3] : gpio_reg;
+
+
+always@(negedge reset_n or posedge mclk)
+begin
+ if(reset_n == 1'b0) begin
+ gpio_ss <= 'h0;
+ gpio_reg <= 'h0;
+ end else begin
+ gpio_reg <= gpio_out;
+ if(cfg_mode == 1'b0) begin // De-glitch sampling at 1us pulse
+ if(pulse_1us) gpio_ss <= {gpio_ss[2:0],gpio_in};
+ end else begin // De-glitch on on every system clock
+ gpio_ss <= {gpio_ss[2:0],gpio_in};
+ end
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_intr.sv b/verilog/rtl/gpio/src/gpio_intr.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/gpio_intr.sv
rename to verilog/rtl/gpio/src/gpio_intr.sv
diff --git a/verilog/rtl/pinmux/src/gpio_reg.sv b/verilog/rtl/gpio/src/gpio_reg.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/gpio_reg.sv
rename to verilog/rtl/gpio/src/gpio_reg.sv
diff --git a/verilog/rtl/pinmux/src/gpio_top.sv b/verilog/rtl/gpio/src/gpio_top.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/gpio_top.sv
rename to verilog/rtl/gpio/src/gpio_top.sv
diff --git a/verilog/rtl/pinmux/src/pwm_reg.sv b/verilog/rtl/pinmux/src/pwm_blk_reg.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/pwm_reg.sv
rename to verilog/rtl/pinmux/src/pwm_blk_reg.sv
diff --git a/verilog/rtl/pwm/src/pwm.sv b/verilog/rtl/pwm/src/pwm.sv
new file mode 100644
index 0000000..df9cf3a
--- /dev/null
+++ b/verilog/rtl/pwm/src/pwm.sv
@@ -0,0 +1,271 @@
+
+//-------------------------------------------------------------------
+// PWM waveform period: 1000/((cfg_pwm_high+1) + (cfg_pwm_low+1))
+// For 1 Second with Duty cycle 50 = 1000/((499+1) + (499+1))
+// For 1 Second with 1ms On and 999ms Off = 1000/((0+1) + (998+1))
+// Timing Run's with 1 Milisecond pulse
+//-------------------------------------------------------------------
+
+module pwm(
+
+ input logic h_reset_n ,
+ input logic mclk ,
+
+ output logic pwm_wfm_o ,
+ output logic pwm_os_done ,
+ output logic pwm_ovflow_pe ,
+ output logic gpio_tgr ,
+
+ input logic [7:0] pad_gpio ,
+
+ input logic cfg_pwm_enb , // pwm operation enable
+ input logic [3:0] cfg_pwm_scale , // pwm clock scaling
+ input logic cfg_pwm_oneshot , // pwm OneShot mode
+ input logic cfg_pwm_frun , // pwm is free running
+ input logic cfg_pwm_gpio_enb , // pwm gpio based trigger
+ input logic cfg_pwm_gpio_edge , // pwm gpio based trigger edge
+ input logic [2:0] cfg_pwm_gpio_sel , // gpio Selection
+ input logic cfg_pwm_hold , // Hold data pwm data During pwm Disable
+ input logic cfg_pwm_inv , // invert output
+ input logic cfg_pwm_zeropd , // Reset on pmw_cnt match to period
+ input logic [1:0] cfg_pwm_mode , // pwm Pulse Generation mode
+ input logic cfg_comp0_center , // Compare cnt at comp0 center
+ input logic cfg_comp1_center , // Compare cnt at comp1 center
+ input logic cfg_comp2_center , // Compare cnt at comp2 center
+ input logic cfg_comp3_center , // Compare cnt at comp3 center
+ input logic [15:0] cfg_pwm_period , // pwm period
+ input logic [15:0] cfg_pwm_comp0 , // compare0
+ input logic [15:0] cfg_pwm_comp1 , // compare1
+ input logic [15:0] cfg_pwm_comp2 , // compare2
+ input logic [15:0] cfg_pwm_comp3 // compare3
+);
+
+logic [14:0] pwm_scnt ; // PWM Scaling counter
+logic [15:0] pwm_cnt ; // PWM counter
+logic cnt_trg ;
+logic pwm_wfm_i ;
+logic pwm_wfm_hold;
+logic comp0_match ;
+logic comp1_match ;
+logic comp2_match ;
+logic comp3_match ;
+logic gpio_fedge ; // GPIO first edge detection
+//--------------------------------
+// Counter Scaling
+// In GPIO mode, wait for first GPIO transition
+//--------------------------------
+
+always @(posedge mclk or negedge h_reset_n)
+begin
+ if ( ~h_reset_n ) begin
+ pwm_scnt <= 15'h0;
+ end else begin
+ if(cfg_pwm_enb) begin
+ if(gpio_tgr || (cfg_pwm_gpio_enb && !gpio_fedge)) begin
+ pwm_scnt <= 15'h0;
+ end else begin
+ pwm_scnt <= pwm_scnt + 1;
+ end
+ end else begin
+ pwm_scnt <= 15'h0;
+ end
+ end
+end
+
+//-----------------------------------------------------------------------------
+// pwm_scaling used to decide on the trigger event for the pwm_cnt
+// 0 ==> pwm_cnt increment every system cycle
+// 1 ==> 2^0 => pmw_cnt increase once in two system cycle
+// 15 ==>a 2^15 => pwm_cnt increase once in 32768 system cycle
+//-----------------------------------------------------------------------------
+
+always_comb
+begin
+ cnt_trg = 0;
+ case(cfg_pwm_scale)
+ 4'b0000: cnt_trg = 1;
+ 4'b0001: cnt_trg = pwm_scnt[0];
+ 4'b0010: cnt_trg = &pwm_scnt[1:0];
+ 4'b0011: cnt_trg = &pwm_scnt[2:0];
+ 4'b0100: cnt_trg = &pwm_scnt[3:0];
+ 4'b0101: cnt_trg = &pwm_scnt[4:0];
+ 4'b0110: cnt_trg = &pwm_scnt[5:0];
+ 4'b0111: cnt_trg = &pwm_scnt[6:0];
+ 4'b1000: cnt_trg = &pwm_scnt[7:0];
+ 4'b1001: cnt_trg = &pwm_scnt[8:0];
+ 4'b1010: cnt_trg = &pwm_scnt[9:0];
+ 4'b1011: cnt_trg = &pwm_scnt[10:0];
+ 4'b1100: cnt_trg = &pwm_scnt[11:0];
+ 4'b1101: cnt_trg = &pwm_scnt[12:0];
+ 4'b1110: cnt_trg = &pwm_scnt[13:0];
+ 4'b1111: cnt_trg = &pwm_scnt[14:0];
+ default: cnt_trg = 0;
+ endcase
+end
+
+//----------------------------------------------------------
+//Counter Overflow condition
+// 1. At Roll Over
+// 2. If compare on period enable, then at period
+//----------------------------------------------------------
+logic pwm_ovflow_l;
+wire pwm_ovflow = ((&pwm_cnt) | (cfg_pwm_zeropd && (pwm_cnt == cfg_pwm_period))) & cfg_pwm_enb;
+
+
+// overflow single cycle pos edge pulse
+assign pwm_ovflow_pe = (!pwm_ovflow_l & pwm_ovflow);
+
+// Don't generate PWM done at exact clash at gpio trigger, higer priority to gpio trigger
+assign pwm_os_done = (cfg_pwm_oneshot && !gpio_tgr) ? pwm_ovflow_pe : 1'b0;
+
+always @(posedge mclk or negedge h_reset_n)
+begin
+ if ( ~h_reset_n ) begin
+ pwm_cnt <= 16'h0;
+ pwm_ovflow_l <= 1'b0;
+ end else begin
+ pwm_ovflow_l <= pwm_ovflow;
+ if(cfg_pwm_enb) begin
+ if(gpio_tgr || (cfg_pwm_gpio_enb && !gpio_fedge)) begin
+ pwm_cnt <= 'h0;
+ end else if(cnt_trg) begin
+ if(pwm_ovflow) begin
+ pwm_cnt <= 'h0;
+ end else begin
+ pwm_cnt <= pwm_cnt + 1;
+ end
+ end
+ end else begin
+ pwm_cnt <= 16'h0;
+ end
+ end
+end
+
+//-----------------------------
+// compare-0 match logic generation
+//------------------------------
+
+always_comb begin
+ comp0_match = 0;
+ if(cfg_comp0_center)begin
+ comp0_match = (({16{pwm_cnt[15]}} ^ pwm_cnt) >= cfg_pwm_comp0);
+ end else begin
+ comp0_match = (pwm_cnt >= cfg_pwm_comp0);
+ end
+end
+
+//-----------------------------
+// compare-1 match logic generation
+//------------------------------
+always_comb begin
+ comp1_match = 0;
+ if(cfg_comp1_center)begin
+ comp1_match = (({16{pwm_cnt[15]}}^ pwm_cnt) >= cfg_pwm_comp1);
+ end else begin
+ comp1_match = (pwm_cnt >= cfg_pwm_comp1);
+ end
+end
+
+//-----------------------------
+// compare-2 match logic generation
+//------------------------------
+always_comb begin
+ comp2_match = 0;
+ if(cfg_comp2_center)begin
+ comp2_match = (({16{pwm_cnt[15]}} ^ pwm_cnt) >= cfg_pwm_comp2);
+ end else begin
+ comp2_match = (pwm_cnt >= cfg_pwm_comp2);
+ end
+end
+
+//-----------------------------
+// compare-3 match logic generation
+//------------------------------
+always_comb begin
+ comp3_match = 0;
+ if(cfg_comp3_center) begin
+ comp3_match = (({16{pwm_cnt[15]}} ^ pwm_cnt) >= cfg_pwm_comp3);
+ end else begin
+ comp3_match = (pwm_cnt >= cfg_pwm_comp3);
+ end
+end
+
+//---------------------------------------------
+// Consolidated pwm waform generation
+// based on pwm mode
+//---------------------------------------------
+
+always_comb begin
+ pwm_wfm_i = 0;
+ case(cfg_pwm_mode)
+ 2'b00: pwm_wfm_i = comp0_match;
+ 2'b01: pwm_wfm_i = comp0_match ^ comp1_match;
+ 2'b10: pwm_wfm_i = comp0_match ^ comp1_match ^ comp2_match;
+ 2'b11: pwm_wfm_i = comp0_match ^ comp1_match ^ comp2_match ^ comp3_match;
+ default: pwm_wfm_i=0;
+ endcase
+end
+
+//-----------------------------------------------
+// Holding the pwm waveform in active region
+//------------------------------------------------
+always @(posedge mclk or negedge h_reset_n)
+begin
+ if ( ~h_reset_n ) begin
+ pwm_wfm_hold <= 1'b0;
+ end else if(cfg_pwm_enb) begin
+ pwm_wfm_hold <= pwm_wfm_i;
+ end
+end
+
+//--------------------------------------------
+// Final Waveform output generation based
+// on pwm_hold and pwm_inv combination
+//--------------------------------------------
+always_comb begin
+ pwm_wfm_o = 0;
+ if(!cfg_pwm_enb && cfg_pwm_hold) begin
+ if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_hold;
+ else pwm_wfm_o = pwm_wfm_hold;
+ end else begin
+ if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_i;
+ pwm_wfm_o = pwm_wfm_i;
+ end
+end
+
+//----------------------------------------
+// GPIO Trigger Generation
+//----------------------------------------
+logic gpio_l;
+wire gpio = pad_gpio[cfg_pwm_gpio_sel];
+
+// GPIO Pos and Neg Edge Selection
+wire gpio_pe = (gpio & !gpio_l);
+wire gpio_ne = (!gpio & gpio_l);
+
+always @(posedge mclk or negedge h_reset_n)
+begin
+ if ( ~h_reset_n ) begin
+ gpio_l <= 1'b0;
+ gpio_fedge <= 1'b0;
+ gpio_tgr <= 1'b0;
+ end else begin
+ gpio_l <= gpio;
+ if(cfg_pwm_enb && cfg_pwm_gpio_enb) begin
+ if(cfg_pwm_gpio_edge) begin
+ gpio_tgr <= gpio_ne;
+ gpio_fedge <= 1'b1; // gpio first edge detect
+ end else begin
+ gpio_tgr <= gpio_pe;
+ gpio_fedge <= 1'b1;
+ end
+ end else begin
+ gpio_l <= 1'b0;
+ gpio_fedge <= 1'b0;
+ gpio_tgr <= 1'b0;
+ end
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/pwm/src/pwm_blk_reg.sv b/verilog/rtl/pwm/src/pwm_blk_reg.sv
new file mode 100644
index 0000000..450b580
--- /dev/null
+++ b/verilog/rtl/pwm/src/pwm_blk_reg.sv
@@ -0,0 +1,285 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// PWM Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//// 0.2 - 13th Sept 2022, Dinesh A ////
+//// Change Register to PWM Based ////
+//////////////////////////////////////////////////////////////////////
+//
+module pwm_blk_reg (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [1:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+ input logic cfg_pwm_enb , // PWM operation enable
+ input logic cfg_pwm_dupdate , // Disable Config update
+ input logic pwm_cfg_update , // Update the pwm config on roll-over or completion
+
+ output logic [3:0] cfg_pwm_scale , // clock scaling
+ output logic cfg_pwm_oneshot , // PWM OneShot mode
+ output logic cfg_pwm_frun , // PWM is free running
+ output logic cfg_pwm_gpio_enb , // PWM GPIO based trigger enable
+ output logic cfg_pwm_gpio_edge , // PWM GPIO based trigger edge
+ output logic [2:0] cfg_pwm_gpio_sel , // GPIO Selection
+ output logic cfg_pwm_hold , // Hold data PWM data During PWM Disable
+ output logic cfg_pwm_inv , // invert output
+ output logic cfg_pwm_zeropd , // Reset on pmw_cnt match to period
+ output logic [1:0] cfg_pwm_mode , // PWM Pulse Generation mode
+ output logic cfg_comp0_center , // Compare cnt at comp0 center
+ output logic cfg_comp1_center , // Compare cnt at comp1 center
+ output logic cfg_comp2_center , // Compare cnt at comp2 center
+ output logic cfg_comp3_center , // Compare cnt at comp3 center
+ output logic [15:0] cfg_pwm_period , // PWM period
+ output logic [15:0] cfg_pwm_comp0 , // compare0
+ output logic [15:0] cfg_pwm_comp1 , // compare1
+ output logic [15:0] cfg_pwm_comp2 , // compare2
+ output logic [15:0] cfg_pwm_comp3 // compare3
+
+ );
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [1:0] sw_addr ; // addressing 16 registers
+logic [31:0] sw_reg_wdata ;
+logic [3:0] sw_be ;
+
+logic [31:0] reg_out ;
+logic [31:0] reg_0 ; // CONFIG - Unused
+logic [31:0] reg_1 ; // PWM-REG-0
+logic [31:0] reg_2 ; // PWM-REG-1
+logic [31:0] reg_3 ; // PWM-REG-2
+logic [31:0] reg_4 ; // PWM-REG-3
+logic [31:0] reg_5 ; // PWM-REG-4
+logic [31:0] reg_6 ; // PWM-REG-5
+
+assign sw_addr = reg_addr;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign sw_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3);
+
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+//--------------------------------------------
+// PWM-0 Config
+//---------------------------------------------
+logic [31:0] pwm_cfg0;
+
+assign cfg_pwm_scale = pwm_cfg0[3:0];
+assign cfg_pwm_oneshot = pwm_cfg0[4];
+assign cfg_pwm_frun = pwm_cfg0[5];
+assign cfg_pwm_gpio_enb = pwm_cfg0[6];
+assign cfg_pwm_gpio_edge = pwm_cfg0[7];
+assign cfg_pwm_gpio_sel = pwm_cfg0[10:8];
+assign cfg_pwm_hold = pwm_cfg0[11];
+assign cfg_pwm_mode = pwm_cfg0[13:12];
+assign cfg_pwm_inv = pwm_cfg0[14];
+assign cfg_pwm_zeropd = pwm_cfg0[15]; // Reset on Matching Period
+assign cfg_comp0_center = pwm_cfg0[16];
+assign cfg_comp1_center = pwm_cfg0[17];
+assign cfg_comp2_center = pwm_cfg0[18];
+assign cfg_comp3_center = pwm_cfg0[19];
+
+gen_32b_reg #(32'h0) u_reg_0 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_0 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_0 )
+ );
+
+pwm_cfg_dglitch u_dglitch_0 (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ .enb (cfg_pwm_enb ),
+ .cfg_update (pwm_cfg_update ),
+ .cfg_dupdate (cfg_pwm_dupdate ),
+ .reg_in (reg_0 ),
+ .reg_out (pwm_cfg0 )
+
+
+ );
+//-----------------------------------------------------------------------
+// Logic for PWM-1 Config
+//-----------------------------------------------------------------------
+logic [31:0] pwm_cfg1;
+assign cfg_pwm_period = pwm_cfg1[15:0];
+
+gen_32b_reg #(32'h0) u_reg_1 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_1 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_1 )
+ );
+
+pwm_cfg_dglitch u_dglitch_1 (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ .enb (cfg_pwm_enb ),
+ .cfg_update (pwm_cfg_update ),
+ .cfg_dupdate (cfg_pwm_dupdate ),
+ .reg_in (reg_1 ),
+ .reg_out (pwm_cfg1 )
+
+
+ );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-2 Config
+//-----------------------------------------------------------------------
+logic [31:0] pwm_cfg2;
+assign cfg_pwm_comp0 = pwm_cfg2[15:0]; // Comparator-0
+assign cfg_pwm_comp1 = pwm_cfg2[31:16]; // Comparator-1
+gen_32b_reg #(32'h0) u_reg_2 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_2 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_2 )
+ );
+
+pwm_cfg_dglitch u_dglitch_2 (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ .enb (cfg_pwm_enb ),
+ .cfg_update (pwm_cfg_update ),
+ .cfg_dupdate (cfg_pwm_dupdate ),
+ .reg_in (reg_2 ),
+ .reg_out (pwm_cfg2 )
+
+
+ );
+//-----------------------------------------------------------------------
+// Logic for PWM-3 Config
+//-----------------------------------------------------------------------
+logic [31:0] pwm_cfg3;
+assign cfg_pwm_comp2 = reg_3[15:0]; // Comparator-2
+assign cfg_pwm_comp3 = reg_3[31:16]; // Comparator-3
+gen_32b_reg #(32'h0) u_reg_3 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_3 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_3 )
+ );
+
+
+pwm_cfg_dglitch u_dglitch_3 (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ .enb (cfg_pwm_enb ),
+ .cfg_update (pwm_cfg_update ),
+ .cfg_dupdate (cfg_pwm_dupdate ),
+ .reg_in (reg_3 ),
+ .reg_out (pwm_cfg3 )
+
+
+ );
+
+always_comb
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [1:0])
+ 2'b00 : reg_out [31:0] = reg_0 [31:0];
+ 2'b01 : reg_out [31:0] = reg_1 [31:0];
+ 2'b10 : reg_out [31:0] = reg_2 [31:0];
+ 2'b11 : reg_out [31:0] = reg_3 [31:0];
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pwm/src/pwm_cfg_dglitch.sv b/verilog/rtl/pwm/src/pwm_cfg_dglitch.sv
new file mode 100644
index 0000000..87d536b
--- /dev/null
+++ b/verilog/rtl/pwm/src/pwm_cfg_dglitch.sv
@@ -0,0 +1,37 @@
+
+/*************************************************************
+ This block added to block abort changing of config during PWM config.
+ pwm config will be update only in following condition
+ 1. When pwm is in disable condition
+ 2. When disable_update = 0 and cfg_update = 1
+*************************************************************/
+
+
+module pwm_cfg_dglitch (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+ input logic enb , // Operation Enable
+ input logic cfg_update , // Update config
+ input logic cfg_dupdate , // Disable config update
+ input logic [31:0] reg_in ,
+ output logic [31:0] reg_out
+
+ );
+
+
+
+always @(posedge mclk or negedge h_reset_n) begin
+ if ( ~h_reset_n ) begin
+ reg_out <= 'h0;
+ end else begin
+ if(!cfg_dupdate) begin
+ if(!enb || cfg_update) begin
+ reg_out <= reg_in;
+ end
+ end
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/pwm/src/pwm_core.sv b/verilog/rtl/pwm/src/pwm_core.sv
new file mode 100644
index 0000000..9c708db
--- /dev/null
+++ b/verilog/rtl/pwm/src/pwm_core.sv
@@ -0,0 +1,144 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+//////////////////////////////////////////////////////////////////////
+module pwm_core (
+
+ input logic h_reset_n ,
+ input logic mclk ,
+
+// Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [1:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+ input logic cfg_pwm_enb , // pwm operation enable
+ input logic cfg_pwm_dupdate , // Disable Config update
+ input logic [7:0] pad_gpio ,
+ output logic pwm_wfm_o ,
+ output logic pwm_os_done ,
+ output logic pwm_ovflow ,
+ output logic gpio_tgr
+
+
+
+);
+
+logic [3:0] cfg_pwm_scale ; // pwm clock scaling
+logic cfg_pwm_oneshot ; // pwm OneShot mode
+logic cfg_pwm_frun ; // pwm is free running
+logic cfg_pwm_gpio_enb ; // pwm gpio based trigger
+logic cfg_pwm_gpio_edge ; // pwm gpio based trigger edge
+logic [2:0] cfg_pwm_gpio_sel ; // gpio Selection
+logic cfg_pwm_hold ; // Hold data pwm data During pwm Disable
+logic cfg_pwm_inv ; // invert output
+logic cfg_pwm_zeropd ; // Reset on pmw_cnt match to period
+logic [1:0] cfg_pwm_mode ; // pwm Pulse Generation mode
+logic cfg_comp0_center ; // Compare cnt at comp0 center
+logic cfg_comp1_center ; // Compare cnt at comp1 center
+logic cfg_comp2_center ; // Compare cnt at comp2 center
+logic cfg_comp3_center ; // Compare cnt at comp3 center
+logic [15:0] cfg_pwm_period ; // pwm period
+logic [15:0] cfg_pwm_comp0 ; // compare0
+logic [15:0] cfg_pwm_comp1 ; // compare1
+logic [15:0] cfg_pwm_comp2 ; // compare2
+logic [15:0] cfg_pwm_comp3 ; // compare3
+
+
+
+
+pwm_blk_reg u_reg (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ .reg_cs (reg_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_rdata ),
+ .reg_ack (reg_ack ),
+
+ .cfg_pwm_enb (cfg_pwm_enb ), // PWM operation enable
+ .cfg_pwm_dupdate (cfg_pwm_dupdate ), // Disable Config update
+ .pwm_cfg_update (pwm_ovflow ), // Update the pwm config on roll-over or completion
+
+ .cfg_pwm_scale (cfg_pwm_scale ), // clock scaling
+ .cfg_pwm_oneshot (cfg_pwm_oneshot ), // PWM OneShot mode
+ .cfg_pwm_frun (cfg_pwm_frun ), // PWM is free running
+ .cfg_pwm_gpio_enb (cfg_pwm_gpio_enb ), // PWM GPIO based trigger enable
+ .cfg_pwm_gpio_edge (cfg_pwm_gpio_edge ), // PWM GPIO based trigger edge
+ .cfg_pwm_gpio_sel (cfg_pwm_gpio_sel ), // GPIO Selection
+ .cfg_pwm_hold (cfg_pwm_hold ), // Hold data PWM data During PWM Disable
+ .cfg_pwm_inv (cfg_pwm_inv ), // invert output
+ .cfg_pwm_zeropd (cfg_pwm_zeropd ), // Reset on pmw_cnt match to period
+ .cfg_pwm_mode (cfg_pwm_mode ), // PWM Pulse Generation mode
+ .cfg_comp0_center (cfg_comp0_center ), // Compare cnt at comp0 center
+ .cfg_comp1_center (cfg_comp1_center ), // Compare cnt at comp1 center
+ .cfg_comp2_center (cfg_comp2_center ), // Compare cnt at comp2 center
+ .cfg_comp3_center (cfg_comp3_center ), // Compare cnt at comp3 center
+ .cfg_pwm_period (cfg_pwm_period ), // PWM period
+ .cfg_pwm_comp0 (cfg_pwm_comp0 ), // compare0
+ .cfg_pwm_comp1 (cfg_pwm_comp1 ), // compare1
+ .cfg_pwm_comp2 (cfg_pwm_comp2 ), // compare2
+ .cfg_pwm_comp3 (cfg_pwm_comp3 ) // compare3
+
+ );
+
+
+
+pwm u_pwm (
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+
+ .pwm_wfm_o (pwm_wfm_o ),
+ .pwm_os_done (pwm_os_done ),
+ .pwm_ovflow_pe (pwm_ovflow ),
+ .gpio_tgr (gpio_tgr ),
+
+ .pad_gpio (pad_gpio ),
+
+ .cfg_pwm_enb (cfg_pwm_enb ),
+ .cfg_pwm_scale (cfg_pwm_scale ),
+ .cfg_pwm_oneshot (cfg_pwm_oneshot ),
+ .cfg_pwm_frun (cfg_pwm_frun ),
+ .cfg_pwm_gpio_enb (cfg_pwm_gpio_enb ),
+ .cfg_pwm_gpio_edge (cfg_pwm_gpio_edge ),
+ .cfg_pwm_gpio_sel (cfg_pwm_gpio_sel ),
+ .cfg_pwm_hold (cfg_pwm_hold ),
+ .cfg_pwm_inv (cfg_pwm_inv ),
+ .cfg_pwm_zeropd (cfg_pwm_zeropd ),
+ .cfg_pwm_mode (cfg_pwm_mode ),
+ .cfg_comp0_center (cfg_comp0_center ),
+ .cfg_comp1_center (cfg_comp1_center ),
+ .cfg_comp2_center (cfg_comp2_center ),
+ .cfg_comp3_center (cfg_comp3_center ),
+ .cfg_pwm_period (cfg_pwm_period ),
+ .cfg_pwm_comp0 (cfg_pwm_comp0 ),
+ .cfg_pwm_comp1 (cfg_pwm_comp1 ),
+ .cfg_pwm_comp2 (cfg_pwm_comp2 ),
+ .cfg_pwm_comp3 (cfg_pwm_comp3 )
+ );
+
+endmodule
diff --git a/verilog/rtl/pwm/src/pwm_glbl_reg.sv b/verilog/rtl/pwm/src/pwm_glbl_reg.sv
new file mode 100644
index 0000000..3868a78
--- /dev/null
+++ b/verilog/rtl/pwm/src/pwm_glbl_reg.sv
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// PWM Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//// 0.2 - 13th Sept 2022, Dinesh A ////
+//// Change Register to PWM Based ////
+//////////////////////////////////////////////////////////////////////
+//
+module pwm_glbl_reg (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [1:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+ output logic [5:0] cfg_pwm_enb , // PWM operation enable
+ output logic [5:0] cfg_pwm_dupdate , // Disable Config update
+
+ input logic [5:0] pwm_os_done , // Indicate oneshot sequence over
+ input logic [5:0] pwm_ovflow , // pwm sequence cross over
+ input logic [5:0] gpio_tgr , // Enable PWM based on trigger
+
+ output logic pwm_intr
+
+
+ );
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [1:0] sw_addr ; // addressing 16 registers
+logic [31:0] sw_reg_wdata ;
+logic [3:0] sw_be ;
+
+logic [31:0] reg_out ;
+logic [5:0] reg_0 ; // CONFIG - Unused
+logic [31:0] reg_1 ; // PWM-REG-0
+logic [31:0] reg_2 ; // PWM-REG-1
+logic [31:0] reg_3 ; // PWM-REG-2
+
+assign sw_addr = reg_addr;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign sw_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3);
+
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+
+//-----------------------------------------
+// PWM Enable Generation
+//----------------------------------------
+
+assign cfg_pwm_enb = reg_0[5:0];
+
+//------------------------------------------------------------------------
+// Design wise has avoided the pwm_os_done & gpio_tgr occur at same cycle
+//------------------------------------------------------------------------
+always @ (posedge mclk or negedge h_reset_n)
+begin
+ if (h_reset_n == 1'b0) begin
+ reg_0[5:0] <= 'h0;
+ end else if (reg_cs && sw_wr_en_0 && sw_be[0]) begin
+ reg_0[5:0] <= sw_reg_wdata[5:0] | gpio_tgr;
+ end else begin
+ reg_0[5:0] <= (reg_0[5:0] | gpio_tgr) ^ pwm_os_done;
+ end
+end
+
+
+//-----------------------------------------------------------------------
+// Logic for PWM-1 Config
+//-----------------------------------------------------------------------
+assign cfg_pwm_dupdate = reg_1[5:0];
+
+generic_register #(6,6'h0 ) u_reg_1 (
+ .we ({6{sw_wr_en_1 &
+ reg_ack &
+ sw_be[0] }} ),
+ .data_in (sw_reg_wdata[5:0] ),
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_1[5:0] )
+ );
+
+assign reg_1[31:6] = 'h0;
+
+//-----------------------------------------------------------------------
+// Reg-2: Interrupt Mask
+//-----------------------------------------------------------------------
+
+generic_register #(6,6'h0 ) u_reg_2 (
+ .we ({6{sw_wr_en_2 &
+ reg_ack &
+ sw_be[0] }} ),
+ .data_in (sw_reg_wdata[5:0] ),
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_2[5:0] )
+ );
+
+assign reg_2[31:6] = 'h0;
+//-----------------------------------------------------------------------
+// Reg-3: Interrupt Status
+//-----------------------------------------------------------------------
+
+assign pwm_intr = |(reg_2[5:0] & reg_3[5:0]);
+
+generic_intr_stat_reg #(.WD(6),
+ .RESET_DEFAULT(0)) u_reg4 (
+ //inputs
+ .clk (mclk ),
+ .reset_n (h_reset_n ),
+ .reg_we ({6{sw_wr_en_3 &
+ reg_ack &
+ sw_be[0]}}),
+ .reg_din ( sw_reg_wdata[5:0] ),
+ .hware_req ( pwm_ovflow ),
+
+ //outputs
+ .data_out ( reg_3[5:0] )
+ );
+
+assign reg_3[31:6] = 'h0;
+
+always_comb
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [1:0])
+ 2'b00 : reg_out [31:0] = {26'h0,reg_0 [5:0]};
+ 2'b01 : reg_out [31:0] = reg_1 [31:0];
+ 2'b10 : reg_out [31:0] = reg_2 [31:0];
+ 2'b11 : reg_out [31:0] = reg_3 [31:0];
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pwm/src/pwm_top.sv b/verilog/rtl/pwm/src/pwm_top.sv
new file mode 100644
index 0000000..e097c93
--- /dev/null
+++ b/verilog/rtl/pwm/src/pwm_top.sv
@@ -0,0 +1,295 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// PWM Top ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+/// Includes 6 PWM ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//// 0.2 - 14th Sept 2022, Dinesh A ////
+//// Improved PWM logic ////
+//////////////////////////////////////////////////////////////////////
+
+module pwm_top (
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic h_reset_n,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [4:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ input logic [7:0] pad_gpio,
+ output logic [5:0] pwm_wfm ,
+ output logic pwm_intr
+
+ );
+
+//---------------------------------------------------
+// 6 PWM variabled
+//---------------------------------------------------
+
+logic [5:0] cfg_pwm_enb ;
+logic [5:0] cfg_pwm_dupdate ;
+logic [5:0] pwm_os_done ;
+logic [5:0] pwm_ovflow ;
+logic [5:0] gpio_tgr ;
+logic reg_cs_glbl ;
+logic [5:0] reg_cs_pwm ;
+logic reg_ack_glbl ;
+logic [31:0] reg_rdata_glbl ;
+logic reg_ack_pwm0 ;
+logic [31:0] reg_rdata_pwm0 ;
+logic reg_ack_pwm1 ;
+logic [31:0] reg_rdata_pwm1 ;
+logic reg_ack_pwm2 ;
+logic [31:0] reg_rdata_pwm2 ;
+logic reg_ack_pwm3 ;
+logic [31:0] reg_rdata_pwm3 ;
+logic reg_ack_pwm4 ;
+logic [31:0] reg_rdata_pwm4 ;
+logic reg_ack_pwm5 ;
+logic [31:0] reg_rdata_pwm5 ;
+
+//------------------------------------------------------
+// Register Map Decoding
+
+`define SEL_GLBL 3'b000 // GLOBAL REGISTER
+`define SEL_PWM0 3'b001 // PWM-0
+`define SEL_PWM1 3'b010 // PWM-1
+`define SEL_PWM2 3'b011 // PWM-2
+`define SEL_PWM3 3'b100 // PWM-3
+`define SEL_PWM4 3'b101 // PWM-4
+`define SEL_PWM5 3'b110 // PWM-5
+
+assign reg_rdata = (reg_addr[4:2] == `SEL_GLBL) ? {reg_rdata_glbl} :
+ (reg_addr[4:2] == `SEL_PWM0) ? {reg_rdata_pwm0} :
+ (reg_addr[4:2] == `SEL_PWM1) ? {reg_rdata_pwm1} :
+ (reg_addr[4:2] == `SEL_PWM2) ? {reg_rdata_pwm2} :
+ (reg_addr[4:2] == `SEL_PWM3) ? {reg_rdata_pwm3} :
+ (reg_addr[4:2] == `SEL_PWM4) ? {reg_rdata_pwm4} :
+ (reg_addr[4:2] == `SEL_PWM5) ? {reg_rdata_pwm5} : 'h0;
+
+assign reg_ack = (reg_addr[4:2] == `SEL_GLBL) ? reg_ack_glbl :
+ (reg_addr[4:2] == `SEL_PWM0) ? reg_ack_pwm0 :
+ (reg_addr[4:2] == `SEL_PWM1) ? reg_ack_pwm1 :
+ (reg_addr[4:2] == `SEL_PWM2) ? reg_ack_pwm2 :
+ (reg_addr[4:2] == `SEL_PWM3) ? reg_ack_pwm3 :
+ (reg_addr[4:2] == `SEL_PWM4) ? reg_ack_pwm4 :
+ (reg_addr[4:2] == `SEL_PWM5) ? reg_ack_pwm5 : 'h0;
+
+assign reg_cs_glbl = (reg_addr[4:2] == `SEL_GLBL) ? reg_cs : 1'b0;
+assign reg_cs_pwm[0] = (reg_addr[4:2] == `SEL_PWM0) ? reg_cs : 1'b0;
+assign reg_cs_pwm[1] = (reg_addr[4:2] == `SEL_PWM1) ? reg_cs : 1'b0;
+assign reg_cs_pwm[2] = (reg_addr[4:2] == `SEL_PWM2) ? reg_cs : 1'b0;
+assign reg_cs_pwm[3] = (reg_addr[4:2] == `SEL_PWM3) ? reg_cs : 1'b0;
+assign reg_cs_pwm[4] = (reg_addr[4:2] == `SEL_PWM4) ? reg_cs : 1'b0;
+assign reg_cs_pwm[5] = (reg_addr[4:2] == `SEL_PWM5) ? reg_cs : 1'b0;
+
+pwm_glbl_reg u_glbl_reg (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_cs_glbl ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[1:0] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_rdata_glbl ),
+ .reg_ack (reg_ack_glbl ),
+
+ .cfg_pwm_enb (cfg_pwm_enb ),
+ .cfg_pwm_dupdate (cfg_pwm_dupdate ),
+
+ .pwm_os_done (pwm_os_done ),
+ .pwm_ovflow (pwm_ovflow ),
+ .gpio_tgr (gpio_tgr ),
+
+ .pwm_intr (pwm_intr )
+
+
+ );
+
+
+// 6 PWM Waveform Generator
+
+pwm_core u_pwm_0(
+
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+
+ .reg_cs (reg_cs_pwm[0] ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[1:0] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_rdata_pwm0 ),
+ .reg_ack (reg_ack_pwm0 ),
+
+ .cfg_pwm_enb (cfg_pwm_enb[0] ), // pwm operation enable
+ .cfg_pwm_dupdate (cfg_pwm_dupdate[0] ), // Disable Config update
+ .pad_gpio (pad_gpio ),
+ .pwm_os_done (pwm_os_done[0] ),
+ .pwm_ovflow (pwm_ovflow[0] ),
+ .gpio_tgr (gpio_tgr[0] ),
+ .pwm_wfm_o (pwm_wfm[0] )
+
+);
+
+pwm_core u_pwm_1(
+
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+
+ .reg_cs (reg_cs_pwm[1] ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[1:0] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_rdata_pwm1 ),
+ .reg_ack (reg_ack_pwm1 ),
+
+ .cfg_pwm_enb (cfg_pwm_enb[1] ), // pwm operation enable
+ .cfg_pwm_dupdate (cfg_pwm_dupdate[1] ), // Disable Config update
+ .pad_gpio (pad_gpio ),
+ .pwm_os_done (pwm_os_done[1] ),
+ .pwm_ovflow (pwm_ovflow[1] ),
+ .gpio_tgr (gpio_tgr[1] ),
+ .pwm_wfm_o (pwm_wfm[1] )
+
+);
+pwm_core u_pwm_2(
+
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+
+ .reg_cs (reg_cs_pwm[2] ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[1:0] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_rdata_pwm2 ),
+ .reg_ack (reg_ack_pwm2 ),
+
+ .cfg_pwm_enb (cfg_pwm_enb[2] ), // pwm operation enable
+ .cfg_pwm_dupdate (cfg_pwm_dupdate[2] ), // Disable Config update
+ .pad_gpio (pad_gpio ),
+ .pwm_os_done (pwm_os_done[2] ),
+ .pwm_ovflow (pwm_ovflow[2] ),
+ .gpio_tgr (gpio_tgr[2] ),
+ .pwm_wfm_o (pwm_wfm[2] )
+
+);
+pwm_core u_pwm_3(
+
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+
+ .reg_cs (reg_cs_pwm[3] ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[1:0] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_rdata_pwm3 ),
+ .reg_ack (reg_ack_pwm3 ),
+
+ .cfg_pwm_enb (cfg_pwm_enb[3] ), // pwm operation enable
+ .cfg_pwm_dupdate (cfg_pwm_dupdate[3] ), // Disable Config update
+ .pad_gpio (pad_gpio ),
+ .pwm_os_done (pwm_os_done[3] ),
+ .pwm_ovflow (pwm_ovflow[3] ),
+ .gpio_tgr (gpio_tgr[3] ),
+ .pwm_wfm_o (pwm_wfm[3] )
+
+);
+pwm_core u_pwm_4(
+
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+
+ .reg_cs (reg_cs_pwm[4] ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[1:0] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_rdata_pwm4 ),
+ .reg_ack (reg_ack_pwm4 ),
+
+ .cfg_pwm_enb (cfg_pwm_enb[4] ), // pwm operation enable
+ .cfg_pwm_dupdate (cfg_pwm_dupdate[4] ), // Disable Config update
+ .pad_gpio (pad_gpio ),
+ .pwm_os_done (pwm_os_done[4] ),
+ .pwm_ovflow (pwm_ovflow[4] ),
+ .gpio_tgr (gpio_tgr[4] ),
+ .pwm_wfm_o (pwm_wfm[4] )
+
+);
+pwm_core u_pwm_5(
+
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+
+ .reg_cs (reg_cs_pwm[5] ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[1:0] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_rdata_pwm5 ),
+ .reg_ack (reg_ack_pwm5 ),
+
+ .cfg_pwm_enb (cfg_pwm_enb[5] ), // pwm operation enable
+ .cfg_pwm_dupdate (cfg_pwm_dupdate[5] ), // Disable Config update
+ .pad_gpio (pad_gpio ),
+ .pwm_os_done (pwm_os_done[5] ),
+ .pwm_ovflow (pwm_ovflow[5] ),
+ .gpio_tgr (gpio_tgr[5] ),
+ .pwm_wfm_o (pwm_wfm[5] )
+
+);
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/timer.sv b/verilog/rtl/timer/src/timer.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/timer.sv
rename to verilog/rtl/timer/src/timer.sv
diff --git a/verilog/rtl/pinmux/src/timer_reg.sv b/verilog/rtl/timer/src/timer_reg.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/timer_reg.sv
rename to verilog/rtl/timer/src/timer_reg.sv
diff --git a/verilog/rtl/pinmux/src/timer_top.sv b/verilog/rtl/timer/src/timer_top.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/timer_top.sv
rename to verilog/rtl/timer/src/timer_top.sv
diff --git a/verilog/rtl/pinmux/src/ws281x_driver.sv b/verilog/rtl/ws281x/src/ws281x_driver.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/ws281x_driver.sv
rename to verilog/rtl/ws281x/src/ws281x_driver.sv
diff --git a/verilog/rtl/pinmux/src/ws281x_reg.sv b/verilog/rtl/ws281x/src/ws281x_reg.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/ws281x_reg.sv
rename to verilog/rtl/ws281x/src/ws281x_reg.sv
diff --git a/verilog/rtl/pinmux/src/ws281x_top.sv b/verilog/rtl/ws281x/src/ws281x_top.sv
similarity index 100%
rename from verilog/rtl/pinmux/src/ws281x_top.sv
rename to verilog/rtl/ws281x/src/ws281x_top.sv
