security core and fpu integrated
diff --git a/.gitmodules b/.gitmodules
index 72dbb4f..3d2b0f8 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,3 +7,9 @@
[submodule "verilog/rtl/yifive/ycr1cr"]
path = verilog/rtl/yifive/ycr1c
url = https://github.com/dineshannayya/ycr1cr.git
+[submodule "verilog/rtl/security_core"]
+ path = verilog/rtl/security_core
+ url = https://github.com/dineshannayya/security_core
+[submodule "verilog/rtl/fpu"]
+ path = verilog/rtl/fpu
+ url = https://github.com/dineshannayya/fpu
diff --git a/README.md b/README.md
index 176670f..71b2b80 100644
--- a/README.md
+++ b/README.md
@@ -588,7 +588,7 @@
We are looking for community help in following activity, interested user can ping me in efabless slack platform
* **Analog Design** - ADC, DAC, PLL,
-* **Digital Design** - New IP Integration, Encription,DSP, Floating point functions
+* **Digital Design** - New IP Integration, Encription,DSP, DMA controller, 10Mb MAC, Floating point functions
* **Verification** - Improving the Verification flow
* **Linux Porting** - Build Root integration
* **Arudino Software Update** - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
diff --git a/openlane/Makefile b/openlane/Makefile
index 14d5aac..c21989a 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -43,7 +43,7 @@
@sleep 1
@if [ -f ./$*/interactive.tcl ]; then\
- docker run --rm \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
-v $(MCW_ROOT):$(MCW_ROOT) \
@@ -57,7 +57,7 @@
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
- docker run --rm \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
diff --git a/openlane/dg_pll/base.sdc b/openlane/dg_pll/base.sdc
new file mode 100644
index 0000000..b10a47b
--- /dev/null
+++ b/openlane/dg_pll/base.sdc
@@ -0,0 +1,28 @@
+current_design dg_pll
+
+create_clock [get_pins {"ringosc.ibufp01/Y"} ] -name "pll_control_clock" -period 6.6666666666667
+
+set_propagated_clock [get_clocks {pll_control_clock}]
+
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
diff --git a/openlane/digital_pll/config.tcl b/openlane/dg_pll/config.tcl
similarity index 80%
rename from openlane/digital_pll/config.tcl
rename to openlane/dg_pll/config.tcl
index a56efd0..ab632d6 100644
--- a/openlane/digital_pll/config.tcl
+++ b/openlane/dg_pll/config.tcl
@@ -15,12 +15,12 @@
set script_dir [file dirname [file normalize [info script]]]
-set ::env(DESIGN_NAME) digital_pll
+set ::env(DESIGN_NAME) dg_pll
set ::env(DESIGN_IS_CORE) 0
-set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/digital_pll.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/digital_pll_controller.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/digital_pll/src/ring_osc2x13.v"
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/dg_pll.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/digital_pll_controller.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/dg_pll/src/ring_osc2x13.v"
set ::env(CLOCK_PORT) ""
set ::env(CLOCK_TREE_SYNTH) 0
@@ -41,30 +41,44 @@
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 90 100"
+set ::env(GRT_OBS) "met4 0 0 90 100"
+
#set ::env(TOP_MARGIN_MULT) 2
#set ::env(BOTTOM_MARGIN_MULT) 2
#LVS Issue - DEF Base looks to having issue
-#set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
set ::env(CELL_PAD) 0
## PDN
set ::env(FP_PDN_VPITCH) 40
set ::env(FP_PDN_HPITCH) 40
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+set ::env(FP_PDN_VOFFSET) "5"
+set ::env(FP_PDN_HOFFSET) "5"
+set ::env(FP_PDN_HSPACING) {13.8}
+set ::env(FP_PDN_VSPACING) {13.8}
+set ::env(FP_PDN_HORIZONTAL_HALO) "10"
+set ::env(FP_PDN_VERTICAL_HALO) "10"
## Placement
set ::env(PL_TARGET_DENSITY) 0.82
-## Routing
-#set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
-#set ::env(GLB_RT_ADJUSTMENT) 0
-#set ::env(GLB_RT_MINLAYER) 2
-#set ::env(GLB_RT_MAXLAYER) 6
+## Routing
+
+#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
@@ -77,11 +91,4 @@
## Diode Insertion
#set ::env(DIODE_INSERTION_STRATEGY) "4"
-set ::env(FP_PDN_VOFFSET) "5"
-set ::env(FP_PDN_VPITCH) "40"
-set ::env(FP_PDN_HOFFSET) "5"
-set ::env(FP_PDN_HPITCH) "40"
-set ::env(FP_PDN_HWIDTH) {6.2}
-set ::env(FP_PDN_VWIDTH) {6.2}
-set ::env(FP_PDN_HSPACING) {15}
-set ::env(FP_PDN_VSPACING) {15}
+
diff --git a/openlane/digital_pll/interactive.tcl b/openlane/dg_pll/interactive.tcl
similarity index 100%
rename from openlane/digital_pll/interactive.tcl
rename to openlane/dg_pll/interactive.tcl
diff --git a/openlane/digital_pll/macro.cfg b/openlane/dg_pll/macro.cfg
similarity index 100%
rename from openlane/digital_pll/macro.cfg
rename to openlane/dg_pll/macro.cfg
diff --git a/openlane/digital_pll/pin_order.cfg b/openlane/dg_pll/pin_order.cfg
similarity index 100%
rename from openlane/digital_pll/pin_order.cfg
rename to openlane/dg_pll/pin_order.cfg
diff --git a/openlane/digital_pll/base.sdc b/openlane/digital_pll/base.sdc
deleted file mode 100644
index 062e55d..0000000
--- a/openlane/digital_pll/base.sdc
+++ /dev/null
@@ -1,36 +0,0 @@
-
-
-current_design digital_pll
-
-create_clock [get_pins {"ringosc.ibufp01/Y"} ] -name "pll_control_clock" -period 6.6666666666667
-
-set_propagated_clock [get_clocks {pll_control_clock}]
-
-set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
-set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
-puts "\[INFO\]: Setting output delay to: $output_delay_value"
-puts "\[INFO\]: Setting input delay to: $input_delay_value"
-
-set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs]
-set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load $cap_load [all_outputs]
-
-puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
-set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
-set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
-
-puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
-set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_control_clock}]
-
-puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
-set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_control_clock}]
-
-
-set_max_transition 1.00 [current_design]
-set_max_capacitance 0.2 [current_design]
-set_max_fanout 10 [current_design]
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index de3eda0..667b5a5 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -93,7 +93,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 500 850"
+set ::env(DIE_AREA) "0 0 520 850"
# If you're going to use multiple power domains, then keep this disabled.
@@ -132,13 +132,16 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
set ::env(DIODE_INSERTION_STRATEGY) 4
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index 72106cb..a8e15ef 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -2,7 +2,9 @@
#MANUAL_PLACE
#S
-cpu_core_rst_n\[1\] 000 0 2
+cpu_core_rst_n\[3\] 000 0 2
+cpu_core_rst_n\[2\]
+cpu_core_rst_n\[1\]
cpu_core_rst_n\[0\]
cpu_intf_rst_n
qspim_rst_n
@@ -62,82 +64,13 @@
spis_miso
spis_mosi
-cfg_strap_pad_ctrl 0100 0 4
-user_clock1
+user_clock1 0100 0 4
user_clock2
int_pll_clock
xtal_clk
-e_reset_n
-p_reset_n
s_reset_n
rtc_clk
usb_clk
-strap_uartm\[1\]
-strap_uartm\[0\]
-strap_sticky\[31\]
-strap_sticky\[30\]
-strap_sticky\[29\]
-strap_sticky\[28\]
-strap_sticky\[27\]
-strap_sticky\[26\]
-strap_sticky\[25\]
-strap_sticky\[24\]
-strap_sticky\[23\]
-strap_sticky\[22\]
-strap_sticky\[21\]
-strap_sticky\[20\]
-strap_sticky\[19\]
-strap_sticky\[18\]
-strap_sticky\[17\]
-strap_sticky\[16\]
-strap_sticky\[15\]
-strap_sticky\[14\]
-strap_sticky\[13\]
-strap_sticky\[12\]
-strap_sticky\[11\]
-strap_sticky\[10\]
-strap_sticky\[9\]
-strap_sticky\[8\]
-strap_sticky\[7\]
-strap_sticky\[6\]
-strap_sticky\[5\]
-strap_sticky\[4\]
-strap_sticky\[3\]
-strap_sticky\[2\]
-strap_sticky\[1\]
-strap_sticky\[0\]
-system_strap\[31\]
-system_strap\[30\]
-system_strap\[29\]
-system_strap\[28\]
-system_strap\[27\]
-system_strap\[26\]
-system_strap\[25\]
-system_strap\[24\]
-system_strap\[23\]
-system_strap\[22\]
-system_strap\[21\]
-system_strap\[20\]
-system_strap\[19\]
-system_strap\[18\]
-system_strap\[17\]
-system_strap\[16\]
-system_strap\[15\]
-system_strap\[14\]
-system_strap\[13\]
-system_strap\[12\]
-system_strap\[11\]
-system_strap\[10\]
-system_strap\[9\]
-system_strap\[8\]
-system_strap\[7\]
-system_strap\[6\]
-system_strap\[5\]
-system_strap\[4\]
-system_strap\[3\]
-system_strap\[2\]
-system_strap\[1\]
-system_strap\[0\]
pinmux_debug\[0\] 0300 0 2
pinmux_debug\[1\]
@@ -174,8 +107,80 @@
cpu_clk
#W
+strap_sticky\[31\] 000 0 2
+strap_sticky\[30\]
+strap_sticky\[29\]
+strap_sticky\[28\]
+strap_sticky\[27\]
+strap_sticky\[26\]
+strap_sticky\[25\]
+strap_sticky\[24\]
+strap_sticky\[23\]
+strap_sticky\[22\]
+strap_sticky\[21\]
+strap_sticky\[20\]
+strap_sticky\[19\]
+strap_sticky\[18\]
+strap_sticky\[17\]
+strap_sticky\[16\]
+strap_sticky\[15\]
+strap_sticky\[14\]
+strap_sticky\[13\]
+strap_sticky\[12\]
+strap_sticky\[11\]
+strap_sticky\[10\]
+strap_sticky\[9\]
+strap_sticky\[8\]
+strap_sticky\[7\]
+strap_sticky\[6\]
+strap_sticky\[5\]
+strap_sticky\[4\]
+strap_sticky\[3\]
+strap_sticky\[2\]
+strap_sticky\[1\]
+strap_sticky\[0\]
-soft_irq
+strap_uartm\[1\]
+strap_uartm\[0\]
+
+system_strap\[31\]
+system_strap\[30\]
+system_strap\[29\]
+system_strap\[28\]
+system_strap\[27\]
+system_strap\[26\]
+system_strap\[25\]
+system_strap\[24\]
+system_strap\[23\]
+system_strap\[22\]
+system_strap\[21\]
+system_strap\[20\]
+system_strap\[19\]
+system_strap\[18\]
+system_strap\[17\]
+system_strap\[16\]
+system_strap\[15\]
+system_strap\[14\]
+system_strap\[13\]
+system_strap\[12\]
+system_strap\[11\]
+system_strap\[10\]
+system_strap\[9\]
+system_strap\[8\]
+system_strap\[7\]
+system_strap\[6\]
+system_strap\[5\]
+system_strap\[4\]
+system_strap\[3\]
+system_strap\[2\]
+system_strap\[1\]
+system_strap\[0\]
+
+p_reset_n
+e_reset_n
+cfg_strap_pad_ctrl
+
+soft_irq 200 0 2
irq_lines\[31\]
irq_lines\[30\]
irq_lines\[29\]
@@ -219,7 +224,7 @@
-reg_cs 200 0
+reg_cs 260 0 2
reg_wr
reg_addr\[9\]
reg_addr\[8\]
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index c376278..9c49d24 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -73,6 +73,9 @@
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 450 550"
+#set ::env(GRT_OBS) " \
+# met4 0 0 450 550"
+
set ::env(PL_TIME_DRIVEN) 1
set ::env(PL_TARGET_DENSITY) "0.42"
@@ -95,6 +98,11 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index 9f93b81..c078759 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -55,7 +55,7 @@
#W
-cfg_cska_sp_co\[3\] 0000 0 2
+cfg_cska_sp_co\[3\] 0200 0 2
cfg_cska_sp_co\[2\]
cfg_cska_sp_co\[1\]
cfg_cska_sp_co\[0\]
@@ -67,7 +67,7 @@
wbd_clk_spi
mclk
-wbd_stb_i 0100 0 2
+wbd_stb_i 0300 0 2
wbd_we_i
wbd_adr_i\[31\]
wbd_adr_i\[30\]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 9870805..7576c81 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -118,6 +118,11 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
index aba1684..2801070 100644
--- a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
@@ -2,7 +2,7 @@
#MANUAL_PLACE
#W
-cfg_cska_uart\[3\] 0000 0 2
+cfg_cska_uart\[3\] 0200 0 2
cfg_cska_uart\[2\]
cfg_cska_uart\[1\]
cfg_cska_uart\[0\]
@@ -10,7 +10,7 @@
wbd_clk_uart
app_clk
-reg_cs 0100 0 2
+reg_cs 0300 0 2
reg_wr
reg_addr\[8\]
reg_addr\[7\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index bb6ae69..b393d73 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -73,9 +73,11 @@
$::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \
$::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/ycr_iconnect.v \
- $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/dg_pll.v \
$::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
$::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/aes_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/fpu_wrapper.v \
"
set ::env(EXTRA_LEFS) "\
@@ -87,9 +89,11 @@
$lef_root/ycr_intf.lef \
$lef_root/ycr_core_top.lef \
$lef_root/ycr_iconnect.lef \
- $lef_root/digital_pll.lef \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+ $lef_root/dg_pll.lef \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
$lef_root/dac_top.lef \
+ $lef_root/aes_top.lef \
+ $lef_root/fpu_wrapper.lef \
"
set ::env(EXTRA_GDS_FILES) "\
@@ -101,8 +105,10 @@
$gds_root/ycr_intf.gds \
$gds_root/ycr_core_top.gds \
$gds_root/ycr_iconnect.gds \
- $gds_root/digital_pll.gds \
+ $gds_root/dg_pll.gds \
$gds_root/dac_top.gds \
+ $gds_root/aes_top.gds \
+ $gds_root/fpu_wrapper.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -128,8 +134,8 @@
set ::env(FP_PDN_HPITCH) "80"
set ::env(FP_PDN_HWIDTH) {6.2}
set ::env(FP_PDN_VWIDTH) {6.2}
-set ::env(FP_PDN_HSPACING) {33.8}
-set ::env(FP_PDN_VSPACING) {33.8}
+set ::env(FP_PDN_HSPACING) {13.8}
+set ::env(FP_PDN_VSPACING) {13.8}
set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
@@ -138,6 +144,7 @@
set ::env(VDD_PIN) {vccd1}
set ::env(GND_PIN) {vssd1}
+set ::env(PDN_STRIPE) {vccd1 vdda1 vssd1 vssa1}
set ::env(DRT_OPT_ITERS) {32}
set ::env(GRT_OBS) " \
@@ -167,10 +174,12 @@
u_dcache_2kb vccd1 vssd1 vccd1 vssd1,\
u_uart_i2c_usb_spi vccd1 vssd1 vccd1 vssd1,\
u_wb_host vccd1 vssd1 vccd1 vssd1,\
- u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1, \
+ u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1,\
u_riscv_top.u_connect vccd1 vssd1 VPWR VGND, \
- u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1, \
- u_4x8bit_dac vccd1 vssd1 vccd1 vssd1
+ u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1,\
+ u_4x8bit_dac vdda1 vssa1 vccd1 vssd1,\
+ u_aes vdda1 vssa1 vccd1 vssd1
+ u_fpu vdda1 vssa1 vccd1 vssd1
"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a5faf73..cdcc8a2 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,11 +1,13 @@
-u_4x8bit_dac 1850 2500 N
-u_qspi_master 2250 650 N
-u_uart_i2c_usb_spi 2250 1350 N
-u_pinmux 2250 2250 N
-u_pll 2500 3228 N
+u_4x8bit_dac 1850 2500 N
+u_qspi_master 2250 450 N
+u_uart_i2c_usb_spi 2250 1100 N
+u_pinmux 2250 2000 N
+u_pll 2500 3028 N
+u_fpu 1000 2600 N
+u_aes 50 2600 N
u_riscv_top.i_core_top_0 50 1400 N
-u_riscv_top.u_connect 735 1400 N
+u_riscv_top.u_connect 740 1400 N
u_riscv_top.u_intf 950 650 N
u_dcache_2kb 150 130 N
u_icache_2kb 950 130 N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index c1e213d..b2a2b42 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -93,7 +93,7 @@
-pitch $::env(FP_PDN_VPITCH) \
-offset $::env(FP_PDN_VOFFSET) \
-spacing $::env(FP_PDN_VSPACING) \
- -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -nets "$::env(PDN_STRIPE)" \
-starts_with POWER -extend_to_core_ring
add_pdn_stripe \
@@ -103,7 +103,7 @@
-pitch $::env(FP_PDN_HPITCH) \
-offset $::env(FP_PDN_HOFFSET) \
-spacing $::env(FP_PDN_HSPACING) \
- -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -nets "$::env(PDN_STRIPE)" \
-starts_with POWER -extend_to_core_ring
add_pdn_connect \
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index f2b9028..b4c0b35 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -85,8 +85,10 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 450 425"
+set ::env(DIE_AREA) "0 0 400 425"
+set ::env(GRT_OBS) " \
+ met4 0 0 400 425"
# If you're going to use multiple power domains, then keep this disabled.
set ::env(RUN_CVC) 0
@@ -111,11 +113,15 @@
set ::env(RT_MAX_LAYER) {met4}
#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
set ::env(DIODE_INSERTION_STRATEGY) 4
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 26c9f8e..8c93e59 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -158,51 +158,89 @@
#N
-wbd_int_rst_n 0100 0 2
-cfg_clk_ctrl1\[31\]
-cfg_clk_ctrl1\[30\]
-cfg_clk_ctrl1\[29\]
-cfg_clk_ctrl1\[28\]
-cfg_clk_ctrl1\[27\]
-cfg_clk_ctrl1\[26\]
-cfg_clk_ctrl1\[25\]
-cfg_clk_ctrl1\[24\]
-cfg_clk_ctrl1\[23\]
-cfg_clk_ctrl1\[22\]
-cfg_clk_ctrl1\[21\]
-cfg_clk_ctrl1\[20\]
-cfg_clk_ctrl1\[19\]
-cfg_clk_ctrl1\[18\]
-cfg_clk_ctrl1\[17\]
-cfg_clk_ctrl1\[16\]
-cfg_clk_ctrl1\[15\]
-cfg_clk_ctrl1\[14\]
-cfg_clk_ctrl1\[13\]
-cfg_clk_ctrl1\[12\]
-cfg_clk_ctrl1\[11\]
-cfg_clk_ctrl1\[10\]
-cfg_clk_ctrl1\[9\]
-cfg_clk_ctrl1\[8\]
-cfg_clk_ctrl1\[3\]
-cfg_clk_ctrl1\[2\]
-cfg_clk_ctrl1\[1\]
-cfg_clk_ctrl1\[0\]
+cfg_clk_skew_ctrl2\[31\] 0000 0 2
+cfg_clk_skew_ctrl2\[30\]
+cfg_clk_skew_ctrl2\[29\]
+cfg_clk_skew_ctrl2\[28\]
+cfg_clk_skew_ctrl2\[27\]
+cfg_clk_skew_ctrl2\[26\]
+cfg_clk_skew_ctrl2\[25\]
+cfg_clk_skew_ctrl2\[24\]
+
+cfg_clk_skew_ctrl1\[31\]
+cfg_clk_skew_ctrl1\[30\]
+cfg_clk_skew_ctrl1\[29\]
+cfg_clk_skew_ctrl1\[28\]
+
+cfg_clk_skew_ctrl1\[7\]
+cfg_cska_wh\[3\]
+cfg_clk_skew_ctrl1\[6\]
+cfg_cska_wh\[2\]
+cfg_clk_skew_ctrl1\[5\]
+cfg_cska_wh\[1\]
+cfg_clk_skew_ctrl1\[4\]
+cfg_cska_wh\[0\]
+
+wbd_int_rst_n 0100 0 2
+cfg_clk_skew_ctrl2\[23\]
+cfg_clk_skew_ctrl2\[22\]
+cfg_clk_skew_ctrl2\[21\]
+cfg_clk_skew_ctrl2\[20\]
+cfg_clk_skew_ctrl2\[19\]
+cfg_clk_skew_ctrl2\[18\]
+cfg_clk_skew_ctrl2\[17\]
+cfg_clk_skew_ctrl2\[16\]
+cfg_clk_skew_ctrl2\[15\]
+cfg_clk_skew_ctrl2\[14\]
+cfg_clk_skew_ctrl2\[13\]
+cfg_clk_skew_ctrl2\[12\]
+cfg_clk_skew_ctrl2\[11\]
+cfg_clk_skew_ctrl2\[10\]
+cfg_clk_skew_ctrl2\[9\]
+cfg_clk_skew_ctrl2\[8\]
+cfg_clk_skew_ctrl2\[7\]
+cfg_clk_skew_ctrl2\[6\]
+cfg_clk_skew_ctrl2\[5\]
+cfg_clk_skew_ctrl2\[4\]
+cfg_clk_skew_ctrl2\[3\]
+cfg_clk_skew_ctrl2\[2\]
+cfg_clk_skew_ctrl2\[1\]
+cfg_clk_skew_ctrl2\[0\]
+
+cfg_clk_skew_ctrl1\[27\]
+cfg_clk_skew_ctrl1\[26\]
+cfg_clk_skew_ctrl1\[25\]
+cfg_clk_skew_ctrl1\[24\]
+cfg_clk_skew_ctrl1\[23\]
+cfg_clk_skew_ctrl1\[22\]
+cfg_clk_skew_ctrl1\[21\]
+cfg_clk_skew_ctrl1\[20\]
+cfg_clk_skew_ctrl1\[19\]
+cfg_clk_skew_ctrl1\[18\]
+cfg_clk_skew_ctrl1\[17\]
+cfg_clk_skew_ctrl1\[16\]
+cfg_clk_skew_ctrl1\[15\]
+cfg_clk_skew_ctrl1\[14\]
+cfg_clk_skew_ctrl1\[13\]
+cfg_clk_skew_ctrl1\[12\]
+cfg_clk_skew_ctrl1\[11\]
+cfg_clk_skew_ctrl1\[10\]
+cfg_clk_skew_ctrl1\[9\]
+cfg_clk_skew_ctrl1\[8\]
+
+cfg_clk_skew_ctrl1\[3\]
+cfg_clk_skew_ctrl1\[2\]
+cfg_clk_skew_ctrl1\[1\]
+cfg_clk_skew_ctrl1\[0\]
+
wbd_clk_int
wbs_clk_out
wbs_clk_i
wbd_clk_wh
-cfg_clk_ctrl1\[7\]
-cfg_cska_wh\[3\]
-cfg_clk_ctrl1\[6\]
-cfg_cska_wh\[2\]
-cfg_clk_ctrl1\[5\]
-cfg_cska_wh\[1\]
-cfg_clk_ctrl1\[4\]
-cfg_cska_wh\[0\]
-wbs_stb_o 160 0 2
+wbs_stb_o 200 0 2
wbs_we_o
wbs_adr_o\[31\]
wbs_adr_o\[30\]
@@ -309,15 +347,7 @@
wbs_cyc_o
-cfg_strap_pad_ctrl
-e_reset_n
-int_pll_clock
-p_reset_n
-s_reset_n
-xtal_clk
-strap_uartm\[1\]
-strap_uartm\[0\]
-strap_sticky\[31\]
+strap_sticky\[31\] 325 0 2
strap_sticky\[30\]
strap_sticky\[29\]
strap_sticky\[28\]
@@ -349,6 +379,10 @@
strap_sticky\[2\]
strap_sticky\[1\]
strap_sticky\[0\]
+
+strap_uartm\[1\]
+strap_uartm\[0\]
+
system_strap\[31\]
system_strap\[30\]
system_strap\[29\]
@@ -381,3 +415,11 @@
system_strap\[2\]
system_strap\[1\]
system_strap\[0\]
+
+cfg_strap_pad_ctrl
+e_reset_n
+p_reset_n
+
+int_pll_clock
+xtal_clk
+s_reset_n
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 58b9acb..1cd2a7e 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -52,7 +52,7 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
- CH_DATA_WD=53 \
+ CH_DATA_WD=154 \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
@@ -71,8 +71,9 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 300 1725"
+set ::env(DIE_AREA) "0 0 300 1800"
+#set ::env(GRT_OBS) "met4 0 0 300 1725"
# If you're going to use multiple power domains, then keep this disabled.
set ::env(RUN_CVC) 0
@@ -118,11 +119,15 @@
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 93ca457..7038097 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -4,6 +4,30 @@
#S
rst_n 000 0 2
+ch_data_in\[43\]
+ch_data_in\[42\]
+ch_data_in\[41\]
+ch_data_in\[40\]
+ch_data_in\[39\]
+ch_data_in\[38\]
+ch_data_in\[37\]
+ch_data_in\[36\]
+ch_data_in\[35\]
+ch_data_in\[34\]
+ch_data_in\[33\]
+ch_data_in\[32\]
+ch_data_in\[31\]
+ch_data_in\[30\]
+ch_data_in\[29\]
+ch_data_in\[28\]
+ch_data_in\[27\]
+ch_data_in\[26\]
+ch_data_in\[25\]
+ch_data_in\[24\]
+ch_data_in\[23\]
+ch_data_in\[22\]
+ch_data_in\[21\]
+ch_data_in\[20\]
ch_data_in\[19\]
ch_data_in\[18\]
ch_data_in\[17\]
@@ -24,10 +48,12 @@
ch_data_in\[2\]
ch_data_in\[1\]
ch_data_in\[0\]
+
cfg_cska_wi\[3\]
cfg_cska_wi\[2\]
cfg_cska_wi\[1\]
cfg_cska_wi\[0\]
+
ch_clk_in\[3\]
ch_clk_in\[2\]
ch_clk_in\[1\]
@@ -37,7 +63,7 @@
clk_i
-m0_wbd_stb_i 060 0 2
+m0_wbd_stb_i 100 0 2
m0_wbd_we_i
m0_wbd_adr_i\[31\]
m0_wbd_adr_i\[30\]
@@ -144,44 +170,98 @@
m0_wbd_err_o
m0_wbd_cyc_i
+ch_data_in\[153\] 225 0 2
+ch_data_in\[152\]
+ch_data_in\[151\]
+ch_data_in\[150\]
+
+ch_data_in\[149\]
+ch_data_in\[148\]
+ch_data_in\[147\]
+ch_data_in\[146\]
+
+ch_data_out\[145\]
+ch_data_out\[144\]
+ch_data_out\[143\]
+ch_data_out\[142\]
+ch_data_out\[141\]
+ch_data_out\[140\]
+ch_data_out\[139\]
+ch_data_out\[138\]
+ch_data_out\[137\]
+ch_data_out\[136\]
+ch_data_out\[135\]
+ch_data_out\[134\]
+ch_data_out\[133\]
+ch_data_out\[132\]
+ch_data_out\[131\]
+ch_data_out\[130\]
+ch_data_out\[129\]
+ch_data_out\[128\]
+ch_data_out\[127\]
+ch_data_out\[126\]
+ch_data_out\[125\]
+ch_data_out\[124\]
+ch_data_out\[123\]
+ch_data_out\[122\]
+ch_data_out\[121\]
+ch_data_out\[120\]
+ch_data_out\[119\]
+ch_data_out\[118\]
+ch_data_out\[117\]
+ch_data_out\[116\]
+ch_data_out\[115\]
+ch_data_out\[114\]
+
+ch_data_out\[113\]
+ch_data_out\[112\]
+
+ch_data_in\[111\]
+ch_data_in\[110\]
+ch_data_in\[109\]
+ch_data_in\[108\]
+ch_data_in\[107\]
+ch_data_in\[106\]
+ch_data_in\[105\]
+ch_data_in\[104\]
+ch_data_in\[103\]
+ch_data_in\[102\]
+ch_data_in\[101\]
+ch_data_in\[100\]
+ch_data_in\[99\]
+ch_data_in\[98\]
+ch_data_in\[97\]
+ch_data_in\[96\]
+ch_data_in\[95\]
+ch_data_in\[94\]
+ch_data_in\[93\]
+ch_data_in\[92\]
+ch_data_in\[91\]
+ch_data_in\[90\]
+ch_data_in\[89\]
+ch_data_in\[88\]
+ch_data_in\[87\]
+ch_data_in\[86\]
+ch_data_in\[85\]
+ch_data_in\[84\]
+ch_data_in\[83\]
+ch_data_in\[82\]
+ch_data_in\[81\]
+ch_data_in\[80\]
+
+ch_data_in\[79\]
+ch_data_in\[78\]
+ch_data_in\[77\]
+
#W
-ch_data_out\[52\] 000 0 2
-ch_data_out\[51\]
-ch_data_out\[50\]
-ch_data_out\[49\]
-ch_data_out\[48\]
-ch_data_out\[47\]
-ch_data_out\[46\]
-ch_data_out\[45\]
-ch_data_out\[44\]
-ch_data_out\[43\]
-ch_data_out\[42\]
-ch_data_out\[41\]
-ch_data_out\[40\]
-ch_data_out\[39\]
-ch_data_out\[38\]
-ch_data_out\[37\]
-ch_data_out\[36\]
-ch_data_out\[35\]
-ch_data_out\[34\]
-ch_data_out\[33\]
-ch_data_out\[32\]
-ch_data_out\[31\]
-ch_data_out\[30\]
-ch_data_out\[29\]
-ch_data_out\[28\]
-ch_data_out\[27\]
-ch_data_out\[26\]
-ch_data_out\[25\]
-ch_data_out\[24\]
-ch_data_out\[23\]
+ch_data_out\[23\] 000 0 2
ch_data_out\[22\]
ch_data_out\[21\]
ch_data_out\[20\]
-ch_data_out\[3\]
+ch_data_out\[3\] 050 0 2
ch_data_out\[2\]
ch_data_out\[1\]
ch_data_out\[0\]
@@ -189,6 +269,7 @@
ch_clk_out\[0\]
m1_wbd_stb_i 100 0 2
+m1_wbd_cyc_i
m1_wbd_we_i
m1_wbd_adr_i\[31\]
m1_wbd_adr_i\[30\]
@@ -294,12 +375,12 @@
m1_wbd_dat_o\[2\]
m1_wbd_dat_o\[1\]
m1_wbd_dat_o\[0\]
-m1_wbd_ack_o
m1_wbd_lack_o
+m1_wbd_ack_o
m1_wbd_err_o
-m1_wbd_cyc_i
m2_wbd_stb_i 300 0 2
+m2_wbd_cyc_i
m2_wbd_we_i
m2_wbd_adr_i\[31\]
m2_wbd_adr_i\[30\]
@@ -415,9 +496,9 @@
m2_wbd_ack_o
m2_wbd_lack_o
m2_wbd_err_o
-m2_wbd_cyc_i
m3_wbd_stb_i 500 0 2
+m3_wbd_cyc_i
m3_wbd_we_i
m3_wbd_adr_i\[31\]
m3_wbd_adr_i\[30\]
@@ -501,8 +582,72 @@
m3_wbd_ack_o
m3_wbd_lack_o
m3_wbd_err_o
-m3_wbd_cyc_i
+ch_data_out\[43\] 650 0 2
+ch_data_out\[42\]
+ch_data_out\[41\]
+ch_data_out\[40\]
+ch_data_out\[39\]
+ch_data_out\[38\]
+ch_data_out\[37\]
+ch_data_out\[36\]
+ch_data_out\[35\]
+ch_data_out\[34\]
+ch_data_out\[33\]
+ch_data_out\[32\]
+ch_data_out\[31\]
+ch_data_out\[30\]
+ch_data_out\[29\]
+ch_data_out\[28\]
+
+ch_data_out\[76\] 1600 0 2
+ch_data_out\[75\]
+ch_data_out\[74\]
+ch_data_out\[73\]
+ch_data_out\[72\]
+ch_data_out\[71\]
+ch_data_out\[70\]
+ch_data_out\[69\]
+ch_data_out\[68\]
+ch_data_out\[67\]
+ch_data_out\[66\]
+ch_data_out\[65\]
+ch_data_out\[64\]
+ch_data_out\[63\]
+ch_data_out\[62\]
+ch_data_out\[61\]
+ch_data_out\[60\]
+ch_data_out\[59\]
+ch_data_out\[58\]
+ch_data_out\[57\]
+ch_data_out\[56\]
+ch_data_out\[55\]
+ch_data_out\[54\]
+ch_data_out\[53\]
+ch_data_out\[52\]
+ch_data_out\[51\]
+ch_data_out\[50\]
+ch_data_out\[49\]
+ch_data_out\[48\]
+ch_data_out\[47\]
+ch_data_out\[46\]
+ch_data_out\[45\]
+ch_data_out\[44\]
+
+ch_data_out\[27\]
+ch_data_out\[26\]
+ch_data_out\[25\]
+ch_data_out\[24\]
+
+ch_data_out\[153\] 1700 0 2
+ch_data_out\[152\]
+ch_data_out\[151\]
+ch_data_out\[150\]
+
+ch_data_out\[149\]
+ch_data_out\[148\]
+ch_data_out\[147\]
+ch_data_out\[146\]
#E
ch_data_out\[19\] 0000 0 2
@@ -633,13 +778,13 @@
s0_wbd_cyc_o
-ch_data_out\[11\] 0700 0 2
+ch_data_out\[11\] 0650 0 2
ch_data_out\[10\]
ch_data_out\[9\]
ch_data_out\[8\]
ch_clk_out\[2\]
-s1_wbd_stb_o 0800 0 2
+s1_wbd_stb_o 0750 0 2
s1_wbd_we_o
s1_wbd_adr_o\[8\]
s1_wbd_adr_o\[7\]
@@ -721,7 +866,106 @@
s1_wbd_ack_i
s1_wbd_cyc_o
-ch_data_in\[52\] 1500 0 2
+
+ch_data_in\[145\] 1350 0 2
+ch_data_in\[144\]
+ch_data_in\[143\]
+ch_data_in\[142\]
+ch_data_in\[141\]
+ch_data_in\[140\]
+ch_data_in\[139\]
+ch_data_in\[138\]
+ch_data_in\[137\]
+ch_data_in\[136\]
+ch_data_in\[135\]
+ch_data_in\[134\]
+ch_data_in\[133\]
+ch_data_in\[132\]
+ch_data_in\[131\]
+ch_data_in\[130\]
+ch_data_in\[129\]
+ch_data_in\[128\]
+ch_data_in\[127\]
+ch_data_in\[126\]
+ch_data_in\[125\]
+ch_data_in\[124\]
+ch_data_in\[123\]
+ch_data_in\[122\]
+ch_data_in\[121\]
+ch_data_in\[120\]
+ch_data_in\[119\]
+ch_data_in\[118\]
+ch_data_in\[117\]
+ch_data_in\[116\]
+ch_data_in\[115\]
+ch_data_in\[114\]
+
+ch_data_in\[113\]
+ch_data_in\[112\]
+
+
+ch_data_out\[111\]
+ch_data_out\[110\]
+ch_data_out\[109\]
+ch_data_out\[108\]
+ch_data_out\[107\]
+ch_data_out\[106\]
+ch_data_out\[105\]
+ch_data_out\[104\]
+ch_data_out\[103\]
+ch_data_out\[102\]
+ch_data_out\[101\]
+ch_data_out\[100\]
+ch_data_out\[99\]
+ch_data_out\[98\]
+ch_data_out\[97\]
+ch_data_out\[96\]
+ch_data_out\[95\]
+ch_data_out\[94\]
+ch_data_out\[93\]
+ch_data_out\[92\]
+ch_data_out\[91\]
+ch_data_out\[90\]
+ch_data_out\[89\]
+ch_data_out\[88\]
+ch_data_out\[87\]
+ch_data_out\[86\]
+ch_data_out\[85\]
+ch_data_out\[84\]
+ch_data_out\[83\]
+ch_data_out\[82\]
+ch_data_out\[81\]
+ch_data_out\[80\]
+
+ch_data_out\[79\]
+ch_data_out\[78\]
+ch_data_out\[77\]
+
+ch_data_in\[76\] 1550 0 2
+ch_data_in\[75\]
+ch_data_in\[74\]
+ch_data_in\[73\]
+ch_data_in\[72\]
+ch_data_in\[71\]
+ch_data_in\[70\]
+ch_data_in\[69\]
+ch_data_in\[68\]
+ch_data_in\[67\]
+ch_data_in\[66\]
+ch_data_in\[65\]
+ch_data_in\[64\]
+ch_data_in\[63\]
+ch_data_in\[62\]
+ch_data_in\[61\]
+ch_data_in\[60\]
+ch_data_in\[59\]
+ch_data_in\[58\]
+ch_data_in\[57\]
+ch_data_in\[56\]
+ch_data_in\[55\]
+ch_data_in\[54\]
+ch_data_in\[53\]
+ch_data_in\[52\]
ch_data_in\[51\]
ch_data_in\[50\]
ch_data_in\[49\]
@@ -730,30 +974,6 @@
ch_data_in\[46\]
ch_data_in\[45\]
ch_data_in\[44\]
-ch_data_in\[43\]
-ch_data_in\[42\]
-ch_data_in\[41\]
-ch_data_in\[40\]
-ch_data_in\[39\]
-ch_data_in\[38\]
-ch_data_in\[37\]
-ch_data_in\[36\]
-ch_data_in\[35\]
-ch_data_in\[34\]
-ch_data_in\[33\]
-ch_data_in\[32\]
-ch_data_in\[31\]
-ch_data_in\[30\]
-ch_data_in\[29\]
-ch_data_in\[28\]
-ch_data_in\[27\]
-ch_data_in\[26\]
-ch_data_in\[25\]
-ch_data_in\[24\]
-ch_data_in\[23\]
-ch_data_in\[22\]
-ch_data_in\[21\]
-ch_data_in\[20\]
ch_data_out\[15\]
ch_data_out\[14\]
@@ -761,7 +981,7 @@
ch_data_out\[12\]
ch_clk_out\[3\]
-s2_wbd_stb_o 1600 0 2
+s2_wbd_stb_o 1610 0 2
s2_wbd_we_o
s2_wbd_adr_o\[9\]
s2_wbd_adr_o\[8\]
@@ -844,3 +1064,4 @@
s2_wbd_ack_i
s2_wbd_cyc_o
+
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index 03cc613..160df0d 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -33,6 +33,8 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_core_top.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dm.sv \
@@ -77,7 +79,7 @@
set ::env(DIE_AREA) "0 0 540 950 "
set ::env(PL_TARGET_DENSITY) 0.45
-set ::env(CELL_PAD) "8"
+#set ::env(CELL_PAD) "8"
## Routing
set ::env(GRT_ADJUSTMENT) 0.2
@@ -90,7 +92,7 @@
set ::env(DIODE_INSERTION_STRATEGY) 3
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
@@ -107,7 +109,11 @@
set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
#PDN
set ::env(FP_PDN_VPITCH) 100
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index 8fc1648..222f71f 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -336,6 +336,12 @@
rst_n
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
clk
clk_o
diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl
index 943e7e6..fdcd6df 100644
--- a/openlane/ycr_iconnect/config.tcl
+++ b/openlane/ycr_iconnect/config.tcl
@@ -34,6 +34,8 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_router.sv \
@@ -43,7 +45,6 @@
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_timer.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_arb.sv \
- $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo2.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv \
"
@@ -60,24 +61,28 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 380 1100"
+set ::env(DIE_AREA) "0 0 400 1100"
set ::env(PL_TARGET_DENSITY) 0.20
-#set ::env(CELL_PAD) 2
+set ::env(CELL_PAD) 8
#set ::env(GRT_ADJUSTMENT) {0.2}
-#set ::env(GLB_RT_ADJUSTMENT) {0.2}
#set ::env(PL_ROUTABILITY_DRIVEN) "1"
set ::env(PL_TIME_DRIVEN) "1"
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
set ::env(DIODE_INSERTION_STRATEGY) 3
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/ycr_iconnect/pin_order.cfg b/openlane/ycr_iconnect/pin_order.cfg
index 2ecb2b2..254fda4 100644
--- a/openlane/ycr_iconnect/pin_order.cfg
+++ b/openlane/ycr_iconnect/pin_order.cfg
@@ -816,8 +816,8 @@
riscv_debug\[1\]
riscv_debug\[0\]
-#N
-core_irq_lines_i\[31\]
+#E
+core_irq_lines_i\[31\] 850 0 2
core_irq_lines_i\[30\]
core_irq_lines_i\[29\]
core_irq_lines_i\[28\]
@@ -851,9 +851,178 @@
core_irq_lines_i\[0\]
core_irq_soft_i
+cfg_ccska\[3\]
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
core_clk
rtc_clk
pwrup_rst_n
cpu_intf_rst_n
cfg_bypass_icache
cfg_bypass_dcache
+
+
+#N
+aes_dmem_req_ack
+aes_dmem_req
+aes_dmem_cmd
+aes_dmem_width\[1\]
+aes_dmem_width\[0\]
+aes_dmem_addr\[6\]
+aes_dmem_addr\[5\]
+aes_dmem_addr\[4\]
+aes_dmem_addr\[3\]
+aes_dmem_addr\[2\]
+aes_dmem_addr\[1\]
+aes_dmem_addr\[0\]
+aes_dmem_wdata\[31\]
+aes_dmem_wdata\[30\]
+aes_dmem_wdata\[29\]
+aes_dmem_wdata\[28\]
+aes_dmem_wdata\[27\]
+aes_dmem_wdata\[26\]
+aes_dmem_wdata\[25\]
+aes_dmem_wdata\[24\]
+aes_dmem_wdata\[23\]
+aes_dmem_wdata\[22\]
+aes_dmem_wdata\[21\]
+aes_dmem_wdata\[20\]
+aes_dmem_wdata\[19\]
+aes_dmem_wdata\[18\]
+aes_dmem_wdata\[17\]
+aes_dmem_wdata\[16\]
+aes_dmem_wdata\[15\]
+aes_dmem_wdata\[14\]
+aes_dmem_wdata\[13\]
+aes_dmem_wdata\[12\]
+aes_dmem_wdata\[11\]
+aes_dmem_wdata\[10\]
+aes_dmem_wdata\[9\]
+aes_dmem_wdata\[8\]
+aes_dmem_wdata\[7\]
+aes_dmem_wdata\[6\]
+aes_dmem_wdata\[5\]
+aes_dmem_wdata\[4\]
+aes_dmem_wdata\[3\]
+aes_dmem_wdata\[2\]
+aes_dmem_wdata\[1\]
+aes_dmem_wdata\[0\]
+aes_dmem_rdata\[31\]
+aes_dmem_rdata\[30\]
+aes_dmem_rdata\[29\]
+aes_dmem_rdata\[28\]
+aes_dmem_rdata\[27\]
+aes_dmem_rdata\[26\]
+aes_dmem_rdata\[25\]
+aes_dmem_rdata\[24\]
+aes_dmem_rdata\[23\]
+aes_dmem_rdata\[22\]
+aes_dmem_rdata\[21\]
+aes_dmem_rdata\[20\]
+aes_dmem_rdata\[19\]
+aes_dmem_rdata\[18\]
+aes_dmem_rdata\[17\]
+aes_dmem_rdata\[16\]
+aes_dmem_rdata\[15\]
+aes_dmem_rdata\[14\]
+aes_dmem_rdata\[13\]
+aes_dmem_rdata\[12\]
+aes_dmem_rdata\[11\]
+aes_dmem_rdata\[10\]
+aes_dmem_rdata\[9\]
+aes_dmem_rdata\[8\]
+aes_dmem_rdata\[7\]
+aes_dmem_rdata\[6\]
+aes_dmem_rdata\[5\]
+aes_dmem_rdata\[4\]
+aes_dmem_rdata\[3\]
+aes_dmem_rdata\[2\]
+aes_dmem_rdata\[1\]
+aes_dmem_rdata\[0\]
+aes_dmem_resp\[1\]
+aes_dmem_resp\[0\]
+
+
+
+fpu_dmem_req_ack 0200 0 2
+fpu_dmem_req
+fpu_dmem_cmd
+fpu_dmem_width\[1\]
+fpu_dmem_width\[0\]
+fpu_dmem_addr\[4\]
+fpu_dmem_addr\[3\]
+fpu_dmem_addr\[2\]
+fpu_dmem_addr\[1\]
+fpu_dmem_addr\[0\]
+fpu_dmem_wdata\[31\]
+fpu_dmem_wdata\[30\]
+fpu_dmem_wdata\[29\]
+fpu_dmem_wdata\[28\]
+fpu_dmem_wdata\[27\]
+fpu_dmem_wdata\[26\]
+fpu_dmem_wdata\[25\]
+fpu_dmem_wdata\[24\]
+fpu_dmem_wdata\[23\]
+fpu_dmem_wdata\[22\]
+fpu_dmem_wdata\[21\]
+fpu_dmem_wdata\[20\]
+fpu_dmem_wdata\[19\]
+fpu_dmem_wdata\[18\]
+fpu_dmem_wdata\[17\]
+fpu_dmem_wdata\[16\]
+fpu_dmem_wdata\[15\]
+fpu_dmem_wdata\[14\]
+fpu_dmem_wdata\[13\]
+fpu_dmem_wdata\[12\]
+fpu_dmem_wdata\[11\]
+fpu_dmem_wdata\[10\]
+fpu_dmem_wdata\[9\]
+fpu_dmem_wdata\[8\]
+fpu_dmem_wdata\[7\]
+fpu_dmem_wdata\[6\]
+fpu_dmem_wdata\[5\]
+fpu_dmem_wdata\[4\]
+fpu_dmem_wdata\[3\]
+fpu_dmem_wdata\[2\]
+fpu_dmem_wdata\[1\]
+fpu_dmem_wdata\[0\]
+fpu_dmem_rdata\[31\]
+fpu_dmem_rdata\[30\]
+fpu_dmem_rdata\[29\]
+fpu_dmem_rdata\[28\]
+fpu_dmem_rdata\[27\]
+fpu_dmem_rdata\[26\]
+fpu_dmem_rdata\[25\]
+fpu_dmem_rdata\[24\]
+fpu_dmem_rdata\[23\]
+fpu_dmem_rdata\[22\]
+fpu_dmem_rdata\[21\]
+fpu_dmem_rdata\[20\]
+fpu_dmem_rdata\[19\]
+fpu_dmem_rdata\[18\]
+fpu_dmem_rdata\[17\]
+fpu_dmem_rdata\[16\]
+fpu_dmem_rdata\[15\]
+fpu_dmem_rdata\[14\]
+fpu_dmem_rdata\[13\]
+fpu_dmem_rdata\[12\]
+fpu_dmem_rdata\[11\]
+fpu_dmem_rdata\[10\]
+fpu_dmem_rdata\[9\]
+fpu_dmem_rdata\[8\]
+fpu_dmem_rdata\[7\]
+fpu_dmem_rdata\[6\]
+fpu_dmem_rdata\[5\]
+fpu_dmem_rdata\[4\]
+fpu_dmem_rdata\[3\]
+fpu_dmem_rdata\[2\]
+fpu_dmem_rdata\[1\]
+fpu_dmem_rdata\[0\]
+fpu_dmem_resp\[1\]
+fpu_dmem_resp\[0\]
+
+
+
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 14c8aba..2f2e6d0 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -78,7 +78,7 @@
set ::env(DIODE_INSERTION_STRATEGY) 3
#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg
index 016df72..cbeff2f 100644
--- a/openlane/ycr_intf/pin_order.cfg
+++ b/openlane/ycr_intf/pin_order.cfg
@@ -391,7 +391,6 @@
wb_rst_n 500 0
pwrup_rst_n
-core_clk
cpu_intf_rst_n
#W
@@ -528,15 +527,24 @@
#E
-cfg_cska_riscv\[3\] 0000 0 2
-cfg_cska_riscv\[2\]
-cfg_cska_riscv\[1\]
-cfg_cska_riscv\[0\]
+cfg_ccska\[3\] 0000 0 2
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_int
+core_clk_skew
+core_clk
+
+cfg_wcska\[3\] 0050 0 2
+cfg_wcska\[2\]
+cfg_wcska\[1\]
+cfg_wcska\[0\]
wbd_clk_int
-wbd_clk_riscv
+wbd_clk_skew
wb_clk
wbd_dmem_stb_o 0100 0 2
+wbd_dmem_cyc_o
wbd_dmem_we_o
wbd_dmem_adr_o\[31\]
wbd_dmem_adr_o\[30\]
@@ -647,6 +655,7 @@
wbd_dmem_err_i
wb_dcache_stb_o 0300 0 2
+wb_dcache_cyc_o
wb_dcache_we_o
wb_dcache_adr_o\[31\]
wb_dcache_adr_o\[30\]
@@ -762,9 +771,9 @@
wb_dcache_ack_i
wb_dcache_lack_i
wb_dcache_err_i
-wb_dcache_cyc_o
wb_icache_stb_o 500 0 2
+wb_icache_cyc_o
wb_icache_we_o
wb_icache_adr_o\[31\]
wb_icache_adr_o\[30\]
@@ -848,7 +857,6 @@
wb_icache_ack_i
wb_icache_lack_i
wb_icache_err_i
-wb_icache_cyc_o
cfg_icache_pfet_dis
cfg_icache_ntag_pfet_dis
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index 9c9b9cd..e60a09c 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -1,165 +1,176 @@
- set ::env(USER_ROOT) ".."
- set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
- set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw7/sky130B"
+ set ::env(USER_ROOT) ".."
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
- read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
- read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core.v
- read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/DFFRAM.v
- read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v
- read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+
+
+ read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/RAM128.v
+ read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/RAM256.v
+ read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v
+
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/buff_flash_clkrst.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_signal_buffering_alt.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v
+ read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v
+
# User project netlist
- read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
- read_verilog $::env(USER_ROOT)/verilog/gl/ycr_iconnect.v
- read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
- read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
- read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
- read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
- read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
- read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v
- read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_iconnect.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/dg_pll.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/aes_top.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/fpu_wrapper.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
link_design caravel
- read_spef -path soc/DFFRAM_0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef
- read_spef -path soc/core $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core.spef
- read_spef -path soc $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core_wrapper.spef
- read_spef -path padframe $::env(CARAVEL_ROOT)/spef/chip_io.spef
- read_spef -path rstb_level $::env(CARAVEL_ROOT)/spef/xres_buf.spef
- read_spef -path pll $::env(CARAVEL_ROOT)/spef/digital_pll.spef
- read_spef -path housekeeping $::env(CARAVEL_ROOT)/spef/housekeeping.spef
- read_spef -path mgmt_buffers/powergood_check $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef
- read_spef -path mgmt_buffers/mprj_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef
- read_spef -path mgmt_buffers/mprj2_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef
- read_spef -path clocking $::env(CARAVEL_ROOT)/spef/caravel_clocking.spef
- read_spef -path mgmt_buffers $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef
- read_spef -path \gpio_control_bidir_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_bidir_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_bidir_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_bidir_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1a[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1a[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1a[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1a[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1a[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_1a[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[11] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[12] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[13] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[14] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[15] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path \gpio_control_in_2[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path gpio_defaults_block_0[0] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_0[1] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_5 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_6 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_7 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_8 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_9 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_10 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_11 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_12 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_13 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_14 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_15 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_16 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_17 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_18 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_19 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_20 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_21 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_22 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_23 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_24 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_25 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_26 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_27 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_28 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_29 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_2[0] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_2[1] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_2[2] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_30 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_31 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_32 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_33 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_34 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_35 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_36 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
- read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+
+ read_spef -path soc/core.RAM128 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/RAM128.spef
+ read_spef -path soc/core.RAM256 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/RAM256.spef
+ read_spef -path soc $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core_wrapper.spef
+ read_spef -path padframe $::env(CARAVEL_ROOT)/spef/chip_io.spef
+ read_spef -path rstb_level $::env(CARAVEL_ROOT)/spef/xres_buf.spef
+ read_spef -path pll $::env(CARAVEL_ROOT)/spef/digital_pll.spef
+ read_spef -path housekeeping $::env(CARAVEL_ROOT)/spef/housekeeping.spef
+ read_spef -path mgmt_buffers/powergood_check $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef
+ read_spef -path mgmt_buffers/mprj_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef
+ read_spef -path mgmt_buffers/mprj2_logic_high_inst $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef
+ read_spef -path mgmt_buffers $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef
+ read_spef -path \gpio_control_bidir_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_bidir_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_bidir_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_bidir_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_1a[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[0] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[10] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[11] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[12] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[13] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[14] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[15] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[1] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[2] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[3] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[4] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[5] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[6] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path \gpio_control_in_2[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+ read_spef -path gpio_defaults_block_0 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+ read_spef -path gpio_defaults_block_1 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+ read_spef -path gpio_defaults_block_2 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_3 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_4 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_5 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_6 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_7 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_8 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_9 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_10 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_11 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_12 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_13 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_14 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_15 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_16 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_17 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_18 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_19 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_20 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_21 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_22 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_23 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_24 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_25 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_26 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_27 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_28 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_29 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_30 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_31 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_32 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_33 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_34 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_35 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_36 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path flash_clkrst_buffers $::env(CARAVEL_ROOT)/spef/buff_flash_clkrst.spef
## User Project Spef
- read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/spef/ycr_iconnect.spef
- read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef
- read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef
- read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux_top.spef
- read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
- read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
- read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
- read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef
- read_spef -path mprj/u_pll $::env(USER_ROOT)/spef/digital_pll.spef
- read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
+ read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/spef/ycr_iconnect.spef
+ read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef
+ read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef
+ read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux_top.spef
+ read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
+ read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
+ read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
+ read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef
+ read_spef -path mprj/u_pll $::env(USER_ROOT)/spef/dg_pll.spef
+ read_spef -path mprj/u_aes $::env(USER_ROOT)/spef/aes_top.spef
+ read_spef -path mprj/u_fpu $::env(USER_ROOT)/spef/fpu_wrapper.spef
+ read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
+
+ read_spef $::env(CARAVEL_ROOT)/spef/caravel.spef
read_sdc -echo ./sdc/caravel.sdc
- set_propagated_clock [all_clocks]
check_setup -verbose > unconstraints.rpt
report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
@@ -168,6 +179,23 @@
report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10
report_check_types -max_slew -max_capacitance -max_fanout -violators > slew.cap.fanout.vio.rpt
+ echo " Management Area Interface "
+ report_checks -to soc/core_clk -unconstrained -group_count 1
+ echo " User project Interface "
+ report_checks -to mprj/wb_clk_i -unconstrained -group_count 1
+ report_checks -to mprj/wb_rst_i -unconstrained -group_count 1
+ report_checks -to mprj/wbs_cyc_i -unconstrained -group_count 1
+ report_checks -to mprj/wbs_stb_i -unconstrained -group_count 1
+ report_checks -to mprj/wbs_we_i -unconstrained -group_count 1
+ report_checks -to mprj/wbs_sel_i[*] -unconstrained -group_count 4
+ report_checks -to mprj/wbs_adr_i[*] -unconstrained -group_count 32
+ report_checks -to mprj/io_in[*] -unconstrained -group_count 32
+ report_checks -to mprj/user_clock2 -unconstrained -group_count 32
+ report_checks -to mprj/user_irq[*] -unconstrained -group_count 32
+ report_checks -to mprj/la_data_in[*] -unconstrained -group_count 128
+ report_checks -to mprj/la_oenb[*] -unconstrained -group_count 128
+
+
echo "Wishbone Interface Timing.................." > wb.max.rpt
echo "Wishbone Interface Timing.................." > wb.min.rpt
set wb_port [get_pins {mprj/wbs_adr_i[*]}]
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 327fed6..da521e3 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -1,24 +1,18 @@
-set ::env(IO_PCT) "0.2"
-set ::env(SYNTH_CAP_LOAD) "1"
set ::env(SYNTH_TIMING_DERATE) 0.01
set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25
set ::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) 0.25
set ::env(SYNTH_CLOCK_TRANSITION) 0.15
## MASTER CLOCKS
-create_clock [get_ports {"clock"} ] -name "master_clock" -period 25
-create_clock [get_pins clocking/user_clk ] -name "user_clk2" -period 25
-create_generated_clock -name csclk -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 1 -invert -comment {csclk} [get_pins housekeeping/_8847_/X]
-#create_clock [get_pins clocking/pll_clk ] -name "pll_clk" -period 25
-#create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25
-#create_clock [get_pins housekeeping/serial_clock ] -name "serial_clock" -period 50
-#create_clock [get_pins housekeeping/serial_load ] -name "serial_load" -period 50
+create_clock -name clk -period 25 [get_ports {clock}]
-create_generated_clock -name serial_clock -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 2 -comment {Serial Shift Clock} [get_pins housekeeping/serial_clock]
-create_generated_clock -name serial_load -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 2 -comment {Serial Shift Clock} [get_pins housekeeping/serial_load]
+create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ]
+create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
+create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
-create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks master_clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+### User Project Clocks
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clk] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_pinmux/int_pll_clock}]
create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
@@ -27,26 +21,100 @@
create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
create_clock -name cpu_clk -period 10.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
-create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_pinmux/rtc_clk}]
+create_clock -name rtc_ref_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
create_clock -name pll_ref_clk -period 20.0000 [get_pins {mprj/u_pinmux/pll_ref_clk}]
create_clock -name pll_clk_0 -period 5.0000 [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
create_clock -name usb_ref_clk -period 5.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
-create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_pinmux/usb_clk}]
+create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_usb.u_buf/X}]
create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name dbg_ref_clk -period 10.0000 [get_pins {mprj/u_pinmux/clkbuf_0_u_glbl_reg.dbg_clk_ref/X}]
-## Case analysis
+set_clock_groups \
+ -name clock_group \
+ -logically_exclusive \
+ -group [get_clocks {wb_clk clk}]\
+ -group [get_clocks {hk_serial_clk} ]\
+ -group [get_clocks {hk_serial_load} ]\
+ -group [get_clocks {hkspi_clk} ]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}]\
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {pll_ref_clk}]\
+ -group [get_clocks {pll_clk_0}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {uarts0_clk}]\
+ -group [get_clocks {uarts1_clk}]\
+ -group [get_clocks {uartm_clk}]\
+ -group [get_clocks {dbg_ref_clk}]\
+ -group [get_clocks {rtc_ref_clk}]\
+ -comment {Async Clock group}
+
+set_propagated_clock [all_clocks]
+
+set_max_fanout 12 [current_design]
+# synthesis max fanout should be less than 12 (7 maybe)
+
+
+######################################################
+# Caravel Case Analysis
+#######################################################
+#assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
+#assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
+#assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
+
+set_case_analysis 0 clock_ctrl/_205_/S
+set_case_analysis 0 clock_ctrl/_206_/S
+set_case_analysis 0 clock_ctrl/_208_/S
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
+set_case_analysis 0 [get_pins housekeeping/_3936_/S]
+set_case_analysis 0 [get_pins housekeeping/_3937_/S]
+
+# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0
+
+set_case_analysis 1 [get_pins padframe/*_pad/DM[2]]
+set_case_analysis 1 [get_pins padframe/*_pad/DM[1]]
+set_case_analysis 0 [get_pins padframe/*_pad/DM[0]]
+set_case_analysis 0 [get_pins padframe/*_pad/SLOW]
+set_case_analysis 0 [get_pins padframe/*_pad/ANALOG_EN]
+
+set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[2]]
+set_case_analysis 1 [get_pins padframe/*_io_pad*/DM[1]]
+set_case_analysis 0 [get_pins padframe/*_io_pad*/DM[0]]
+set_case_analysis 0 [get_pins padframe/*_io_pad*/SLOW]
+set_case_analysis 0 [get_pins padframe/*_io_pad*/ANALOG_EN]
+
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
+
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]]
+
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
+set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
+
+#################################################################
+## User Case analysis
+#################################################################
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}]
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}]
-
set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}]
set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}]
set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
@@ -62,10 +130,10 @@
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
@@ -73,10 +141,26 @@
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
-set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+# clock skew cntrl-2
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
+
#Keept the SRAM clock driving edge at pos edge
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
@@ -84,106 +168,132 @@
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
-#disable clock gating check at static clock select pins
-#set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.genblk1.u_mux/S]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_ccska[0]}]
-set_false_path -through [get_pins housekeeping/serial_resetn]
-#set_case_analysis 0 [get_pins housekeeping/serial_bb_enable]
-set_case_analysis 0 [get_pins housekeeping/_9787_/Q]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_ccska[0]}]
+############## Caravel False Path ########################################################
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
-set_propagated_clock [all_clocks]
+set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
+set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
+set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
+set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]]
+set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]]
+set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]]
+set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]]
+set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]]
+set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]]
+set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]]
+set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]]
+set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]]
+set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]]
+set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]]
+set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]]
+set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]]
+set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]]
+set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]]
+set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]]
+set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]]
+set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]]
+set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]]
+set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]]
+set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]]
+set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]]
+set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]]
+set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]]
+set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]]
+set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]]
+set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]]
+set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]]
+set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]]
+set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]]
+set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]]
+set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]]
+set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]]
-#set_multicycle_path -setup -from [get_clocks {master_clock}] -to [get_clocks {csclk}] 2
-#set_multicycle_path -hold -from [get_clocks {master_clock}] -to [get_clocks {csclk}] 2
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
-set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {wb_clk master_clock}]\
- -group [get_clocks {csclk} ]\
- -group [get_clocks {serial_clock} ]\
- -group [get_clocks {serial_load} ]\
- -group [get_clocks {user_clk2}]\
- -group [get_clocks {int_pll_clock}]\
- -group [get_clocks {wbs_clk_i}]\
- -group [get_clocks {wbs_ref_clk}]\
- -group [get_clocks {cpu_clk}]\
- -group [get_clocks {cpu_ref_clk}]\
- -group [get_clocks {rtc_clk}]\
- -group [get_clocks {usb_ref_clk}]\
- -group [get_clocks {pll_ref_clk}]\
- -group [get_clocks {pll_clk_0}]\
- -group [get_clocks {usb_clk}]\
- -group [get_clocks {uarts0_clk}]\
- -group [get_clocks {uarts1_clk}]\
- -group [get_clocks {uartm_clk}]\
- -comment {Async Clock group}
-## INPUT/OUTPUT DELAYS
-set input_delay_value 1
-set output_delay_value [expr 25 * $::env(IO_PCT)]
+################ Caravel Timing Constraints ##########################################################
+
+
+set input_delay_value 4
+set output_delay_value 4
puts "\[INFO\]: Setting output delay to: $output_delay_value"
puts "\[INFO\]: Setting input delay to: $input_delay_value"
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {gpio}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[0]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[1]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[2]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[3]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[4]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[5]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[6]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[7]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[8]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[9]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[10]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[11]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[12]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[13]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[14]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[15]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[16]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[17]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[18]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[19]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[20]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[21]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[22]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[23]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[24]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[25]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[26]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[27]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[28]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[29]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[30]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[31]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[32]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[33]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[34]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[35]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[36]}]
-set_input_delay $input_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {mprj_io[37]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
-set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_csb}]
-set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_clk}]
-set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_io0}]
-set_output_delay $output_delay_value -clock [get_clocks {master_clock}] -add_delay [get_ports {flash_io1}]
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
+
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
-## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
-set_case_analysis 0 [get_pins housekeeping/_4449_/S]
-set_case_analysis 0 [get_pins housekeeping/_4450_/S]
+####################################################################################################
-## FALSE PATHS (ASYNCHRONOUS INPUTS)
-set_false_path -from [get_ports {resetb}]
-set_false_path -from [get_ports mprj_io[*]]
-set_false_path -from [get_ports gpio]
+
+
# TODO set this as parameter
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+set cap_load 10
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
+#add input transition for the inputs pins
+set_input_transition 2 [all_inputs]
+
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
@@ -276,7 +386,3 @@
#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
-
-
-puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
-set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {master_clock}]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index bbb8f3f..3a02890 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,19 +19,19 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2
+PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_aes_core user_fpu_core
all: ${PATTERNS}
echo "################# RTL Test case Summary #####################" > regression.rpt
- #xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt &
- #for i in ${PATTERNS}; do \
- # ( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
- #done
- echo "################# GL Test case Summary #####################" >> regression.rpt
- \rm -rf */*.vvp
+ xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt &
for i in ${PATTERNS}; do \
- ( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
+ ( cd $$i && make | tee run.rtl.log && grep Monitor run.rtl.log | grep $$i >> ../regression.rpt) ; \
done
+ #echo "################# GL Test case Summary #####################" >> regression.rpt
+ #\rm -rf */*.vvp
+ #for i in ${PATTERNS}; do \
+ # ( cd $$i && make SIM=GL | tee run.gl.log && grep Monitor run.gl.log | grep $$i >> ../regression.rpt) ; \
+ #done
echo "################# End of Test case Summary #####################" >> regression.rpt
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index b618915..368b494 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -168,7 +168,7 @@
tb_uart.uart_init;
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
- repeat (1000) @(posedge clock); // wait for Processor Get Ready
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
index 7f5b1c0..7cce107 100644
--- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -205,6 +205,7 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
dCnt = 0;
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index d1141a8..6f91eae 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -165,7 +165,7 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- repeat (1000) @(posedge clock); // wait for Processor Get Ready
+ repeat (8000) @(posedge clock); // wait for Processor Get Ready
flag = 1;
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index 72c3fbe..1ae2309 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -117,13 +117,14 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(3, `TB_TOP);
- $dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0);
- $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect);
- $dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf);
- $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_uart0_core);
- $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm);
- $dumpvars(0, `TB_TOP.u_top.u_pinmux);
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(0, `TB_TOP.tb_uart);
+ //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.i_core_top_0);
+ //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_connect);
+ //$dumpvars(0, `TB_TOP.u_top.u_riscv_top.u_intf);
+ $dumpvars(1, `TB_TOP.u_top.u_uart_i2c_usb_spi);
+ //$dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi.u_i2cm);
+ //$dumpvars(0, `TB_TOP.u_top.u_pinmux);
end
`endif
@@ -172,13 +173,13 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- u_i2c_slave_0.debug = 0; // disable i2c bfm debug message
- u_i2c_slave_1.debug = 0; // disable i2c bfm debug message
- u_i2c_slave_2.debug = 0; // disable i2c bfm debug message
- u_i2c_slave_3.debug = 0; // disable i2c bfm debug message
- u_i2c_slave_4.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_0.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_1.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_2.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_3.debug = 0; // disable i2c bfm debug message
+ u_i2c_slave_4.debug = 0; // disable i2c bfm debug message
- repeat (1000) @(posedge clock); // wait for Processor Get Ready
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
compare_start = 1;
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
index 40f9df8..882a549 100644
--- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -175,7 +175,7 @@
u_i2c_slave_0.debug = 1; // disable i2c bfm debug message
u_i2c_slave_1.debug = 1; // disable i2c bfm debug message
- repeat (1000) @(posedge clock); // wait for Processor Get Ready
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
compare_start = 1;
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
index abbaa1d..f3f29e1 100644
--- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -175,7 +175,7 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- repeat (1000) @(posedge clock); // wait for Processor Get Ready
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
compare_start = 1;
diff --git a/verilog/dv/common/agents/caravel_task.sv b/verilog/dv/common/agents/caravel_task.sv
index 83a9c70..70ff764 100644
--- a/verilog/dv/common/agents/caravel_task.sv
+++ b/verilog/dv/common/agents/caravel_task.sv
@@ -170,3 +170,33 @@
endgenerate
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+// for 230400 Baud = (50Mhz/230400) = 216.7
+baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+// Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+// Test bench baud clock , 16x of above value
+// 13 * 16 = 208,
+// (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+// Test bench half cycle counter to toggle it
+// 208/2 = 104
+ baud_div = baud_div/2;
+//As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 8425b64..6bda236 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,7 @@
begin
// Run in Fast Sim Mode
`ifdef GL
- force u_top.u_wb_host._09718_.Q= 1'b1;
+ force u_top.u_wb_host._10673_.Q= 1'b1;
`else
force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1;
`endif
diff --git a/verilog/dv/common/firmware/int_reg_map.h b/verilog/dv/common/firmware/int_reg_map.h
index fa79ec1..4c56c49 100644
--- a/verilog/dv/common/firmware/int_reg_map.h
+++ b/verilog/dv/common/firmware/int_reg_map.h
@@ -90,3 +90,50 @@
#define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x1001011C) // Reg-7
#define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x10010120) // Reg-8
+// AES Encription Register
+#define reg_aes_enc_ctrl (*(volatile uint32_t*)0x0C490080) // Reg-0
+
+#define reg_aes_enc_key_dw0 (*(volatile uint32_t*)0x0C490084) // Reg-1
+#define reg_aes_enc_key_dw1 (*(volatile uint32_t*)0x0C490088) // Reg-2
+#define reg_aes_enc_key_dw2 (*(volatile uint32_t*)0x0C49008C) // Reg-3
+#define reg_aes_enc_key_dw3 (*(volatile uint32_t*)0x0C490090) // Reg-4
+#define reg_aes_enc_key_bptr (*(volatile uint8_t*)0x0C490093) // Last Addr Location
+
+#define reg_aes_enc_text_in_dw0 (*(volatile uint32_t*)0x0C490094) // Reg-5
+#define reg_aes_enc_text_in_dw1 (*(volatile uint32_t*)0x0C490098) // Reg-6
+#define reg_aes_enc_text_in_dw2 (*(volatile uint32_t*)0x0C49009C) // Reg-7
+#define reg_aes_enc_text_in_dw3 (*(volatile uint32_t*)0x0C4900A0) // Reg-8
+#define reg_aes_enc_text_in_bptr (*(volatile uint8_t*)0x0C4900A3) // Last Addr Location
+
+#define reg_aes_enc_text_out_dw0 (*(volatile uint32_t*)0x0C4900A4) // Reg-9
+#define reg_aes_enc_text_out_dw1 (*(volatile uint32_t*)0x0C4900A8) // Reg-10
+#define reg_aes_enc_text_out_dw2 (*(volatile uint32_t*)0x0C4900AC) // Reg-11
+#define reg_aes_enc_text_out_dw3 (*(volatile uint32_t*)0x0C4900B0) // Reg-12
+#define reg_aes_enc_text_out_bptr (*(volatile uint8_t*)0x0C4900B3) // Last Addr Location
+
+// AES Decryption Register
+#define reg_aes_dec_ctrl (*(volatile uint32_t*)0x0C4900C0) // Reg-0
+#define reg_aes_dec_key_dw0 (*(volatile uint32_t*)0x0C4900C4) // Reg-1
+#define reg_aes_dec_key_dw1 (*(volatile uint32_t*)0x0C4900C8) // Reg-2
+#define reg_aes_dec_key_dw2 (*(volatile uint32_t*)0x0C4900CC) // Reg-3
+#define reg_aes_dec_key_dw3 (*(volatile uint32_t*)0x0C4900D0) // Reg-4
+#define reg_aes_dec_key_bptr (*(volatile uint8_t*)0x0C4900D3) // Last Addr Location
+
+#define reg_aes_dec_text_in_dw0 (*(volatile uint32_t*)0x0C4900D4) // Reg-5
+#define reg_aes_dec_text_in_dw1 (*(volatile uint32_t*)0x0C4900D8) // Reg-6
+#define reg_aes_dec_text_in_dw2 (*(volatile uint32_t*)0x0C4900DC) // Reg-7
+#define reg_aes_dec_text_in_dw3 (*(volatile uint32_t*)0x0C4900E0) // Reg-8
+#define reg_aes_dec_text_in_bptr (*(volatile uint8_t*)0x0C4900E3) // Last Addr Location
+
+#define reg_aes_dec_text_out_dw0 (*(volatile uint32_t*)0x0C4900E4) // Reg-9
+#define reg_aes_dec_text_out_dw1 (*(volatile uint32_t*)0x0C4900E8) // Reg-10
+#define reg_aes_dec_text_out_dw2 (*(volatile uint32_t*)0x0C4900EC) // Reg-11
+#define reg_aes_dec_text_out_dw3 (*(volatile uint32_t*)0x0C4900F0) // Reg-12
+#define reg_aes_dec_text_out_bptr (*(volatile uint8_t*)0x0C4900F3) // Last Addr Location
+
+// FPU Core
+#define reg_fpu_ctrl (*(volatile uint32_t*)0x0C490100) // Reg-0
+#define reg_fpu_din1 (*(volatile uint32_t*)0x0C490104) // Reg-1
+#define reg_fpu_din2 (*(volatile uint32_t*)0x0C490108) // Reg-2
+#define reg_fpu_res (*(volatile uint32_t*)0x0C49010C) // Reg-3
+
diff --git a/verilog/dv/uart_master_test2/uart_master_test2_tb.v b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
index 6ed5609..257363e 100644
--- a/verilog/dv/uart_master_test2/uart_master_test2_tb.v
+++ b/verilog/dv/uart_master_test2/uart_master_test2_tb.v
@@ -99,34 +99,6 @@
$display("%c[0m",27);
$finish;
end
- /*************************************************************************
- * This is Baud Rate to clock divider conversion for Test Bench
- * Note: DUT uses 16x baud clock, where are test bench uses directly
- * baud clock, Due to 16x Baud clock requirement at RTL, there will be
- * some resolution loss, we expect at lower baud rate this resolution
- * loss will be less. For Quick simulation perpose higher baud rate used
- * *************************************************************************/
- task tb_set_uart_baud;
- input [31:0] ref_clk;
- input [31:0] baud_rate;
- output [31:0] baud_div;
- reg [31:0] baud_div;
- begin
- // for 230400 Baud = (50Mhz/230400) = 216.7
- baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
- // Baud 16x = 216/16 = 13
- baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
- // Test bench baud clock , 16x of above value
- // 13 * 16 = 208,
- // (Note if you see original value was 216, now it's 208 )
- baud_div = baud_div * 16;
- // Test bench half cycle counter to toggle it
- // 208/2 = 104
- baud_div = baud_div/2;
- //As counter run's from 0 , substract from 1
- baud_div = baud_div-1;
- end
- endtask
initial begin
diff --git a/verilog/dv/user_aes/user_aes.c b/verilog/dv/user_aes/user_aes.c
index 2830ebe..1b7a697 100644
--- a/verilog/dv/user_aes/user_aes.c
+++ b/verilog/dv/user_aes/user_aes.c
@@ -60,6 +60,7 @@
reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART
reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
reg_glbl_multi_func |=0x100; // Enable UART Multi func
+ reg_gpio_dsel =0xFF00; // Enable PORT B As output
reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
// GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
// bit[7:0] - core-0
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v
index 3d47bd3..55aba10 100644
--- a/verilog/dv/user_aes/user_aes_tb.v
+++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -21,9 +21,7 @@
//// This file is part of the Riscduino cores project ////
//// ////
//// Description ////
-//// This is a standalone test bench to validate the ////
-//// Digital core with Risc core executing code from TCM/SRAM. ////
-//// with icache and dcache bypass mode ////
+//// To validate Software AES Encription & Decription ////
//// ////
//// To Do: ////
//// nothing ////
@@ -32,7 +30,7 @@
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 7th Nov 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -98,24 +96,24 @@
/************* Port-B Mapping **********************************
- * Pin-14 PB0/CLKO/ICP1 digital_io[11]
- * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[12]
- * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13]
- * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14]
- * Pin-18 PB4/MISO digital_io[15]
- * Pin-19 PB5/SCK digital_io[16]
- * Pin-9 PB6/XTAL1/TOSC1 digital_io[6]
- * Pin-10 PB7/XTAL2/TOSC2 digital_io[7]
+ * Pin-14 PB0/CLKO/ICP1 digital_io[16]
+ * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[17]
+ * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[18]
+ * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[19]
+ * Pin-18 PB4/MISO digital_io[20]
+ * Pin-19 PB5/SCK digital_io[21]
+ * Pin-9 PB6/XTAL1/TOSC1 digital_io[11]
+ * Pin-10 PB7/XTAL2/TOSC2 digital_io[12]
* ********************************************************/
- wire [7:0] port_b_in = { io_out[7],
- io_out[6],
- io_out[16],
- io_out[15],
- io_out[14],
- io_out[13],
- io_out[12],
- io_out[11]
+ wire [7:0] port_b_in = { io_out[12],
+ io_out[11],
+ io_out[21],
+ io_out[20],
+ io_out[19],
+ io_out[18],
+ io_out[17],
+ io_out[16]
};
initial begin
test_fail = 0;
@@ -195,7 +193,7 @@
repeat (1400000) @(posedge clock);
end
begin
- wait(port_b_in == 8'h18);
+ wait(port_b_in == 8'h18 || port_b_in == 8'hA8);
end
begin
while(1) begin
diff --git a/verilog/dv/user_aes_core/Makefile b/verilog/dv/user_aes_core/Makefile
new file mode 100644
index 0000000..8dc518c
--- /dev/null
+++ b/verilog/dv/user_aes_core/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_aes_core
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/sc_print.c -o sc_print.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+ ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o sc_print.o crt.o -nostartfiles -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+ rm crt.o ${PATTERN}.o
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_aes_core/user_aes_core.c b/verilog/dv/user_aes_core/user_aes_core.c
new file mode 100644
index 0000000..43b3dec
--- /dev/null
+++ b/verilog/dv/user_aes_core/user_aes_core.c
@@ -0,0 +1,196 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+#define SC_SIM_OUTPORT (0xf0000000)
+
+
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+
+// Enable ECB, CTR and CBC mode. Note this can be done before including aes.h or at compile-time.
+// E.g. with GCC by using the -D flag: gcc -c aes.c -DCBC=0 -DCTR=1 -DECB=1
+#define CBC 1
+#define AES_BLOCKLEN 16
+
+//#include "aes.h"
+#include "int_reg_map.h"
+#include "common_misc.h"
+#include "common_bthread.h"
+
+static const uint8_t key[] = { 0x44, 0x69, 0x6e, 0x65, 0x73, 0x68, 0x20, 0x20, 0x20, 0x41, 0x6e, 0x6e, 0x61, 0x79, 0x79, 0x61 };
+static const uint8_t enc_text[] = { 0xFE, 0x67, 0x23, 0x29, 0xDE, 0x2C, 0x41, 0xCE, 0x75, 0x79, 0x28, 0x12, 0xA0, 0x35, 0x66, 0xD0,
+ 0xC4, 0xBB, 0x67, 0x66, 0xAC, 0x09, 0x5B, 0xF7, 0xA9, 0xAF, 0x5D, 0x1C, 0xEC, 0xCE, 0x44, 0x54,
+ 0x44, 0x84, 0xCF, 0xBB, 0x0A, 0x37, 0x7A, 0xC4, 0x41, 0x3F, 0xD1, 0x86, 0x28, 0xBC, 0x18, 0x0C,
+ 0x8D, 0x08, 0xB4, 0xAB, 0x58, 0x88, 0xC0, 0xBF, 0x3D, 0xBC, 0xDD, 0x15, 0xB2, 0x31, 0x98, 0x66,
+ 0x00, 0xA9, 0x40, 0x2C, 0x88, 0x4C, 0xD4, 0x85, 0x1A, 0xF8, 0xD8, 0xB3, 0x42, 0xE4, 0xF3, 0x3D,
+ 0xBC, 0xB2, 0x2A, 0x5A, 0x6A, 0x24, 0x93, 0x24, 0xAC, 0xC1, 0x05, 0xE7, 0xAE, 0x75, 0xD1, 0xB2,
+ 0x90, 0x9A, 0xE8, 0xE5, 0xEF, 0x57, 0x24, 0x08, 0x74, 0xDA, 0x98, 0x85, 0x56, 0xF0, 0x38, 0xFB,
+ 0xF2, 0x04, 0xD1, 0xE9, 0x77, 0x2B, 0x9F, 0x62, 0x37, 0x0B, 0x08, 0x0F, 0x40, 0xC1, 0x70, 0xC1,
+ 0x11, 0x76, 0xC1, 0x61, 0xAF, 0x65, 0x57, 0x81, 0x31, 0x0C, 0xE9, 0x02, 0x9B, 0x75, 0x0F, 0x12 };
+
+static const uint8_t plain_text[]= { 0x52, 0x69, 0x73, 0x63, 0x64, 0x75, 0x69, 0x6e, 0x6f, 0x20, 0x69, 0x73, 0x20, 0x61, 0x20, 0x53,
+ 0x69, 0x6e, 0x67, 0x6c, 0x65, 0x20, 0x33, 0x32, 0x20, 0x62, 0x69, 0x74, 0x20, 0x52, 0x49, 0x53,
+ 0x43, 0x20, 0x56, 0x20, 0x62, 0x61, 0x73, 0x65, 0x64, 0x20, 0x53, 0x4f, 0x43, 0x20, 0x64, 0x65,
+ 0x73, 0x69, 0x67, 0x6e, 0x20, 0x70, 0x69, 0x6e, 0x20, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69,
+ 0x62, 0x6c, 0x65, 0x20, 0x74, 0x6f, 0x20, 0x61, 0x72, 0x64, 0x75, 0x69, 0x6e, 0x6f, 0x20, 0x70,
+ 0x6c, 0x61, 0x74, 0x66, 0x6f, 0x72, 0x6d, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x74, 0x68, 0x69, 0x73,
+ 0x20, 0x73, 0x6f, 0x63, 0x20, 0x74, 0x61, 0x72, 0x67, 0x65, 0x74, 0x65, 0x64, 0x20, 0x66, 0x6f,
+ 0x72, 0x20, 0x65, 0x66, 0x61, 0x62, 0x6c, 0x65, 0x73, 0x73, 0x20, 0x53, 0x68, 0x75, 0x74, 0x74 };
+
+static void phex(uint8_t* str,uint8_t len);
+static int test_encrypt(void);
+static int test_decrypt(void);
+
+int main(void)
+{
+ int exit;
+
+ //printf("\nTesting AES128\n\n");
+
+ reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART
+ reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
+ reg_glbl_multi_func |=0x100; // Enable UART Multi func
+ reg_gpio_dsel =0xFF00; // Enable PORT B As output
+ reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
+
+ //// GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ //// bit[7:0] - core-0
+ //// bit[15:8] - core-1
+ //// bit[23:16] - core-2
+ //// bit[31:24] - core-3
+
+ reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main
+
+ reg_gpio_odata = 0x00000100;
+ reg_glbl_soft_reg_0 = 0x00000000;
+ exit = test_encrypt();
+ reg_gpio_odata = 0x00000200;
+
+ reg_glbl_soft_reg_0 = exit;
+ exit += test_decrypt();
+ reg_gpio_odata = 0x00000300;
+ reg_glbl_soft_reg_0 = exit;
+
+ if(exit == 0) {
+ reg_gpio_odata = 0x00001800;
+ } else {
+ reg_gpio_odata = 0x0000A800;
+ }
+
+ return exit;
+}
+
+
+// prints string as hex
+static void phex(uint8_t* str,uint8_t len )
+{
+
+ uint32_t iPayload;
+ unsigned char i,j;
+ for (i = 0; i < len; ++i)
+ printf("%.2x", str[i]);
+
+ printf("\n");
+
+ for (i = 0; i < len/4; ++i) {
+ iPayload = 0x00;
+ for (j = 0; j < 4; ++j) {
+ iPayload = (iPayload << 8) | str[(i*4)+j];
+ }
+ printf("%0x", iPayload);
+ }
+
+ printf("\n");
+}
+
+static int test_decrypt(void)
+{
+
+ uint8_t ErrCnt = 0x00;
+ unsigned char i,j;
+
+
+ for (i = 0; i < 8; i += 1) {
+ // Write 16B Encryption Text and Key
+ for (j = 0; j < 16; ++j) {
+ *(®_aes_dec_key_bptr-j) = key[j];
+ *(®_aes_dec_text_in_bptr-j) = enc_text[(i*AES_BLOCKLEN)+j];
+
+ }
+ // Enable the Decrption Engine and Wait for completion
+ reg_aes_dec_ctrl = 0x1;
+ while(reg_aes_dec_ctrl);
+
+ // Validate the 16B of Encrypted Data
+ for (j = 0; j < 16; ++j) {
+ if(plain_text[(i*AES_BLOCKLEN)+j] != *(®_aes_dec_text_out_bptr-j)) {
+ ErrCnt++;
+ }
+
+ }
+ }
+
+
+ if (ErrCnt == 0) {
+ //printf("SUCCESS!\n");
+ return(0);
+ } else {
+ //printf("FAILURE!\n");
+ return(1);
+ }
+}
+
+static int test_encrypt(void)
+{
+ uint8_t ErrCnt = 0x00;
+ unsigned char i,j;
+
+
+ for (i = 0; i < 8; i += 1) {
+ // Write 16B Plan Text and Key
+ for (j = 0; j < 16; ++j) {
+ *(®_aes_enc_key_bptr-j) = key[j];
+ *(®_aes_enc_text_in_bptr-j) = plain_text[(i*AES_BLOCKLEN)+j];
+
+ }
+ // Enable the Encryption Engine and Wait for completion
+ reg_aes_enc_ctrl = 0x1;
+ while(reg_aes_enc_ctrl);
+
+ // Validate the 16B of Encrypted Data
+ for (j = 0; j < 16; ++j) {
+ if(enc_text[(i*AES_BLOCKLEN)+j] != *(®_aes_enc_text_out_bptr-j)) {
+ ErrCnt++;
+ }
+
+ }
+ }
+
+ if (ErrCnt == 0) {
+ //printf("SUCCESS!\n");
+ return(0);
+ } else {
+ //printf("FAILURE!\n");
+ return(1);
+ }
+}
+
+
+
+
+
diff --git a/verilog/dv/user_aes_core/user_aes_core_tb.v b/verilog/dv/user_aes_core/user_aes_core_tb.v
new file mode 100644
index 0000000..017a14a
--- /dev/null
+++ b/verilog/dv/user_aes_core/user_aes_core_tb.v
@@ -0,0 +1,294 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the Riscduino cores project ////
+//// ////
+//// Description ////
+//// To validate AES IP Encription & Decription ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 7th Nov 2022, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+module user_aes_tb;
+
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+`include "user_tasks.sv"
+
+
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+reg [1:0] uart_data_bit ;
+reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+reg uart_stick_parity ; // 1: force even parity
+reg uart_parity_en ; // parity enable
+reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0] uart_data ;
+reg [15:0] uart_divisor ; // divided by n * 16
+reg [15:0] uart_timeout ;// wait time limit
+
+reg [15:0] uart_rx_nu ;
+reg [15:0] uart_tx_nu ;
+reg [7:0] uart_write_data [0:39];
+reg uart_fifo_enable ; // fifo mode disable
+
+
+
+ /************* Port-B Mapping **********************************
+ * Pin-14 PB0/CLKO/ICP1 digital_io[16]
+ * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[17]
+ * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[18]
+ * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[19]
+ * Pin-18 PB4/MISO digital_io[20]
+ * Pin-19 PB5/SCK digital_io[21]
+ * Pin-9 PB6/XTAL1/TOSC1 digital_io[11]
+ * Pin-10 PB7/XTAL2/TOSC2 digital_io[12]
+ * ********************************************************/
+
+ wire [7:0] port_b_in = { io_out[12],
+ io_out[11],
+ io_out[21],
+ io_out[20],
+ io_out[19],
+ io_out[18],
+ io_out[17],
+ io_out[16]
+ };
+ initial begin
+ test_fail = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(2, user_aes_tb);
+ $dumpvars(0, user_aes_tb.u_top.u_aes);
+ $dumpvars(0, user_aes_tb.u_top.u_riscv_top);
+ $dumpvars(0, user_aes_tb.u_top.u_pinmux);
+ end
+ `endif
+
+ initial begin
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
+
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ uart_divisor = 15;// divided by n * 16
+ uart_timeout = 500;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Uart Test Started");
+
+ // Remove Wb Reset
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ // Enable UART Multi Functional Ports
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
+
+ wait_riscv_boot();
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart.uart_init;
+ wb_user_core_write(`ADDR_SPACE_UART0+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ // Set the PORT-B Direction as Output
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h0000FF00);
+ // Set the GPIO Output data: 0x00000000
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000);
+
+ fork
+ begin
+ repeat (1400000) @(posedge clock);
+ end
+ begin
+ wait(port_b_in == 8'h18 || port_b_in == 8'hA8);
+ end
+ begin
+ while(1) begin
+ wb_user_core_read(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,read_data);
+ repeat (1000) @(posedge clock);
+ end
+ end
+ join_any
+
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000);
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+ $finish;
+
+ end
+
+
+
+// SSPI Slave I/F
+assign io_in[5] = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK
+
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[28];
+ wire flash_csb = io_out[29];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[33];
+ wire #1 io_oeb_30 = io_oeb[34];
+ wire #1 io_oeb_31 = io_oeb[35];
+ wire #1 io_oeb_32 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+
+ assign io_in[33] = flash_io0;
+ assign io_in[34] = flash_io1;
+ assign io_in[35] = flash_io2;
+ assign io_in[36] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("user_aes_core.hex"),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[7];
+assign io_in[6] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index feab774..2865bda 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -145,33 +145,33 @@
reg [1:0] strap_skew;
wire [31:0] skew_config;
-assign skew_config[3:0] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[3:0] :
- (strap_skew == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 :
- (strap_skew == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4;
+assign skew_config[3:0] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[3:0] :
+ (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[3:0] + 2 :
+ (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[3:0] + 4 : CLK_SKEW1_RESET_VAL[3:0]-4;
-assign skew_config[7:4] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[7:4] :
- (strap_skew == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 :
- (strap_skew == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4;
+assign skew_config[7:4] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[7:4] :
+ (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[7:4] + 2 :
+ (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[7:4] + 4 : CLK_SKEW1_RESET_VAL[7:4]-4;
-assign skew_config[11:8] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[11:8] :
- (strap_skew == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 :
- (strap_skew == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4;
+assign skew_config[11:8] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[11:8] :
+ (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[11:8] + 2 :
+ (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[11:8] + 4 : CLK_SKEW1_RESET_VAL[11:8]-4;
-assign skew_config[15:12] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[15:12] :
- (strap_skew == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 :
- (strap_skew == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4;
+assign skew_config[15:12] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[15:12] :
+ (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[15:12] + 2 :
+ (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[15:12] + 4 : CLK_SKEW1_RESET_VAL[15:12]-4;
-assign skew_config[19:16] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[19:16] :
- (strap_skew == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 :
- (strap_skew == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4;
+assign skew_config[19:16] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[19:16] :
+ (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[19:16] + 2 :
+ (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[19:16] + 4 : CLK_SKEW1_RESET_VAL[19:16]-4;
-assign skew_config[23:20] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[23:20] :
- (strap_skew == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 :
- (strap_skew == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4;
+assign skew_config[23:20] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[23:20] :
+ (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[23:20] + 2 :
+ (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[23:20] + 4 : CLK_SKEW1_RESET_VAL[23:20]-4;
-assign skew_config[27:24] = (strap_skew == 2'b00) ? SKEW_RESET_VAL[27:24] :
- (strap_skew == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 :
- (strap_skew == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4;
+assign skew_config[27:24] = (strap_skew == 2'b00) ? CLK_SKEW1_RESET_VAL[27:24] :
+ (strap_skew == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 :
+ (strap_skew == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
assign skew_config[31:28] = 4'b0;
@@ -194,7 +194,7 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(0, `TB_TOP);
+ $dumpvars(1, `TB_TOP);
$dumpvars(1, `TB_TOP.u_top);
$dumpvars(0, `TB_TOP.u_top.u_pll);
$dumpvars(0, `TB_TOP.u_top.u_wb_host);
@@ -279,7 +279,8 @@
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_PAD_STRAP,read_data,strap_in);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_STRAP_STICKY,read_data,strap_sticky);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SYSTEM_STRAP,read_data,strap_sticky);
- wb_user_core_read_check(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,read_data,clk_ctrl2);
+ wb_user_core_read(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,read_data);
+ if(read_data[23:16] != clk_ctrl2) test_fail = 1;
clock_monitor2(cpu_clk_cfg,wbs_clk_cfg);
end
end
@@ -479,9 +480,40 @@
`endif
$display("##########################################################");
- $display("Step-10,Monitor: Checking the chip signature :");
- $display("###################################################");
+ $display("Step-10,Monitor: Analog Config checks ");
+ $display("##########################################################");
test_id = 10;
+ test_step = 14;
+
+ // Remove Wb/PinMux Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC0,'h11);
+ wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC1,'h22);
+ wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC2,'h33);
+ wb_user_core_write(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC3,'h44);
+ wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC0,read_data,'h11);
+ wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC1,read_data,'h22);
+ wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC2,read_data,'h33);
+ wb_user_core_read_check(`ADDR_SPACE_ANALOG+`ANALOG_CFG_DAC3,read_data,'h44);
+ repeat (10) @(posedge clock);
+ if((u_top.u_4x8bit_dac.DIn0 != 'h11) || (u_top.u_4x8bit_dac.DIn1 != 'h22) ||
+ (u_top.u_4x8bit_dac.DIn2 != 'h33) || (u_top.u_4x8bit_dac.DIn3 != 'h44)) begin
+ test_fail = 1;
+ end
+
+ if(test_fail == 1) begin
+ $display("ERROR: Step-10,Monitor: Analog Config check - FAILED");
+ end else begin
+ $display("STATUS: Step-10,Monitor: Ananlog Config check - PASSED");
+
+ $display("##########################################################");
+
+ end
+ $display("##########################################################");
+ $display("Step-11,Monitor: Checking the chip signature :");
+ $display("###################################################");
+ test_id = 11;
test_step = 14;
// Remove Wb/PinMux Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
@@ -490,9 +522,9 @@
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
if(test_fail == 1) begin
- $display("ERROR: Step-10,Monitor: Checking the chip signature - FAILED");
+ $display("ERROR: Step-11,Monitor: Checking the chip signature - FAILED");
end else begin
- $display("STATUS: Step-10,Monitor: Checking the chip signature - PASSED");
+ $display("STATUS: Step-11,Monitor: Checking the chip signature - PASSED");
$display("##########################################################");
@@ -636,7 +668,7 @@
input real exp_period;
begin
`ifdef GL
- force clock_mon = u_top.u_wb_host._09314_.Q;
+ force clock_mon = u_top.u_wb_host._09635_.Q;
`else
force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
`endif
diff --git a/verilog/dv/user_fpu_core/Makefile b/verilog/dv/user_fpu_core/Makefile
new file mode 100644
index 0000000..34afdb1
--- /dev/null
+++ b/verilog/dv/user_fpu_core/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_fpu_core
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/sc_print.c -o sc_print.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+ ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o sc_print.o crt.o -nostartfiles -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+ rm crt.o ${PATTERN}.o
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_fpu_core/user_fpu_core.c b/verilog/dv/user_fpu_core/user_fpu_core.c
new file mode 100644
index 0000000..c5e6832
--- /dev/null
+++ b/verilog/dv/user_fpu_core/user_fpu_core.c
@@ -0,0 +1,226 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+#define SC_SIM_OUTPORT (0xf0000000)
+
+
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+
+#include "int_reg_map.h"
+#include "common_misc.h"
+#include "common_bthread.h"
+
+#define CMD_FPU_SP_ADD 0x1 // Single Precision (32 bit) Adder
+#define CMD_FPU_SP_MUL 0x2 // Single Precision (32 bit) Multipler
+#define CMD_FPU_SP_DIV 0x3 // Single Precision (32 bit) Divider
+#define CMD_FPU_SP_F2I 0x4 // Single Precision (32 bit) Float to Integer
+#define CMD_FPU_SP_I2F 0x5 // Single Precision (32 bit) Integer to Float
+#define CMD_FPU_DP_ADD 0x9 // Double Precision (64 bit) Adder
+#define CMD_FPU_DP_MUL 0xA // Double Precision (64 bit) Multipler
+#define CMD_FPU_DP_DIV 0xB // Double Precision (64 bit) Divider
+
+int fpu_check(uint8_t Cmd, uint32_t Din1, uint32_t Din2, uint32_t Result);
+
+int main(void)
+{
+ int exit;
+
+ //printf("\nTesting FPU CORE LOGIC\n\n");
+
+ reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART
+ reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
+ reg_glbl_multi_func |=0x100; // Enable UART Multi func
+ reg_gpio_dsel =0xFF00; // Enable PORT B As output
+ reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
+
+ //// GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ //// bit[7:0] - core-0
+ //// bit[15:8] - core-1
+ //// bit[23:16] - core-2
+ //// bit[31:24] - core-3
+
+ reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main
+
+ reg_gpio_odata = 0x00000100;
+ reg_glbl_soft_reg_0 = 0x00000000;
+ //--------------------------------------
+ // Floating Point Addition
+ //--------------------------------------
+
+ // TEST-1: Addition: Din1: 0.500000 Din2: 1.500000 Res: 2.000000
+ exit = fpu_check(CMD_FPU_SP_ADD,0x3f000000,0x3fc00000,0x40000000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-2: Addition: Din1: 0.500000 Din2: 1.250000 Res: 1.750000
+ exit += fpu_check(CMD_FPU_SP_ADD,0x3f000000,0x3fa00000,0x3fe00000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-3: Addition: Din1: 0.500000 Din2: 0.250000 Res: 0.750000
+ exit += fpu_check(CMD_FPU_SP_ADD,0x3f000000,0x3e800000,0x3f400000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-4: Addition: Din1: 2.000000 Din2: -2.000000 Res: 0.000000
+ exit += fpu_check(CMD_FPU_SP_ADD,0x40000000,0xc0000000,0x00000000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-5: Addition: Din1: -0.000000 Din2: 0.000000 Res: 0.000000
+ exit += fpu_check(CMD_FPU_SP_ADD,0x83e73d5c,0x1c800000,0x1c800000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-6: Addition: Din1: -1.211871 Din2: -2.889479 Res: -4.101350
+ exit += fpu_check(CMD_FPU_SP_ADD,0xbf9b1e94,0xc038ed3a,0xc0833e42);
+ reg_glbl_soft_reg_0 = exit;
+
+ //--------------------------------------
+ // Floating Point Multiplication
+ //--------------------------------------
+ // TEST-1: Multiplier: Din1: 0.500000 Din2: 1.500000 Res: 0.750000
+ exit += fpu_check(CMD_FPU_SP_MUL,0x3f000000,0x3fc00000,0x3f400000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-2: Multiplier: Din1: 0.500000 Din2: 1.250000 Res: 0.625000
+ exit += fpu_check(CMD_FPU_SP_MUL,0x3f000000,0x3fa00000,0x3f200000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-3: Multiplier: Din1: 0.500000 Din2: 0.250000 Res: 0.125000
+ exit += fpu_check(CMD_FPU_SP_MUL,0x3f000000,0x3e800000,0x3e000000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-4: Multiplier: Din1: 0.000000 Din2: -0.000000 Res: -0.000000
+ exit += fpu_check(CMD_FPU_SP_MUL,0x22cb525a,0xadd79efa,0x912b406d);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-5: Multiplier: Din1: 2.000000 Din2: -2.000000 Res: -4.000000
+ exit += fpu_check(CMD_FPU_SP_MUL,0x40000000,0xc0000000,0xc0800000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-6: Multiplier: Din1: -1.211871 Din2: -2.889479 Res: 3.501675
+ exit += fpu_check(CMD_FPU_SP_MUL,0xbf9b1e94,0xc038ed3a,0x40601b72);
+ reg_glbl_soft_reg_0 = exit;
+
+ //--------------------------------------
+ // Floating Point Division
+ //--------------------------------------
+ // TEST-1: Division: Din1: 0.500000 Din2: 1.500000 Res: 0.750000
+ exit += fpu_check(CMD_FPU_SP_DIV,0x3f000000,0x3fc00000,0x3eaaaaab);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-2: Division: Din1: 0.500000 Din2: 1.250000 Res: 0.400000
+ exit += fpu_check(CMD_FPU_SP_DIV,0x3f000000,0x3fa00000,0x3ecccccd);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-3: Division: Din1: 0.500000 Din2: 0.250000 Res: 2.000000
+ exit += fpu_check(CMD_FPU_SP_DIV,0x3f000000,0x3e800000,0x40000000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-4: Division: Din1: 0.000000 Din2: -0.000000 Res: 0.000000
+ exit += fpu_check(CMD_FPU_SP_DIV,0x22cb525a,0xadd79efa,0xb47165bd);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-5: Division: Din1: 2.000000 Din2: -2.000000 Res: -1.000000
+ exit += fpu_check(CMD_FPU_SP_DIV,0x40000000,0xc0000000,0xbf800000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-6: Division: Din1: -1.211871 Din2: -2.889479 Res: 0.419408
+ exit += fpu_check(CMD_FPU_SP_DIV,0xbf9b1e94,0xc038ed3a,0x3ed6bca5);
+ reg_glbl_soft_reg_0 = exit;
+
+ //--------------------------------------
+ // Intger To Floating Point
+ //--------------------------------------
+ // TEST-1: I2F: Input: 1069547520 Result: 1069547520.000000
+ exit += fpu_check(CMD_FPU_SP_I2F,0x3fc00000,0x0,0x4e7f0000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-2: I2F: Input: 1067450368 Result: 1067450368.000000
+ exit += fpu_check(CMD_FPU_SP_I2F,0x3fa00000,0x0,0x4e7e8000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-3: I2F: Input: 1048576000 Result: 1048576000.000000
+ exit += fpu_check(CMD_FPU_SP_I2F,0x3e800000,0x0,0x4e7a0000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-4: I2F: Input: 1075838976 Result: 1075838976.000000
+ exit += fpu_check(CMD_FPU_SP_I2F,0x40200000,0x0,0x4e804000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-5: I2F: Input: 1084017869 Result: 1084017920.000000
+ exit += fpu_check(CMD_FPU_SP_I2F,0x409ccccd,0x0,0x4e81399a);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-6: I2F: Input: -1071644672 Result: -1071644672.000000
+ exit += fpu_check(CMD_FPU_SP_I2F,0xc0200000,0x0,0xce7f8000);
+ reg_glbl_soft_reg_0 = exit;
+
+ //--------------------------------------
+ // Floating To Integer Point
+ //--------------------------------------
+ // TEST-1: F2I: Input: 1.500000 Result: 1
+ exit += fpu_check(CMD_FPU_SP_F2I,0x3fc00000,0x0,0x00000001);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-2: F2I: Input: 1.250000 Result: 1
+ exit += fpu_check(CMD_FPU_SP_F2I,0x3fa00000,0x0,0x00000001);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-3: F2I: Input: 0.250000 Result: 0
+ exit += fpu_check(CMD_FPU_SP_F2I,0x3e800000,0x0,0x00000000);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-4: F2I: Input: 2.500000 Result: 2
+ exit += fpu_check(CMD_FPU_SP_F2I,0x40200000,0x0,0x00000002);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-5: F2I: Input: -2.500000 Result: -2
+ exit += fpu_check(CMD_FPU_SP_F2I,0xc0200000,0x0,0xfffffffe);
+ reg_glbl_soft_reg_0 = exit;
+
+ // TEST-6: F2I: Input: -222.800003 Result: -222
+ exit += fpu_check(CMD_FPU_SP_F2I,0xc35ecccd,0x0,0xffffff22);
+ reg_glbl_soft_reg_0 = exit;
+
+ if(exit == 0) {
+ reg_gpio_odata = 0x00001800;
+ } else {
+ reg_gpio_odata = 0x0000A800;
+ }
+
+ return exit;
+}
+
+int fpu_check(uint8_t Cmd, uint32_t Din1, uint32_t Din2, uint32_t Result){
+
+
+ reg_fpu_din1 = Din1;
+ reg_fpu_din2 = Din2;
+ reg_fpu_ctrl = Cmd | 0x80000000;
+
+ while(reg_fpu_ctrl & 0x80000000); // Wait for FPU completion
+
+ reg_glbl_soft_reg_1 = reg_fpu_res;
+ reg_glbl_soft_reg_2 = Result;
+ if(reg_fpu_res != Result) return 1;
+ else return 0;
+
+}
+
+
+
+
+
diff --git a/verilog/dv/user_fpu_core/user_fpu_core_tb.v b/verilog/dv/user_fpu_core/user_fpu_core_tb.v
new file mode 100644
index 0000000..41b4ffe
--- /dev/null
+++ b/verilog/dv/user_fpu_core/user_fpu_core_tb.v
@@ -0,0 +1,294 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the Riscduino cores project ////
+//// ////
+//// Description ////
+//// To validate FPU Core ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 10th Nov 2022, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+module user_fpu_tb;
+
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+`include "user_tasks.sv"
+
+
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+reg [1:0] uart_data_bit ;
+reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+reg uart_stick_parity ; // 1: force even parity
+reg uart_parity_en ; // parity enable
+reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0] uart_data ;
+reg [15:0] uart_divisor ; // divided by n * 16
+reg [15:0] uart_timeout ;// wait time limit
+
+reg [15:0] uart_rx_nu ;
+reg [15:0] uart_tx_nu ;
+reg [7:0] uart_write_data [0:39];
+reg uart_fifo_enable ; // fifo mode disable
+
+
+
+ /************* Port-B Mapping **********************************
+ * Pin-14 PB0/CLKO/ICP1 digital_io[16]
+ * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[17]
+ * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[18]
+ * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[19]
+ * Pin-18 PB4/MISO digital_io[20]
+ * Pin-19 PB5/SCK digital_io[21]
+ * Pin-9 PB6/XTAL1/TOSC1 digital_io[11]
+ * Pin-10 PB7/XTAL2/TOSC2 digital_io[12]
+ * ********************************************************/
+
+ wire [7:0] port_b_in = { io_out[12],
+ io_out[11],
+ io_out[21],
+ io_out[20],
+ io_out[19],
+ io_out[18],
+ io_out[17],
+ io_out[16]
+ };
+ initial begin
+ test_fail = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(2, user_fpu_tb);
+ $dumpvars(0, user_fpu_tb.u_top.u_fpu);
+ $dumpvars(0, user_fpu_tb.u_top.u_riscv_top);
+ $dumpvars(0, user_fpu_tb.u_top.u_pinmux);
+ end
+ `endif
+
+ initial begin
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
+
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ uart_divisor = 15;// divided by n * 16
+ uart_timeout = 500;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Uart Test Started");
+
+ // Remove Wb Reset
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ // Enable UART Multi Functional Ports
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
+
+ wait_riscv_boot();
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart.uart_init;
+ wb_user_core_write(`ADDR_SPACE_UART0+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ // Set the PORT-B Direction as Output
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h0000FF00);
+ // Set the GPIO Output data: 0x00000000
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000);
+
+ fork
+ begin
+ repeat (1400000) @(posedge clock);
+ end
+ begin
+ wait(port_b_in == 8'h18 || port_b_in == 8'hA8);
+ end
+ begin
+ while(1) begin
+ wb_user_core_read(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,read_data);
+ repeat (1000) @(posedge clock);
+ end
+ end
+ join_any
+
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000);
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+ $finish;
+
+ end
+
+
+
+// SSPI Slave I/F
+assign io_in[5] = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK
+
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[28];
+ wire flash_csb = io_out[29];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[33];
+ wire #1 io_oeb_30 = io_oeb[34];
+ wire #1 io_oeb_31 = io_oeb[35];
+ wire #1 io_oeb_32 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+
+ assign io_in[33] = flash_io0;
+ assign io_in[34] = flash_io1;
+ assign io_in[35] = flash_io2;
+ assign io_in[36] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("user_fpu_core.hex"),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[7];
+assign io_in[6] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index b8bce21..3c425ce 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -98,9 +98,11 @@
initial begin
$dumpfile("simx.vcd");
$dumpvars(1, `TB_GLBL);
- $dumpvars(0, `TB_GLBL.u_top.u_wb_host);
+ $dumpvars(1, `TB_GLBL.pwm_monitor);
+ $dumpvars(1, `TB_GLBL.check_clock_period);
+ $dumpvars(1, `TB_GLBL.u_top.u_wb_host);
$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
- $dumpvars(0, `TB_GLBL.u_top.u_intercon);
+ $dumpvars(1, `TB_GLBL.u_top.u_intercon);
end
`endif
@@ -741,7 +743,7 @@
$display("STATUS: Step-10, PWM One Shot + mode:3 + Comparator Center - PASSED");
end
$display("Check Sum: %x ",check_sum);
- if(check_sum != 16'hc638) test_fail = 1;
+ if(check_sum != 16'hc692) test_fail = 1;
repeat (100) @(posedge clock);
// $display("+1000 cycles");
@@ -777,6 +779,16 @@
wire pwm4 = pwm_wfm[4];
wire pwm5 = pwm_wfm[5];
+
+reg [2:0] pwm_sel;
+
+assign clock_mon = (pwm_sel == 0) ? pwm0 :
+ (pwm_sel == 1) ? pwm1 :
+ (pwm_sel == 2) ? pwm2 :
+ (pwm_sel == 3) ? pwm3 :
+ (pwm_sel == 4) ? pwm4 : pwm5;
+
+
task pwm_monitor;
input [31:0] pwm0_period;
input [31:0] pwm1_period;
@@ -785,29 +797,29 @@
input [31:0] pwm4_period;
input [31:0] pwm5_period;
begin
- force clock_mon = pwm0;
+ pwm_sel = 3'h0;
+ repeat (100) @(posedge clock);
check_clock_period("PWM0 Clock",pwm0_period);
- release clock_mon;
- force clock_mon = pwm1;
+ pwm_sel = 3'h1;
+ repeat (100) @(posedge clock);
check_clock_period("PWM1 Clock",pwm1_period);
- release clock_mon;
- force clock_mon = pwm2;
+ pwm_sel = 3'h2;
+ repeat (100) @(posedge clock);
check_clock_period("PWM2 Clock",pwm2_period);
- release clock_mon;
- force clock_mon = pwm3;
+ pwm_sel = 3'h3;
+ repeat (100) @(posedge clock);
check_clock_period("PWM3 Clock",pwm3_period);
- release clock_mon;
- force clock_mon = pwm4;
+ pwm_sel = 3'h4;
+ repeat (100) @(posedge clock);
check_clock_period("PWM4 Clock",pwm4_period);
- release clock_mon;
- force clock_mon = pwm5;
+ pwm_sel = 3'h5;
+ repeat (100) @(posedge clock);
check_clock_period("PWM5 Clock",pwm5_period);
- release clock_mon;
end
endtask
@@ -821,7 +833,7 @@
time prev_t, next_t, periodd;
begin
$timeformat(-12,3,"ns",10);
- repeat(1) @(posedge clock_mon);
+ repeat(2) @(posedge clock_mon);
repeat(1) @(posedge clock_mon);
prev_t = $realtime;
repeat(2) @(posedge clock_mon);
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 8029645..935aa9e 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -118,6 +118,7 @@
$dumpvars(1, `TB_TOP);
$dumpvars(2, `TB_TOP.u_top);
$dumpvars(0, `TB_TOP.u_top.u_wb_host);
+ $dumpvars(2, `TB_TOP.u_top.u_riscv_top);
$dumpvars(0, `TB_TOP.u_top.u_pinmux);
end
`endif
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 8eae099..b9c8247 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -217,3 +217,8 @@
#-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v
#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
+
+
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
+
+-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v
diff --git a/verilog/includes/includes.gl.lib b/verilog/includes/includes.gl.lib
index 9a0c428..f6100e2 100644
--- a/verilog/includes/includes.gl.lib
+++ b/verilog/includes/includes.gl.lib
@@ -9,6 +9,5 @@
-v $(PDK_ROOT)/sky130B/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
#$(USER_PROJECT_VERILOG)/gl/digital_pll.v
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 0dee772..c52c530 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -3,6 +3,7 @@
+incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
+incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
+incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl
+incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm
+incdir+$(USER_PROJECT_VERILOG)/dv/common/model
+incdir+$(USER_PROJECT_VERILOG)/dv/common/agents
@@ -135,6 +136,16 @@
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_arb.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_sbox.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_rcon.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_key_expand_128.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_cipher_top.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_inv_sbox.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/core/aes_inv_cipher_top.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/top/aes_top.sv
+$(USER_PROJECT_VERILOG)/rtl/security_core/verilog/rtl/aes128/top/aes_reg.sv
+
+
-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv
-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv
-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv
@@ -144,3 +155,15 @@
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/fpu_wrapper/src/fpu_wrapper.sv
+-v $(USER_PROJECT_VERILOG)/rtl/fpu_wrapper/src/fpu_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_mul.sv
+-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_div.sv
+-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_add.sv
+-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_f2i.sv
+-v $(USER_PROJECT_VERILOG)/rtl/fpu/verilog/rtl/fpu_sp_i2f.sv
+
+
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
diff --git a/verilog/includes/includes.rtl.lib b/verilog/includes/includes.rtl.lib
index 5045805..9db7739 100644
--- a/verilog/includes/includes.rtl.lib
+++ b/verilog/includes/includes.rtl.lib
@@ -1,3 +1,2 @@
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v
--v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/digital_pll_controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/dg_pll/src/dg_pll.v
similarity index 98%
rename from verilog/rtl/digital_pll/src/digital_pll.v
rename to verilog/rtl/dg_pll/src/dg_pll.v
index 79cb52e..a364783 100644
--- a/verilog/rtl/digital_pll/src/digital_pll.v
+++ b/verilog/rtl/dg_pll/src/dg_pll.v
@@ -54,7 +54,7 @@
// Digital PLL (ring oscillator + controller)
// Technically this is a frequency locked loop, not a phase locked loop.
-module digital_pll(
+module dg_pll(
`ifdef USE_POWER_PINS
VPWR,
VGND,
diff --git a/verilog/rtl/digital_pll/src/digital_pll_controller.v b/verilog/rtl/dg_pll/src/digital_pll_controller.v
similarity index 100%
rename from verilog/rtl/digital_pll/src/digital_pll_controller.v
rename to verilog/rtl/dg_pll/src/digital_pll_controller.v
diff --git a/verilog/rtl/digital_pll/src/ring_osc2x13.v b/verilog/rtl/dg_pll/src/ring_osc2x13.v
similarity index 100%
rename from verilog/rtl/digital_pll/src/ring_osc2x13.v
rename to verilog/rtl/dg_pll/src/ring_osc2x13.v
diff --git a/verilog/rtl/dig2ana/src/dig2ana_reg.sv b/verilog/rtl/dig2ana/src/dig2ana_reg.sv
index ba7b364..b0ad653 100644
--- a/verilog/rtl/dig2ana/src/dig2ana_reg.sv
+++ b/verilog/rtl/dig2ana/src/dig2ana_reg.sv
@@ -105,7 +105,7 @@
if (h_reset_n == 1'b0) begin
reg_rdata <= 'h0;
reg_ack <= 1'b0;
- end else if (reg_cs && !reg_ack && sw_rd_en) begin
+ end else if (reg_cs && !reg_ack) begin
reg_rdata <= reg_out[DW-1:0] ;
reg_ack <= 1'b1;
end else begin
@@ -129,7 +129,7 @@
.data_out (reg_0[7:0] )
);
-assign reg_0[31:24] = 'h0;
+assign reg_0[31:8] = 'h0;
//-----------------------------------------------------------------------
// reg-1
@@ -147,7 +147,7 @@
.data_out (reg_1[7:0] )
);
-assign reg_1[31:24] = 'h0;
+assign reg_1[31:8] = 'h0;
//-----------------------------------------------------------------------
// reg-2
@@ -165,7 +165,7 @@
.data_out (reg_2[7:0] )
);
-assign reg_2[31:24] = 'h0;
+assign reg_2[31:8] = 'h0;
//-----------------------------------------------------------------------
// reg-3
@@ -183,7 +183,7 @@
.data_out (reg_3[7:0] )
);
-assign reg_3[31:24] = 'h0;
+assign reg_3[31:8] = 'h0;
//-----------------------------------------------------------------------
// Register Read Path Multiplexer instantiation
diff --git a/verilog/rtl/fpu b/verilog/rtl/fpu
new file mode 160000
index 0000000..105f901
--- /dev/null
+++ b/verilog/rtl/fpu
@@ -0,0 +1 @@
+Subproject commit 105f90130c507523bc6f45ca16431901fdd415c3
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index cc2912e..e8243ad 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -66,7 +66,7 @@
// Global Reset control
- output logic [1:0] cpu_core_rst_n ,
+ output logic [3:0] cpu_core_rst_n ,
output logic cpu_intf_rst_n ,
output logic qspim_rst_n ,
output logic sspim_rst_n ,
@@ -282,6 +282,10 @@
ctech_buf u_buf_cpu0_rst (.A(cfg_rst_ctrl[8]),.X(cpu_core_rst_n[0]));
ctech_buf u_buf_cpu1_rst (.A(cfg_rst_ctrl[9]),.X(cpu_core_rst_n[1]));
+ctech_buf u_buf_cpu2_rst (.A(cfg_rst_ctrl[10]),.X(cpu_core_rst_n[2]));
+ctech_buf u_buf_cpu3_rst (.A(cfg_rst_ctrl[11]),.X(cpu_core_rst_n[3]));
+
+
//---------------------------------------------------------
// Default reset value decided based on riscv boot mode
@@ -756,6 +760,9 @@
(cfg_mon_sel == 4'b110) ? usb_clk :
(cfg_mon_sel == 4'b111) ? rtc_clk : 1'b0;
+wire dbg_clk_ref_buf;
+ctech_clk_buf u_clkbuf_dbg_ref (.A (dbg_clk_ref), . X(dbg_clk_ref_buf));
+
// DIv16 to debug monitor purpose
logic dbg_clk_div16;
@@ -763,7 +770,7 @@
// Outputs
.clk_o (dbg_clk_div16 ),
// Inputs
- .mclk (dbg_clk_ref ),
+ .mclk (dbg_clk_ref_buf ),
.reset_n (e_reset_n ),
.clk_div_ratio (4'hE )
);
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 0a78310..001bd66 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -106,7 +106,7 @@
output logic rtc_clk ,
// Global Reset control
- output logic [1:0] cpu_core_rst_n ,
+ output logic [3:0] cpu_core_rst_n ,
output logic cpu_intf_rst_n ,
output logic qspim_rst_n ,
output logic sspim_rst_n ,
@@ -647,8 +647,8 @@
.reg_cs (reg_d2a_cs ),
.reg_wr (reg_wr ),
.reg_addr (reg_addr[5:2] ),
- .reg_wdata (reg_wdata[15:0] ),
- .reg_be (reg_be[1:0] ),
+ .reg_wdata (reg_wdata[31:0] ),
+ .reg_be (reg_be[3:0] ),
// Outputs
.reg_rdata (reg_d2a_rdata ),
diff --git a/verilog/rtl/pwm/src/pwm.sv b/verilog/rtl/pwm/src/pwm.sv
index 922c369..2ed7a03 100644
--- a/verilog/rtl/pwm/src/pwm.sv
+++ b/verilog/rtl/pwm/src/pwm.sv
@@ -45,7 +45,7 @@
logic [15:0] pwm_cnt ; // PWM counter
logic cnt_trg ;
logic pwm_wfm_i ;
-logic pwm_wfm_hold;
+logic pwm_wfm_r ; // Register pwm
logic comp0_match ;
logic comp1_match ;
logic comp2_match ;
@@ -214,25 +214,27 @@
always @(posedge mclk or negedge h_reset_n)
begin
if ( ~h_reset_n ) begin
- pwm_wfm_hold <= 1'b0;
- end else if(cfg_pwm_enb) begin
- pwm_wfm_hold <= pwm_wfm_i;
+ pwm_wfm_r <= 1'b0;
+ end else begin
+ if(cfg_pwm_hold) begin
+ if(cfg_pwm_enb ) begin
+ pwm_wfm_r <= pwm_wfm_i;
+ end
+ end else begin
+ pwm_wfm_r <= pwm_wfm_i;
+ end
end
end
+
//--------------------------------------------
// Final Waveform output generation based
// on pwm_hold and pwm_inv combination
//--------------------------------------------
always_comb begin
pwm_wfm_o = 0;
- if(!cfg_pwm_enb && cfg_pwm_hold) begin
- if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_hold;
- else pwm_wfm_o = pwm_wfm_hold;
- end else begin
- if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_i;
- else pwm_wfm_o = pwm_wfm_i;
- end
+ if(cfg_pwm_inv) pwm_wfm_o = !pwm_wfm_r;
+ else pwm_wfm_o = pwm_wfm_r;
end
//----------------------------------------
diff --git a/verilog/rtl/security_core b/verilog/rtl/security_core
new file mode 160000
index 0000000..472d98e
--- /dev/null
+++ b/verilog/rtl/security_core
@@ -0,0 +1 @@
+Subproject commit 472d98ee3bfb82a4adaf40b7d5d329ba61f51588
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 4c63893..4dfe03c 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,11 +4,12 @@
// ASCI Representation of RISC = 32'h8273_8343
parameter CHIP_SIGNATURE = 32'h8273_8343;
// Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2909_2022;
+parameter CHIP_RELEASE_DATE = 32'h0711_2022;
// Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION = 32'h0005_6000;
+parameter CHIP_REVISION = 32'h0005_7000;
-parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_0111;
+parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_1100;
+parameter CLK_SKEW2_RESET_VAL = 32'b0000;
parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1010_0000;
@@ -138,13 +139,13 @@
`define STRAP_RISCV_CACHE_BYPASS 13
`define STRAP_RISCV_SRAM_CLK_EDGE 14
`define STRAP_QSPI_PRE_SRAM 15 // Previous SRAM Strap Status
-`define STRAP_CLK_SKEW_WI 17:16
-`define STRAP_CLK_SKEW_WH 19:18
-`define STRAP_CLK_SKEW_RISCV 21:20
-`define STRAP_CLK_SKEW_QSPI 23:22
-`define STRAP_CLK_SKEW_UART 25:24
-`define STRAP_CLK_SKEW_PINMUX 27:26
-`define STRAP_CLK_SKEW_QSPI_CO 29:28
+`define STRAP_SCLK_SKEW_WI 17:16
+`define STRAP_SCLK_SKEW_WH 19:18
+`define STRAP_SCLK_SKEW_RISCV 21:20
+`define STRAP_SCLK_SKEW_QSPI 23:22
+`define STRAP_SCLK_SKEW_UART 25:24
+`define STRAP_SCLK_SKEW_PINMUX 27:26
+`define STRAP_SCLK_SKEW_QSPI_CO 29:28
`define STRAP_QSPI_INIT_BYPASS 30
`define STRAP_SOFT_REBOOT_REQ 31
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2a12a4b..74017e8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -40,6 +40,7 @@
//// 13. 3 x Hardware Timer ////
//// 14. UART Master ////
//// 15. SPI Slave (As Arduino ISP) ////
+//// 16. AES 126 Encription/Decryption ////
//// ////
//// To Do: ////
//// nothing ////
@@ -282,7 +283,10 @@
//// B. digital_pll is re-synth with maual placement ////
//// 5.6 Sept 29 2022, Dinesh A ////
//// A. 4x 8bit DAC Integration ////
-////
+//// B. clock skew control added for core clock ////
+//// 5.7 Nov 7, 2022, Dinesh A ////
+//// A. AES 128 Bit Encription and Decryption integration ////
+//// B. FPU Integration ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -584,7 +588,7 @@
// CPU Configuration
//----------------------------------------------------
wire cpu_intf_rst_n ;
-wire [1:0] cpu_core_rst_n ;
+wire [3:0] cpu_core_rst_n ;
wire qspim_rst_n ;
wire sspim_rst_n ;
wire [1:0] uart_rst_n ; // uart reset
@@ -607,22 +611,23 @@
wire [7:0] cfg_glb_ctrl ;
-wire [31:0] cfg_clk_ctrl1 ;
-wire [3:0] cfg_cska_wi ; // clock skew adjust for wishbone interconnect
-wire [3:0] cfg_cska_wh ; // clock skew adjust for web host
+wire [31:0] cfg_clk_skew_ctrl1 ;
+wire [31:0] cfg_clk_skew_ctrl2 ;
+wire [3:0] cfg_wcska_wi ; // clock skew adjust for wishbone interconnect
+wire [3:0] cfg_wcska_wh ; // clock skew adjust for web host
-wire [3:0] cfg_cska_riscv ; // clock skew adjust for riscv
-wire [3:0] cfg_cska_uart ; // clock skew adjust for uart
-wire [3:0] cfg_cska_qspi ; // clock skew adjust for spi
-wire [3:0] cfg_cska_pinmux ; // clock skew adjust for pinmux
-wire [3:0] cfg_cska_qspi_co ; // clock skew adjust for global reg
+wire [3:0] cfg_wcska_riscv ; // clock skew adjust for riscv
+wire [3:0] cfg_wcska_uart ; // clock skew adjust for uart
+wire [3:0] cfg_wcska_qspi ; // clock skew adjust for spi
+wire [3:0] cfg_wcska_pinmux ; // clock skew adjust for pinmux
+wire [3:0] cfg_wcska_qspi_co ; // clock skew adjust for global reg
// Bus Repeater Signals output from Wishbone Interface
-wire [3:0] cfg_cska_riscv_rp ; // clock skew adjust for riscv
-wire [3:0] cfg_cska_uart_rp ; // clock skew adjust for uart
-wire [3:0] cfg_cska_qspi_rp ; // clock skew adjust for spi
-wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux
-wire [3:0] cfg_cska_qspi_co_rp ; // clock skew adjust for global reg
+wire [3:0] cfg_wcska_riscv_rp ; // clock skew adjust for riscv
+wire [3:0] cfg_wcska_uart_rp ; // clock skew adjust for uart
+wire [3:0] cfg_wcska_qspi_rp ; // clock skew adjust for spi
+wire [3:0] cfg_wcska_pinmux_rp ; // clock skew adjust for pinmux
+wire [3:0] cfg_wcska_qspi_co_rp ; // clock skew adjust for global reg
wire [31:0] irq_lines_rp ; // Repeater
wire soft_irq_rp ; // Repeater
@@ -741,6 +746,36 @@
wire usb_intr_o ;
wire i2cm_intr_o ;
+//------------------------------------------------------------
+// AES Integration local decleration
+//------------------------------------------------------------
+wire cpu_clk_aes ;
+wire [3:0] cfg_ccska_aes ;
+wire [3:0] cfg_ccska_aes_rp ;
+wire aes_dmem_req ;
+wire aes_dmem_cmd ;
+wire [1:0] aes_dmem_width ;
+wire [6:0] aes_dmem_addr ;
+wire [31:0] aes_dmem_wdata ;
+wire aes_dmem_req_ack ;
+wire [31:0] aes_dmem_rdata ;
+wire [1:0] aes_dmem_resp ;
+
+//------------------------------------------------------------
+// FPU Integration local decleration
+//------------------------------------------------------------
+wire cpu_clk_fpu ;
+wire [3:0] cfg_ccska_fpu ;
+wire [3:0] cfg_ccska_fpu_rp ;
+wire fpu_dmem_req ;
+wire fpu_dmem_cmd ;
+wire [1:0] fpu_dmem_width ;
+wire [4:0] fpu_dmem_addr ;
+wire [31:0] fpu_dmem_wdata ;
+wire fpu_dmem_req_ack ;
+wire [31:0] fpu_dmem_rdata ;
+wire [1:0] fpu_dmem_resp ;
+
//----------------------------------------------------------------
// UART Master I/F
// -------------------------------------------------------------
@@ -764,6 +799,10 @@
wire s_reset_n ;
wire cfg_strap_pad_ctrl ;
+wire e_reset_n_rp ;
+wire p_reset_n_rp ;
+wire s_reset_n_rp ;
+wire cfg_strap_pad_ctrl_rp ;
//----------------------------------------------------------------------
// DAC Config
//----------------------------------------------------------------------
@@ -778,6 +817,11 @@
wire [31:0] system_strap ;
wire [31:0] strap_sticky ;
wire [1:0] strap_uartm ;
+
+wire [31:0] system_strap_rp ;
+wire [31:0] strap_sticky_rp ;
+wire [1:0] strap_uartm_rp ;
+
wire [1:0] strap_qspi_flash = system_strap[`STRAP_QSPI_FLASH];
wire strap_qspi_sram = system_strap[`STRAP_QSPI_SRAM];
wire strap_qspi_pre_sram = system_strap[`STRAP_QSPI_PRE_SRAM];
@@ -795,22 +839,43 @@
wire cfg_bypass_dcache = cfg_riscv_ctrl[11];
/////////////////////////////////////////////////////////
-// Clock Skew Ctrl
+// System/WB Clock Skew Ctrl
////////////////////////////////////////////////////////
-assign cfg_cska_wi = cfg_clk_ctrl1[3:0];
-assign cfg_cska_wh = cfg_clk_ctrl1[7:4];
-assign cfg_cska_riscv = cfg_clk_ctrl1[11:8];
-assign cfg_cska_qspi = cfg_clk_ctrl1[15:12];
-assign cfg_cska_uart = cfg_clk_ctrl1[19:16];
-assign cfg_cska_pinmux = cfg_clk_ctrl1[23:20];
-assign cfg_cska_qspi_co = cfg_clk_ctrl1[27:24];
+assign cfg_wcska_wi = cfg_clk_skew_ctrl1[3:0];
+assign cfg_wcska_wh = cfg_clk_skew_ctrl1[7:4];
+assign cfg_wcska_riscv = cfg_clk_skew_ctrl1[11:8];
+assign cfg_wcska_qspi = cfg_clk_skew_ctrl1[15:12];
+assign cfg_wcska_uart = cfg_clk_skew_ctrl1[19:16];
+assign cfg_wcska_pinmux = cfg_clk_skew_ctrl1[23:20];
+assign cfg_wcska_qspi_co = cfg_clk_skew_ctrl1[27:24];
+/////////////////////////////////////////////////////////
+// RISCV Clock skew control
+/////////////////////////////////////////////////////////
+wire [3:0] cfg_ccska_riscv_intf_rp ;
+wire [3:0] cfg_ccska_riscv_icon_rp ;
+wire [3:0] cfg_ccska_riscv_core0_rp ;
+wire [3:0] cfg_ccska_riscv_core1_rp ;
+wire [3:0] cfg_ccska_riscv_core2_rp ;
+wire [3:0] cfg_ccska_riscv_core3_rp ;
+
+wire [3:0] cfg_ccska_riscv_intf = cfg_clk_skew_ctrl2[3:0];
+wire [3:0] cfg_ccska_riscv_icon = cfg_clk_skew_ctrl2[7:4];
+wire [3:0] cfg_ccska_riscv_core0 = cfg_clk_skew_ctrl2[11:8];
+wire [3:0] cfg_ccska_riscv_core1 = cfg_clk_skew_ctrl2[15:12];
+wire [3:0] cfg_ccska_riscv_core2 = cfg_clk_skew_ctrl2[19:16];
+wire [3:0] cfg_ccska_riscv_core3 = cfg_clk_skew_ctrl2[23:20];
+assign cfg_ccska_aes = cfg_clk_skew_ctrl2[27:24];
+assign cfg_ccska_fpu = cfg_clk_skew_ctrl2[31:28];
assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug};
wire int_pll_clock = pll_clk_out[0];
+/***********************************************
+ Wishbone HOST
+*************************************************/
wb_host u_wb_host(
`ifdef USE_POWER_PINS
@@ -830,8 +895,8 @@
.s_reset_n (s_reset_n ), // soft reset
.cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ),
.system_strap (system_strap ),
- .strap_sticky (strap_sticky ),
- .strap_uartm (strap_uartm ),
+ .strap_sticky (strap_sticky_rp ),
+ .strap_uartm (strap_uartm_rp ),
.wbd_int_rst_n (wbd_int_rst_n ),
.wbd_pll_rst_n (wbd_pll_rst_n ),
@@ -852,7 +917,7 @@
// Clock Skeq Adjust
.wbd_clk_int (wbd_clk_int ),
.wbd_clk_wh (wbd_clk_wh ),
- .cfg_cska_wh (cfg_cska_wh ),
+ .cfg_cska_wh (cfg_wcska_wh ),
// Slave Port
.wbs_clk_out (wbd_clk_int ),
@@ -867,7 +932,8 @@
.wbs_ack_i (wbd_int_ack_o ),
.wbs_err_i (wbd_int_err_o ),
- .cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
+ .cfg_clk_skew_ctrl1 (cfg_clk_skew_ctrl1 ),
+ .cfg_clk_skew_ctrl2 (cfg_clk_skew_ctrl2 ),
.la_data_in (la_data_in[17:0] ),
@@ -884,9 +950,12 @@
);
+/****************************************************************
+ Digital PLL
+*****************************************************************/
// This rtl/gds picked from efabless caravel project
-digital_pll u_pll(
+dg_pll u_pll(
`ifdef USE_POWER_PINS
.VPWR (vccd1 ),
.VGND (vssd1 ),
@@ -907,67 +976,71 @@
//------------------------------------------------------------------------------
ycr_top_wb u_riscv_top (
`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
`endif
- .wbd_clk_int (wbd_clk_risc_rp ),
- .cfg_cska_riscv (cfg_cska_riscv_rp ),
- .wbd_clk_riscv (wbd_clk_riscv_skew ),
+ .wbd_clk_int (wbd_clk_risc_rp ),
+ .cfg_wcska_riscv_intf (cfg_wcska_riscv_rp ),
+ .wbd_clk_skew (wbd_clk_riscv_skew ),
// Reset
- .pwrup_rst_n (wbd_int_rst_n ),
- .rst_n (wbd_int_rst_n ),
- .cpu_intf_rst_n (cpu_intf_rst_n ),
- .cpu_core_rst_n (cpu_core_rst_n[0] ),
- .riscv_debug (riscv_debug ),
- .cfg_sram_lphase (cfg_riscv_sram_lphase ),
- .cfg_cache_ctrl (cfg_riscv_cache_ctrl ),
- .cfg_bypass_icache (cfg_bypass_icache ),
- .cfg_bypass_dcache (cfg_bypass_dcache ),
+ .pwrup_rst_n (wbd_int_rst_n ),
+ .rst_n (wbd_int_rst_n ),
+ .cpu_intf_rst_n (cpu_intf_rst_n ),
+ .cpu_core_rst_n (cpu_core_rst_n[0] ),
+ .riscv_debug (riscv_debug ),
+ .cfg_sram_lphase (cfg_riscv_sram_lphase ),
+ .cfg_cache_ctrl (cfg_riscv_cache_ctrl ),
+ .cfg_bypass_icache (cfg_bypass_icache ),
+ .cfg_bypass_dcache (cfg_bypass_dcache ),
// Clock
- .core_clk (cpu_clk ),
- .rtc_clk (rtc_clk ),
+ .core_clk_int (cpu_clk ),
+ .cfg_ccska_riscv_intf (cfg_ccska_riscv_intf_rp ),
+ .cfg_ccska_riscv_icon (cfg_ccska_riscv_icon_rp ),
+ .cfg_ccska_riscv_core0 (cfg_ccska_riscv_core0_rp ),
+
+ .rtc_clk (rtc_clk ),
// IRQ
- .irq_lines (irq_lines_rp ),
- .soft_irq (soft_irq_rp ), // TODO - Interrupts
+ .irq_lines (irq_lines_rp ),
+ .soft_irq (soft_irq_rp ), // TODO - Interrupts
// DFT
- // .test_mode (1'b0 ), // Moved inside IP
- // .test_rst_n (1'b1 ), // Moved inside IP
+ // .test_mode (1'b0 ), // Moved inside IP
+ // .test_rst_n (1'b1 ), // Moved inside IP
`ifndef SCR1_TCM_MEM
// SRAM-0 PORT-0
- .sram0_clk0 (sram0_clk0 ),
- .sram0_csb0 (sram0_csb0 ),
- .sram0_web0 (sram0_web0 ),
- .sram0_addr0 (sram0_addr0 ),
- .sram0_wmask0 (sram0_wmask0 ),
- .sram0_din0 (sram0_din0 ),
- .sram0_dout0 (sram0_dout0 ),
+ .sram0_clk0 (sram0_clk0 ),
+ .sram0_csb0 (sram0_csb0 ),
+ .sram0_web0 (sram0_web0 ),
+ .sram0_addr0 (sram0_addr0 ),
+ .sram0_wmask0 (sram0_wmask0 ),
+ .sram0_din0 (sram0_din0 ),
+ .sram0_dout0 (sram0_dout0 ),
// SRAM-0 PORT-0
- .sram0_clk1 (sram0_clk1 ),
- .sram0_csb1 (sram0_csb1 ),
- .sram0_addr1 (sram0_addr1 ),
- .sram0_dout1 (sram0_dout1 ),
+ .sram0_clk1 (sram0_clk1 ),
+ .sram0_csb1 (sram0_csb1 ),
+ .sram0_addr1 (sram0_addr1 ),
+ .sram0_dout1 (sram0_dout1 ),
// // SRAM-1 PORT-0
- // .sram1_clk0 (sram1_clk0 ),
- // .sram1_csb0 (sram1_csb0 ),
- // .sram1_web0 (sram1_web0 ),
- // .sram1_addr0 (sram1_addr0 ),
- // .sram1_wmask0 (sram1_wmask0 ),
- // .sram1_din0 (sram1_din0 ),
- // .sram1_dout0 (sram1_dout0 ),
+ // .sram1_clk0 (sram1_clk0 ),
+ // .sram1_csb0 (sram1_csb0 ),
+ // .sram1_web0 (sram1_web0 ),
+ // .sram1_addr0 (sram1_addr0 ),
+ // .sram1_wmask0 (sram1_wmask0 ),
+ // .sram1_din0 (sram1_din0 ),
+ // .sram1_dout0 (sram1_dout0 ),
//
// // SRAM PORT-0
- // .sram1_clk1 (sram1_clk1 ),
- // .sram1_csb1 (sram1_csb1 ),
- // .sram1_addr1 (sram1_addr1 ),
- // .sram1_dout1 (sram1_dout1 ),
+ // .sram1_clk1 (sram1_clk1 ),
+ // .sram1_csb1 (sram1_csb1 ),
+ // .sram1_addr1 (sram1_addr1 ),
+ // .sram1_dout1 (sram1_dout1 ),
`endif
.wb_rst_n (wbd_int_rst_n ),
@@ -1038,7 +1111,25 @@
.wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ),
.wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ),
.wbd_dmem_lack_i (wbd_riscv_dmem_lack_o ),
- .wbd_dmem_err_i (wbd_riscv_dmem_err_o )
+ .wbd_dmem_err_i (wbd_riscv_dmem_err_o ),
+
+ .aes_dmem_req (aes_dmem_req ),
+ .aes_dmem_cmd (aes_dmem_cmd ),
+ .aes_dmem_width (aes_dmem_width ),
+ .aes_dmem_addr (aes_dmem_addr ),
+ .aes_dmem_wdata (aes_dmem_wdata ),
+ .aes_dmem_req_ack (aes_dmem_req_ack ),
+ .aes_dmem_rdata (aes_dmem_rdata ),
+ .aes_dmem_resp (aes_dmem_resp ),
+
+ .fpu_dmem_req (fpu_dmem_req ),
+ .fpu_dmem_cmd (fpu_dmem_cmd ),
+ .fpu_dmem_width (fpu_dmem_width ),
+ .fpu_dmem_addr (fpu_dmem_addr ),
+ .fpu_dmem_wdata (fpu_dmem_wdata ),
+ .fpu_dmem_req_ack (fpu_dmem_req_ack ),
+ .fpu_dmem_rdata (fpu_dmem_rdata ),
+ .fpu_dmem_resp (fpu_dmem_resp )
);
`ifndef SCR1_TCM_MEM
@@ -1126,6 +1217,57 @@
.dout1 (dcache_mem_dout1 )
);
+/***********************************************
+ AES 128 Bit
+*************************************************/
+aes_top u_aes (
+`ifdef USE_POWER_PINS
+ .vccd1 (vdda1 ),
+ .vssd1 (vssa1 ),
+`endif
+
+ .mclk (cpu_clk_aes ),
+ .rst_n (cpu_intf_rst_n ),
+
+ .cfg_cska (cfg_ccska_aes_rp ),
+ .wbd_clk_int (cpu_clk ),
+ .wbd_clk_out (cpu_clk_aes ),
+
+ .dmem_req (aes_dmem_req ),
+ .dmem_cmd (aes_dmem_cmd ),
+ .dmem_width (aes_dmem_width ),
+ .dmem_addr (aes_dmem_addr ),
+ .dmem_wdata (aes_dmem_wdata ),
+ .dmem_req_ack (aes_dmem_req_ack ),
+ .dmem_rdata (aes_dmem_rdata ),
+ .dmem_resp (aes_dmem_resp )
+);
+
+/***********************************************
+ FPU
+*************************************************/
+fpu_wrapper u_fpu (
+`ifdef USE_POWER_PINS
+ .vccd1 (vdda1 ),
+ .vssd1 (vssa1 ),
+`endif
+
+ .mclk (cpu_clk_fpu ),
+ .rst_n (cpu_intf_rst_n ),
+
+ .cfg_cska (cfg_ccska_fpu_rp ),
+ .wbd_clk_int (cpu_clk ),
+ .wbd_clk_out (cpu_clk_fpu ),
+
+ .dmem_req (fpu_dmem_req ),
+ .dmem_cmd (fpu_dmem_cmd ),
+ .dmem_width (fpu_dmem_width ),
+ .dmem_addr (fpu_dmem_addr ),
+ .dmem_wdata (fpu_dmem_wdata ),
+ .dmem_req_ack (fpu_dmem_req_ack ),
+ .dmem_rdata (fpu_dmem_rdata ),
+ .dmem_resp (fpu_dmem_resp )
+);
/*********************************************************
* SPI Master
@@ -1154,8 +1296,8 @@
.cfg_init_bypass (strap_qspi_init_bypass ),
// Clock Skew Adjust
- .cfg_cska_sp_co (cfg_cska_qspi_co_rp ),
- .cfg_cska_spi (cfg_cska_qspi_rp ),
+ .cfg_cska_sp_co (cfg_wcska_qspi_co_rp ),
+ .cfg_cska_spi (cfg_wcska_qspi_rp ),
.wbd_clk_int (wbd_clk_qspi_rp ),
.wbd_clk_spi (wbd_clk_spi ),
@@ -1187,7 +1329,7 @@
wb_interconnect #(
`ifndef SYNTHESIS
.CH_CLK_WD (4 ),
- .CH_DATA_WD (53 )
+ .CH_DATA_WD (154 )
`endif
) u_intercon (
`ifdef USE_POWER_PINS
@@ -1205,31 +1347,61 @@
wbd_clk_qspi_rp,
wbd_clk_risc_rp} ),
.ch_data_in ({
+ cfg_ccska_fpu[3:0],
+ cfg_ccska_aes[3:0],
+ strap_sticky[31:0],
+ strap_uartm[1:0],
+ system_strap[31:0],
+ p_reset_n,
+ e_reset_n,
+ cfg_strap_pad_ctrl,
soft_irq,
irq_lines[31:0],
- cfg_cska_qspi_co[3:0],
- cfg_cska_pinmux[3:0],
- cfg_cska_uart[3:0],
- cfg_cska_qspi[3:0],
- cfg_cska_riscv[3:0]
+ cfg_ccska_riscv_core3[3:0],
+ cfg_ccska_riscv_core2[3:0],
+ cfg_ccska_riscv_core1[3:0],
+ cfg_ccska_riscv_core0[3:0],
+ cfg_ccska_riscv_icon[3:0],
+ cfg_ccska_riscv_intf[3:0],
+
+ cfg_wcska_qspi_co[3:0],
+ cfg_wcska_pinmux[3:0],
+ cfg_wcska_uart[3:0],
+ cfg_wcska_qspi[3:0],
+ cfg_wcska_riscv[3:0]
} ),
.ch_data_out ({
+ cfg_ccska_fpu_rp[3:0],
+ cfg_ccska_aes_rp[3:0],
+ strap_sticky_rp[31:0],
+ strap_uartm_rp[1:0],
+ system_strap_rp[31:0],
+ p_reset_n_rp,
+ e_reset_n_rp,
+ cfg_strap_pad_ctrl_rp,
soft_irq_rp,
irq_lines_rp[31:0],
- cfg_cska_qspi_co_rp[3:0],
- cfg_cska_pinmux_rp[3:0],
- cfg_cska_uart_rp[3:0],
- cfg_cska_qspi_rp[3:0],
- cfg_cska_riscv_rp[3:0]
- } ),
+ cfg_ccska_riscv_core3_rp[3:0],
+ cfg_ccska_riscv_core2_rp[3:0],
+ cfg_ccska_riscv_core1_rp[3:0],
+ cfg_ccska_riscv_core0_rp[3:0],
+ cfg_ccska_riscv_icon_rp[3:0],
+ cfg_ccska_riscv_intf_rp[3:0],
+
+ cfg_wcska_qspi_co_rp[3:0],
+ cfg_wcska_pinmux_rp[3:0],
+ cfg_wcska_uart_rp[3:0],
+ cfg_wcska_qspi_rp[3:0],
+ cfg_wcska_riscv_rp[3:0]
+ } ),
// Clock Skew adjust
- .wbd_clk_int (wbd_clk_int ),
- .cfg_cska_wi (cfg_cska_wi ),
- .wbd_clk_wi (wbd_clk_wi_skew ),
+ .wbd_clk_int (wbd_clk_int ),
+ .cfg_cska_wi (cfg_wcska_wi ),
+ .wbd_clk_wi (wbd_clk_wi_skew ),
.clk_i (wbd_clk_wi_skew ),
.rst_n (wbd_int_rst_n ),
@@ -1333,7 +1505,7 @@
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
.wbd_clk_int (wbd_clk_uart_rp ),
- .cfg_cska_uart (cfg_cska_uart_rp ),
+ .cfg_cska_uart (cfg_wcska_uart_rp ),
.wbd_clk_uart (wbd_clk_uart_skew ),
.uart_rstn (uart_rst_n ), // uart reset
@@ -1391,19 +1563,19 @@
.vssd1 (vssd1 ),// User area 1 digital ground
`endif
//clk skew adjust
- .cfg_cska_pinmux (cfg_cska_pinmux_rp ),
+ .cfg_cska_pinmux (cfg_wcska_pinmux_rp ),
.wbd_clk_int (wbd_clk_pinmux_rp ),
.wbd_clk_pinmux (wbd_clk_pinmux_skew ),
// System Signals
// Inputs
.mclk (wbd_clk_pinmux_skew ),
- .e_reset_n (e_reset_n ),
- .p_reset_n (p_reset_n ),
+ .e_reset_n (e_reset_n_rp ),
+ .p_reset_n (p_reset_n_rp ),
.s_reset_n (wbd_int_rst_n ),
- .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ),
- .system_strap (system_strap ),
+ .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl_rp ),
+ .system_strap (system_strap_rp ),
.strap_sticky (strap_sticky ),
.strap_uartm (strap_uartm ),
@@ -1514,7 +1686,13 @@
);
+
+
dac_top u_4x8bit_dac(
+`ifdef USE_POWER_PINS
+ .vccd1 (vdda1 ),
+ .vssd1 (vssa1 ),
+`endif
.Vref (analog_io[23]),
.DIn0 (cfg_dac0_mux_sel),
.DIn1 (cfg_dac1_mux_sel),
@@ -1525,4 +1703,7 @@
.Vout2(analog_io[17] ),
.Vout3(analog_io[18] )
);
+
+
+
endmodule : user_project_wrapper
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 28b4293..3c904f9 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -15,6 +15,7 @@
`define ADDR_SPACE_TIMER 32'h3002_0180
`define ADDR_SPACE_SEMA 32'h3002_0200
`define ADDR_SPACE_WS281X 32'h3002_0280
+`define ADDR_SPACE_ANALOG 32'h3002_0300
`define ADDR_SPACE_WBHOST 32'h3008_0000
//--------------------------------------------------
@@ -125,6 +126,15 @@
`define SEMA_CFG_LOCK_14 8'h38 // reg_14 - Semaphore Lock Bit-14
`define SEMA_CFG_STATUS 8'h3C // reg_15 - Semaphore Lock Status
+
+//----------------------------------------------------
+// Analog Configuration
+//----------------------------------------------------
+`define ANALOG_CFG_DAC0 8'h00
+`define ANALOG_CFG_DAC1 8'h04
+`define ANALOG_CFG_DAC2 8'h08
+`define ANALOG_CFG_DAC3 8'h0C
+
//----------------------------------------------------------
// QSPI Register Map
//----------------------------------------------------------
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index d56b92a..cc966e2 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -142,7 +142,8 @@
input logic wbs_ack_i , // acknowlegement
input logic wbs_err_i , // error
- output logic [31:0] cfg_clk_ctrl1 ,
+ output logic [31:0] cfg_clk_skew_ctrl1 ,
+ output logic [31:0] cfg_clk_skew_ctrl2 ,
input logic [17:0] la_data_in ,
@@ -487,7 +488,8 @@
.wbs_clk_out (wbs_clk_out ), // System clock
.cfg_bank_sel (cfg_bank_sel ),
- .cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
+ .cfg_clk_skew_ctrl1 (cfg_clk_skew_ctrl1 ),
+ .cfg_clk_skew_ctrl2 (cfg_clk_skew_ctrl2 ),
.cfg_fast_sim (cfg_fast_sim )
);
diff --git a/verilog/rtl/wb_host/src/wbh_reg.sv b/verilog/rtl/wb_host/src/wbh_reg.sv
index 5985135..ab3ad2b 100644
--- a/verilog/rtl/wb_host/src/wbh_reg.sv
+++ b/verilog/rtl/wb_host/src/wbh_reg.sv
@@ -61,12 +61,14 @@
output logic [15:0] cfg_bank_sel ,
- output logic [31:0] cfg_clk_ctrl1 ,
+ output logic [31:0] cfg_clk_skew_ctrl1 ,
+ output logic [31:0] cfg_clk_skew_ctrl2 ,
output logic cfg_fast_sim
);
logic [2:0] sw_addr ;
+logic [3:0] sw_be ;
logic sw_rd_en ;
logic sw_wr_en ;
logic sw_wr_en_0 ;
@@ -78,10 +80,10 @@
logic [31:0] reg_out ;
logic [31:0] reg_0 ; // Software_Reg_0
-logic [7:0] cfg_clk_ctrl2 ;
+logic [7:0] cfg_clk_ctrl ;
logic [3:0] cfg_wb_clk_ctrl ;
logic [3:0] cfg_cpu_clk_ctrl ;
-logic [31:0] cfg_glb_ctrl ;
+logic [15:0] cfg_glb_ctrl ;
logic wbs_clk_div ;
logic wbs_ref_clk_div_2 ;
logic wbs_ref_clk_div_4 ;
@@ -89,6 +91,7 @@
assign sw_addr = reg_addr ;
+assign sw_be = reg_be ;
assign sw_rd_en = reg_cs & !reg_wr;
assign sw_wr_en = reg_cs & reg_wr;
@@ -120,10 +123,29 @@
end
+//-----------------------------------
+// reg-out mux
+//-----------------------------------
+
+always @( *)
+begin
+ reg_out [31:0] = 'h0;
+
+ case (sw_addr [2:0])
+ 3'b000 : reg_out [31:0] = {8'h0,cfg_clk_ctrl[7:0],cfg_glb_ctrl[15:0]};
+ 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};
+ 3'b010 : reg_out [31:0] = cfg_clk_skew_ctrl1 [31:0];
+ 3'b011 : reg_out [31:0] = cfg_clk_skew_ctrl2[31:0];
+ 3'b101 : reg_out [31:0] = system_strap [31:0];
+ default : reg_out [31:0] = 'h0;
+ endcase
+end
+
+
+//-----------------------------------
+// reg-0
//-------------------------------------
-// Global + Clock Control
-// -------------------------------------
-assign cfg_glb_ctrl = reg_0[31:0];
+
// Reset control
// On Power-up wb & pll power default enabled
ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0] & s_reset_n),.X(wbd_int_rst_n));
@@ -132,38 +154,36 @@
//assign cfg_fast_sim = cfg_glb_ctrl[8];
ctech_clk_buf u_fastsim_buf (.A (cfg_glb_ctrl[8]), . X(cfg_fast_sim)); // To Bypass Reset FSM initial wait time
-
-
-assign cfg_wb_clk_ctrl = cfg_clk_ctrl2[3:0];
-assign cfg_cpu_clk_ctrl = cfg_clk_ctrl2[7:4];
-
-
-always @( *)
-begin
- reg_out [31:0] = 'h0;
-
- case (sw_addr [2:0])
- 3'b000 : reg_out [31:0] = reg_0;
- 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};
- 3'b010 : reg_out [31:0] = cfg_clk_ctrl1 [31:0];
- 3'b011 : reg_out [31:0] = {24'h0,cfg_clk_ctrl2 [7:0]};
- 3'b101 : reg_out [31:0] = system_strap [31:0];
- default : reg_out [31:0] = 'h0;
- endcase
-end
-
-
-
-generic_register #(32,32'h3 ) u_glb_ctrl (
- .we ({32{sw_wr_en_0}} ),
- .data_in (reg_wdata[31:0] ),
- .reset_n (e_reset_n ),
- .clk (mclk ),
+gen_16b_reg #(16'h3 ) u_glb_ctrl (
+ .cs (sw_wr_en_0 ),
+ .we (sw_be[1:0] ),
+ .data_in (reg_wdata[15:0] ),
+ .reset_n (e_reset_n ),
+ .clk (mclk ),
//List of Outs
- .data_out (reg_0[31:0])
+ .data_out (cfg_glb_ctrl[15:0])
);
+
+//--------------------------------
+// clock control
+//--------------------------------
+assign cfg_wb_clk_ctrl = cfg_clk_ctrl[3:0];
+assign cfg_cpu_clk_ctrl = cfg_clk_ctrl[7:4];
+always @ (posedge mclk) begin
+ if (p_reset_n == 1'b0) begin
+ cfg_clk_ctrl <= strap_sticky[7:0] ;
+ end
+ else begin
+ if(sw_wr_en_0 & sw_be[2] )
+ cfg_clk_ctrl <= reg_wdata[23:16];
+ end
+end
+//-------------------------------------------------
+// reg-1
+//-------------------------------------------------
+
generic_register #(16,16'h1000 ) u_bank_sel (
.we ({16{sw_wr_en_1}} ),
.data_in (reg_wdata[15:0] ),
@@ -175,75 +195,68 @@
);
//-----------------------------------------------
-// clock control-1
+// reg-2: clock skew control-1
//----------------------------------------------
wire [31:0] rst_clk_ctrl1;
-assign rst_clk_ctrl1[3:0] = (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b00) ? SKEW_RESET_VAL[3:0] :
- (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4;
+assign rst_clk_ctrl1[3:0] = (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b00) ? CLK_SKEW1_RESET_VAL[3:0] :
+ (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b01) ? CLK_SKEW1_RESET_VAL[3:0] + 2 :
+ (strap_sticky[`STRAP_SCLK_SKEW_WI] == 2'b10) ? CLK_SKEW1_RESET_VAL[3:0] + 4 : CLK_SKEW1_RESET_VAL[3:0]-4;
-assign rst_clk_ctrl1[7:4] = (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b00) ? SKEW_RESET_VAL[7:4] :
- (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4;
+assign rst_clk_ctrl1[7:4] = (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b00) ? CLK_SKEW1_RESET_VAL[7:4] :
+ (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b01) ? CLK_SKEW1_RESET_VAL[7:4] + 2 :
+ (strap_sticky[`STRAP_SCLK_SKEW_WH] == 2'b10) ? CLK_SKEW1_RESET_VAL[7:4] + 4 : CLK_SKEW1_RESET_VAL[7:4]-4;
-assign rst_clk_ctrl1[11:8] = (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b00) ? SKEW_RESET_VAL[11:8] :
- (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4;
+assign rst_clk_ctrl1[11:8] = (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b00) ? CLK_SKEW1_RESET_VAL[11:8] :
+ (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b01) ? CLK_SKEW1_RESET_VAL[11:8] + 2 :
+ (strap_sticky[`STRAP_SCLK_SKEW_RISCV] == 2'b10) ? CLK_SKEW1_RESET_VAL[11:8] + 4 : CLK_SKEW1_RESET_VAL[11:8]-4;
-assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b00) ? SKEW_RESET_VAL[15:12] :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4;
+assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b00) ? CLK_SKEW1_RESET_VAL[15:12] :
+ (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b01) ? CLK_SKEW1_RESET_VAL[15:12] + 2 :
+ (strap_sticky[`STRAP_SCLK_SKEW_QSPI] == 2'b10) ? CLK_SKEW1_RESET_VAL[15:12] + 4 : CLK_SKEW1_RESET_VAL[15:12]-4;
-assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b00) ? SKEW_RESET_VAL[19:16] :
- (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4;
+assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b00) ? CLK_SKEW1_RESET_VAL[19:16] :
+ (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b01) ? CLK_SKEW1_RESET_VAL[19:16] + 2 :
+ (strap_sticky[`STRAP_SCLK_SKEW_UART] == 2'b10) ? CLK_SKEW1_RESET_VAL[19:16] + 4 : CLK_SKEW1_RESET_VAL[19:16]-4;
-assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b00) ? SKEW_RESET_VAL[23:20] :
- (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4;
+assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b00) ? CLK_SKEW1_RESET_VAL[23:20] :
+ (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b01) ? CLK_SKEW1_RESET_VAL[23:20] + 2 :
+ (strap_sticky[`STRAP_SCLK_SKEW_PINMUX] == 2'b10) ? CLK_SKEW1_RESET_VAL[23:20] + 4 : CLK_SKEW1_RESET_VAL[23:20]-4;
-assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b00) ? SKEW_RESET_VAL[27:24] :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4;
+assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b00) ? CLK_SKEW1_RESET_VAL[27:24] :
+ (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b01) ? CLK_SKEW1_RESET_VAL[27:24] + 2 :
+ (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b10) ? CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
assign rst_clk_ctrl1[31:28] = 4'b0;
always @ (posedge mclk ) begin
if (p_reset_n == 1'b0) begin
- cfg_clk_ctrl1 <= rst_clk_ctrl1 ;
+ cfg_clk_skew_ctrl1 <= rst_clk_ctrl1 ;
end
else begin
if(sw_wr_en_2 )
- cfg_clk_ctrl1 <= reg_wdata[31:0];
+ cfg_clk_skew_ctrl1 <= reg_wdata[31:0];
end
end
-//--------------------------------
-// clock control-2
-//--------------------------------
-always @ (posedge mclk) begin
- if (p_reset_n == 1'b0) begin
- cfg_clk_ctrl2 <= strap_sticky[7:0] ;
- end
- else begin
- if(sw_wr_en_3 )
- cfg_clk_ctrl2 <= reg_wdata[7:0];
- end
-end
-
+//-----------------------------------------------
+// reg-3: clock skew control-2
+// This skew control the RISCV clock, Since riscv clock need to stable on power-up
+// we have not given any strap control for it.
+//----------------------------------------------
always @ (posedge mclk ) begin
if (p_reset_n == 1'b0) begin
- cfg_clk_ctrl2 <= strap_sticky[7:0] ;
+ cfg_clk_skew_ctrl2 <= CLK_SKEW2_RESET_VAL ;
end
else begin
if(sw_wr_en_3 )
- cfg_clk_ctrl2 <= reg_wdata[7:0];
+ cfg_clk_skew_ctrl2 <= reg_wdata[31:0];
end
end
+
//-------------------------------------------------------------
// Note: system_strap reset (p_reset_n) will be released
// eariler than s_reset_n to take care of strap loading
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
index 564632d..1e4cb5e 160000
--- a/verilog/rtl/yifive/ycr1c
+++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@
-Subproject commit 564632db2e360384f3af7d61b7d87f6ec03b9b3c
+Subproject commit 1e4cb5efa0493cc33e68d6ace31d77b289446d6c
